From nobody Tue Apr 14 14:07:43 2026 Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 2EA2E37CD47; Tue, 14 Apr 2026 07:23:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=114.242.206.163 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776151399; cv=none; b=Qc4mxN/0tMF6d2CicEQsAkC3sRJI+IYbA/o9k5fzHAE7N5esxiFcT6DaNZUNZ1FSJiqqgw/oi26VoT0VNP/HJTbG2/yauJHgRadirxWvhlfZKiBWorANNr2EzwSbHAStrXxjG02prAxvL9ogEckA0kXYeopEjsUu4gmM1dSe6XY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776151399; c=relaxed/simple; bh=m9vLfXkwAGNcbtz4PWLItZyVz3fDONiH0jAW58kcJVA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=e/Zgr9Zc53ADVP02orHNe7bB3tYquISpxddizkEiEyuVf5/l/pJRtxou//RXzOz7wDg8DqUZ8tkORm9kvwEGSnOLoAxKP6g9SCgi7GqoidV7tyeDCP9i6udM3AxmNy1jRipBRYYOOHQpUEdJf7bmpJF+YykjLEuOcIQih6GLZl4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn; spf=pass smtp.mailfrom=loongson.cn; arc=none smtp.client-ip=114.242.206.163 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=loongson.cn Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8Dx8epk691p8mkAAA--.2096S3; Tue, 14 Apr 2026 15:23:16 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJCxfcJi691pErxsAA--.8539S3; Tue, 14 Apr 2026 15:23:16 +0800 (CST) From: Bibo Mao To: Huacai Chen Cc: kernel@xen0n.name, kvm@vger.kernel.org, loongarch@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 1/3] LoongArch: KVM: Move AVEC interrupt injection in switch loop Date: Tue, 14 Apr 2026 15:23:11 +0800 Message-Id: <20260414072313.3801110-2-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20260414072313.3801110-1-maobibo@loongson.cn> References: <20260414072313.3801110-1-maobibo@loongson.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJCxfcJi691pErxsAA--.8539S3 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Content-Type: text/plain; charset="utf-8" When AVEC interrupt controller is emulated in user space, AVEC interrupt is injected by software like SIP0/IPI interrupt. Here move AVEC interrupt injection in switch loop. Signed-off-by: Bibo Mao --- arch/loongarch/kvm/interrupt.c | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) diff --git a/arch/loongarch/kvm/interrupt.c b/arch/loongarch/kvm/interrupt.c index fb704f4c8ac5..f67dddfec7d0 100644 --- a/arch/loongarch/kvm/interrupt.c +++ b/arch/loongarch/kvm/interrupt.c @@ -32,12 +32,11 @@ static int kvm_irq_deliver(struct kvm_vcpu *vcpu, unsig= ned int priority) if (priority < EXCCODE_INT_NUM) irq =3D priority_to_irq[priority]; =20 - if (kvm_guest_has_msgint(&vcpu->arch) && (priority =3D=3D INT_AVEC)) { - set_gcsr_estat(irq); - return 1; - } - switch (priority) { + case INT_AVEC: + if (!kvm_guest_has_msgint(&vcpu->arch)) + break; + fallthrough; case INT_TI: case INT_IPI: case INT_SWI0: @@ -64,12 +63,11 @@ static int kvm_irq_clear(struct kvm_vcpu *vcpu, unsigne= d int priority) if (priority < EXCCODE_INT_NUM) irq =3D priority_to_irq[priority]; =20 - if (kvm_guest_has_msgint(&vcpu->arch) && (priority =3D=3D INT_AVEC)) { - clear_gcsr_estat(irq); - return 1; - } - switch (priority) { + case INT_AVEC: + if (!kvm_guest_has_msgint(&vcpu->arch)) + break; + fallthrough; case INT_TI: case INT_IPI: case INT_SWI0: --=20 2.39.3 From nobody Tue Apr 14 14:07:43 2026 Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 67AD036E47F; Tue, 14 Apr 2026 07:23:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=114.242.206.163 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776151411; cv=none; b=WK1vpn5poz59IQOQC9WscYcXNh6UJqkfj9aDkx3g8KTovwaeWNS/Sr6SoBR2YeE9m92/nYwwBxtgAt06jSdij9qI++HYCnZLf2vWVvoSKALN2L26atP+gXlxZbhiErk0LeR2K6dAoHbVgRx6PCRYMhin21gaC+JwtoDOyfavYmc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776151411; c=relaxed/simple; bh=tESCXq+yp8XK39DMet5wQKnmpLoNPeIl300dX6w+ZZ4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=XpB/ZRdz3m2k6uard5kIA2hKnPKj8vb+uuz0TgSFj90bt7Rtbfg0oauL/AA/lVDxdH3K4irkadWMurJtwipCFuHA/aEDiLklVQk+P+fHbvMoKUFhthSsXr8WSCSXVJWJmIj1OzCaMihS1wbIzktJ0Ig7rVQL2tQnHwixtykCVPI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn; spf=pass smtp.mailfrom=loongson.cn; arc=none smtp.client-ip=114.242.206.163 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=loongson.cn Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8AxAutn691p+2kAAA--.2106S3; Tue, 14 Apr 2026 15:23:19 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJCxfcJi691pErxsAA--.8539S4; Tue, 14 Apr 2026 15:23:18 +0800 (CST) From: Bibo Mao To: Huacai Chen Cc: kernel@xen0n.name, kvm@vger.kernel.org, loongarch@lists.linux.dev, linux-kernel@vger.kernel.org, stable@vger.kernel.org Subject: [PATCH 2/3] LoongArch: KVM: Fix HW timer interrupt lost when inject interrupt from software Date: Tue, 14 Apr 2026 15:23:12 +0800 Message-Id: <20260414072313.3801110-3-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20260414072313.3801110-1-maobibo@loongson.cn> References: <20260414072313.3801110-1-maobibo@loongson.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJCxfcJi691pErxsAA--.8539S4 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Content-Type: text/plain; charset="utf-8" With passthrough HW timer, timer interrupt is injected by HW. When inject emulated CPU interrupt by software such CPU_SIP0/CPU_IPI, HW timer interrupt may be lost. Here check whether there is timer tick value reversion before and after injecting emulated CPU interrupt by software, timer enabling by reading timer cfg register is skipped here. If timer tick value is detected with value changed, timer should be enabled. And inject timer interrupt by software if there is. Cc: Fixes: f45ad5b8aa93 ("LoongArch: KVM: Implement vcpu interrupt operations"). Signed-off-by: Bibo Mao --- arch/loongarch/kvm/interrupt.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/loongarch/kvm/interrupt.c b/arch/loongarch/kvm/interrupt.c index f67dddfec7d0..422515744dc0 100644 --- a/arch/loongarch/kvm/interrupt.c +++ b/arch/loongarch/kvm/interrupt.c @@ -27,6 +27,7 @@ static unsigned int priority_to_irq[EXCCODE_INT_NUM] =3D { static int kvm_irq_deliver(struct kvm_vcpu *vcpu, unsigned int priority) { unsigned int irq =3D 0; + unsigned long old, new; =20 clear_bit(priority, &vcpu->arch.irq_pending); if (priority < EXCCODE_INT_NUM) @@ -41,7 +42,20 @@ static int kvm_irq_deliver(struct kvm_vcpu *vcpu, unsign= ed int priority) case INT_IPI: case INT_SWI0: case INT_SWI1: + old =3D kvm_read_hw_gcsr(LOONGARCH_CSR_TVAL); set_gcsr_estat(irq); + new =3D kvm_read_hw_gcsr(LOONGARCH_CSR_TVAL); + /* + * On some platforms, the passthrought HW timer interrupt + * is lost when inject CPU interrupt by software if HW + * timer interrupt is arriving. + * + * Here check whether there is inversion with timer tick + * value, inject timer interrupt by SW if so. + */ + + if (new > old) + set_gcsr_estat(CPU_TIMER); break; =20 case INT_HWI0 ... INT_HWI7: @@ -58,6 +72,7 @@ static int kvm_irq_deliver(struct kvm_vcpu *vcpu, unsigne= d int priority) static int kvm_irq_clear(struct kvm_vcpu *vcpu, unsigned int priority) { unsigned int irq =3D 0; + unsigned long old, new; =20 clear_bit(priority, &vcpu->arch.irq_clear); if (priority < EXCCODE_INT_NUM) @@ -72,7 +87,11 @@ static int kvm_irq_clear(struct kvm_vcpu *vcpu, unsigned= int priority) case INT_IPI: case INT_SWI0: case INT_SWI1: + old =3D kvm_read_hw_gcsr(LOONGARCH_CSR_TVAL); clear_gcsr_estat(irq); + new =3D kvm_read_hw_gcsr(LOONGARCH_CSR_TVAL); + if (new > old) + set_gcsr_estat(CPU_TIMER); break; =20 case INT_HWI0 ... INT_HWI7: --=20 2.39.3 From nobody Tue Apr 14 14:07:43 2026 Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by smtp.subspace.kernel.org (Postfix) with ESMTP id A9F9336215C; Tue, 14 Apr 2026 07:23:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=114.242.206.163 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776151403; cv=none; b=h/4xkfT8vP4BA8ToIYGL5P4/f8bwr2PVjzuVu9NI6CEzboXLiuNx1dVb5Ic9MR5QZ4ZfX9Em6t7cjDaNTCXsBinz0A4CxZ9CdHXRbfU+WMQy26JYQ7qa0aAnckaiPSePgTXt+jKhldu7aaS6tWtIKQ2AHFvBxq9G5dtR+vAfkso= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776151403; c=relaxed/simple; bh=Z+bwjUhmShsgv2GqX9EsdR4Sma3va+gfYpHzP5mkAU4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=ho/mzocQIPv5Ve4xZS4gVJvzOCUmfmao8OvGb2EXQmWDisTgCMxljN4d8gBQMVU8XljvGpENQYbtj4/jxPNbfmNRG64fdrZTW33Cq6Xb0w9H/ngnXOk6BgYsijcffoLHEiQgCdw+wuibblg8kaak8kKOK+KXqQZEd/wf/lpDrzs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn; spf=pass smtp.mailfrom=loongson.cn; arc=none smtp.client-ip=114.242.206.163 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=loongson.cn Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8Dx8epn691p_2kAAA--.2097S3; Tue, 14 Apr 2026 15:23:19 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJCxfcJi691pErxsAA--.8539S5; Tue, 14 Apr 2026 15:23:19 +0800 (CST) From: Bibo Mao To: Huacai Chen Cc: kernel@xen0n.name, kvm@vger.kernel.org, loongarch@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 3/3] LoongArch: KVM: Move unconditional delay in timer clear scenery Date: Tue, 14 Apr 2026 15:23:13 +0800 Message-Id: <20260414072313.3801110-4-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20260414072313.3801110-1-maobibo@loongson.cn> References: <20260414072313.3801110-1-maobibo@loongson.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJCxfcJi691pErxsAA--.8539S5 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Content-Type: text/plain; charset="utf-8" When timer interrupt arrives in guest kernel, guest kernel clears the timer interrupt and program timer with the next incoming event. During this stage, timer tick is -1 and timer interrupt status is disabled in ESTAT register. KVM hypervisor need write zero with timer tick register and wait timer interrupt injection from HW side, and then clear timer interrupt. So there is 2 cycle delay in KVM hypervisor to emulate such scenery, and the delay is unnecessary if there is no need to clear timer interrupt. Here move 2 timer cycle delay in timer clear scenery and add timer estat checking after delay, and set max timer expire value if timer interrupt does not arrive still. Signed-off-by: Bibo Mao --- arch/loongarch/kvm/timer.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/arch/loongarch/kvm/timer.c b/arch/loongarch/kvm/timer.c index 29c2aaba63c3..c83f72a7c746 100644 --- a/arch/loongarch/kvm/timer.c +++ b/arch/loongarch/kvm/timer.c @@ -96,15 +96,27 @@ void kvm_restore_timer(struct kvm_vcpu *vcpu) * and set CSR TVAL with -1 */ write_gcsr_timertick(0); - __delay(2); /* Wait cycles until timer interrupt injected */ =20 /* * Writing CSR_TINTCLR_TI to LOONGARCH_CSR_TINTCLR will clear * timer interrupt, and CSR TVAL keeps unchanged with -1, it * avoids spurious timer interrupt */ - if (!(estat & CPU_TIMER)) + if (!(estat & CPU_TIMER)) { + __delay(2); /* Wait cycles until timer interrupt injected */ + + /* + * Fail to restore timer with timer tick =3D=3D -1 and + * timer interrupt disabled. + * + * Write timer tick with max value, timer will go + * down from max tick value + */ + estat =3D kvm_read_hw_gcsr(LOONGARCH_CSR_ESTAT); + if (!(estat & CPU_TIMER)) + write_gcsr_timertick(CSR_TCFG_VAL); gcsr_write(CSR_TINTCLR_TI, LOONGARCH_CSR_TINTCLR); + } return; } =20 --=20 2.39.3