From nobody Tue Apr 14 13:59:22 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D5BB535A3B2; Tue, 14 Apr 2026 07:05:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.9 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776150333; cv=none; b=h6g1l9gqn+QAuYz8nArkubeWsfnWK0Vil0/h6auDzwDkaYjcLdYsqaTNryFlAIPWfGHW47cenySSk53KESXVUU6KzUVFK3OQTJ4DbFqTUMkl/ez2H2yHvuZnh9mYom8ZD+4A6r/FSm1cFu7b5avN4JKaJc0CQnMX9Qa2q6hZvys= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776150333; c=relaxed/simple; bh=UEaAzxTV5k9qgAQSvHOrlSueZGJf50PP0Vc880X5kxY=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=bjNKiCP++hWn3deRmGJ2BrlPwzuTUjkzX/G4hiKQGuZvZt10KyPab1hOp/XWBrAhZ+AZNQ6SUFuBEh+LE2FmnHarev9I8moCbOOs5jdG5F4ZaxnuG41kkFsGDDOhhkn9x3hBlm1/JTk2gSFsWlf2wMynjTFOkt51EkwVcgHqjxI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Lb11EKax; arc=none smtp.client-ip=198.175.65.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Lb11EKax" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1776150330; x=1807686330; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=UEaAzxTV5k9qgAQSvHOrlSueZGJf50PP0Vc880X5kxY=; b=Lb11EKax1zGODQKuo5qgnlDVPLQ11eCe3wNkqt3roXYJxc1Vkyd3qlUc bkhUAEoeFltUW8WBmn/Joea+JZobdE1OyYHfpwo6j5J4fb5ad9uZICuP9 Y4L23DQFQYZ3Qi8P6cYh8dFZbgyFRCNjgQs0aeaZrY6tork4DvGAcs/CK +byjS15qQwx/sN+DtDVy58THQdH8v3wLYd4Nz3bI0oDVIRMOeJvnH4p+W eAmRs5peH3ftWSpK2+GkAFQFeIcF01fb6hXrqBNO6YrpUhnQrSxXgLEXD CtgihOMWqBHizNvz9iWSvwtcpexiUzXCmuQgTCjCXbAeV2NioXb/Wfki7 Q==; X-CSE-ConnectionGUID: oMJ1SYlySDeF4gcsQvGrSQ== X-CSE-MsgGUID: r6C/ohE9SR21x7aZwIPZKA== X-IronPort-AV: E=McAfee;i="6800,10657,11758"; a="99742465" X-IronPort-AV: E=Sophos;i="6.23,179,1770624000"; d="scan'208";a="99742465" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Apr 2026 00:05:29 -0700 X-CSE-ConnectionGUID: uqTXe9gHSgSP8qxj2lBBJw== X-CSE-MsgGUID: AAVr1BnyRwinhOcehdtPBw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,179,1770624000"; d="scan'208";a="231744549" Received: from guptapa-desk.jf.intel.com (HELO desk) ([10.165.239.46]) by fmviesa004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Apr 2026 00:05:28 -0700 Date: Tue, 14 Apr 2026 00:05:28 -0700 From: Pawan Gupta To: x86@kernel.org, Jon Kohler , Nikolay Borisov , "H. Peter Anvin" , Josh Poimboeuf , David Kaplan , Sean Christopherson , Borislav Petkov , Dave Hansen , Peter Zijlstra , Alexei Starovoitov , Daniel Borkmann , Andrii Nakryiko , KP Singh , Jiri Olsa , "David S. Miller" , David Laight , Andy Lutomirski , Thomas Gleixner , Ingo Molnar , David Ahern , Martin KaFai Lau , Eduard Zingerman , Song Liu , Yonghong Song , John Fastabend , Stanislav Fomichev , Hao Luo , Paolo Bonzini , Jonathan Corbet Cc: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, Asit Mallick , Tao Zhang , bpf@vger.kernel.org, netdev@vger.kernel.org, linux-doc@vger.kernel.org Subject: [PATCH v10 01/12] x86/bhi: x86/vmscape: Move LFENCE out of clear_bhb_loop() Message-ID: <20260414-vmscape-bhb-v10-1-efa924abae5f@linux.intel.com> X-Mailer: b4 0.16-dev References: <20260414-vmscape-bhb-v10-0-efa924abae5f@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20260414-vmscape-bhb-v10-0-efa924abae5f@linux.intel.com> Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Currently, the BHB clearing sequence is followed by an LFENCE to prevent transient execution of subsequent indirect branches prematurely. However, the LFENCE barrier could be unnecessary in certain cases. For example, when the kernel is using the BHI_DIS_S mitigation, and BHB clearing is only needed for userspace. In such cases, the LFENCE is redundant because ring transitions would provide the necessary serialization. Below is a quick recap of BHI mitigation options: On Alder Lake and newer BHI_DIS_S: Hardware control to mitigate BHI in ring0. This has low performance overhead. Long loop: Alternatively, a longer version of the BHB clearing sequence can be used to mitigate BHI. It can also be used to mitigate the BHI variant of VMSCAPE. This is not yet implemented in Linux. On older CPUs Short loop: Clears BHB at kernel entry and VMexit. The "Long loop" is effective on older CPUs as well, but should be avoided because of unnecessary overhead. On Alder Lake and newer CPUs, eIBRS isolates the indirect targets between guest and host. But when affected by the BHI variant of VMSCAPE, a guest's branch history may still influence indirect branches in userspace. This also means the big hammer IBPB could be replaced with a cheaper option that clears the BHB at exit-to-userspace after a VMexit. In preparation for adding the support for the BHB sequence (without LFENCE) on newer CPUs, move the LFENCE to the caller side after clear_bhb_loop() is executed. Allow callers to decide whether they need the LFENCE or not. This adds a few extra bytes to the call sites, but it obviates the need for multiple variants of clear_bhb_loop(). Suggested-by: Dave Hansen Tested-by: Jon Kohler Reviewed-by: Nikolay Borisov Signed-off-by: Pawan Gupta --- arch/x86/entry/entry_64.S | 5 ++++- arch/x86/include/asm/nospec-branch.h | 4 ++-- arch/x86/net/bpf_jit_comp.c | 2 ++ 3 files changed, 8 insertions(+), 3 deletions(-) diff --git a/arch/x86/entry/entry_64.S b/arch/x86/entry/entry_64.S index 42447b1e1dff..3a180a36ca0e 100644 --- a/arch/x86/entry/entry_64.S +++ b/arch/x86/entry/entry_64.S @@ -1528,6 +1528,9 @@ SYM_CODE_END(rewind_stack_and_make_dead) * refactored in the future if needed. The .skips are for safety, to ensure * that all RETs are in the second half of a cacheline to mitigate Indirect * Target Selection, rather than taking the slowpath via its_return_thunk. + * + * Note, callers should use a speculation barrier like LFENCE immediately = after + * a call to this function to ensure BHB is cleared before indirect branch= es. */ SYM_FUNC_START(clear_bhb_loop) ANNOTATE_NOENDBR @@ -1562,7 +1565,7 @@ SYM_FUNC_START(clear_bhb_loop) sub $1, %ecx jnz 1b .Lret2: RET -5: lfence +5: pop %rbp RET SYM_FUNC_END(clear_bhb_loop) diff --git a/arch/x86/include/asm/nospec-branch.h b/arch/x86/include/asm/no= spec-branch.h index 4f4b5e8a1574..70b377fcbc1c 100644 --- a/arch/x86/include/asm/nospec-branch.h +++ b/arch/x86/include/asm/nospec-branch.h @@ -331,11 +331,11 @@ =20 #ifdef CONFIG_X86_64 .macro CLEAR_BRANCH_HISTORY - ALTERNATIVE "", "call clear_bhb_loop", X86_FEATURE_CLEAR_BHB_LOOP + ALTERNATIVE "", "call clear_bhb_loop; lfence", X86_FEATURE_CLEAR_BHB_LOOP .endm =20 .macro CLEAR_BRANCH_HISTORY_VMEXIT - ALTERNATIVE "", "call clear_bhb_loop", X86_FEATURE_CLEAR_BHB_VMEXIT + ALTERNATIVE "", "call clear_bhb_loop; lfence", X86_FEATURE_CLEAR_BHB_VMEX= IT .endm #else #define CLEAR_BRANCH_HISTORY diff --git a/arch/x86/net/bpf_jit_comp.c b/arch/x86/net/bpf_jit_comp.c index e9b78040d703..63d6c9fa5e80 100644 --- a/arch/x86/net/bpf_jit_comp.c +++ b/arch/x86/net/bpf_jit_comp.c @@ -1624,6 +1624,8 @@ static int emit_spectre_bhb_barrier(u8 **pprog, u8 *i= p, =20 if (emit_call(&prog, func, ip)) return -EINVAL; + /* Don't speculate past this until BHB is cleared */ + EMIT_LFENCE(); EMIT1(0x59); /* pop rcx */ EMIT1(0x58); /* pop rax */ } --=20 2.34.1 From nobody Tue Apr 14 13:59:22 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D3BED342519; Tue, 14 Apr 2026 07:06:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776150370; cv=none; b=AemKy7zn7+lRhCFFNrA+80Us240s7GBT888Jq6dX87eLqrs9y8aBGWei4UQfAzmSpzDeSCplWX5ZiW5qyoZ7xDFR6ISPn20eyRoXPDl5zhEXwWVZKF9hLJM9Sb3muK3YDZd4sJzJ92SM9vvrv93RctiDErqVL2woEPPPcz38wEc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776150370; c=relaxed/simple; bh=HoDN0XYx5hRbRHIiPcm/8zQ8DC0db38UWRcLtxFcyPE=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=Js4iOR35mlly9Exvo2jtaeqrkzGdga68TxMDCnZpsl+9bjpqVQp7q78ge7GpB3eF9TSjSJ4BPUbV3pAcAsGo0umNuyCgTUlxEazzXVMh4ie17sJc2MdPARxihdtvBWOee2DnAT3xiDbYK7Sja5sEnKfmbdbqKUV09VNFPHx54YU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Fofmpddf; arc=none smtp.client-ip=192.198.163.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Fofmpddf" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1776150369; x=1807686369; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=HoDN0XYx5hRbRHIiPcm/8zQ8DC0db38UWRcLtxFcyPE=; b=Fofmpddfl7WkhcifktLcY0rEOeB2+nEpP3XazH2s43NSnrmo6Ds8WJOa ipPv1mc70cOMcRghsdH3ZvQWYeT9ggNuvofH465CLZ9kzDCnhFvHIQ1qT UBC2j0jk0dbt6JB9FxPnV+zF0pIyN6GLd1efX5eDJqxhVoPTwjY5asxuw o5iyyX2NJ+sfmHZoC0sNAw9pBVzx8JdYYqsUXKHqcmZlAit1QHFxL6WAd fOID9XA2Nk2caNBYPzhCqKsinIlZDM9xenHNbcjmdneN/7fBjTAEmdaWk t5gp97wO651FLs7uLXEWh32wGDG2XsA5/xakH60M5YgzWn/CmOPb78J34 g==; X-CSE-ConnectionGUID: NSNbPF9fSDaIya2FTDceBw== X-CSE-MsgGUID: VZ7ResY3TzaTGZSIA2zjqA== X-IronPort-AV: E=McAfee;i="6800,10657,11758"; a="80983413" X-IronPort-AV: E=Sophos;i="6.23,179,1770624000"; d="scan'208";a="80983413" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Apr 2026 00:06:01 -0700 X-CSE-ConnectionGUID: VkkaHAwsT8291STVcV95NQ== X-CSE-MsgGUID: cu1GAqAIS9abSmoV4dLO/Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,179,1770624000"; d="scan'208";a="234941751" Received: from guptapa-desk.jf.intel.com (HELO desk) ([10.165.239.46]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Apr 2026 00:05:44 -0700 Date: Tue, 14 Apr 2026 00:05:44 -0700 From: Pawan Gupta To: x86@kernel.org, Jon Kohler , Nikolay Borisov , "H. Peter Anvin" , Josh Poimboeuf , David Kaplan , Sean Christopherson , Borislav Petkov , Dave Hansen , Peter Zijlstra , Alexei Starovoitov , Daniel Borkmann , Andrii Nakryiko , KP Singh , Jiri Olsa , "David S. Miller" , David Laight , Andy Lutomirski , Thomas Gleixner , Ingo Molnar , David Ahern , Martin KaFai Lau , Eduard Zingerman , Song Liu , Yonghong Song , John Fastabend , Stanislav Fomichev , Hao Luo , Paolo Bonzini , Jonathan Corbet Cc: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, Asit Mallick , Tao Zhang , bpf@vger.kernel.org, netdev@vger.kernel.org, linux-doc@vger.kernel.org Subject: [PATCH v10 02/12] x86/bhi: Make clear_bhb_loop() effective on newer CPUs Message-ID: <20260414-vmscape-bhb-v10-2-efa924abae5f@linux.intel.com> X-Mailer: b4 0.16-dev References: <20260414-vmscape-bhb-v10-0-efa924abae5f@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20260414-vmscape-bhb-v10-0-efa924abae5f@linux.intel.com> Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" As a mitigation for BHI, clear_bhb_loop() executes branches that overwrite the Branch History Buffer (BHB). On Alder Lake and newer parts this sequence is not sufficient because it doesn't clear enough entries. This was not an issue because these CPUs use the BHI_DIS_S hardware mitigation in the kernel. Now with VMSCAPE (BHI variant) it is also required to isolate branch history between guests and userspace. Since BHI_DIS_S only protects the kernel, the newer CPUs also use IBPB. A cheaper alternative to the current IBPB mitigation is clear_bhb_loop(). But it currently does not clear enough BHB entries to be effective on newer CPUs with larger BHB. At boot, dynamically set the loop count of clear_bhb_loop() such that it is effective on newer CPUs too. Introduce global loop counts, initializing them with appropriate value based on the hardware feature X86_FEATURE_BHI_CTRL. Suggested-by: Dave Hansen Signed-off-by: Pawan Gupta --- arch/x86/entry/entry_64.S | 8 +++++--- arch/x86/include/asm/nospec-branch.h | 2 ++ arch/x86/kernel/cpu/bugs.c | 13 +++++++++++++ 3 files changed, 20 insertions(+), 3 deletions(-) diff --git a/arch/x86/entry/entry_64.S b/arch/x86/entry/entry_64.S index 3a180a36ca0e..bbd4b1c7ec04 100644 --- a/arch/x86/entry/entry_64.S +++ b/arch/x86/entry/entry_64.S @@ -1536,7 +1536,9 @@ SYM_FUNC_START(clear_bhb_loop) ANNOTATE_NOENDBR push %rbp mov %rsp, %rbp - movl $5, %ecx + + movzbl bhb_seq_outer_loop(%rip), %ecx + ANNOTATE_INTRA_FUNCTION_CALL call 1f jmp 5f @@ -1556,8 +1558,8 @@ SYM_FUNC_START(clear_bhb_loop) * This should be ideally be: .skip 32 - (.Lret2 - 2f), 0xcc * but some Clang versions (e.g. 18) don't like this. */ - .skip 32 - 18, 0xcc -2: movl $5, %eax + .skip 32 - 20, 0xcc +2: movzbl bhb_seq_inner_loop(%rip), %eax 3: jmp 4f nop 4: sub $1, %eax diff --git a/arch/x86/include/asm/nospec-branch.h b/arch/x86/include/asm/no= spec-branch.h index 70b377fcbc1c..87b83ae7c97f 100644 --- a/arch/x86/include/asm/nospec-branch.h +++ b/arch/x86/include/asm/nospec-branch.h @@ -548,6 +548,8 @@ DECLARE_PER_CPU(u64, x86_spec_ctrl_current); extern void update_spec_ctrl_cond(u64 val); extern u64 spec_ctrl_current(void); =20 +extern u8 bhb_seq_inner_loop, bhb_seq_outer_loop; + /* * With retpoline, we must use IBRS to restrict branch prediction * before calling into firmware. diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index 83f51cab0b1e..2cb4a96247d8 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -2047,6 +2047,10 @@ enum bhi_mitigations { static enum bhi_mitigations bhi_mitigation __ro_after_init =3D IS_ENABLED(CONFIG_MITIGATION_SPECTRE_BHI) ? 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Peter Anvin" , Josh Poimboeuf , David Kaplan , Sean Christopherson , Borislav Petkov , Dave Hansen , Peter Zijlstra , Alexei Starovoitov , Daniel Borkmann , Andrii Nakryiko , KP Singh , Jiri Olsa , "David S. Miller" , David Laight , Andy Lutomirski , Thomas Gleixner , Ingo Molnar , David Ahern , Martin KaFai Lau , Eduard Zingerman , Song Liu , Yonghong Song , John Fastabend , Stanislav Fomichev , Hao Luo , Paolo Bonzini , Jonathan Corbet Cc: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, Asit Mallick , Tao Zhang , bpf@vger.kernel.org, netdev@vger.kernel.org, linux-doc@vger.kernel.org Subject: [PATCH v10 03/12] x86/bhi: Rename clear_bhb_loop() to clear_bhb_loop_nofence() Message-ID: <20260414-vmscape-bhb-v10-3-efa924abae5f@linux.intel.com> X-Mailer: b4 0.16-dev References: <20260414-vmscape-bhb-v10-0-efa924abae5f@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20260414-vmscape-bhb-v10-0-efa924abae5f@linux.intel.com> Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" To reflect the recent change that moved LFENCE to the caller side. Suggested-by: Borislav Petkov Reviewed-by: Nikolay Borisov Tested-by: Jon Kohler Signed-off-by: Pawan Gupta --- arch/x86/entry/entry_64.S | 8 ++++---- arch/x86/include/asm/nospec-branch.h | 6 +++--- arch/x86/net/bpf_jit_comp.c | 2 +- 3 files changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/x86/entry/entry_64.S b/arch/x86/entry/entry_64.S index bbd4b1c7ec04..1f56d086d312 100644 --- a/arch/x86/entry/entry_64.S +++ b/arch/x86/entry/entry_64.S @@ -1532,7 +1532,7 @@ SYM_CODE_END(rewind_stack_and_make_dead) * Note, callers should use a speculation barrier like LFENCE immediately = after * a call to this function to ensure BHB is cleared before indirect branch= es. */ -SYM_FUNC_START(clear_bhb_loop) +SYM_FUNC_START(clear_bhb_loop_nofence) ANNOTATE_NOENDBR push %rbp mov %rsp, %rbp @@ -1570,6 +1570,6 @@ SYM_FUNC_START(clear_bhb_loop) 5: pop %rbp RET -SYM_FUNC_END(clear_bhb_loop) -EXPORT_SYMBOL_FOR_KVM(clear_bhb_loop) -STACK_FRAME_NON_STANDARD(clear_bhb_loop) +SYM_FUNC_END(clear_bhb_loop_nofence) +EXPORT_SYMBOL_FOR_KVM(clear_bhb_loop_nofence) +STACK_FRAME_NON_STANDARD(clear_bhb_loop_nofence) diff --git a/arch/x86/include/asm/nospec-branch.h b/arch/x86/include/asm/no= spec-branch.h index 87b83ae7c97f..157eb69c7f0f 100644 --- a/arch/x86/include/asm/nospec-branch.h +++ b/arch/x86/include/asm/nospec-branch.h @@ -331,11 +331,11 @@ =20 #ifdef CONFIG_X86_64 .macro CLEAR_BRANCH_HISTORY - ALTERNATIVE "", "call clear_bhb_loop; lfence", X86_FEATURE_CLEAR_BHB_LOOP + ALTERNATIVE "", "call clear_bhb_loop_nofence; lfence", X86_FEATURE_CLEAR_= BHB_LOOP .endm =20 .macro CLEAR_BRANCH_HISTORY_VMEXIT - ALTERNATIVE "", "call clear_bhb_loop; lfence", X86_FEATURE_CLEAR_BHB_VMEX= IT + ALTERNATIVE "", "call clear_bhb_loop_nofence; lfence", X86_FEATURE_CLEAR_= BHB_VMEXIT .endm #else #define CLEAR_BRANCH_HISTORY @@ -389,7 +389,7 @@ extern void entry_untrain_ret(void); extern void write_ibpb(void); =20 #ifdef CONFIG_X86_64 -extern void clear_bhb_loop(void); +extern void clear_bhb_loop_nofence(void); #endif =20 extern void (*x86_return_thunk)(void); diff --git a/arch/x86/net/bpf_jit_comp.c b/arch/x86/net/bpf_jit_comp.c index 63d6c9fa5e80..f40e88f87273 100644 --- a/arch/x86/net/bpf_jit_comp.c +++ b/arch/x86/net/bpf_jit_comp.c @@ -1619,7 +1619,7 @@ static int emit_spectre_bhb_barrier(u8 **pprog, u8 *i= p, EMIT1(0x51); /* push rcx */ ip +=3D 2; =20 - func =3D (u8 *)clear_bhb_loop; + func =3D (u8 *)clear_bhb_loop_nofence; ip +=3D x86_call_depth_emit_accounting(&prog, func, ip); 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X-CSE-ConnectionGUID: DztxSaOmT9SR2K1OZdUscA== X-CSE-MsgGUID: +IIV1xSoT76PMgiiir8P6A== X-IronPort-AV: E=McAfee;i="6800,10657,11758"; a="102555074" X-IronPort-AV: E=Sophos;i="6.23,179,1770624000"; d="scan'208";a="102555074" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Apr 2026 00:06:17 -0700 X-CSE-ConnectionGUID: pqph0lOtTau+82SCirFJmQ== X-CSE-MsgGUID: EPdP/xZdTiSxXjXrG9pEFQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,179,1770624000"; d="scan'208";a="234043845" Received: from guptapa-desk.jf.intel.com (HELO desk) ([10.165.239.46]) by ORVIESA003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Apr 2026 00:06:17 -0700 Date: Tue, 14 Apr 2026 00:06:17 -0700 From: Pawan Gupta To: x86@kernel.org, Jon Kohler , Nikolay Borisov , "H. Peter Anvin" , Josh Poimboeuf , David Kaplan , Sean Christopherson , Borislav Petkov , Dave Hansen , Peter Zijlstra , Alexei Starovoitov , Daniel Borkmann , Andrii Nakryiko , KP Singh , Jiri Olsa , "David S. Miller" , David Laight , Andy Lutomirski , Thomas Gleixner , Ingo Molnar , David Ahern , Martin KaFai Lau , Eduard Zingerman , Song Liu , Yonghong Song , John Fastabend , Stanislav Fomichev , Hao Luo , Paolo Bonzini , Jonathan Corbet Cc: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, Asit Mallick , Tao Zhang , bpf@vger.kernel.org, netdev@vger.kernel.org, linux-doc@vger.kernel.org Subject: [PATCH v10 04/12] x86/vmscape: Rename x86_ibpb_exit_to_user to x86_predictor_flush_exit_to_user Message-ID: <20260414-vmscape-bhb-v10-4-efa924abae5f@linux.intel.com> X-Mailer: b4 0.16-dev References: <20260414-vmscape-bhb-v10-0-efa924abae5f@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20260414-vmscape-bhb-v10-0-efa924abae5f@linux.intel.com> Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" With the upcoming changes x86_ibpb_exit_to_user will also be used when BHB clearing sequence is used. Rename it cover both the cases. No functional change. Suggested-by: Sean Christopherson Tested-by: Jon Kohler Acked-by: Sean Christopherson Signed-off-by: Pawan Gupta --- arch/x86/include/asm/entry-common.h | 6 +++--- arch/x86/include/asm/nospec-branch.h | 2 +- arch/x86/kernel/cpu/bugs.c | 4 ++-- arch/x86/kvm/x86.c | 2 +- 4 files changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/x86/include/asm/entry-common.h b/arch/x86/include/asm/ent= ry-common.h index ce3eb6d5fdf9..c45858db16c9 100644 --- a/arch/x86/include/asm/entry-common.h +++ b/arch/x86/include/asm/entry-common.h @@ -94,11 +94,11 @@ static inline void arch_exit_to_user_mode_prepare(struc= t pt_regs *regs, */ choose_random_kstack_offset(rdtsc()); =20 - /* Avoid unnecessary reads of 'x86_ibpb_exit_to_user' */ + /* Avoid unnecessary reads of 'x86_predictor_flush_exit_to_user' */ if (cpu_feature_enabled(X86_FEATURE_IBPB_EXIT_TO_USER) && - this_cpu_read(x86_ibpb_exit_to_user)) { + this_cpu_read(x86_predictor_flush_exit_to_user)) { indirect_branch_prediction_barrier(); - this_cpu_write(x86_ibpb_exit_to_user, false); + this_cpu_write(x86_predictor_flush_exit_to_user, false); } } #define arch_exit_to_user_mode_prepare arch_exit_to_user_mode_prepare diff --git a/arch/x86/include/asm/nospec-branch.h b/arch/x86/include/asm/no= spec-branch.h index 157eb69c7f0f..0381db59c39d 100644 --- a/arch/x86/include/asm/nospec-branch.h +++ b/arch/x86/include/asm/nospec-branch.h @@ -533,7 +533,7 @@ void alternative_msr_write(unsigned int msr, u64 val, u= nsigned int feature) : "memory"); } =20 -DECLARE_PER_CPU(bool, x86_ibpb_exit_to_user); +DECLARE_PER_CPU(bool, x86_predictor_flush_exit_to_user); =20 static inline void indirect_branch_prediction_barrier(void) { diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index 2cb4a96247d8..002bf4adccc3 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -65,8 +65,8 @@ EXPORT_PER_CPU_SYMBOL_GPL(x86_spec_ctrl_current); * be needed to before running userspace. That IBPB will flush the branch * predictor content. */ -DEFINE_PER_CPU(bool, x86_ibpb_exit_to_user); -EXPORT_PER_CPU_SYMBOL_GPL(x86_ibpb_exit_to_user); +DEFINE_PER_CPU(bool, x86_predictor_flush_exit_to_user); +EXPORT_PER_CPU_SYMBOL_GPL(x86_predictor_flush_exit_to_user); =20 u64 x86_pred_cmd __ro_after_init =3D PRED_CMD_IBPB; =20 diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index fd1c4a36b593..45d7cfedc507 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -11464,7 +11464,7 @@ static int vcpu_enter_guest(struct kvm_vcpu *vcpu) * may migrate to. */ if (cpu_feature_enabled(X86_FEATURE_IBPB_EXIT_TO_USER)) - this_cpu_write(x86_ibpb_exit_to_user, true); + this_cpu_write(x86_predictor_flush_exit_to_user, true); =20 /* * Consume any pending interrupts, including the possible source of --=20 2.34.1 From nobody Tue Apr 14 13:59:22 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E3BBB35A925; Tue, 14 Apr 2026 07:07:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.9 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776150441; cv=none; b=qL1MqGelf7UKCNrjhKlrhQAsEEOwFy7vKjyz3A/y9jBxw/wstU0Sx8V90DRVHaAqn+7tPWnnJbdxkQcFErBqwVG/Ps+HJ++7TECWjTB4OFyuvOUmW7XQYoKA9+z1STrhmoX20f5vluXKOubnN3OJ+tZXU8KCBH+CV/qy7uaQdco= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776150441; c=relaxed/simple; bh=Z+UBFYvZmhxdkKBWIZKrd5/Lkbp8grvu2K8zVnKyDK0=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=sWv1IFsRpYwhpncGZ6fpsCX222lqoz3MN4xO/ut7hnRZeYes/OIBBUBR5Zugt34ue5CkLeKxJTQyNupWdQOzMYZojY1N8HDImKoHyGG5stBIORzyVteG3lBQb0xVQUonNLtga587FM3qGE43lk1a5S8QlAXKqz/crAf7jaCNJBs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=hUUMm3eX; arc=none smtp.client-ip=198.175.65.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="hUUMm3eX" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1776150438; x=1807686438; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=Z+UBFYvZmhxdkKBWIZKrd5/Lkbp8grvu2K8zVnKyDK0=; b=hUUMm3eXx/RplDzaBdTyWbdY/6d8pNxTYUsq5CkXEojhQGmJGIhsG72q FS7hkSZ3XuZa2YCE9OQVChu/nUmsQjcjimK+IJ9lIJ9WeVUQl+RE//Rqf 3pV+Mm6tXnHblHBGZwFbdNbz1TYdzDVQ8Qsn7dSCqW74w+reOYw/6mZ+C kTmbe9wLYJwmTujstz928DKowsqwqPRXoOHx1qR8LC393Nv10zc56WDyE ptr7q8aZ4b3Nd9dnWrlEZpWxI8kkj4pGbOgZrsLLnr2GUJR6VM2GtUNDP HD2oPaP5U9HdNHznYVbS3bGkGVxUYfXx3xHAEUom9OHDah3XRle+a2zaX w==; X-CSE-ConnectionGUID: S9WeEtGMR+WxJeuSnEX8Bg== X-CSE-MsgGUID: yAG9xyVTTt6jrKBi/jCZzQ== X-IronPort-AV: E=McAfee;i="6800,10657,11758"; a="99742672" X-IronPort-AV: E=Sophos;i="6.23,179,1770624000"; d="scan'208";a="99742672" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Apr 2026 00:06:32 -0700 X-CSE-ConnectionGUID: i8s5DN8vTFeTmGMX/ltYVw== X-CSE-MsgGUID: Zu5w6HYMSvuqPfjOy39EwA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,179,1770624000"; d="scan'208";a="231744873" Received: from guptapa-desk.jf.intel.com (HELO desk) ([10.165.239.46]) by fmviesa004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Apr 2026 00:06:32 -0700 Date: Tue, 14 Apr 2026 00:06:32 -0700 From: Pawan Gupta To: x86@kernel.org, Jon Kohler , Nikolay Borisov , "H. Peter Anvin" , Josh Poimboeuf , David Kaplan , Sean Christopherson , Borislav Petkov , Dave Hansen , Peter Zijlstra , Alexei Starovoitov , Daniel Borkmann , Andrii Nakryiko , KP Singh , Jiri Olsa , "David S. Miller" , David Laight , Andy Lutomirski , Thomas Gleixner , Ingo Molnar , David Ahern , Martin KaFai Lau , Eduard Zingerman , Song Liu , Yonghong Song , John Fastabend , Stanislav Fomichev , Hao Luo , Paolo Bonzini , Jonathan Corbet Cc: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, Asit Mallick , Tao Zhang , bpf@vger.kernel.org, netdev@vger.kernel.org, linux-doc@vger.kernel.org Subject: [PATCH v10 05/12] x86/vmscape: Move mitigation selection to a switch() Message-ID: <20260414-vmscape-bhb-v10-5-efa924abae5f@linux.intel.com> X-Mailer: b4 0.16-dev References: <20260414-vmscape-bhb-v10-0-efa924abae5f@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20260414-vmscape-bhb-v10-0-efa924abae5f@linux.intel.com> Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This ensures that all mitigation modes are explicitly handled, while keeping the mitigation selection for each mode together. This also prepares for adding BHB-clearing mitigation mode for VMSCAPE. Tested-by: Jon Kohler Reviewed-by: Nikolay Borisov Signed-off-by: Pawan Gupta --- arch/x86/kernel/cpu/bugs.c | 24 ++++++++++++++++++++---- 1 file changed, 20 insertions(+), 4 deletions(-) diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index 002bf4adccc3..636280c612f0 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -3088,17 +3088,33 @@ early_param("vmscape", vmscape_parse_cmdline); =20 static void __init vmscape_select_mitigation(void) { - if (!boot_cpu_has_bug(X86_BUG_VMSCAPE) || - !boot_cpu_has(X86_FEATURE_IBPB)) { + if (!boot_cpu_has_bug(X86_BUG_VMSCAPE)) { vmscape_mitigation =3D VMSCAPE_MITIGATION_NONE; return; } =20 - if (vmscape_mitigation =3D=3D VMSCAPE_MITIGATION_AUTO) { - if (should_mitigate_vuln(X86_BUG_VMSCAPE)) + if ((vmscape_mitigation =3D=3D VMSCAPE_MITIGATION_AUTO) && + !should_mitigate_vuln(X86_BUG_VMSCAPE)) + vmscape_mitigation =3D VMSCAPE_MITIGATION_NONE; + + switch (vmscape_mitigation) { + case VMSCAPE_MITIGATION_NONE: + break; + + case VMSCAPE_MITIGATION_IBPB_EXIT_TO_USER: + if (!boot_cpu_has(X86_FEATURE_IBPB)) + vmscape_mitigation =3D VMSCAPE_MITIGATION_NONE; + break; + + case VMSCAPE_MITIGATION_AUTO: + if (boot_cpu_has(X86_FEATURE_IBPB)) vmscape_mitigation =3D VMSCAPE_MITIGATION_IBPB_EXIT_TO_USER; else vmscape_mitigation =3D VMSCAPE_MITIGATION_NONE; + break; + + default: + break; } } =20 --=20 2.34.1 From nobody Tue Apr 14 13:59:22 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 68A2935E956; Tue, 14 Apr 2026 07:07:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.9 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776150442; cv=none; b=hlXJjwc2DCXthQfSnngB9QZyRpwMCeGP+bq8lZ5PvQLVGpTRht0h/y5+Ng7c9OcLIoCCpSVC3FmuumqosGFJk/gpkCMhgNndl7sZrgJNziJAnz1inEx6cXhQLXE8KLsuvtK6A8EoOoNs4g6wdjCY12lwHgrCjl8FxcmWlID4Xac= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776150442; c=relaxed/simple; bh=YsdvlQqeVior0g/k+WAElPcnRGxse6gI8p2joQTg8Fc=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=rJC0DzCBip2KX0dk3hJje0tFhnRoN1+lcKeMN3i9tbcN7zhJ/PxD2o7FCDDF0MeVbRrNrKf5pfXLTegzO1YlU3fmcbc9N1WcorjnIyCnsKKWSOxCM3Ub7EOCRTORpcLwMpMIw1g7cYTpRP5dH5bPR2lI8SibR8yB9ln1o21NcTk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=PovEGdae; arc=none smtp.client-ip=198.175.65.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="PovEGdae" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1776150440; x=1807686440; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=YsdvlQqeVior0g/k+WAElPcnRGxse6gI8p2joQTg8Fc=; b=PovEGdae8yNB/AX6euDry4JoYMxrWZxXzWQoydG3w9Fo3DkpObX9cW11 LhogVTP9YqI5XKURzMV02suRkYUbou9mx8ijnZDxWuPAAikWmj1q/ZBdM XOllFPlhSCogrn/MVT6MzKcbdHy+y8lXhJIuhvPWJve2OwyI7p8CMemuO 9SK1DEOMHe8ubqjXs/550mf+1MuE+mc4LD/ObxDC2oA95IsI6dQVcIo81 6XJpVQg6MCkB5YYU1QcF4Q8f/V+NUQppeef4E6j8lUunybJcaYE1nPQX8 +3S98Jh/pUZXctD5T5iV4bsaKNTs6kN/XTN8yoW6pEakgv255dpFetnBD Q==; X-CSE-ConnectionGUID: rFHTN/mrSRa0XFt8ZVzD0A== X-CSE-MsgGUID: eFYd2JKhRuaLPIihMKletg== X-IronPort-AV: E=McAfee;i="6800,10657,11758"; a="99742708" X-IronPort-AV: E=Sophos;i="6.23,179,1770624000"; d="scan'208";a="99742708" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Apr 2026 00:06:49 -0700 X-CSE-ConnectionGUID: Qqv0CU4hSmi1Ya0DhafpcQ== X-CSE-MsgGUID: ld6HPmOxQI28P4mVvbJYIw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,179,1770624000"; d="scan'208";a="231744909" Received: from guptapa-desk.jf.intel.com (HELO desk) ([10.165.239.46]) by fmviesa004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Apr 2026 00:06:49 -0700 Date: Tue, 14 Apr 2026 00:06:48 -0700 From: Pawan Gupta To: x86@kernel.org, Jon Kohler , Nikolay Borisov , "H. Peter Anvin" , Josh Poimboeuf , David Kaplan , Sean Christopherson , Borislav Petkov , Dave Hansen , Peter Zijlstra , Alexei Starovoitov , Daniel Borkmann , Andrii Nakryiko , KP Singh , Jiri Olsa , "David S. Miller" , David Laight , Andy Lutomirski , Thomas Gleixner , Ingo Molnar , David Ahern , Martin KaFai Lau , Eduard Zingerman , Song Liu , Yonghong Song , John Fastabend , Stanislav Fomichev , Hao Luo , Paolo Bonzini , Jonathan Corbet Cc: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, Asit Mallick , Tao Zhang , bpf@vger.kernel.org, netdev@vger.kernel.org, linux-doc@vger.kernel.org Subject: [PATCH v10 06/12] x86/vmscape: Use write_ibpb() instead of indirect_branch_prediction_barrier() Message-ID: <20260414-vmscape-bhb-v10-6-efa924abae5f@linux.intel.com> X-Mailer: b4 0.16-dev References: <20260414-vmscape-bhb-v10-0-efa924abae5f@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20260414-vmscape-bhb-v10-0-efa924abae5f@linux.intel.com> Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" indirect_branch_prediction_barrier() is a wrapper to write_ibpb(), which also checks if the CPU supports IBPB. For VMSCAPE, call to indirect_branch_prediction_barrier() is only possible when CPU supports IBPB. Simply call write_ibpb() directly to avoid unnecessary alternative patching. Suggested-by: Dave Hansen Tested-by: Jon Kohler Reviewed-by: Nikolay Borisov Signed-off-by: Pawan Gupta --- arch/x86/include/asm/entry-common.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/include/asm/entry-common.h b/arch/x86/include/asm/ent= ry-common.h index c45858db16c9..78b143673ca7 100644 --- a/arch/x86/include/asm/entry-common.h +++ b/arch/x86/include/asm/entry-common.h @@ -97,7 +97,7 @@ static inline void arch_exit_to_user_mode_prepare(struct = pt_regs *regs, /* Avoid unnecessary reads of 'x86_predictor_flush_exit_to_user' */ if (cpu_feature_enabled(X86_FEATURE_IBPB_EXIT_TO_USER) && this_cpu_read(x86_predictor_flush_exit_to_user)) { - indirect_branch_prediction_barrier(); + write_ibpb(); this_cpu_write(x86_predictor_flush_exit_to_user, false); } } --=20 2.34.1 From nobody Tue Apr 14 13:59:22 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 40B5C35A925; Tue, 14 Apr 2026 07:07:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776150428; cv=none; b=r2hT2MoUrliPr6lLDfe6X75AvlqNpdGE4F0XItKWcumiIvBmjb9WqpKsAQQzMXPpSfUwgoMXgDcMaOqkl65ThZx3OGh6KhUtsdO8vMv7BxSfcwCK94nXbwfAh4o1A8ryQtWjXgjptv9eJIOGlwj6g5S+IZxi5trYnJdwyC8mfhM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776150428; c=relaxed/simple; bh=ru4xmAG5090zMTorvzBMO3CkMmXYAyYQWFiIdf/Og8c=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=ObpIU4IwfJdzbonjTgrTUfiJy52JxeX6yoxN+QZNkEfI+59IsIjN18MH0aql9au2CIYh6lct+Gf5IK0QnRvAsc16WdfnX3SMs06bt8zYqXxMG1U7XO/1dsSDj8I/S+LwH/DPsHnya9PQtkjBGiDLmfe6wEhmaIbtlhxI2edM7VQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=KWMZxDbo; arc=none smtp.client-ip=198.175.65.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="KWMZxDbo" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1776150428; x=1807686428; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=ru4xmAG5090zMTorvzBMO3CkMmXYAyYQWFiIdf/Og8c=; b=KWMZxDboe5ZZE8TD0yEhFVGtVXdInqzl5WXVx0txiXJsKtEdK5vlzZNr Zp71RSgF6m5VuPCSMD+/q3CsnfId/KyokoGT3pd0DN0HSpukB6woVW29+ I77EVp1apG8YzPECuwM55OZsHmuZYx4xDcZmdfnkc5LuCXEPDb8Fv2DEf Lf+H/f96/1vgpfuyYjrAnreu5Nj4ib2TwQOSzL7IRYh8bmFoSOxSG7SuZ O8C4pVWZ2s1AoAezdIpoTiVaMylx/+4DbDUBaQpAy72YS++23Yh57iBq0 g51ozkiFse6rSfdtlbMb2XOMprRWtBzy5U5+RvRNQ4+84El8JADJJNPDZ A==; X-CSE-ConnectionGUID: 0rWqj1kMRUCSHfHUyrpRvg== X-CSE-MsgGUID: Itpu1xHuS82Mxdf2iLi/qA== X-IronPort-AV: E=McAfee;i="6800,10657,11758"; a="77279725" X-IronPort-AV: E=Sophos;i="6.23,179,1770624000"; d="scan'208";a="77279725" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Apr 2026 00:07:07 -0700 X-CSE-ConnectionGUID: B+lsJgTXQpCjAHLtvJHINg== X-CSE-MsgGUID: Uoq8nSZtSuSIdJW7nhtEjg== X-ExtLoop1: 1 Received: from guptapa-desk.jf.intel.com (HELO desk) ([10.165.239.46]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Apr 2026 00:07:05 -0700 Date: Tue, 14 Apr 2026 00:07:05 -0700 From: Pawan Gupta To: x86@kernel.org, Jon Kohler , Nikolay Borisov , "H. Peter Anvin" , Josh Poimboeuf , David Kaplan , Sean Christopherson , Borislav Petkov , Dave Hansen , Peter Zijlstra , Alexei Starovoitov , Daniel Borkmann , Andrii Nakryiko , KP Singh , Jiri Olsa , "David S. Miller" , David Laight , Andy Lutomirski , Thomas Gleixner , Ingo Molnar , David Ahern , Martin KaFai Lau , Eduard Zingerman , Song Liu , Yonghong Song , John Fastabend , Stanislav Fomichev , Hao Luo , Paolo Bonzini , Jonathan Corbet Cc: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, Asit Mallick , Tao Zhang , bpf@vger.kernel.org, netdev@vger.kernel.org, linux-doc@vger.kernel.org Subject: [PATCH v10 07/12] static_call: Add EXPORT_STATIC_CALL_FOR_MODULES() Message-ID: <20260414-vmscape-bhb-v10-7-efa924abae5f@linux.intel.com> X-Mailer: b4 0.16-dev References: <20260414-vmscape-bhb-v10-0-efa924abae5f@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20260414-vmscape-bhb-v10-0-efa924abae5f@linux.intel.com> Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" There is EXPORT_STATIC_CALL_TRAMP() that hides the static key from all modules. But there is no equivalent of EXPORT_SYMBOL_FOR_MODULES() to restrict symbol visibility to only certain modules. Add EXPORT_STATIC_CALL_FOR_MODULES(name, mods) that wraps both the key and the trampoline with EXPORT_SYMBOL_FOR_MODULES(), allowing only a limited set of modules to see and update the static key. The immediate user is KVM, in the following commit. checkpatch reported below warnings with this change that I believe don't apply in this case: include/linux/static_call.h:219: WARNING: Non-declarative macros with mul= tiple statements should be enclosed in a do - while loop include/linux/static_call.h:220: WARNING: EXPORT_SYMBOL(foo); should imme= diately follow its function/variable Suggested-by: Peter Zijlstra Signed-off-by: Pawan Gupta --- include/linux/static_call.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/include/linux/static_call.h b/include/linux/static_call.h index 78a77a4ae0ea..b610afd1ed55 100644 --- a/include/linux/static_call.h +++ b/include/linux/static_call.h @@ -216,6 +216,9 @@ extern long __static_call_return0(void); #define EXPORT_STATIC_CALL_GPL(name) \ EXPORT_SYMBOL_GPL(STATIC_CALL_KEY(name)); \ EXPORT_SYMBOL_GPL(STATIC_CALL_TRAMP(name)) +#define EXPORT_STATIC_CALL_FOR_MODULES(name, mods) \ + EXPORT_SYMBOL_FOR_MODULES(STATIC_CALL_KEY(name), mods); \ + EXPORT_SYMBOL_FOR_MODULES(STATIC_CALL_TRAMP(name), mods) =20 /* Leave the key unexported, so modules can't change static call targets: = */ #define EXPORT_STATIC_CALL_TRAMP(name) \ @@ -276,6 +279,9 @@ extern long __static_call_return0(void); #define EXPORT_STATIC_CALL_GPL(name) \ EXPORT_SYMBOL_GPL(STATIC_CALL_KEY(name)); \ EXPORT_SYMBOL_GPL(STATIC_CALL_TRAMP(name)) +#define EXPORT_STATIC_CALL_FOR_MODULES(name, mods) \ + EXPORT_SYMBOL_FOR_MODULES(STATIC_CALL_KEY(name), mods); \ + EXPORT_SYMBOL_FOR_MODULES(STATIC_CALL_TRAMP(name), mods) =20 /* Leave the key unexported, so modules can't change static call targets: = */ #define EXPORT_STATIC_CALL_TRAMP(name) \ @@ -346,6 +352,8 @@ static inline int static_call_text_reserved(void *start= , void *end) =20 #define EXPORT_STATIC_CALL(name) EXPORT_SYMBOL(STATIC_CALL_KEY(name)) #define EXPORT_STATIC_CALL_GPL(name) EXPORT_SYMBOL_GPL(STATIC_CALL_KEY(nam= e)) +#define EXPORT_STATIC_CALL_FOR_MODULES(name, mods) \ + EXPORT_SYMBOL_FOR_MODULES(STATIC_CALL_KEY(name), mods) =20 #endif /* CONFIG_HAVE_STATIC_CALL */ =20 --=20 2.34.1 From nobody Tue Apr 14 13:59:22 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 34E7D36EA99; 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a="77279752" X-IronPort-AV: E=Sophos;i="6.23,179,1770624000"; d="scan'208";a="77279752" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Apr 2026 00:07:23 -0700 X-CSE-ConnectionGUID: KWGZfSwARvKo4geOUIPkKA== X-CSE-MsgGUID: j3Be09BiRdyShxoi7H87AA== X-ExtLoop1: 1 Received: from guptapa-desk.jf.intel.com (HELO desk) ([10.165.239.46]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Apr 2026 00:07:21 -0700 Date: Tue, 14 Apr 2026 00:07:21 -0700 From: Pawan Gupta To: x86@kernel.org, Jon Kohler , Nikolay Borisov , "H. Peter Anvin" , Josh Poimboeuf , David Kaplan , Sean Christopherson , Borislav Petkov , Dave Hansen , Peter Zijlstra , Alexei Starovoitov , Daniel Borkmann , Andrii Nakryiko , KP Singh , Jiri Olsa , "David S. Miller" , David Laight , Andy Lutomirski , Thomas Gleixner , Ingo Molnar , David Ahern , Martin KaFai Lau , Eduard Zingerman , Song Liu , Yonghong Song , John Fastabend , Stanislav Fomichev , Hao Luo , Paolo Bonzini , Jonathan Corbet Cc: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, Asit Mallick , Tao Zhang , bpf@vger.kernel.org, netdev@vger.kernel.org, linux-doc@vger.kernel.org Subject: [PATCH v10 08/12] kvm: Define EXPORT_STATIC_CALL_FOR_KVM() Message-ID: <20260414-vmscape-bhb-v10-8-efa924abae5f@linux.intel.com> X-Mailer: b4 0.16-dev References: <20260414-vmscape-bhb-v10-0-efa924abae5f@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20260414-vmscape-bhb-v10-0-efa924abae5f@linux.intel.com> Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" EXPORT_SYMBOL_FOR_KVM() exists to export symbols to KVM modules. Static calls need the same treatment when the core kernel defines a static_call that KVM needs access to (e.g. from a VM-exit path). Define EXPORT_STATIC_CALL_FOR_KVM() as the static_call analogue of EXPORT_SYMBOL_FOR_KVM(). The same three-way logic applies: - KVM_SUB_MODULES defined: export to "kvm," plus all sub-modules - KVM=3Dm, no sub-modules: export to "kvm" only - KVM built-in: no export needed (noop) As with EXPORT_SYMBOL_FOR_KVM(), allow architectures to override the definition (e.g. to suppress the export when kvm.ko itself will not be built despite CONFIG_KVM=3Dm). Add the x86 no-op override in arch/x86/include/asm/kvm_types.h for that case. Signed-off-by: Pawan Gupta --- arch/x86/include/asm/kvm_types.h | 1 + include/linux/kvm_types.h | 13 ++++++++++++- 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/kvm_types.h b/arch/x86/include/asm/kvm_ty= pes.h index d7c704ed1be9..bceeaed2940e 100644 --- a/arch/x86/include/asm/kvm_types.h +++ b/arch/x86/include/asm/kvm_types.h @@ -15,6 +15,7 @@ * at least one vendor module is enabled. */ #define EXPORT_SYMBOL_FOR_KVM(symbol) +#define EXPORT_STATIC_CALL_FOR_KVM(symbol) #endif =20 #define KVM_ARCH_NR_OBJS_PER_MEMORY_CACHE 40 diff --git a/include/linux/kvm_types.h b/include/linux/kvm_types.h index a568d8e6f4e8..c81f4fdba625 100644 --- a/include/linux/kvm_types.h +++ b/include/linux/kvm_types.h @@ -13,6 +13,8 @@ EXPORT_SYMBOL_FOR_MODULES(symbol, __stringify(KVM_SUB_MODULES)) #define EXPORT_SYMBOL_FOR_KVM(symbol) \ EXPORT_SYMBOL_FOR_MODULES(symbol, "kvm," __stringify(KVM_SUB_MODULES)) +#define EXPORT_STATIC_CALL_FOR_KVM(symbol) \ + EXPORT_STATIC_CALL_FOR_MODULES(symbol, "kvm," __stringify(KVM_SUB_MODULES= )) #else #define EXPORT_SYMBOL_FOR_KVM_INTERNAL(symbol) /* @@ -27,7 +29,16 @@ #define EXPORT_SYMBOL_FOR_KVM(symbol) #endif /* IS_MODULE(CONFIG_KVM) */ #endif /* EXPORT_SYMBOL_FOR_KVM */ -#endif + +#ifndef EXPORT_STATIC_CALL_FOR_KVM +#if IS_MODULE(CONFIG_KVM) +#define EXPORT_STATIC_CALL_FOR_KVM(symbol) EXPORT_STATIC_CALL_FOR_MODULES(= symbol, "kvm") +#else +#define EXPORT_STATIC_CALL_FOR_KVM(symbol) +#endif /* IS_MODULE(CONFIG_KVM) */ +#endif /* EXPORT_STATIC_CALL_FOR_KVM */ + +#endif /* KVM_SUB_MODULES */ =20 #ifndef __ASSEMBLER__ =20 --=20 2.34.1 From nobody Tue Apr 14 13:59:22 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DEF8B370D4A; Tue, 14 Apr 2026 07:08:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.17 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776150508; cv=none; b=c5ujsxUAgjtg/3ifos566k/jKCu6GzeZ7W+Xf/IXnxsH7GMCrkJFIEPzKaTZFISJpXhnkO2HjU0slM5MbrVFrup8ZiRvh6ytME6WCnFYmtS8bZg7XTWQDDjaeoQ4rESWrpxfGB7zg1zTncRBJGnbOfDurgrnn1NzxkWfu6rHPxQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776150508; c=relaxed/simple; bh=TiGR7oSMWc+vxJbVB4aoRASQSlIRQ7cOJfWWR4hvCvk=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=LVRxs4WVFjKNBWGeVNDRgbUd5KU0vFHpBHerYbd9ORjceTXe8NHAy+vwVCYkd/UI+NiwbrT1whmaIFNTNfNj+WBYm3tgRqWTNXRt31NnNQiAvL/hesyXxgoCV9Omio+ZbxEf90lihTXb8l2RLtAN4wOC0bqu6kISHo9dBRqY/yA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=NgX7mgCn; arc=none smtp.client-ip=192.198.163.17 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="NgX7mgCn" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1776150507; x=1807686507; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=TiGR7oSMWc+vxJbVB4aoRASQSlIRQ7cOJfWWR4hvCvk=; b=NgX7mgCntZEO3cbWiZrNDvu3UHq1g8gSmnYU2imFKNkgn6sF7/nvfL3z Q5IeIRMQfAMUlBlXhX58HN3MnDdfFTdrjxPD9kduCYumMK/VJjMGeKs4j K9mZMXo6NPbHi2f5se724bzulizuX3iuKCmBL2z4QDljOh4CftQ84JVNw s91RfJZlyYhQIdkeQQMk8GFruiGpx+eTyoLu2UF7xY2/2JxWV7sx7tdAZ aRP4+c8qWlpQf4BcqClSTpl9+0L2KXOuUhXfB5Pac7wt/bQ8zRymE0/m0 b5T70faYONgedza1WOwqPzmjC5oO6omkV2U0xBHNbxeoKNR4iegYdCSQG w==; X-CSE-ConnectionGUID: Sfga65eYQP6nKbKhjZ4JBw== X-CSE-MsgGUID: HqNGBzDLSUmgPNSu2xN51w== X-IronPort-AV: E=McAfee;i="6800,10657,11758"; a="76980613" X-IronPort-AV: E=Sophos;i="6.23,179,1770624000"; d="scan'208";a="76980613" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by fmvoesa111.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Apr 2026 00:07:39 -0700 X-CSE-ConnectionGUID: e+a2QMyjTxOF30uB72og0A== X-CSE-MsgGUID: zU8k0K7aTmOgN83Ivehbzg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,179,1770624000"; d="scan'208";a="228974739" Received: from guptapa-desk.jf.intel.com (HELO desk) ([10.165.239.46]) by orviesa006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Apr 2026 00:07:37 -0700 Date: Tue, 14 Apr 2026 00:07:37 -0700 From: Pawan Gupta To: x86@kernel.org, Jon Kohler , Nikolay Borisov , "H. Peter Anvin" , Josh Poimboeuf , David Kaplan , Sean Christopherson , Borislav Petkov , Dave Hansen , Peter Zijlstra , Alexei Starovoitov , Daniel Borkmann , Andrii Nakryiko , KP Singh , Jiri Olsa , "David S. Miller" , David Laight , Andy Lutomirski , Thomas Gleixner , Ingo Molnar , David Ahern , Martin KaFai Lau , Eduard Zingerman , Song Liu , Yonghong Song , John Fastabend , Stanislav Fomichev , Hao Luo , Paolo Bonzini , Jonathan Corbet Cc: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, Asit Mallick , Tao Zhang , bpf@vger.kernel.org, netdev@vger.kernel.org, linux-doc@vger.kernel.org Subject: [PATCH v10 09/12] x86/vmscape: Use static_call() for predictor flush Message-ID: <20260414-vmscape-bhb-v10-9-efa924abae5f@linux.intel.com> X-Mailer: b4 0.16-dev References: <20260414-vmscape-bhb-v10-0-efa924abae5f@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20260414-vmscape-bhb-v10-0-efa924abae5f@linux.intel.com> Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Adding more mitigation options at exit-to-userspace for VMSCAPE would usually require a series of checks to decide which mitigation to use. In this case, the mitigation is done by calling a function, which is decided at boot. So, adding more feature flags and multiple checks can be avoided by using static_call() to the mitigating function. Replace the flag-based mitigation selector with a static_call(). This also frees the existing X86_FEATURE_IBPB_EXIT_TO_USER. Suggested-by: Dave Hansen Tested-by: Jon Kohler Signed-off-by: Pawan Gupta --- arch/x86/Kconfig | 1 + arch/x86/include/asm/cpufeatures.h | 2 +- arch/x86/include/asm/entry-common.h | 7 +++---- arch/x86/include/asm/nospec-branch.h | 3 +++ arch/x86/kernel/cpu/bugs.c | 9 ++++++++- arch/x86/kvm/x86.c | 2 +- 6 files changed, 17 insertions(+), 7 deletions(-) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index e2df1b147184..5b8def9ddb98 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -2720,6 +2720,7 @@ config MITIGATION_TSA config MITIGATION_VMSCAPE bool "Mitigate VMSCAPE" depends on KVM + depends on HAVE_STATIC_CALL default y help Enable mitigation for VMSCAPE attacks. VMSCAPE is a hardware security diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpuf= eatures.h index dbe104df339b..b4d529dd6d30 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -503,7 +503,7 @@ #define X86_FEATURE_TSA_SQ_NO (21*32+11) /* AMD CPU not vulnerable to TSA= -SQ */ #define X86_FEATURE_TSA_L1_NO (21*32+12) /* AMD CPU not vulnerable to TSA= -L1 */ #define X86_FEATURE_CLEAR_CPU_BUF_VM (21*32+13) /* Clear CPU buffers using= VERW before VMRUN */ -#define X86_FEATURE_IBPB_EXIT_TO_USER (21*32+14) /* Use IBPB on exit-to-us= erspace, see VMSCAPE bug */ +/* Free */ #define X86_FEATURE_ABMC (21*32+15) /* Assignable Bandwidth Monitoring Co= unters */ #define X86_FEATURE_MSR_IMM (21*32+16) /* MSR immediate form instructions= */ #define X86_FEATURE_SGX_EUPDATESVN (21*32+17) /* Support for ENCLS[EUPDATE= SVN] instruction */ diff --git a/arch/x86/include/asm/entry-common.h b/arch/x86/include/asm/ent= ry-common.h index 78b143673ca7..783e7cb50cae 100644 --- a/arch/x86/include/asm/entry-common.h +++ b/arch/x86/include/asm/entry-common.h @@ -4,6 +4,7 @@ =20 #include #include +#include =20 #include #include @@ -94,10 +95,8 @@ static inline void arch_exit_to_user_mode_prepare(struct= pt_regs *regs, */ choose_random_kstack_offset(rdtsc()); =20 - /* Avoid unnecessary reads of 'x86_predictor_flush_exit_to_user' */ - if (cpu_feature_enabled(X86_FEATURE_IBPB_EXIT_TO_USER) && - this_cpu_read(x86_predictor_flush_exit_to_user)) { - write_ibpb(); + if (unlikely(this_cpu_read(x86_predictor_flush_exit_to_user))) { + static_call_cond(vmscape_predictor_flush)(); this_cpu_write(x86_predictor_flush_exit_to_user, false); } } diff --git a/arch/x86/include/asm/nospec-branch.h b/arch/x86/include/asm/no= spec-branch.h index 0381db59c39d..066fd8095200 100644 --- a/arch/x86/include/asm/nospec-branch.h +++ b/arch/x86/include/asm/nospec-branch.h @@ -542,6 +542,9 @@ static inline void indirect_branch_prediction_barrier(v= oid) :: "rax", "rcx", "rdx", "memory"); } =20 +#include +DECLARE_STATIC_CALL(vmscape_predictor_flush, write_ibpb); + /* The Intel SPEC CTRL MSR base value cache */ extern u64 x86_spec_ctrl_base; DECLARE_PER_CPU(u64, x86_spec_ctrl_current); diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index 636280c612f0..bfc0e41697f6 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -144,6 +144,13 @@ EXPORT_SYMBOL_GPL(cpu_buf_idle_clear); */ DEFINE_STATIC_KEY_FALSE(switch_mm_cond_l1d_flush); =20 +/* + * Controls how vmscape is mitigated e.g. via IBPB or BHB-clear + * sequence. This defaults to no mitigation. + */ +DEFINE_STATIC_CALL_NULL(vmscape_predictor_flush, write_ibpb); +EXPORT_STATIC_CALL_FOR_KVM(vmscape_predictor_flush); + #undef pr_fmt #define pr_fmt(fmt) "mitigations: " fmt =20 @@ -3133,7 +3140,7 @@ static void __init vmscape_update_mitigation(void) static void __init vmscape_apply_mitigation(void) { if (vmscape_mitigation =3D=3D VMSCAPE_MITIGATION_IBPB_EXIT_TO_USER) - setup_force_cpu_cap(X86_FEATURE_IBPB_EXIT_TO_USER); + static_call_update(vmscape_predictor_flush, write_ibpb); } =20 #undef pr_fmt diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 45d7cfedc507..5582056b2fa1 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -11463,7 +11463,7 @@ static int vcpu_enter_guest(struct kvm_vcpu *vcpu) * set for the CPU that actually ran the guest, and not the CPU that it * may migrate to. */ - if (cpu_feature_enabled(X86_FEATURE_IBPB_EXIT_TO_USER)) + if (static_call_query(vmscape_predictor_flush)) this_cpu_write(x86_predictor_flush_exit_to_user, true); =20 /* --=20 2.34.1 From nobody Tue Apr 14 13:59:22 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1104437105A; Tue, 14 Apr 2026 07:08:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.17 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776150510; cv=none; b=mGKcUM6TvthVk6i9z1QmLLevGUvPxJpx+FcjL8jm9YT8wXrWOTAn6myYBj8PaXpJQv6+P3CkDZEflprlhlT6//R33GARTYaVm8JMHeQ4ZMjGLMNQyF15Rq8MuPRkAe45VeJKgf5sHDClK6pZNos57acTKPikFt45DzQz1TfqpEE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776150510; c=relaxed/simple; bh=/5skwiH0gY1oo5ieSmlZoXl/fkBIevmFUlNqtPJTLYQ=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=bfpE0TnT399DmHjXerXlZOAheCge9J0yckQ2vIfPbRz2iTgFP5Ykw0rEaQmyZYvqj5KgUZUbsYjIMJO9H03e9VBMVYNd1YIhR3HtT5PB2DrMPTaqwMeX9G2aUoj8LfBVoFINQJxgfF+lYNNRR8JCJYgSVmDtlx65r6WNxQzrtl0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=X9Zqw883; arc=none smtp.client-ip=192.198.163.17 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="X9Zqw883" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1776150509; x=1807686509; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=/5skwiH0gY1oo5ieSmlZoXl/fkBIevmFUlNqtPJTLYQ=; b=X9Zqw883afLHSZh5WW8T+TCUHQ2tJN4DN2/nhPLeebwlrqYNsdIN7n1z Tn6xzsilMBYx+7s5xF7rhXLJvRlhvrtWeY5rUrdJSb6dpeSeqORc6Zt4n GAJaHYWNI0xafUmZKUIMxiFGovKUdneN4x1MDIYYm9JWxZA0BjrBCcRSS 42+h+qNkKRIYSam1P8RGZj2ZBqsGQH+uPYlJpwOckw4TE5Ugj4CEUOzq4 sFL8Ebj4jf5R5adOhg/HG3qK4zq8FYftuc6rjX8ARRFV+74xf2iycAPYy /GoGXLjz/u2o2VZ92X4ntIRGlyw9AfjNNYLaN28blALF6BKhevWkpQmYu Q==; X-CSE-ConnectionGUID: 1DqyMwXeT1mvwN60ivhVOg== X-CSE-MsgGUID: GbewHZsgR2GH1YKuT8pk5g== X-IronPort-AV: E=McAfee;i="6800,10657,11758"; a="76980649" X-IronPort-AV: E=Sophos;i="6.23,179,1770624000"; d="scan'208";a="76980649" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by fmvoesa111.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Apr 2026 00:07:54 -0700 X-CSE-ConnectionGUID: wf/gjug8TzOgiJchL76yQQ== X-CSE-MsgGUID: oraOJ9/jS3OmjTimA9Yr/g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,179,1770624000"; d="scan'208";a="228974882" Received: from guptapa-desk.jf.intel.com (HELO desk) ([10.165.239.46]) by orviesa006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Apr 2026 00:07:52 -0700 Date: Tue, 14 Apr 2026 00:07:52 -0700 From: Pawan Gupta To: x86@kernel.org, Jon Kohler , Nikolay Borisov , "H. Peter Anvin" , Josh Poimboeuf , David Kaplan , Sean Christopherson , Borislav Petkov , Dave Hansen , Peter Zijlstra , Alexei Starovoitov , Daniel Borkmann , Andrii Nakryiko , KP Singh , Jiri Olsa , "David S. Miller" , David Laight , Andy Lutomirski , Thomas Gleixner , Ingo Molnar , David Ahern , Martin KaFai Lau , Eduard Zingerman , Song Liu , Yonghong Song , John Fastabend , Stanislav Fomichev , Hao Luo , Paolo Bonzini , Jonathan Corbet Cc: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, Asit Mallick , Tao Zhang , bpf@vger.kernel.org, netdev@vger.kernel.org, linux-doc@vger.kernel.org Subject: [PATCH v10 10/12] x86/vmscape: Deploy BHB clearing mitigation Message-ID: <20260414-vmscape-bhb-v10-10-efa924abae5f@linux.intel.com> X-Mailer: b4 0.16-dev References: <20260414-vmscape-bhb-v10-0-efa924abae5f@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20260414-vmscape-bhb-v10-0-efa924abae5f@linux.intel.com> Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" IBPB mitigation for VMSCAPE is an overkill on CPUs that are only affected by the BHI variant of VMSCAPE. On such CPUs, eIBRS already provides indirect branch isolation between guest and host userspace. However, branch history from guest may also influence the indirect branches in host userspace. To mitigate the BHI aspect, use the BHB clearing sequence. Since now, IBPB is not the only mitigation for VMSCAPE, update the documentation to reflect that =3Dauto could select either IBPB or BHB clear mitigation based on the CPU. Reviewed-by: Nikolay Borisov Tested-by: Jon Kohler Signed-off-by: Pawan Gupta --- Documentation/admin-guide/hw-vuln/vmscape.rst | 11 ++++++++- Documentation/admin-guide/kernel-parameters.txt | 4 +++- arch/x86/include/asm/entry-common.h | 4 ++++ arch/x86/include/asm/nospec-branch.h | 2 ++ arch/x86/kernel/cpu/bugs.c | 30 +++++++++++++++++++--= ---- 5 files changed, 42 insertions(+), 9 deletions(-) diff --git a/Documentation/admin-guide/hw-vuln/vmscape.rst b/Documentation/= admin-guide/hw-vuln/vmscape.rst index d9b9a2b6c114..7c40cf70ad7a 100644 --- a/Documentation/admin-guide/hw-vuln/vmscape.rst +++ b/Documentation/admin-guide/hw-vuln/vmscape.rst @@ -86,6 +86,10 @@ The possible values in this file are: run a potentially malicious guest and issues an IBPB before the first exit to userspace after VM-exit. =20 + * 'Mitigation: Clear BHB before exit to userspace': + + As above, conditional BHB clearing mitigation is enabled. + * 'Mitigation: IBPB on VMEXIT': =20 IBPB is issued on every VM-exit. This occurs when other mitigations like @@ -102,9 +106,14 @@ The mitigation can be controlled via the ``vmscape=3D`= ` command line parameter: =20 * ``vmscape=3Dibpb``: =20 - Enable conditional IBPB mitigation (default when CONFIG_MITIGATION_VMSC= APE=3Dy). + Enable conditional IBPB mitigation. =20 * ``vmscape=3Dforce``: =20 Force vulnerability detection and mitigation even on processors that are not known to be affected. + + * ``vmscape=3Dauto``: + + Choose the mitigation based on the VMSCAPE variant the CPU is affected = by. + (default when CONFIG_MITIGATION_VMSCAPE=3Dy) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentatio= n/admin-guide/kernel-parameters.txt index 03a550630644..3853c7109419 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -8378,9 +8378,11 @@ Kernel parameters =20 off - disable the mitigation ibpb - use Indirect Branch Prediction Barrier - (IBPB) mitigation (default) + (IBPB) mitigation force - force vulnerability detection even on unaffected processors + auto - (default) use IBPB or BHB clear + mitigation based on CPU =20 vsyscall=3D [X86-64,EARLY] Controls the behavior of vsyscalls (i.e. calls to diff --git a/arch/x86/include/asm/entry-common.h b/arch/x86/include/asm/ent= ry-common.h index 783e7cb50cae..13db31472f3a 100644 --- a/arch/x86/include/asm/entry-common.h +++ b/arch/x86/include/asm/entry-common.h @@ -96,6 +96,10 @@ static inline void arch_exit_to_user_mode_prepare(struct= pt_regs *regs, choose_random_kstack_offset(rdtsc()); =20 if (unlikely(this_cpu_read(x86_predictor_flush_exit_to_user))) { + /* + * Since the mitigation is for userspace, an explicit + * speculation barrier is not required after flush. + */ static_call_cond(vmscape_predictor_flush)(); this_cpu_write(x86_predictor_flush_exit_to_user, false); } diff --git a/arch/x86/include/asm/nospec-branch.h b/arch/x86/include/asm/no= spec-branch.h index 066fd8095200..38478383139b 100644 --- a/arch/x86/include/asm/nospec-branch.h +++ b/arch/x86/include/asm/nospec-branch.h @@ -390,6 +390,8 @@ extern void write_ibpb(void); =20 #ifdef CONFIG_X86_64 extern void clear_bhb_loop_nofence(void); +#else +static inline void clear_bhb_loop_nofence(void) {} #endif =20 extern void (*x86_return_thunk)(void); diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index bfc0e41697f6..1082ed1fb2e6 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -61,9 +61,8 @@ DEFINE_PER_CPU(u64, x86_spec_ctrl_current); EXPORT_PER_CPU_SYMBOL_GPL(x86_spec_ctrl_current); =20 /* - * Set when the CPU has run a potentially malicious guest. An IBPB will - * be needed to before running userspace. That IBPB will flush the branch - * predictor content. + * Set when the CPU has run a potentially malicious guest. Indicates that a + * branch predictor flush is needed before running userspace. */ DEFINE_PER_CPU(bool, x86_predictor_flush_exit_to_user); EXPORT_PER_CPU_SYMBOL_GPL(x86_predictor_flush_exit_to_user); @@ -3061,13 +3060,15 @@ enum vmscape_mitigations { VMSCAPE_MITIGATION_AUTO, VMSCAPE_MITIGATION_IBPB_EXIT_TO_USER, VMSCAPE_MITIGATION_IBPB_ON_VMEXIT, + VMSCAPE_MITIGATION_BHB_CLEAR_EXIT_TO_USER, }; =20 static const char * const vmscape_strings[] =3D { - [VMSCAPE_MITIGATION_NONE] =3D "Vulnerable", + [VMSCAPE_MITIGATION_NONE] =3D "Vulnerable", /* [VMSCAPE_MITIGATION_AUTO] */ - [VMSCAPE_MITIGATION_IBPB_EXIT_TO_USER] =3D "Mitigation: IBPB before exit = to userspace", - [VMSCAPE_MITIGATION_IBPB_ON_VMEXIT] =3D "Mitigation: IBPB on VMEXIT", + [VMSCAPE_MITIGATION_IBPB_EXIT_TO_USER] =3D "Mitigation: IBPB before exit= to userspace", + [VMSCAPE_MITIGATION_IBPB_ON_VMEXIT] =3D "Mitigation: IBPB on VMEXIT", + [VMSCAPE_MITIGATION_BHB_CLEAR_EXIT_TO_USER] =3D "Mitigation: Clear BHB be= fore exit to userspace", }; =20 static enum vmscape_mitigations vmscape_mitigation __ro_after_init =3D @@ -3085,6 +3086,8 @@ static int __init vmscape_parse_cmdline(char *str) } else if (!strcmp(str, "force")) { setup_force_cpu_bug(X86_BUG_VMSCAPE); vmscape_mitigation =3D VMSCAPE_MITIGATION_AUTO; + } else if (!strcmp(str, "auto")) { + vmscape_mitigation =3D VMSCAPE_MITIGATION_AUTO; } else { pr_err("Ignoring unknown vmscape=3D%s option.\n", str); } @@ -3114,7 +3117,17 @@ static void __init vmscape_select_mitigation(void) break; =20 case VMSCAPE_MITIGATION_AUTO: - if (boot_cpu_has(X86_FEATURE_IBPB)) + /* + * CPUs with BHI_CTRL(ADL and newer) can avoid the IBPB and use + * BHB clear sequence. These CPUs are only vulnerable to the BHI + * variant of the VMSCAPE attack, and thus they do not require a + * full predictor flush. + * + * Note, in 32-bit mode BHB clear sequence is not supported. + */ + if (boot_cpu_has(X86_FEATURE_BHI_CTRL) && IS_ENABLED(CONFIG_X86_64)) + vmscape_mitigation =3D VMSCAPE_MITIGATION_BHB_CLEAR_EXIT_TO_USER; + else if (boot_cpu_has(X86_FEATURE_IBPB)) vmscape_mitigation =3D VMSCAPE_MITIGATION_IBPB_EXIT_TO_USER; else vmscape_mitigation =3D VMSCAPE_MITIGATION_NONE; @@ -3141,6 +3154,8 @@ static void __init vmscape_apply_mitigation(void) { if (vmscape_mitigation =3D=3D VMSCAPE_MITIGATION_IBPB_EXIT_TO_USER) static_call_update(vmscape_predictor_flush, write_ibpb); + else if (vmscape_mitigation =3D=3D VMSCAPE_MITIGATION_BHB_CLEAR_EXIT_TO_U= SER) + static_call_update(vmscape_predictor_flush, clear_bhb_loop_nofence); } =20 #undef pr_fmt @@ -3232,6 +3247,7 @@ void cpu_bugs_smt_update(void) break; case VMSCAPE_MITIGATION_IBPB_ON_VMEXIT: case VMSCAPE_MITIGATION_IBPB_EXIT_TO_USER: + case VMSCAPE_MITIGATION_BHB_CLEAR_EXIT_TO_USER: /* * Hypervisors can be attacked across-threads, warn for SMT when * STIBP is not already enabled system-wide. --=20 2.34.1 From nobody Tue Apr 14 13:59:22 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 93DFB35FF57; Tue, 14 Apr 2026 07:08:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776150490; cv=none; b=lH+g2Qf30cs84fww0Z/KxZqhM7hnQhDJQtfOIb1n7DeFwB+KYyefavKeahnmWxiufjIYyoIc5x0sMwyifctPB6TFkb+dyERVApz8juW61GUnVAhkXAlEZ4dpT0KvmCMx9D5LxopAGJM/0IQgnItPr6sMeHkV4filSqVqeMkCJkg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776150490; c=relaxed/simple; bh=6gK4EmiJjoxMBErZvB2QlG52OKl4TSLVAd68WmRFl3s=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=t9nQnXQJ65cY2YqMk619cwdvaaEAKWW3o88lyZaqMsKr5/SMjv83RsrnA6ldSW+NipZ0bxMW19reXH7hM2VJsBLirhYfxIKhSNllC13UEatnYX17sur38ztDgdbicOKDgwNMVvPz0/xhlsPxQQdqQRhykD1Noa5IltXPLcFlQgc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=AQLSFzLd; arc=none smtp.client-ip=192.198.163.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="AQLSFzLd" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1776150488; x=1807686488; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=6gK4EmiJjoxMBErZvB2QlG52OKl4TSLVAd68WmRFl3s=; b=AQLSFzLdmdWaWw2tR8tjzBrpo2tN82CeK9/QF+Ox59NsXwK1Lmg67bOt VjL4UbYGo5qvMZvYK13YSE142L4XBUIzKw1shKHncPIXKu3AbhW7qiWhQ /2ps/s9KrRRPWe8rTP8UdHPdMDpXzd5+tvRzq4st5cjvu84HAB28v7wxD JNcRS0UMKOO1UayixB1SoMTvHEvuSnKF6b3EagpEa7StpYeC0KZlRgFMN IM9XNdZq9FOI+4V5rWaVOjxM2NymdmU5MFZ7pUzCDrTL9xHfUHsjX58kE GisvJxaAjmd02pQ+R9foF+RLAAMcfhFDxx3vjtmyyiQk8zdO34VINbgt4 A==; X-CSE-ConnectionGUID: EI4OJlwzQGyKqmCpx6jsYw== X-CSE-MsgGUID: Nnj2sNKdT0u9vFgfj72utw== X-IronPort-AV: E=McAfee;i="6800,10657,11758"; a="80983572" X-IronPort-AV: E=Sophos;i="6.23,179,1770624000"; d="scan'208";a="80983572" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Apr 2026 00:08:08 -0700 X-CSE-ConnectionGUID: qe1Tj7DpR1GMXevU9CZkkQ== X-CSE-MsgGUID: y4GmX7THR3O6YrFvtFcK5Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,179,1770624000"; d="scan'208";a="260430933" Received: from guptapa-desk.jf.intel.com (HELO desk) ([10.165.239.46]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Apr 2026 00:08:08 -0700 Date: Tue, 14 Apr 2026 00:08:07 -0700 From: Pawan Gupta To: x86@kernel.org, Jon Kohler , Nikolay Borisov , "H. Peter Anvin" , Josh Poimboeuf , David Kaplan , Sean Christopherson , Borislav Petkov , Dave Hansen , Peter Zijlstra , Alexei Starovoitov , Daniel Borkmann , Andrii Nakryiko , KP Singh , Jiri Olsa , "David S. Miller" , David Laight , Andy Lutomirski , Thomas Gleixner , Ingo Molnar , David Ahern , Martin KaFai Lau , Eduard Zingerman , Song Liu , Yonghong Song , John Fastabend , Stanislav Fomichev , Hao Luo , Paolo Bonzini , Jonathan Corbet Cc: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, Asit Mallick , Tao Zhang , bpf@vger.kernel.org, netdev@vger.kernel.org, linux-doc@vger.kernel.org Subject: [PATCH v10 11/12] x86/vmscape: Resolve conflict between attack-vectors and vmscape=force Message-ID: <20260414-vmscape-bhb-v10-11-efa924abae5f@linux.intel.com> X-Mailer: b4 0.16-dev References: <20260414-vmscape-bhb-v10-0-efa924abae5f@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20260414-vmscape-bhb-v10-0-efa924abae5f@linux.intel.com> Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" vmscape=3Dforce option currently defaults to AUTO mitigation. This lets attack-vector controls to override the vmscape mitigation. Preventing the user from being able to force VMSCAPE mitigation. When vmscape mitigation is forced, allow it be deployed irrespective of attack vectors. Introduce VMSCAPE_MITIGATION_ON that wins over attack-vector controls. Tested-by: Jon Kohler Reviewed-by: Nikolay Borisov Signed-off-by: Pawan Gupta --- arch/x86/kernel/cpu/bugs.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index 1082ed1fb2e6..fbdb137720c4 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -3058,6 +3058,7 @@ static void __init srso_apply_mitigation(void) enum vmscape_mitigations { VMSCAPE_MITIGATION_NONE, VMSCAPE_MITIGATION_AUTO, + VMSCAPE_MITIGATION_ON, VMSCAPE_MITIGATION_IBPB_EXIT_TO_USER, VMSCAPE_MITIGATION_IBPB_ON_VMEXIT, VMSCAPE_MITIGATION_BHB_CLEAR_EXIT_TO_USER, @@ -3066,6 +3067,7 @@ enum vmscape_mitigations { static const char * const vmscape_strings[] =3D { [VMSCAPE_MITIGATION_NONE] =3D "Vulnerable", /* [VMSCAPE_MITIGATION_AUTO] */ + /* [VMSCAPE_MITIGATION_ON] */ [VMSCAPE_MITIGATION_IBPB_EXIT_TO_USER] =3D "Mitigation: IBPB before exit= to userspace", [VMSCAPE_MITIGATION_IBPB_ON_VMEXIT] =3D "Mitigation: IBPB on VMEXIT", [VMSCAPE_MITIGATION_BHB_CLEAR_EXIT_TO_USER] =3D "Mitigation: Clear BHB be= fore exit to userspace", @@ -3085,7 +3087,7 @@ static int __init vmscape_parse_cmdline(char *str) vmscape_mitigation =3D VMSCAPE_MITIGATION_IBPB_EXIT_TO_USER; } else if (!strcmp(str, "force")) { setup_force_cpu_bug(X86_BUG_VMSCAPE); - vmscape_mitigation =3D VMSCAPE_MITIGATION_AUTO; + vmscape_mitigation =3D VMSCAPE_MITIGATION_ON; } else if (!strcmp(str, "auto")) { vmscape_mitigation =3D VMSCAPE_MITIGATION_AUTO; } else { @@ -3117,6 +3119,7 @@ static void __init vmscape_select_mitigation(void) break; =20 case VMSCAPE_MITIGATION_AUTO: + case VMSCAPE_MITIGATION_ON: /* * CPUs with BHI_CTRL(ADL and newer) can avoid the IBPB and use * BHB clear sequence. These CPUs are only vulnerable to the BHI @@ -3244,6 +3247,7 @@ void cpu_bugs_smt_update(void) switch (vmscape_mitigation) { case VMSCAPE_MITIGATION_NONE: case VMSCAPE_MITIGATION_AUTO: + case VMSCAPE_MITIGATION_ON: break; case VMSCAPE_MITIGATION_IBPB_ON_VMEXIT: case VMSCAPE_MITIGATION_IBPB_EXIT_TO_USER: --=20 2.34.1 From nobody Tue Apr 14 13:59:22 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1BCE435C19D; Tue, 14 Apr 2026 07:08:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776150505; cv=none; b=CMmVCDuAOlW0UL9oCVvbhoIc1PNEFZpA/p01QPXcfY7LDzMfYzZdTereEtVHjlKcyZ6SM4MOn/adIhzSmhMrkhXn1+h2zG854edt9+qasla322mAFUSvIdpOd4CcoQb2uF0W9IDajiy+mJz3908gekdltQ+8+fHxcLXzg+RSGy4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776150505; c=relaxed/simple; bh=b6MuRVTf/ZgA9L22eiHzgpdsNzUtE5SipssmAjn0OuY=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=UVfhkwFq5Vf4s7giWcZgDrVjEIiQF349ElD/JALYojc2AiYGC/pktqtH3LyILX2UIzCx5N7NC3l9tmUVMSTJAWk0SjRNxFNAeQZNQXiXl+mICMCIqIo3ZGCfg8bdgYyUuIV+tCvtxnBQafpNpsBBrCXTyJV7vaDgVpCxBzfUjuw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=P8tSNWgM; arc=none smtp.client-ip=192.198.163.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="P8tSNWgM" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1776150504; x=1807686504; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=b6MuRVTf/ZgA9L22eiHzgpdsNzUtE5SipssmAjn0OuY=; b=P8tSNWgMYvEdUSbOvtvyWbGWHNkPBV42KoBE5O6Anr3YeYufxFfVTs0e v8M/XfwDzuazOQ5MIdiWGTrmMw2f7o6a0Q6ZZFcs8obqwaWH+OaisXdNs zyHL2LpDHq5bvFVrXKHQ7hWcMvMw+VSE5eWziiZcZxjryeo4xfmZtMpsn Msi3WdB5T/7+MF+f3LxYvBG2gy8xqbJhuxPQGal0mKADcJfEKmcfz0ZKg Mg5NW9ym7gz1LzXgCEPD7ldr/roIbNYcAJoaD8gJBvfJXin9PAg8PhhAN 32mhf/hQKAT1p9LU1pRE+QvWLHu+VR55vaEKcVtU9Q2VbPV2NdK0ZtsvN Q==; X-CSE-ConnectionGUID: NMRY7v9FQpmq7n0YQVktpg== X-CSE-MsgGUID: U0ssOPYOT52TndIdHSdD8Q== X-IronPort-AV: E=McAfee;i="6800,10657,11758"; a="80983622" X-IronPort-AV: E=Sophos;i="6.23,179,1770624000"; d="scan'208";a="80983622" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Apr 2026 00:08:23 -0700 X-CSE-ConnectionGUID: xTvYt0ysQf2QLw0aTex+Yg== X-CSE-MsgGUID: EWbHBLF3QeiWNViVG5/ctQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,179,1770624000"; d="scan'208";a="260430964" Received: from guptapa-desk.jf.intel.com (HELO desk) ([10.165.239.46]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Apr 2026 00:08:23 -0700 Date: Tue, 14 Apr 2026 00:08:22 -0700 From: Pawan Gupta To: x86@kernel.org, Jon Kohler , Nikolay Borisov , "H. Peter Anvin" , Josh Poimboeuf , David Kaplan , Sean Christopherson , Borislav Petkov , Dave Hansen , Peter Zijlstra , Alexei Starovoitov , Daniel Borkmann , Andrii Nakryiko , KP Singh , Jiri Olsa , "David S. Miller" , David Laight , Andy Lutomirski , Thomas Gleixner , Ingo Molnar , David Ahern , Martin KaFai Lau , Eduard Zingerman , Song Liu , Yonghong Song , John Fastabend , Stanislav Fomichev , Hao Luo , Paolo Bonzini , Jonathan Corbet Cc: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, Asit Mallick , Tao Zhang , bpf@vger.kernel.org, netdev@vger.kernel.org, linux-doc@vger.kernel.org Subject: [PATCH v10 12/12] x86/vmscape: Add cmdline vmscape=on to override attack vector controls Message-ID: <20260414-vmscape-bhb-v10-12-efa924abae5f@linux.intel.com> X-Mailer: b4 0.16-dev References: <20260414-vmscape-bhb-v10-0-efa924abae5f@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20260414-vmscape-bhb-v10-0-efa924abae5f@linux.intel.com> Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In general, individual mitigation knobs override the attack vector controls. For VMSCAPE, =3Dibpb exists but nothing to select BHB clearing mitigation. The =3Dforce option would select BHB clearing when supported, b= ut with a side-effect of also forcing the bug, hence deploying the mitigation on unaffected parts too. Add a new cmdline option vmscape=3Don to enable the mitigation based on the VMSCAPE variant the CPU is affected by. Reviewed-by: Nikolay Borisov Tested-by: Jon Kohler Signed-off-by: Pawan Gupta --- Documentation/admin-guide/hw-vuln/vmscape.rst | 4 ++++ Documentation/admin-guide/kernel-parameters.txt | 2 ++ arch/x86/kernel/cpu/bugs.c | 2 ++ 3 files changed, 8 insertions(+) diff --git a/Documentation/admin-guide/hw-vuln/vmscape.rst b/Documentation/= admin-guide/hw-vuln/vmscape.rst index 7c40cf70ad7a..2558a5c3d956 100644 --- a/Documentation/admin-guide/hw-vuln/vmscape.rst +++ b/Documentation/admin-guide/hw-vuln/vmscape.rst @@ -117,3 +117,7 @@ The mitigation can be controlled via the ``vmscape=3D``= command line parameter: =20 Choose the mitigation based on the VMSCAPE variant the CPU is affected = by. (default when CONFIG_MITIGATION_VMSCAPE=3Dy) + + * ``vmscape=3Don``: + + Same as ``auto``, except that it overrides attack vector controls. diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentatio= n/admin-guide/kernel-parameters.txt index 3853c7109419..98204d464477 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -8383,6 +8383,8 @@ Kernel parameters unaffected processors auto - (default) use IBPB or BHB clear mitigation based on CPU + on - same as "auto", but override attack + vector control =20 vsyscall=3D [X86-64,EARLY] Controls the behavior of vsyscalls (i.e. calls to diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index fbdb137720c4..4e0b77fb21dd 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -3088,6 +3088,8 @@ static int __init vmscape_parse_cmdline(char *str) } else if (!strcmp(str, "force")) { setup_force_cpu_bug(X86_BUG_VMSCAPE); vmscape_mitigation =3D VMSCAPE_MITIGATION_ON; + } else if (!strcmp(str, "on")) { + vmscape_mitigation =3D VMSCAPE_MITIGATION_ON; } else if (!strcmp(str, "auto")) { vmscape_mitigation =3D VMSCAPE_MITIGATION_AUTO; } else { --=20 2.34.1