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[93.143.58.160]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43d7400708dsm25595266f8f.25.2026.04.14.12.54.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Apr 2026 12:54:12 -0700 (PDT) From: =?utf-8?q?Duje_Mihanovi=C4=87?= Date: Tue, 14 Apr 2026 21:51:50 +0200 Subject: [PATCH 1/4] dt-bindings: clock: marvell,pxa1908: Add #reset-cells Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260414-pxa1908-clk-reset-v1-1-94bae5f3a8cf@dujemihanovic.xyz> References: <20260414-pxa1908-clk-reset-v1-0-94bae5f3a8cf@dujemihanovic.xyz> In-Reply-To: <20260414-pxa1908-clk-reset-v1-0-94bae5f3a8cf@dujemihanovic.xyz> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Karel Balej , linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, =?utf-8?q?Duje_Mihanovi=C4=87?= X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1567; i=duje@dujemihanovic.xyz; s=20260328; h=from:subject:message-id; bh=BP5R8FC0EJnxLApQpaXSZEWsmn62r66uFEV2C/KCEqY=; b=owGbwMvMwCW2z0j3+uHIyKOMp9WSGDLvzU5kk19Q6f9Oed3e5NN7fN78Vj66ocpzyxLjw5f5N 13f4P1NoaOUhUGMi0FWTJGFeancJb7U8IkORbZJMHNYmUCGMHBxCsBE7FwY/js+uC+51Ywjbtls 0RLNJ/tPm77RCL7zUDHs9ROV61LtRosYGdYUulnavbrP/MfxxR7m9bllPQqe8ltdp0RI6blrta6 exQUA X-Developer-Key: i=duje@dujemihanovic.xyz; a=openpgp; fpr=9BD463017690089DAA8DC266275F544B3B1B4792 From: Duje Mihanovi=C4=87 The APBC and APBCP controllers have reset lines exposed. Give them a #reset-cells so that they may be used as reset controllers. Signed-off-by: Duje Mihanovi=C4=87 Reviewed-by: Krzysztof Kozlowski --- .../devicetree/bindings/clock/marvell,pxa1908.yaml | 34 +++++++++++++++---= ---- 1 file changed, 24 insertions(+), 10 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/marvell,pxa1908.yaml b= /Documentation/devicetree/bindings/clock/marvell,pxa1908.yaml index 6f3a8578fe2a..0db5504013d5 100644 --- a/Documentation/devicetree/bindings/clock/marvell,pxa1908.yaml +++ b/Documentation/devicetree/bindings/clock/marvell,pxa1908.yaml @@ -37,6 +37,9 @@ properties: '#power-domain-cells': const: 1 =20 + '#reset-cells': + const: 1 + required: - compatible - reg @@ -44,16 +47,27 @@ required: =20 additionalProperties: false =20 -if: - not: - properties: - compatible: - contains: - const: marvell,pxa1908-apmu - -then: - properties: - '#power-domain-cells': false +allOf: + - if: + not: + properties: + compatible: + contains: + const: marvell,pxa1908-apmu + then: + properties: + '#power-domain-cells': false + - if: + not: + properties: + compatible: + contains: + enum: + - marvell,pxa1908-apbc + - marvell,pxa1908-apbcp + then: + properties: + '#reset-cells': false =20 examples: # APMU block: --=20 2.53.0 From nobody Sat Jun 20 14:16:12 2026 Received: from mail-wr1-f43.google.com (mail-wr1-f43.google.com [209.85.221.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D1B0A31F9BC for ; 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[93.143.58.160]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43d7400708dsm25595266f8f.25.2026.04.14.12.54.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Apr 2026 12:54:14 -0700 (PDT) From: =?utf-8?q?Duje_Mihanovi=C4=87?= Date: Tue, 14 Apr 2026 21:51:51 +0200 Subject: [PATCH 2/4] clk: mmp: pxa1908-apbc: Add reset cells Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260414-pxa1908-clk-reset-v1-2-94bae5f3a8cf@dujemihanovic.xyz> References: <20260414-pxa1908-clk-reset-v1-0-94bae5f3a8cf@dujemihanovic.xyz> In-Reply-To: <20260414-pxa1908-clk-reset-v1-0-94bae5f3a8cf@dujemihanovic.xyz> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Karel Balej , linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, =?utf-8?q?Duje_Mihanovi=C4=87?= X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=5428; i=duje@dujemihanovic.xyz; s=20260328; h=from:subject:message-id; bh=y12V/0MXZNM4V87Nu8AZ7/dxPVLqCzcuUl4Cuce0an4=; b=owGbwMvMwCW2z0j3+uHIyKOMp9WSGDLvzU589HF5hHZ6jMYS244ulq95DUmxvfesJ4gqdRiEV O9Y92pNRykLgxgXg6yYIgvzUrlLfKnhEx2KbJNg5rAygQxh4OIUgIkILmZk6JyutO+Th3oDh8DM UFUOYcsnV8q/Lao6OGvb3+O/9bm+LGdkuO2RvXP96akb7s5mWBW/UX9jyJ9zJep7N+yLW/Xod5T sSRYA X-Developer-Key: i=duje@dujemihanovic.xyz; a=openpgp; fpr=9BD463017690089DAA8DC266275F544B3B1B4792 From: Duje Mihanovi=C4=87 It has been concluded by comparing the gate clock masks and vendor code between PXA1908/28 that PXA1908's APBC, similarly to PXA1928's APBC, has controllable reset lines. Describe these in the driver for correctness. Signed-off-by: Duje Mihanovi=C4=87 --- drivers/clk/mmp/clk-pxa1908-apbc.c | 58 +++++++++++++++++++++++++++++-----= ---- 1 file changed, 44 insertions(+), 14 deletions(-) diff --git a/drivers/clk/mmp/clk-pxa1908-apbc.c b/drivers/clk/mmp/clk-pxa19= 08-apbc.c index 3fd7b5e644f3..438ece4f047d 100644 --- a/drivers/clk/mmp/clk-pxa1908-apbc.c +++ b/drivers/clk/mmp/clk-pxa1908-apbc.c @@ -7,6 +7,7 @@ #include =20 #include "clk.h" +#include "reset.h" =20 #define APBC_UART0 0x0 #define APBC_UART1 0x4 @@ -44,22 +45,25 @@ static const char * const uart_parent_names[] =3D {"pll= 1_117", "uart_pll"}; static const char * const ssp_parent_names[] =3D {"pll1_d16", "pll1_d48", = "pll1_d24", "pll1_d12"}; =20 static struct mmp_param_gate_clk apbc_gate_clks[] =3D { - {PXA1908_CLK_TWSI0, "twsi0_clk", "pll1_32", CLK_SET_RATE_PARENT, APBC_TWS= I0, 0x7, 3, 0, 0, NULL}, - {PXA1908_CLK_TWSI1, "twsi1_clk", "pll1_32", CLK_SET_RATE_PARENT, APBC_TWS= I1, 0x7, 3, 0, 0, NULL}, - {PXA1908_CLK_TWSI3, "twsi3_clk", "pll1_32", CLK_SET_RATE_PARENT, APBC_TWS= I3, 0x7, 3, 0, 0, NULL}, - {PXA1908_CLK_GPIO, "gpio_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_GPIO, = 0x7, 3, 0, 0, NULL}, - {PXA1908_CLK_KPC, "kpc_clk", "clk32", CLK_SET_RATE_PARENT, APBC_KPC, 0x7,= 3, 0, MMP_CLK_GATE_NEED_DELAY, NULL}, - {PXA1908_CLK_RTC, "rtc_clk", "clk32", CLK_SET_RATE_PARENT, APBC_RTC, 0x87= , 0x83, 0, MMP_CLK_GATE_NEED_DELAY, NULL}, + {PXA1908_CLK_TWSI0, "twsi0_clk", "pll1_32", CLK_SET_RATE_PARENT, APBC_TWS= I0, 0x3, 3, 0, 0, NULL}, + {PXA1908_CLK_TWSI1, "twsi1_clk", "pll1_32", CLK_SET_RATE_PARENT, APBC_TWS= I1, 0x3, 3, 0, 0, NULL}, + {PXA1908_CLK_TWSI3, "twsi3_clk", "pll1_32", CLK_SET_RATE_PARENT, APBC_TWS= I3, 0x3, 3, 0, 0, NULL}, + {PXA1908_CLK_GPIO, "gpio_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_GPIO, = 0x3, 3, 0, 0, NULL}, + {PXA1908_CLK_KPC, "kpc_clk", "clk32", CLK_SET_RATE_PARENT, APBC_KPC, 0x3,= 3, 0, MMP_CLK_GATE_NEED_DELAY, NULL}, + {PXA1908_CLK_RTC, "rtc_clk", "clk32", CLK_SET_RATE_PARENT, APBC_RTC, 0x83= , 0x83, 0, MMP_CLK_GATE_NEED_DELAY, NULL}, + {PXA1908_CLK_PWM1, "pwm1_clk", "pwm01_apb_share", CLK_SET_RATE_PARENT, AP= BC_PWM1, 0x2, 2, 0, 0, NULL}, + {PXA1908_CLK_PWM3, "pwm3_clk", "pwm23_apb_share", CLK_SET_RATE_PARENT, AP= BC_PWM3, 0x2, 2, 0, 0, NULL}, + {PXA1908_CLK_UART0, "uart0_clk", "uart0_mux", CLK_SET_RATE_PARENT, APBC_U= ART0, 0x3, 3, 0, 0, &uart0_lock}, + {PXA1908_CLK_UART1, "uart1_clk", "uart1_mux", CLK_SET_RATE_PARENT, APBC_U= ART1, 0x3, 3, 0, 0, &uart1_lock}, + {PXA1908_CLK_THERMAL, "thermal_clk", NULL, 0, APBC_THERMAL, 0x3, 3, 0, 0,= NULL}, + {PXA1908_CLK_IPC_RST, "ipc_clk", NULL, 0, APBC_IPC_RST, 0x3, 3, 0, 0, NUL= L}, + {PXA1908_CLK_SSP0, "ssp0_clk", "ssp0_mux", 0, APBC_SSP0, 0x3, 3, 0, 0, NU= LL}, + {PXA1908_CLK_SSP2, "ssp2_clk", "ssp2_mux", 0, APBC_SSP2, 0x3, 3, 0, 0, NU= LL}, +}; + +static struct mmp_param_gate_clk apbc_gate_no_reset_clks[] =3D { {PXA1908_CLK_PWM0, "pwm0_clk", "pwm01_apb_share", CLK_SET_RATE_PARENT, AP= BC_PWM0, 0x2, 2, 0, 0, &pwm0_lock}, - {PXA1908_CLK_PWM1, "pwm1_clk", "pwm01_apb_share", CLK_SET_RATE_PARENT, AP= BC_PWM1, 0x6, 2, 0, 0, NULL}, {PXA1908_CLK_PWM2, "pwm2_clk", "pwm23_apb_share", CLK_SET_RATE_PARENT, AP= BC_PWM2, 0x2, 2, 0, 0, NULL}, - {PXA1908_CLK_PWM3, "pwm3_clk", "pwm23_apb_share", CLK_SET_RATE_PARENT, AP= BC_PWM3, 0x6, 2, 0, 0, NULL}, - {PXA1908_CLK_UART0, "uart0_clk", "uart0_mux", CLK_SET_RATE_PARENT, APBC_U= ART0, 0x7, 3, 0, 0, &uart0_lock}, - {PXA1908_CLK_UART1, "uart1_clk", "uart1_mux", CLK_SET_RATE_PARENT, APBC_U= ART1, 0x7, 3, 0, 0, &uart1_lock}, - {PXA1908_CLK_THERMAL, "thermal_clk", NULL, 0, APBC_THERMAL, 0x7, 3, 0, 0,= NULL}, - {PXA1908_CLK_IPC_RST, "ipc_clk", NULL, 0, APBC_IPC_RST, 0x7, 3, 0, 0, NUL= L}, - {PXA1908_CLK_SSP0, "ssp0_clk", "ssp0_mux", 0, APBC_SSP0, 0x7, 3, 0, 0, NU= LL}, - {PXA1908_CLK_SSP2, "ssp2_clk", "ssp2_mux", 0, APBC_SSP2, 0x7, 3, 0, 0, NU= LL}, }; =20 static struct mmp_param_mux_clk apbc_mux_clks[] =3D { @@ -89,6 +93,30 @@ static void pxa1908_apb_periph_clk_init(struct pxa1908_c= lk_unit *pxa_unit) ARRAY_SIZE(apbc_mux_clks)); mmp_register_gate_clks(unit, apbc_gate_clks, pxa_unit->base, ARRAY_SIZE(apbc_gate_clks)); + mmp_register_gate_clks(unit, apbc_gate_no_reset_clks, pxa_unit->base, + ARRAY_SIZE(apbc_gate_no_reset_clks)); +} + +/* Taken from clk-of-pxa1928.c */ +static void pxa1908_clk_reset_init(struct device_node *np, + struct pxa1908_clk_unit *pxa_unit) +{ + struct mmp_clk_reset_cell *cells; + int nr_cells =3D ARRAY_SIZE(apbc_gate_clks); + + cells =3D kzalloc_objs(*cells, nr_cells); + if (!cells) + return; + + for (int i =3D 0; i < nr_cells; i++) { + cells[i].clk_id =3D apbc_gate_clks[i].id; + cells[i].reg =3D pxa_unit->base + apbc_gate_clks[i].offset; + cells[i].bits =3D BIT(2); + cells[i].flags =3D 0; + cells[i].lock =3D apbc_gate_clks[i].lock; + }; + + mmp_clk_reset_register(np, cells, nr_cells); } =20 static int pxa1908_apbc_probe(struct platform_device *pdev) @@ -107,6 +135,8 @@ static int pxa1908_apbc_probe(struct platform_device *p= dev) =20 pxa1908_apb_periph_clk_init(pxa_unit); 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[93.143.58.160]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43d7400708dsm25595266f8f.25.2026.04.14.12.54.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Apr 2026 12:54:16 -0700 (PDT) From: =?utf-8?q?Duje_Mihanovi=C4=87?= Date: Tue, 14 Apr 2026 21:51:52 +0200 Subject: [PATCH 3/4] clk: mmp: pxa1908-apbcp: Add reset cells Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260414-pxa1908-clk-reset-v1-3-94bae5f3a8cf@dujemihanovic.xyz> References: <20260414-pxa1908-clk-reset-v1-0-94bae5f3a8cf@dujemihanovic.xyz> In-Reply-To: <20260414-pxa1908-clk-reset-v1-0-94bae5f3a8cf@dujemihanovic.xyz> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Karel Balej , linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, =?utf-8?q?Duje_Mihanovi=C4=87?= X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2739; i=duje@dujemihanovic.xyz; s=20260328; h=from:subject:message-id; bh=Q4T/ABQPm6i5MvVgGhQo6QXav/d3IJrFZbQDihPCsb4=; b=owGbwMvMwCW2z0j3+uHIyKOMp9WSGDLvzU68vyn38galmo13tMuVhFiqpQMnXzXuEHfdXjElS P0nB29/RykLgxgXg6yYIgvzUrlLfKnhEx2KbJNg5rAygQxh4OIUgIkcecHI8MnrdNWd572+f04t Nn95Jikr1JNT4tmEB2uPreebskZo1mOG/75vxbsYZHsXO5ef2WNUMWtDa+3sc56tN5PXTzr4xft KES8A X-Developer-Key: i=duje@dujemihanovic.xyz; a=openpgp; fpr=9BD463017690089DAA8DC266275F544B3B1B4792 From: Duje Mihanovi=C4=87 It has been concluded by comparing the gate clock masks and vendor code between PXA1908/28 that PXA1908's APBCP, similarly to PXA1928's APBC, has controllable reset lines. Describe these in the driver for correctness. Signed-off-by: Duje Mihanovi=C4=87 --- drivers/clk/mmp/clk-pxa1908-apbcp.c | 31 ++++++++++++++++++++++++++++--- 1 file changed, 28 insertions(+), 3 deletions(-) diff --git a/drivers/clk/mmp/clk-pxa1908-apbcp.c b/drivers/clk/mmp/clk-pxa1= 908-apbcp.c index f638d7e89b47..1aa476103553 100644 --- a/drivers/clk/mmp/clk-pxa1908-apbcp.c +++ b/drivers/clk/mmp/clk-pxa1908-apbcp.c @@ -7,6 +7,7 @@ #include =20 #include "clk.h" +#include "reset.h" =20 #define APBCP_UART2 0x1c #define APBCP_TWSI2 0x28 @@ -24,9 +25,9 @@ static DEFINE_SPINLOCK(uart2_lock); static const char * const uart_parent_names[] =3D {"pll1_117", "uart_pll"}; =20 static struct mmp_param_gate_clk apbcp_gate_clks[] =3D { - {PXA1908_CLK_UART2, "uart2_clk", "uart2_mux", CLK_SET_RATE_PARENT, APBCP_= UART2, 0x7, 0x3, 0x0, 0, &uart2_lock}, - {PXA1908_CLK_TWSI2, "twsi2_clk", "pll1_32", CLK_SET_RATE_PARENT, APBCP_TW= SI2, 0x7, 0x3, 0x0, 0, NULL}, - {PXA1908_CLK_AICER, "ripc_clk", NULL, 0, APBCP_AICER, 0x7, 0x2, 0x0, 0, N= ULL}, + {PXA1908_CLK_UART2, "uart2_clk", "uart2_mux", CLK_SET_RATE_PARENT, APBCP_= UART2, 0x3, 0x3, 0x0, 0, &uart2_lock}, + {PXA1908_CLK_TWSI2, "twsi2_clk", "pll1_32", CLK_SET_RATE_PARENT, APBCP_TW= SI2, 0x3, 0x3, 0x0, 0, NULL}, + {PXA1908_CLK_AICER, "ripc_clk", NULL, 0, APBCP_AICER, 0x3, 0x2, 0x0, 0, N= ULL}, }; =20 static struct mmp_param_mux_clk apbcp_mux_clks[] =3D { @@ -43,6 +44,28 @@ static void pxa1908_apb_p_periph_clk_init(struct pxa1908= _clk_unit *pxa_unit) ARRAY_SIZE(apbcp_gate_clks)); } =20 +/* Taken from clk-of-pxa1928.c */ +static void pxa1908_clk_reset_init(struct device_node *np, + struct pxa1908_clk_unit *pxa_unit) +{ + struct mmp_clk_reset_cell *cells; + int nr_cells =3D ARRAY_SIZE(apbcp_gate_clks); + + cells =3D kzalloc_objs(*cells, nr_cells); + if (!cells) + return; + + for (int i =3D 0; i < nr_cells; i++) { + cells[i].clk_id =3D apbcp_gate_clks[i].id; + cells[i].reg =3D pxa_unit->base + apbcp_gate_clks[i].offset; + cells[i].bits =3D BIT(2); + cells[i].flags =3D 0; + cells[i].lock =3D apbcp_gate_clks[i].lock; + }; + + mmp_clk_reset_register(np, cells, nr_cells); +} + static int pxa1908_apbcp_probe(struct platform_device *pdev) { struct pxa1908_clk_unit *pxa_unit; @@ -59,6 +82,8 @@ static int pxa1908_apbcp_probe(struct platform_device *pd= ev) =20 pxa1908_apb_p_periph_clk_init(pxa_unit); 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[93.143.58.160]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43d7400708dsm25595266f8f.25.2026.04.14.12.54.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Apr 2026 12:54:17 -0700 (PDT) From: =?utf-8?q?Duje_Mihanovi=C4=87?= Date: Tue, 14 Apr 2026 21:51:53 +0200 Subject: [PATCH 4/4] arm64: dts: marvell: mmp: pxa1908: Add reset cells Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260414-pxa1908-clk-reset-v1-4-94bae5f3a8cf@dujemihanovic.xyz> References: <20260414-pxa1908-clk-reset-v1-0-94bae5f3a8cf@dujemihanovic.xyz> In-Reply-To: <20260414-pxa1908-clk-reset-v1-0-94bae5f3a8cf@dujemihanovic.xyz> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Karel Balej , linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, =?utf-8?q?Duje_Mihanovi=C4=87?= X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=4013; i=duje@dujemihanovic.xyz; s=20260328; h=from:subject:message-id; bh=kl4so4YGhRFTk6k5KZvqqawzD5p7cMzaSqktF31UoyA=; b=owGbwMvMwCW2z0j3+uHIyKOMp9WSGDLvzU68sktuSvCp0Ohk9bsnNbry6xribDI2aM+cl2Pgp 3nYbqp/RykLgxgXg6yYIgvzUrlLfKnhEx2KbJNg5rAygQxh4OIUgInwVjIyrF5ZvTbw2TfG8PI7 h5onnri4Yu+G38v4S0qOBslK/zY6xcbwP+kd5y0Wl+rbMmeufLL9vP7LaeFZmddqyiocpaIVbuq /ZQEA X-Developer-Key: i=duje@dujemihanovic.xyz; a=openpgp; fpr=9BD463017690089DAA8DC266275F544B3B1B4792 From: Duje Mihanovi=C4=87 Add the newly implemented reset cells to the SoC dtsi. Signed-off-by: Duje Mihanovi=C4=87 --- arch/arm64/boot/dts/marvell/mmp/pxa1908.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/marvell/mmp/pxa1908.dtsi b/arch/arm64/boot= /dts/marvell/mmp/pxa1908.dtsi index 5778bfdb8567..05b56a759e27 100644 --- a/arch/arm64/boot/dts/marvell/mmp/pxa1908.dtsi +++ b/arch/arm64/boot/dts/marvell/mmp/pxa1908.dtsi @@ -132,6 +132,7 @@ twsi1: i2c@10800 { reg =3D <0x10800 0x64>; interrupts =3D ; clocks =3D <&apbc PXA1908_CLK_TWSI1>; + resets =3D <&apbc PXA1908_CLK_TWSI1>; mrvl,i2c-fast-mode; status =3D "disabled"; }; @@ -143,6 +144,7 @@ twsi0: i2c@11000 { reg =3D <0x11000 0x64>; interrupts =3D ; clocks =3D <&apbc PXA1908_CLK_TWSI0>; + resets =3D <&apbc PXA1908_CLK_TWSI0>; mrvl,i2c-fast-mode; status =3D "disabled"; }; @@ -154,6 +156,7 @@ twsi3: i2c@13800 { reg =3D <0x13800 0x64>; interrupts =3D ; clocks =3D <&apbc PXA1908_CLK_TWSI3>; + resets =3D <&apbc PXA1908_CLK_TWSI3>; mrvl,i2c-fast-mode; status =3D "disabled"; }; @@ -162,6 +165,7 @@ apbc: clock-controller@15000 { compatible =3D "marvell,pxa1908-apbc"; reg =3D <0x15000 0x1000>; #clock-cells =3D <1>; + #reset-cells =3D <1>; }; =20 uart0: serial@17000 { @@ -169,6 +173,7 @@ uart0: serial@17000 { reg =3D <0x17000 0x1000>; interrupts =3D ; clocks =3D <&apbc PXA1908_CLK_UART0>; + resets =3D <&apbc PXA1908_CLK_UART0>; reg-shift =3D <2>; }; =20 @@ -177,6 +182,7 @@ uart1: serial@18000 { reg =3D <0x18000 0x1000>; interrupts =3D ; clocks =3D <&apbc PXA1908_CLK_UART1>; + resets =3D <&apbc PXA1908_CLK_UART1>; reg-shift =3D <2>; }; =20 @@ -188,6 +194,7 @@ gpio: gpio@19000 { gpio-controller; #gpio-cells =3D <2>; clocks =3D <&apbc PXA1908_CLK_GPIO>; + resets =3D <&apbc PXA1908_CLK_GPIO>; interrupts =3D ; interrupt-names =3D "gpio_mux"; interrupt-controller; @@ -215,6 +222,7 @@ pwm0: pwm@1a000 { compatible =3D "marvell,pxa250-pwm"; reg =3D <0x1a000 0x10>; clocks =3D <&apbc PXA1908_CLK_PWM0>; + resets =3D <&apbc PXA1908_CLK_PWM0>; #pwm-cells =3D <1>; status =3D "disabled"; }; @@ -223,6 +231,7 @@ pwm1: pwm@1a400 { compatible =3D "marvell,pxa250-pwm"; reg =3D <0x1a400 0x10>; clocks =3D <&apbc PXA1908_CLK_PWM1>; + resets =3D <&apbc PXA1908_CLK_PWM1>; #pwm-cells =3D <1>; status =3D "disabled"; }; @@ -231,6 +240,7 @@ pwm2: pwm@1a800 { compatible =3D "marvell,pxa250-pwm"; reg =3D <0x1a800 0x10>; clocks =3D <&apbc PXA1908_CLK_PWM2>; + resets =3D <&apbc PXA1908_CLK_PWM2>; #pwm-cells =3D <1>; status =3D "disabled"; }; @@ -239,6 +249,7 @@ pwm3: pwm@1ac00 { compatible =3D "marvell,pxa250-pwm"; reg =3D <0x1ac00 0x10>; clocks =3D <&apbc PXA1908_CLK_PWM3>; + resets =3D <&apbc PXA1908_CLK_PWM3>; #pwm-cells =3D <1>; status =3D "disabled"; }; @@ -261,6 +272,7 @@ uart2: serial@36000 { reg =3D <0x36000 0x1000>; interrupts =3D ; clocks =3D <&apbcp PXA1908_CLK_UART2>; + resets =3D <&apbcp PXA1908_CLK_UART2>; reg-shift =3D <2>; }; =20 @@ -271,6 +283,7 @@ twsi2: i2c@37000 { reg =3D <0x37000 0x64>; interrupts =3D ; clocks =3D <&apbcp PXA1908_CLK_TWSI2>; + resets =3D <&apbcp PXA1908_CLK_TWSI2>; mrvl,i2c-fast-mode; status =3D "disabled"; }; @@ -279,6 +292,7 @@ apbcp: clock-controller@3b000 { compatible =3D "marvell,pxa1908-apbcp"; reg =3D <0x3b000 0x1000>; #clock-cells =3D <1>; + #reset-cells =3D <1>; }; =20 mpmu: clock-controller@50000 { --=20 2.53.0