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Mon, 13 Apr 2026 22:00:34 -0700 (PDT) Received: from hu-bvisredd-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2b2d4db198asm134678425ad.3.2026.04.13.22.00.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Apr 2026 22:00:33 -0700 (PDT) From: Vishnu Reddy Date: Tue, 14 Apr 2026 10:29:57 +0530 Subject: [PATCH 01/11] dt-bindings: media: qcom,glymur-iris: Add glymur video codec Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260414-glymur-v1-1-7d3d1cf57b16@oss.qualcomm.com> References: <20260414-glymur-v1-0-7d3d1cf57b16@oss.qualcomm.com> In-Reply-To: <20260414-glymur-v1-0-7d3d1cf57b16@oss.qualcomm.com> To: Bryan O'Donoghue , Vikash Garodia , Dikshita Agarwal , Abhinav Kumar , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joerg Roedel , Will Deacon , Robin Murphy , Bjorn Andersson , Konrad Dybcio , Stefan Schmidt , Hans Verkuil Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, iommu@lists.linux.dev, Vishnu Reddy X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; 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Glymur is a new generation of video IP that introduces a dual-core architecture. The second core brings its own power domain, clocks, and reset lines, requiring additional power domains and clocks in the power sequence. Signed-off-by: Vishnu Reddy --- .../bindings/media/qcom,glymur-iris.yaml | 220 +++++++++++++++++= ++++ include/dt-bindings/media/qcom,glymur-iris.h | 11 ++ 2 files changed, 231 insertions(+) diff --git a/Documentation/devicetree/bindings/media/qcom,glymur-iris.yaml = b/Documentation/devicetree/bindings/media/qcom,glymur-iris.yaml new file mode 100644 index 000000000000..10ee02cd1a7d --- /dev/null +++ b/Documentation/devicetree/bindings/media/qcom,glymur-iris.yaml @@ -0,0 +1,220 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/qcom,glymur-iris.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Glymur SoC Iris video encoder and decoder + +maintainers: + - Vishnu Reddy + +description: + The Iris video processing unit on Qualcomm Glymur SoC is a video encode = and + decode accelerator. + +properties: + compatible: + const: qcom,glymur-iris + + reg: + maxItems: 1 + + clocks: + maxItems: 9 + + clock-names: + items: + - const: iface + - const: core + - const: vcodec0_core + - const: iface_ctrl + - const: core_freerun + - const: vcodec0_core_freerun + - const: iface1 + - const: vcodec1_core + - const: vcodec1_core_freerun + + dma-coherent: true + + firmware-name: + maxItems: 1 + + interconnects: + maxItems: 2 + + interconnect-names: + items: + - const: cpu-cfg + - const: video-mem + + interrupts: + maxItems: 1 + + iommus: + maxItems: 4 + + iommu-map: + maxItems: 1 + + memory-region: + maxItems: 1 + + operating-points-v2: true + opp-table: + type: object + + power-domains: + maxItems: 5 + + power-domain-names: + items: + - const: venus + - const: vcodec0 + - const: mxc + - const: mmcx + - const: vcodec1 + + resets: + maxItems: 6 + + reset-names: + items: + - const: bus0 + - const: bus_ctrl + - const: core + - const: vcodec0_core + - const: bus1 + - const: vcodec1_core + +required: + - compatible + - reg + - clocks + - clock-names + - dma-coherent + - interconnects + - interconnect-names + - interrupts + - iommus + - memory-region + - power-domains + - power-domain-names + - resets + - reset-names + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + + video-codec@aa00000 { + compatible =3D "qcom,glymur-iris"; + reg =3D <0x0aa00000 0xf0000>; + + clocks =3D <&gcc_video_axi0_clk>, + <&videocc_mvs0c_clk>, + <&videocc_mvs0_clk>, + <&gcc_video_axi0c_clk>, + <&videocc_mvs0c_freerun_clk>, + <&videocc_mvs0_freerun_clk>, + <&gcc_video_axi1_clk>, + <&videocc_mvs1_clk>, + <&videocc_mvs1_freerun_clk>; + clock-names =3D "iface", + "core", + "vcodec0_core", + "iface_ctrl", + "core_freerun", + "vcodec0_core_freerun", + "iface1", + "vcodec1_core", + "vcodec1_core_freerun"; + + dma-coherent; + + interconnects =3D <&hsc_noc_master_appss_proc &config_noc_slave_ve= nus_cfg>, + <&mmss_noc_master_video &mc_virt_slave_ebi1>; + interconnect-names =3D "cpu-cfg", + "video-mem"; + + interrupts =3D ; + + iommus =3D <&apps_smmu 0x1940 0x0>, + <&apps_smmu 0x1943 0x0>, + <&apps_smmu 0x1944 0x0>, + <&apps_smmu 0x19e0 0x0>; + + iommu-map =3D ; + + memory-region =3D <&video_mem>; + + operating-points-v2 =3D <&iris_opp_table>; + + power-domains =3D <&videocc_mvs0c_gdsc>, + <&videocc_mvs0_gdsc>, + <&rpmhpd RPMHPD_MXC>, + <&rpmhpd RPMHPD_MMCX>, + <&videocc_mvs1_gdsc>; + power-domain-names =3D "venus", + "vcodec0", + "mxc", + "mmcx", + "vcodec1"; + + resets =3D <&gcc_video_axi0_clk_ares>, + <&gcc_video_axi0c_clk_ares>, + <&videocc_mvs0c_freerun_clk_ares>, + <&videocc_mvs0_freerun_clk_ares>, + <&gcc_video_axi1_clk_ares>, + <&videocc_mvs1_freerun_clk_ares>; + reset-names =3D "bus0", + "bus_ctrl", + "core", + "vcodec0_core", + "bus1", + "vcodec1_core"; + + iris_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-240000000 { + opp-hz =3D /bits/ 64 <240000000 240000000 360000000>; + required-opps =3D <&rpmhpd_opp_svs>, + <&rpmhpd_opp_low_svs>; + }; + + opp-338000000 { + opp-hz =3D /bits/ 64 <338000000 338000000 507000000>; + required-opps =3D <&rpmhpd_opp_svs>, + <&rpmhpd_opp_svs>; + }; + + opp-366000000 { + opp-hz =3D /bits/ 64 <366000000 366000000 549000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>, + <&rpmhpd_opp_svs_l1>; + }; + + opp-444000000 { + opp-hz =3D /bits/ 64 <444000000 444000000 666000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>, + <&rpmhpd_opp_nom>; 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Iris devices require their own bus so that each device can run its own dma_configure() logic. Signed-off-by: Vikash Garodia Signed-off-by: Vishnu Reddy --- drivers/iommu/iommu.c | 4 ++++ drivers/media/platform/qcom/iris/Makefile | 4 ++++ drivers/media/platform/qcom/iris/iris_vpu_bus.c | 32 +++++++++++++++++++++= ++++ include/linux/iris_vpu_bus.h | 13 ++++++++++ 4 files changed, 53 insertions(+) diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c index 61c12ba78206..d8ed6ef70ecd 100644 --- a/drivers/iommu/iommu.c +++ b/drivers/iommu/iommu.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -179,6 +180,9 @@ static const struct bus_type * const iommu_buses[] =3D { #ifdef CONFIG_CDX_BUS &cdx_bus_type, #endif +#if IS_ENABLED(CONFIG_VIDEO_QCOM_IRIS) + &iris_vpu_bus_type, +#endif }; =20 /* diff --git a/drivers/media/platform/qcom/iris/Makefile b/drivers/media/plat= form/qcom/iris/Makefile index 2abbd3aeb4af..6f4052b98491 100644 --- a/drivers/media/platform/qcom/iris/Makefile +++ b/drivers/media/platform/qcom/iris/Makefile @@ -31,3 +31,7 @@ qcom-iris-objs +=3D iris_platform_gen1.o endif =20 obj-$(CONFIG_VIDEO_QCOM_IRIS) +=3D qcom-iris.o + +ifdef CONFIG_VIDEO_QCOM_IRIS +obj-y +=3D iris_vpu_bus.o +endif diff --git a/drivers/media/platform/qcom/iris/iris_vpu_bus.c b/drivers/medi= a/platform/qcom/iris/iris_vpu_bus.c new file mode 100644 index 000000000000..b51bb4b82b0e --- /dev/null +++ b/drivers/media/platform/qcom/iris/iris_vpu_bus.c @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include + +#include "iris_platform_common.h" + +static int iris_vpu_bus_dma_configure(struct device *dev) +{ + const u32 *f_id =3D dev_get_drvdata(dev); + + if (!f_id) + return -ENODEV; + + return of_dma_configure_id(dev, dev->parent->of_node, true, f_id); +} + +const struct bus_type iris_vpu_bus_type =3D { + .name =3D "iris-vpu-bus", + .dma_configure =3D iris_vpu_bus_dma_configure, +}; +EXPORT_SYMBOL_GPL(iris_vpu_bus_type); + +static int __init iris_vpu_bus_init(void) +{ + return bus_register(&iris_vpu_bus_type); +} + +postcore_initcall(iris_vpu_bus_init); diff --git a/include/linux/iris_vpu_bus.h b/include/linux/iris_vpu_bus.h new file mode 100644 index 000000000000..5704b226f7d6 --- /dev/null +++ b/include/linux/iris_vpu_bus.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) Qualcomm Innovation Center, Inc. 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These hooks allow platform specific code to initialize and tear down context banks. The Glymur platform requires a dedicated firmware context bank device which is mapped to the firmware stream ID to load the firmware. Signed-off-by: Vishnu Reddy --- .../platform/qcom/iris/iris_platform_common.h | 2 ++ drivers/media/platform/qcom/iris/iris_probe.c | 23 ++++++++++++++++++= +++- 2 files changed, 24 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/driv= ers/media/platform/qcom/iris/iris_platform_common.h index 5a489917580e..55ff6137d9a9 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -219,6 +219,8 @@ struct iris_platform_data { u32 (*get_vpu_buffer_size)(struct iris_inst *inst, enum iris_buffer_type = buffer_type); const struct vpu_ops *vpu_ops; void (*set_preset_registers)(struct iris_core *core); + int (*init_cb_devs)(struct iris_core *core); + void (*deinit_cb_devs)(struct iris_core *core); const struct icc_info *icc_tbl; unsigned int icc_tbl_size; const struct bw_info *bw_tbl_dec; diff --git a/drivers/media/platform/qcom/iris/iris_probe.c b/drivers/media/= platform/qcom/iris/iris_probe.c index ddaacda523ec..34751912f871 100644 --- a/drivers/media/platform/qcom/iris/iris_probe.c +++ b/drivers/media/platform/qcom/iris/iris_probe.c @@ -142,6 +142,20 @@ static int iris_init_resources(struct iris_core *core) return iris_init_resets(core); } =20 +static int iris_init_cb_devs(struct iris_core *core) +{ + if (core->iris_platform_data->init_cb_devs) + return core->iris_platform_data->init_cb_devs(core); + + return 0; +} + +static void iris_deinit_cb_devs(struct iris_core *core) +{ + if (core->iris_platform_data->deinit_cb_devs) + core->iris_platform_data->deinit_cb_devs(core); +} + static int iris_register_video_device(struct iris_core *core, enum domain_= type type) { struct video_device *vdev; @@ -193,6 +207,7 @@ static void iris_remove(struct platform_device *pdev) return; =20 iris_core_deinit(core); + iris_deinit_cb_devs(core); =20 video_unregister_device(core->vdev_dec); video_unregister_device(core->vdev_enc); @@ -259,11 +274,15 @@ static int iris_probe(struct platform_device *pdev) if (ret) return ret; =20 + ret =3D iris_init_cb_devs(core); + if (ret) + return ret; + iris_session_init_caps(core); =20 ret =3D v4l2_device_register(dev, &core->v4l2_dev); if (ret) - return ret; + goto err_deinit_cb; =20 ret =3D iris_register_video_device(core, DECODER); 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The function ID associated with the CB is specified from the platform data, allowing the bus dma_configure callback to apply correct stream ID mapping when device is registered. Signed-off-by: Vikash Garodia Signed-off-by: Vishnu Reddy --- drivers/media/platform/qcom/iris/iris_resources.c | 33 +++++++++++++++++++= ++++ drivers/media/platform/qcom/iris/iris_resources.h | 1 + 2 files changed, 34 insertions(+) diff --git a/drivers/media/platform/qcom/iris/iris_resources.c b/drivers/me= dia/platform/qcom/iris/iris_resources.c index 773f6548370a..a25e0f2e9d26 100644 --- a/drivers/media/platform/qcom/iris/iris_resources.c +++ b/drivers/media/platform/qcom/iris/iris_resources.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -141,3 +142,35 @@ int iris_disable_unprepare_clock(struct iris_core *cor= e, enum platform_clk_type =20 return 0; } + +static void iris_release_cb_dev(struct device *dev) +{ + kfree(dev); +} + +struct device *iris_create_cb_dev(struct iris_core *core, const char *name= , const u32 *f_id) +{ + struct device *dev; + int ret; + + dev =3D kzalloc_obj(*dev); + if (!dev) + return ERR_PTR(-ENOMEM); + + dev->release =3D iris_release_cb_dev; + dev->bus =3D &iris_vpu_bus_type; + dev->parent =3D core->dev; + dev->coherent_dma_mask =3D core->iris_platform_data->dma_mask; + dev->dma_mask =3D &dev->coherent_dma_mask; + + dev_set_name(dev, "%s", name); + dev_set_drvdata(dev, (void *)f_id); + + ret =3D device_register(dev); + if (ret) { + put_device(dev); + return ERR_PTR(ret); + } + + return dev; +} diff --git a/drivers/media/platform/qcom/iris/iris_resources.h b/drivers/me= dia/platform/qcom/iris/iris_resources.h index 6bfbd2dc6db0..4a494627ff23 100644 --- a/drivers/media/platform/qcom/iris/iris_resources.h +++ b/drivers/media/platform/qcom/iris/iris_resources.h @@ -15,5 +15,6 @@ int iris_unset_icc_bw(struct iris_core *core); int iris_set_icc_bw(struct iris_core *core, unsigned long icc_bw); int iris_disable_unprepare_clock(struct iris_core *core, enum platform_clk= _type clk_type); int iris_prepare_enable_clock(struct iris_core *core, enum platform_clk_ty= pe clk_type); +struct device *iris_create_cb_dev(struct iris_core *core, const char *name= , const u32 *f_id); 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Mon, 13 Apr 2026 22:00:59 -0700 (PDT) Received: from hu-bvisredd-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2b2d4db198asm134678425ad.3.2026.04.13.22.00.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Apr 2026 22:00:59 -0700 (PDT) From: Vishnu Reddy Date: Tue, 14 Apr 2026 10:30:01 +0530 Subject: [PATCH 05/11] media: iris: Enable Secure PAS support with IOMMU managed by Linux Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260414-glymur-v1-5-7d3d1cf57b16@oss.qualcomm.com> References: <20260414-glymur-v1-0-7d3d1cf57b16@oss.qualcomm.com> In-Reply-To: <20260414-glymur-v1-0-7d3d1cf57b16@oss.qualcomm.com> To: Bryan O'Donoghue , Vikash Garodia , Dikshita Agarwal , Abhinav Kumar , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joerg Roedel , Will Deacon , Robin Murphy , Bjorn Andersson , Konrad Dybcio , Stefan Schmidt , Hans Verkuil Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, iommu@lists.linux.dev, Vishnu Reddy , Mukesh Ojha X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; 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This includes mapping memory regions and device memory resources for remote processors by intercepting qcom_scm_pas_auth_and_reset() calls. These mappings are later removed during teardown. Additionally, SHM bridge setup is required to enable memory protection for both remoteproc metadata and its memory regions. When the hypervisor is absent, the operating system must perform these configurations instead. Support for handling IOMMU and SHM setup in the absence of a hypervisor is now in place. Extend the Iris driver to enable this functionality on platforms where IOMMU is managed by Linux (i.e., non-Gunyah, non-QHEE). Additionally, the Iris driver must map the firmware and its required resources to the firmware SID, which is now specified via iommu-map in the device tree. Co-developed-by: Vikash Garodia Signed-off-by: Vikash Garodia Signed-off-by: Mukesh Ojha Signed-off-by: Vishnu Reddy --- drivers/media/platform/qcom/iris/iris_core.h | 4 ++ drivers/media/platform/qcom/iris/iris_firmware.c | 71 ++++++++++++++++++++= +--- 2 files changed, 66 insertions(+), 9 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_core.h b/drivers/media/p= latform/qcom/iris/iris_core.h index fb194c967ad4..aa7abef6f0e0 100644 --- a/drivers/media/platform/qcom/iris/iris_core.h +++ b/drivers/media/platform/qcom/iris/iris_core.h @@ -34,6 +34,8 @@ enum domain_type { * struct iris_core - holds core parameters valid for all instances * * @dev: reference to device structure + * @dev_fw: reference to the context bank device used for firmware load + * @ctx_fw: SCM PAS context for authenticated firmware load and shutdown * @reg_base: IO memory base address * @irq: iris irq * @v4l2_dev: a holder for v4l2 device structure @@ -77,6 +79,8 @@ enum domain_type { =20 struct iris_core { struct device *dev; + struct device *dev_fw; + struct qcom_scm_pas_context *ctx_fw; void __iomem *reg_base; int irq; struct v4l2_device v4l2_dev; diff --git a/drivers/media/platform/qcom/iris/iris_firmware.c b/drivers/med= ia/platform/qcom/iris/iris_firmware.c index 5f408024e967..93d77996c83f 100644 --- a/drivers/media/platform/qcom/iris/iris_firmware.c +++ b/drivers/media/platform/qcom/iris/iris_firmware.c @@ -5,6 +5,7 @@ =20 #include #include +#include #include #include #include @@ -13,12 +14,15 @@ #include "iris_firmware.h" =20 #define MAX_FIRMWARE_NAME_SIZE 128 +#define IRIS_FW_START_ADDR 0 =20 static int iris_load_fw_to_memory(struct iris_core *core, const char *fw_n= ame) { + struct device *dev =3D core->dev_fw ? core->dev_fw : core->dev; u32 pas_id =3D core->iris_platform_data->pas_id; const struct firmware *firmware =3D NULL; - struct device *dev =3D core->dev; + struct qcom_scm_pas_context *ctx_fw; + struct iommu_domain *domain; struct resource res; phys_addr_t mem_phys; size_t res_size; @@ -29,13 +33,17 @@ static int iris_load_fw_to_memory(struct iris_core *cor= e, const char *fw_name) if (strlen(fw_name) >=3D MAX_FIRMWARE_NAME_SIZE - 4) return -EINVAL; =20 - ret =3D of_reserved_mem_region_to_resource(dev->of_node, 0, &res); + ret =3D of_reserved_mem_region_to_resource(core->dev->of_node, 0, &res); if (ret) return ret; =20 mem_phys =3D res.start; res_size =3D resource_size(&res); =20 + ctx_fw =3D devm_qcom_scm_pas_context_alloc(dev, pas_id, mem_phys, res_siz= e); + if (IS_ERR(ctx_fw)) + return PTR_ERR(ctx_fw); + ret =3D request_firmware(&firmware, fw_name, dev); if (ret) return ret; @@ -52,9 +60,27 @@ static int iris_load_fw_to_memory(struct iris_core *core= , const char *fw_name) goto err_release_fw; } =20 - ret =3D qcom_mdt_load(dev, firmware, fw_name, - pas_id, mem_virt, mem_phys, res_size, NULL); + ctx_fw->use_tzmem =3D !!core->dev_fw; + ret =3D qcom_mdt_pas_load(ctx_fw, firmware, fw_name, mem_virt, NULL); + if (ret) + goto err_mem_unmap; + + if (ctx_fw->use_tzmem) { + domain =3D iommu_get_domain_for_dev(core->dev_fw); + if (!domain) { + ret =3D -ENODEV; + goto err_mem_unmap; + } + + ret =3D iommu_map(domain, IRIS_FW_START_ADDR, mem_phys, res_size, + IOMMU_READ | IOMMU_WRITE | IOMMU_PRIV, GFP_KERNEL); + if (ret) + goto err_mem_unmap; + } =20 + core->ctx_fw =3D ctx_fw; + +err_mem_unmap: memunmap(mem_virt); err_release_fw: release_firmware(firmware); @@ -62,6 +88,19 @@ static int iris_load_fw_to_memory(struct iris_core *core= , const char *fw_name) return ret; } =20 +static void iris_fw_iommu_unmap(struct iris_core *core) +{ + bool use_tzmem =3D core->ctx_fw->use_tzmem; + struct iommu_domain *domain; + + if (!use_tzmem) + return; + + domain =3D iommu_get_domain_for_dev(core->dev_fw); + if (domain) + iommu_unmap(domain, IRIS_FW_START_ADDR, core->ctx_fw->mem_size); +} + int iris_fw_load(struct iris_core *core) { const struct tz_cp_config *cp_config; @@ -79,10 +118,10 @@ int iris_fw_load(struct iris_core *core) return -ENOMEM; } =20 - ret =3D qcom_scm_pas_auth_and_reset(core->iris_platform_data->pas_id); + ret =3D qcom_scm_pas_prepare_and_auth_reset(core->ctx_fw); if (ret) { dev_err(core->dev, "auth and reset failed: %d\n", ret); - return ret; + goto err_unmap; } =20 for (i =3D 0; i < core->iris_platform_data->tz_cp_config_data_size; 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Writing 1 causes firmware to treat it as 2 VMs. Since only one VM is required, remove this write to leave the register at its reset value of 0. This does not affect other platforms as only Glymur firmware uses this register, earlier platform firmwares ignore it. Fixes: abf5bac63f68a ("media: iris: implement the boot sequence of the firm= ware") Cc: stable@vger.kernel.org Signed-off-by: Vishnu Reddy --- drivers/media/platform/qcom/iris/iris_vpu_common.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/m= edia/platform/qcom/iris/iris_vpu_common.c index 548e5f1727fd..bfd1e762c38e 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_common.c +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c @@ -78,7 +78,6 @@ int iris_vpu_boot_firmware(struct iris_core *core) iris_vpu_setup_ucregion_memory_map(core); =20 writel(ctrl_init, core->reg_base + CTRL_INIT); - writel(0x1, core->reg_base + CPU_CS_SCIACMDARG3); =20 while (!ctrl_status && count < max_tries) { ctrl_status =3D readl(core->reg_base + CTRL_STATUS); --=20 2.34.1 From nobody Tue Apr 14 14:01:53 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 11F562820AC for ; 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Rename them with a vcodec prefix to make the names more meaningful and to easily accommodate vcodec1 enums for the secondary core in the following patches. This patch only renames the macros and does not introduce any functional changes. Signed-off-by: Vishnu Reddy --- .../platform/qcom/iris/iris_platform_common.h | 12 ++++---- .../media/platform/qcom/iris/iris_platform_gen1.c | 6 ++-- .../media/platform/qcom/iris/iris_platform_gen2.c | 6 ++-- .../platform/qcom/iris/iris_platform_sc7280.h | 10 +++---- .../platform/qcom/iris/iris_platform_sm8750.h | 12 ++++---- drivers/media/platform/qcom/iris/iris_vpu3x.c | 25 ++++++++-------- drivers/media/platform/qcom/iris/iris_vpu4x.c | 30 ++++++++++--------- drivers/media/platform/qcom/iris/iris_vpu_common.c | 35 +++++++++++-------= ---- 8 files changed, 70 insertions(+), 66 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/driv= ers/media/platform/qcom/iris/iris_platform_common.h index 55ff6137d9a9..30e9d4d288c6 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -49,14 +49,14 @@ extern const struct iris_platform_data sm8650_data; extern const struct iris_platform_data sm8750_data; =20 enum platform_clk_type { - IRIS_AXI_CLK, /* AXI0 in case of platforms with multiple AXI clocks */ + IRIS_AXI_VCODEC_CLK, IRIS_CTRL_CLK, IRIS_AHB_CLK, - IRIS_HW_CLK, - IRIS_HW_AHB_CLK, - IRIS_AXI1_CLK, + IRIS_VCODEC_CLK, + IRIS_VCODEC_AHB_CLK, + IRIS_AXI_CTRL_CLK, IRIS_CTRL_FREERUN_CLK, - IRIS_HW_FREERUN_CLK, + IRIS_VCODEC_FREERUN_CLK, IRIS_BSE_HW_CLK, IRIS_VPP0_HW_CLK, IRIS_VPP1_HW_CLK, @@ -206,7 +206,7 @@ struct icc_vote_data { =20 enum platform_pm_domain_type { IRIS_CTRL_POWER_DOMAIN, - IRIS_HW_POWER_DOMAIN, + IRIS_VCODEC_POWER_DOMAIN, IRIS_VPP0_HW_POWER_DOMAIN, IRIS_VPP1_HW_POWER_DOMAIN, IRIS_APV_HW_POWER_DOMAIN, diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen1.c b/driver= s/media/platform/qcom/iris/iris_platform_gen1.c index df8e6bf9430e..be6a631f8ede 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen1.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen1.c @@ -284,9 +284,9 @@ static const char * const sm8250_pmdomain_table[] =3D {= "venus", "vcodec0" }; static const char * const sm8250_opp_pd_table[] =3D { "mx" }; =20 static const struct platform_clk_data sm8250_clk_table[] =3D { - {IRIS_AXI_CLK, "iface" }, - {IRIS_CTRL_CLK, "core" }, - {IRIS_HW_CLK, "vcodec0_core" }, + {IRIS_AXI_VCODEC_CLK, "iface" }, + {IRIS_CTRL_CLK, "core" }, + {IRIS_VCODEC_CLK, "vcodec0_core" }, }; =20 static const char * const sm8250_opp_clk_table[] =3D { diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/driver= s/media/platform/qcom/iris/iris_platform_gen2.c index 5da90d47f9c6..47c6b650f0b4 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c @@ -780,9 +780,9 @@ static const char * const sm8550_pmdomain_table[] =3D {= "venus", "vcodec0" }; static const char * const sm8550_opp_pd_table[] =3D { "mxc", "mmcx" }; =20 static const struct platform_clk_data sm8550_clk_table[] =3D { - {IRIS_AXI_CLK, "iface" }, - {IRIS_CTRL_CLK, "core" }, - {IRIS_HW_CLK, "vcodec0_core" }, + {IRIS_AXI_VCODEC_CLK, "iface" }, + {IRIS_CTRL_CLK, "core" }, + {IRIS_VCODEC_CLK, "vcodec0_core" }, }; =20 static const char * const sm8550_opp_clk_table[] =3D { diff --git a/drivers/media/platform/qcom/iris/iris_platform_sc7280.h b/driv= ers/media/platform/qcom/iris/iris_platform_sc7280.h index 0ec8f334df67..6b783e524b81 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_sc7280.h +++ b/drivers/media/platform/qcom/iris/iris_platform_sc7280.h @@ -16,11 +16,11 @@ static const struct bw_info sc7280_bw_table_dec[] =3D { static const char * const sc7280_opp_pd_table[] =3D { "cx" }; =20 static const struct platform_clk_data sc7280_clk_table[] =3D { - {IRIS_CTRL_CLK, "core" }, - {IRIS_AXI_CLK, "iface" }, - {IRIS_AHB_CLK, "bus" }, - {IRIS_HW_CLK, "vcodec_core" }, - {IRIS_HW_AHB_CLK, "vcodec_bus" }, + {IRIS_CTRL_CLK, "core" }, + {IRIS_AXI_VCODEC_CLK, "iface" }, + {IRIS_AHB_CLK, "bus" }, + {IRIS_VCODEC_CLK, "vcodec_core" }, + {IRIS_VCODEC_AHB_CLK, "vcodec_bus" }, }; =20 static const char * const sc7280_opp_clk_table[] =3D { diff --git a/drivers/media/platform/qcom/iris/iris_platform_sm8750.h b/driv= ers/media/platform/qcom/iris/iris_platform_sm8750.h index 719056656a5b..f843f13251c5 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_sm8750.h +++ b/drivers/media/platform/qcom/iris/iris_platform_sm8750.h @@ -11,12 +11,12 @@ static const char * const sm8750_clk_reset_table[] =3D { }; =20 static const struct platform_clk_data sm8750_clk_table[] =3D { - {IRIS_AXI_CLK, "iface" }, - {IRIS_CTRL_CLK, "core" }, - {IRIS_HW_CLK, "vcodec0_core" }, - {IRIS_AXI1_CLK, "iface1" }, - {IRIS_CTRL_FREERUN_CLK, "core_freerun" }, - {IRIS_HW_FREERUN_CLK, "vcodec0_core_freerun" }, + {IRIS_AXI_VCODEC_CLK, "iface" }, + {IRIS_CTRL_CLK, "core" }, + {IRIS_VCODEC_CLK, "vcodec0_core" }, + {IRIS_AXI_CTRL_CLK, "iface1" }, + {IRIS_CTRL_FREERUN_CLK, "core_freerun" }, + {IRIS_VCODEC_FREERUN_CLK, "vcodec0_core_freerun" }, }; =20 #endif diff --git a/drivers/media/platform/qcom/iris/iris_vpu3x.c b/drivers/media/= platform/qcom/iris/iris_vpu3x.c index fe4423b951b1..1f0a3a47d87f 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu3x.c +++ b/drivers/media/platform/qcom/iris/iris_vpu3x.c @@ -209,7 +209,7 @@ static int iris_vpu33_power_off_controller(struct iris_= core *core) =20 disable_power: iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_PO= WER_DOMAIN]); - iris_disable_unprepare_clock(core, IRIS_AXI_CLK); + iris_disable_unprepare_clock(core, IRIS_AXI_VCODEC_CLK); =20 return 0; } @@ -218,36 +218,37 @@ static int iris_vpu35_power_on_hw(struct iris_core *c= ore) { int ret; =20 - ret =3D iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_= HW_POWER_DOMAIN]); + ret =3D iris_enable_power_domains(core, + core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN]); if (ret) return ret; =20 - ret =3D iris_prepare_enable_clock(core, IRIS_AXI_CLK); + ret =3D iris_prepare_enable_clock(core, IRIS_AXI_VCODEC_CLK); if (ret) goto err_disable_power; =20 - ret =3D iris_prepare_enable_clock(core, IRIS_HW_FREERUN_CLK); + ret =3D iris_prepare_enable_clock(core, IRIS_VCODEC_FREERUN_CLK); if (ret) goto err_disable_axi_clk; =20 - ret =3D iris_prepare_enable_clock(core, IRIS_HW_CLK); + ret =3D iris_prepare_enable_clock(core, IRIS_VCODEC_CLK); if (ret) goto err_disable_hw_free_clk; =20 - ret =3D dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER= _DOMAIN], true); + ret =3D dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_VCODEC_P= OWER_DOMAIN], true); if (ret) goto err_disable_hw_clk; =20 return 0; =20 err_disable_hw_clk: - iris_disable_unprepare_clock(core, IRIS_HW_CLK); + iris_disable_unprepare_clock(core, IRIS_VCODEC_CLK); err_disable_hw_free_clk: - iris_disable_unprepare_clock(core, IRIS_HW_FREERUN_CLK); + iris_disable_unprepare_clock(core, IRIS_VCODEC_FREERUN_CLK); err_disable_axi_clk: - iris_disable_unprepare_clock(core, IRIS_AXI_CLK); + iris_disable_unprepare_clock(core, IRIS_AXI_VCODEC_CLK); err_disable_power: - iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWE= R_DOMAIN]); + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_VCODEC_= POWER_DOMAIN]); =20 return ret; } @@ -256,8 +257,8 @@ static void iris_vpu35_power_off_hw(struct iris_core *c= ore) { iris_vpu33_power_off_hardware(core); =20 - iris_disable_unprepare_clock(core, IRIS_HW_FREERUN_CLK); - iris_disable_unprepare_clock(core, IRIS_AXI_CLK); + iris_disable_unprepare_clock(core, IRIS_VCODEC_FREERUN_CLK); + iris_disable_unprepare_clock(core, IRIS_AXI_VCODEC_CLK); } =20 const struct vpu_ops iris_vpu3_ops =3D { diff --git a/drivers/media/platform/qcom/iris/iris_vpu4x.c b/drivers/media/= platform/qcom/iris/iris_vpu4x.c index a8db02ce5c5e..4082d331d2f3 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu4x.c +++ b/drivers/media/platform/qcom/iris/iris_vpu4x.c @@ -27,7 +27,8 @@ static int iris_vpu4x_genpd_set_hwmode(struct iris_core *= core, bool hw_mode, u32 { int ret; =20 - ret =3D dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER= _DOMAIN], hw_mode); + ret =3D dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_VCODEC_P= OWER_DOMAIN], + hw_mode); if (ret) return ret; =20 @@ -63,7 +64,7 @@ static int iris_vpu4x_genpd_set_hwmode(struct iris_core *= core, bool hw_mode, u32 dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_VPP0_HW_POWER_D= OMAIN], !hw_mode); restore_hw_domain_mode: - dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]= , !hw_mode); + dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOM= AIN], !hw_mode); =20 return ret; } @@ -162,15 +163,15 @@ static int iris_vpu4x_enable_hardware_clocks(struct i= ris_core *core, u32 efuse_v { int ret; =20 - ret =3D iris_prepare_enable_clock(core, IRIS_AXI_CLK); + ret =3D iris_prepare_enable_clock(core, IRIS_AXI_VCODEC_CLK); if (ret) return ret; =20 - ret =3D iris_prepare_enable_clock(core, IRIS_HW_FREERUN_CLK); + ret =3D iris_prepare_enable_clock(core, IRIS_VCODEC_FREERUN_CLK); if (ret) goto disable_axi_clock; =20 - ret =3D iris_prepare_enable_clock(core, IRIS_HW_CLK); + ret =3D iris_prepare_enable_clock(core, IRIS_VCODEC_CLK); if (ret) goto disable_hw_free_run_clock; =20 @@ -198,11 +199,11 @@ static int iris_vpu4x_enable_hardware_clocks(struct i= ris_core *core, u32 efuse_v disable_bse_hw_clock: iris_disable_unprepare_clock(core, IRIS_BSE_HW_CLK); disable_hw_clock: - iris_disable_unprepare_clock(core, IRIS_HW_CLK); + iris_disable_unprepare_clock(core, IRIS_VCODEC_CLK); disable_hw_free_run_clock: - iris_disable_unprepare_clock(core, IRIS_HW_FREERUN_CLK); + iris_disable_unprepare_clock(core, IRIS_VCODEC_FREERUN_CLK); disable_axi_clock: - iris_disable_unprepare_clock(core, IRIS_AXI_CLK); + iris_disable_unprepare_clock(core, IRIS_AXI_VCODEC_CLK); =20 return ret; } @@ -216,9 +217,9 @@ static void iris_vpu4x_disable_hardware_clocks(struct i= ris_core *core, u32 efuse iris_disable_unprepare_clock(core, IRIS_VPP0_HW_CLK); =20 iris_disable_unprepare_clock(core, IRIS_BSE_HW_CLK); - iris_disable_unprepare_clock(core, IRIS_HW_CLK); - iris_disable_unprepare_clock(core, IRIS_HW_FREERUN_CLK); - iris_disable_unprepare_clock(core, IRIS_AXI_CLK); + iris_disable_unprepare_clock(core, IRIS_VCODEC_CLK); + iris_disable_unprepare_clock(core, IRIS_VCODEC_FREERUN_CLK); + iris_disable_unprepare_clock(core, IRIS_AXI_VCODEC_CLK); } =20 static int iris_vpu4x_power_on_hardware(struct iris_core *core) @@ -226,7 +227,8 @@ static int iris_vpu4x_power_on_hardware(struct iris_cor= e *core) u32 efuse_value =3D readl(core->reg_base + WRAPPER_EFUSE_MONITOR); int ret; =20 - ret =3D iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_= HW_POWER_DOMAIN]); + ret =3D iris_enable_power_domains(core, + core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN]); if (ret) return ret; =20 @@ -278,7 +280,7 @@ static int iris_vpu4x_power_on_hardware(struct iris_cor= e *core) iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs [IRIS_VPP0_HW_POWER_DOMAIN]); disable_hw_power_domain: - iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWE= R_DOMAIN]); + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_VCODEC_= POWER_DOMAIN]); =20 return ret; } @@ -356,7 +358,7 @@ static void iris_vpu4x_power_off_hardware(struct iris_c= ore *core) iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs [IRIS_VPP0_HW_POWER_DOMAIN]); =20 - iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWE= R_DOMAIN]); + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_VCODEC_= POWER_DOMAIN]); } =20 const struct vpu_ops iris_vpu4x_ops =3D { diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/m= edia/platform/qcom/iris/iris_vpu_common.c index bfd1e762c38e..006fd3ffc752 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_common.c +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c @@ -213,7 +213,7 @@ int iris_vpu_power_off_controller(struct iris_core *cor= e) disable_power: iris_disable_unprepare_clock(core, IRIS_AHB_CLK); iris_disable_unprepare_clock(core, IRIS_CTRL_CLK); - iris_disable_unprepare_clock(core, IRIS_AXI_CLK); + iris_disable_unprepare_clock(core, IRIS_AXI_VCODEC_CLK); iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_PO= WER_DOMAIN]); =20 return 0; @@ -221,10 +221,10 @@ int iris_vpu_power_off_controller(struct iris_core *c= ore) =20 void iris_vpu_power_off_hw(struct iris_core *core) { - dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]= , false); - iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWE= R_DOMAIN]); - iris_disable_unprepare_clock(core, IRIS_HW_AHB_CLK); - iris_disable_unprepare_clock(core, IRIS_HW_CLK); + dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOM= AIN], false); + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_VCODEC_= POWER_DOMAIN]); + iris_disable_unprepare_clock(core, IRIS_VCODEC_AHB_CLK); + iris_disable_unprepare_clock(core, IRIS_VCODEC_CLK); } =20 void iris_vpu_power_off(struct iris_core *core) @@ -251,7 +251,7 @@ int iris_vpu_power_on_controller(struct iris_core *core) if (ret) goto err_disable_power; =20 - ret =3D iris_prepare_enable_clock(core, IRIS_AXI_CLK); + ret =3D iris_prepare_enable_clock(core, IRIS_AXI_VCODEC_CLK); if (ret) goto err_disable_power; =20 @@ -268,7 +268,7 @@ int iris_vpu_power_on_controller(struct iris_core *core) err_disable_ctrl_clock: iris_disable_unprepare_clock(core, IRIS_CTRL_CLK); err_disable_axi_clock: - iris_disable_unprepare_clock(core, IRIS_AXI_CLK); + iris_disable_unprepare_clock(core, IRIS_AXI_VCODEC_CLK); err_disable_power: iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_PO= WER_DOMAIN]); =20 @@ -279,30 +279,31 @@ int iris_vpu_power_on_hw(struct iris_core *core) { int ret; =20 - ret =3D iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_= HW_POWER_DOMAIN]); + ret =3D iris_enable_power_domains(core, + core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN]); if (ret) return ret; =20 - ret =3D iris_prepare_enable_clock(core, IRIS_HW_CLK); + ret =3D iris_prepare_enable_clock(core, IRIS_VCODEC_CLK); if (ret) goto err_disable_power; =20 - ret =3D iris_prepare_enable_clock(core, IRIS_HW_AHB_CLK); + ret =3D iris_prepare_enable_clock(core, IRIS_VCODEC_AHB_CLK); if (ret && ret !=3D -ENOENT) goto err_disable_hw_clock; =20 - ret =3D dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER= _DOMAIN], true); + ret =3D dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_VCODEC_P= OWER_DOMAIN], true); if (ret) goto err_disable_hw_ahb_clock; =20 return 0; =20 err_disable_hw_ahb_clock: - iris_disable_unprepare_clock(core, IRIS_HW_AHB_CLK); + iris_disable_unprepare_clock(core, IRIS_VCODEC_AHB_CLK); err_disable_hw_clock: - iris_disable_unprepare_clock(core, IRIS_HW_CLK); + iris_disable_unprepare_clock(core, IRIS_VCODEC_CLK); err_disable_power: - iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWE= R_DOMAIN]); + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_VCODEC_= POWER_DOMAIN]); =20 return ret; } @@ -362,7 +363,7 @@ int iris_vpu35_vpu4x_power_off_controller(struct iris_c= ore *core) disable_power: iris_disable_unprepare_clock(core, IRIS_CTRL_CLK); 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Signed-off-by: Vishnu Reddy --- .../platform/qcom/iris/iris_platform_common.h | 9 ++ drivers/media/platform/qcom/iris/iris_vpu3x.c | 123 +++++++++++++++++= ++++ drivers/media/platform/qcom/iris/iris_vpu_common.h | 1 + .../platform/qcom/iris/iris_vpu_register_defines.h | 7 ++ 4 files changed, 140 insertions(+) diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/driv= ers/media/platform/qcom/iris/iris_platform_common.h index 30e9d4d288c6..e3c1aff770dd 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -61,6 +61,9 @@ enum platform_clk_type { IRIS_VPP0_HW_CLK, IRIS_VPP1_HW_CLK, IRIS_APV_HW_CLK, + IRIS_AXI_VCODEC1_CLK, + IRIS_VCODEC1_CLK, + IRIS_VCODEC1_FREERUN_CLK, }; =20 struct platform_clk_data { @@ -208,6 +211,12 @@ enum platform_pm_domain_type { IRIS_CTRL_POWER_DOMAIN, IRIS_VCODEC_POWER_DOMAIN, IRIS_VPP0_HW_POWER_DOMAIN, + /* + * On Glymur, vcodec1 power domain is at the same index in pd_devs[] + * as IRIS_VPP0_HW_POWER_DOMAIN. Alias it so that the Glymur power + * domain table is indexed correctly. + */ + IRIS_VCODEC1_POWER_DOMAIN =3D IRIS_VPP0_HW_POWER_DOMAIN, IRIS_VPP1_HW_POWER_DOMAIN, IRIS_APV_HW_POWER_DOMAIN, }; diff --git a/drivers/media/platform/qcom/iris/iris_vpu3x.c b/drivers/media/= platform/qcom/iris/iris_vpu3x.c index 1f0a3a47d87f..3f269f242b36 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu3x.c +++ b/drivers/media/platform/qcom/iris/iris_vpu3x.c @@ -27,6 +27,16 @@ static bool iris_vpu3x_hw_power_collapsed(struct iris_co= re *core) return pwr_status ? false : true; } =20 +static bool iris_vpu36_hw1_power_collapsed(struct iris_core *core) +{ + u32 value, pwr_status; + + value =3D readl(core->reg_base + WRAPPER_CORE_POWER_STATUS); + pwr_status =3D value & BIT(4); + + return pwr_status ? false : true; +} + static void iris_vpu3_power_off_hardware(struct iris_core *core) { u32 reg_val =3D 0, value, i; @@ -261,6 +271,111 @@ static void iris_vpu35_power_off_hw(struct iris_core = *core) iris_disable_unprepare_clock(core, IRIS_AXI_VCODEC_CLK); } =20 +static int iris_vpu36_power_on_hw1(struct iris_core *core) +{ + int ret; + + ret =3D iris_enable_power_domains(core, + core->pmdomain_tbl->pd_devs[IRIS_VCODEC1_POWER_DOMAIN]); + if (ret) + return ret; + + ret =3D iris_prepare_enable_clock(core, IRIS_AXI_VCODEC1_CLK); + if (ret) + goto err_disable_hw1_power; + + ret =3D iris_prepare_enable_clock(core, IRIS_VCODEC1_FREERUN_CLK); + if (ret) + goto err_disable_axi1_clk; + + ret =3D iris_prepare_enable_clock(core, IRIS_VCODEC1_CLK); + if (ret) + goto err_disable_hw1_free_clk; + + ret =3D dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_VCODEC1_= POWER_DOMAIN], true); + if (ret) + goto err_disable_hw1_clk; + + return 0; + +err_disable_hw1_clk: + iris_disable_unprepare_clock(core, IRIS_VCODEC1_CLK); +err_disable_hw1_free_clk: + iris_disable_unprepare_clock(core, IRIS_VCODEC1_FREERUN_CLK); +err_disable_axi1_clk: + iris_disable_unprepare_clock(core, IRIS_AXI_VCODEC1_CLK); +err_disable_hw1_power: + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_VCODEC1= _POWER_DOMAIN]); + + return ret; +} + +static int iris_vpu36_power_on_hw(struct iris_core *core) +{ + int ret; + + ret =3D iris_vpu35_power_on_hw(core); + if (ret) + return ret; + + ret =3D iris_vpu36_power_on_hw1(core); + if (ret) + goto err_power_off_hw; + + return 0; + +err_power_off_hw: + iris_vpu35_power_off_hw(core); + + return ret; +} + +static void iris_vpu36_power_off_hw1(struct iris_core *core) +{ + u32 value, i; + int ret; + + if (iris_vpu36_hw1_power_collapsed(core)) + goto disable_power; + + value =3D readl(core->reg_base + WRAPPER_CORE_CLOCK_CONFIG); + if (value) + writel(CORE_CLK_RUN, core->reg_base + WRAPPER_CORE_CLOCK_CONFIG); + + for (i =3D 0; i < core->iris_platform_data->num_vpp_pipe; i++) { + ret =3D readl_poll_timeout(core->reg_base + VCODEC1_SS_IDLE_STATUSN + 4 = * i, + value, value & DMA_NOC_IDLE, 2000, 20000); + if (ret) + goto disable_power; + } + + writel(REQ_VCODEC1_POWER_DOWN_PREP, core->reg_base + AON_WRAPPER_MVP_NOC_= LPI_CONTROL); + ret =3D readl_poll_timeout(core->reg_base + AON_WRAPPER_MVP_NOC_LPI_STATU= S, + value, value & NOC_LPI_VCODEC1_STATUS_DONE, 2000, 20000); + if (ret) + goto disable_power; + + writel(0, core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CONTROL); + + writel(VCODEC1_BRIDGE_SW_RESET | VCODEC1_BRIDGE_HW_RESET_DISABLE, core->r= eg_base + + CPU_CS_AHB_BRIDGE_SYNC_RESET); + writel(VCODEC1_BRIDGE_HW_RESET_DISABLE, core->reg_base + CPU_CS_AHB_BRIDG= E_SYNC_RESET); + writel(0x0, core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET); + +disable_power: + dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_VCODEC1_POWER_DO= MAIN], false); + iris_disable_unprepare_clock(core, IRIS_VCODEC1_CLK); + iris_disable_unprepare_clock(core, IRIS_VCODEC1_FREERUN_CLK); + iris_disable_unprepare_clock(core, IRIS_AXI_VCODEC1_CLK); + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_VCODEC1= _POWER_DOMAIN]); +} + +static void iris_vpu36_power_off_hw(struct iris_core *core) +{ + iris_vpu35_power_off_hw(core); + iris_vpu36_power_off_hw1(core); +} + const struct vpu_ops iris_vpu3_ops =3D { .power_off_hw =3D iris_vpu3_power_off_hardware, .power_on_hw =3D iris_vpu_power_on_hw, @@ -285,3 +400,11 @@ const struct vpu_ops iris_vpu35_ops =3D { .program_bootup_registers =3D iris_vpu35_vpu4x_program_bootup_registers, .calc_freq =3D iris_vpu3x_vpu4x_calculate_frequency, }; + +const struct vpu_ops iris_vpu36_ops =3D { + .power_off_hw =3D iris_vpu36_power_off_hw, + .power_on_hw =3D iris_vpu36_power_on_hw, + .power_off_controller =3D iris_vpu35_vpu4x_power_off_controller, + .power_on_controller =3D iris_vpu35_vpu4x_power_on_controller, + .calc_freq =3D iris_vpu3x_vpu4x_calculate_frequency, +}; diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.h b/drivers/m= edia/platform/qcom/iris/iris_vpu_common.h index f6dffc613b82..99e75fb4b10d 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_common.h +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.h @@ -12,6 +12,7 @@ extern const struct vpu_ops iris_vpu2_ops; extern const struct vpu_ops iris_vpu3_ops; extern const struct vpu_ops iris_vpu33_ops; extern const struct vpu_ops iris_vpu35_ops; +extern const struct vpu_ops iris_vpu36_ops; extern const struct vpu_ops iris_vpu4x_ops; =20 struct vpu_ops { diff --git a/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h b= /drivers/media/platform/qcom/iris/iris_vpu_register_defines.h index 72168b9ffa73..37f234484f1b 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h +++ b/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h @@ -7,6 +7,7 @@ #define __IRIS_VPU_REGISTER_DEFINES_H__ =20 #define VCODEC_BASE_OFFS 0x00000000 +#define VCODEC1_BASE_OFFS 0x00040000 #define AON_MVP_NOC_RESET 0x0001F000 #define CPU_BASE_OFFS 0x000A0000 #define WRAPPER_BASE_OFFS 0x000B0000 @@ -14,6 +15,8 @@ #define AON_BASE_OFFS 0x000E0000 =20 #define VCODEC_SS_IDLE_STATUSN (VCODEC_BASE_OFFS + 0x70) +#define VCODEC1_SS_IDLE_STATUSN (VCODEC1_BASE_OFFS + 0x70) +#define DMA_NOC_IDLE BIT(22) =20 #define AON_WRAPPER_MVP_NOC_RESET_REQ (AON_MVP_NOC_RESET + 0x000) #define VIDEO_NOC_RESET_REQ (BIT(0) | BIT(1)) @@ -35,6 +38,8 @@ #define CPU_CS_AHB_BRIDGE_SYNC_RESET (CPU_CS_BASE_OFFS + 0x160) #define CORE_BRIDGE_SW_RESET BIT(0) #define CORE_BRIDGE_HW_RESET_DISABLE BIT(1) +#define VCODEC1_BRIDGE_SW_RESET BIT(2) +#define VCODEC1_BRIDGE_HW_RESET_DISABLE BIT(3) =20 #define CPU_CS_X2RPMH (CPU_CS_BASE_OFFS + 0x168) #define MSK_SIGNAL_FROM_TENSILICA BIT(0) @@ -52,11 +57,13 @@ #define WRAPPER_DEBUG_BRIDGE_LPI_STATUS (WRAPPER_BASE_OFFS + 0x58) #define WRAPPER_IRIS_CPU_NOC_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x5C) #define REQ_POWER_DOWN_PREP BIT(0) +#define REQ_VCODEC1_POWER_DOWN_PREP BIT(1) =20 #define WRAPPER_IRIS_CPU_NOC_LPI_STATUS (WRAPPER_BASE_OFFS + 0x60) #define NOC_LPI_STATUS_DONE BIT(0) /* Indicates the NOC handshake is com= plete */ #define NOC_LPI_STATUS_DENY BIT(1) /* Indicates the NOC handshake is den= ied */ #define NOC_LPI_STATUS_ACTIVE BIT(2) /* Indicates the NOC is active */ +#define NOC_LPI_VCODEC1_STATUS_DONE BIT(8) =20 #define WRAPPER_IRIS_VCODEC_VPU_WRAPPER_SPARE_0 (WRAPPER_BASE_OFFS + 0x78) #define WRAPPER_CORE_POWER_STATUS (WRAPPER_BASE_OFFS + 0x80) --=20 2.34.1 From nobody Tue Apr 14 14:01:53 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3D4D126C385 for ; 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Assign the session to vcodec if its MBPF/MBPS capacity allows it, otherwise assign to vcodec1. Communicate the selected vcodec core to firmware using new HFI_PROP_CORE_ID property. Signed-off-by: Vishnu Reddy --- drivers/media/platform/qcom/iris/iris_common.c | 7 +++ drivers/media/platform/qcom/iris/iris_hfi_common.h | 1 + .../platform/qcom/iris/iris_hfi_gen2_command.c | 19 ++++++ .../platform/qcom/iris/iris_hfi_gen2_defines.h | 1 + drivers/media/platform/qcom/iris/iris_instance.h | 2 + .../platform/qcom/iris/iris_platform_common.h | 1 + drivers/media/platform/qcom/iris/iris_utils.c | 68 +++++++++++++++++-= ---- 7 files changed, 83 insertions(+), 16 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_common.c b/drivers/media= /platform/qcom/iris/iris_common.c index 7f1c7fe144f7..e31d4c988c55 100644 --- a/drivers/media/platform/qcom/iris/iris_common.c +++ b/drivers/media/platform/qcom/iris/iris_common.c @@ -49,11 +49,18 @@ void iris_set_ts_metadata(struct iris_inst *inst, struc= t vb2_v4l2_buffer *vbuf) int iris_process_streamon_input(struct iris_inst *inst) { const struct iris_hfi_command_ops *hfi_ops =3D inst->core->hfi_ops; + bool dual_core =3D inst->core->iris_platform_data->dual_core; enum iris_inst_sub_state set_sub_state =3D 0; int ret; =20 iris_scale_power(inst); =20 + if (dual_core) { + ret =3D hfi_ops->session_set_core_id(inst, inst->core_id); + if (ret) + return ret; + } + ret =3D hfi_ops->session_start(inst, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE); if (ret) return ret; diff --git a/drivers/media/platform/qcom/iris/iris_hfi_common.h b/drivers/m= edia/platform/qcom/iris/iris_hfi_common.h index 3edb5ae582b4..fbaf852a6b99 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_common.h +++ b/drivers/media/platform/qcom/iris/iris_hfi_common.h @@ -124,6 +124,7 @@ struct iris_hfi_command_ops { int (*session_drain)(struct iris_inst *inst, u32 plane); int (*session_resume_drain)(struct iris_inst *inst, u32 plane); int (*session_close)(struct iris_inst *inst); + int (*session_set_core_id)(struct iris_inst *inst, u32 core_id); }; =20 struct iris_hfi_response_ops { diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c b/dri= vers/media/platform/qcom/iris/iris_hfi_gen2_command.c index 30bfd90d423b..9d9fae587297 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c @@ -1300,6 +1300,24 @@ static int iris_hfi_gen2_session_release_buffer(stru= ct iris_inst *inst, struct i inst_hfi_gen2->packet->size); } =20 +static int iris_hfi_gen2_set_core_id(struct iris_inst *inst, u32 core_id) +{ + struct iris_inst_hfi_gen2 *inst_hfi_gen2 =3D to_iris_inst_hfi_gen2(inst); + u32 payload =3D core_id; + + iris_hfi_gen2_packet_session_command(inst, + HFI_PROP_CORE_ID, + HFI_HOST_FLAGS_NONE, + HFI_PORT_NONE, + inst->session_id, + HFI_PAYLOAD_U32, + &payload, + sizeof(u32)); + + return iris_hfi_queue_cmd_write(inst->core, inst_hfi_gen2->packet, + inst_hfi_gen2->packet->size); +} + static const struct iris_hfi_command_ops iris_hfi_gen2_command_ops =3D { .sys_init =3D iris_hfi_gen2_sys_init, .sys_image_version =3D iris_hfi_gen2_sys_image_version, @@ -1317,6 +1335,7 @@ static const struct iris_hfi_command_ops iris_hfi_gen= 2_command_ops =3D { .session_drain =3D iris_hfi_gen2_session_drain, .session_resume_drain =3D iris_hfi_gen2_session_resume_drain, .session_close =3D iris_hfi_gen2_session_close, + .session_set_core_id =3D iris_hfi_gen2_set_core_id, }; =20 void iris_hfi_gen2_command_ops_init(struct iris_core *core) diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2_defines.h b/dri= vers/media/platform/qcom/iris/iris_hfi_gen2_defines.h index cecf771c55dd..1926a5344427 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen2_defines.h +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2_defines.h @@ -56,6 +56,7 @@ #define HFI_PROP_BUFFER_HOST_MAX_COUNT 0x03000123 #define HFI_PROP_BUFFER_FW_MIN_OUTPUT_COUNT 0x03000124 #define HFI_PROP_PIC_ORDER_CNT_TYPE 0x03000128 +#define HFI_PROP_CORE_ID 0x030001A9 =20 enum hfi_rate_control { HFI_RC_VBR_CFR =3D 0x00000000, diff --git a/drivers/media/platform/qcom/iris/iris_instance.h b/drivers/med= ia/platform/qcom/iris/iris_instance.h index 16965150f427..dd341ca5be57 100644 --- a/drivers/media/platform/qcom/iris/iris_instance.h +++ b/drivers/media/platform/qcom/iris/iris_instance.h @@ -37,6 +37,7 @@ struct iris_fmt { * * @list: used for attach an instance to the core * @core: pointer to core structure + * @core_id: specifies the hardware core on which the session runs * @session_id: id of current video session * @ctx_q_lock: lock to serialize queues related ioctls * @lock: lock to seralise forward and reverse threads @@ -79,6 +80,7 @@ struct iris_fmt { struct iris_inst { struct list_head list; struct iris_core *core; + u32 core_id; u32 session_id; struct mutex ctx_q_lock;/* lock to serialize queues related ioctls */ struct mutex lock; /* lock to serialize forward and reverse threads */ diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/driv= ers/media/platform/qcom/iris/iris_platform_common.h index e3c1aff770dd..aeb70f54be10 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -258,6 +258,7 @@ struct iris_platform_data { const struct tz_cp_config *tz_cp_config_data; u32 tz_cp_config_data_size; u32 core_arch; + bool dual_core; u32 hw_response_timeout; struct ubwc_config_data *ubwc_config; u32 num_vpp_pipe; diff --git a/drivers/media/platform/qcom/iris/iris_utils.c b/drivers/media/= platform/qcom/iris/iris_utils.c index cfc5b576ec56..38ede9f76d0b 100644 --- a/drivers/media/platform/qcom/iris/iris_utils.c +++ b/drivers/media/platform/qcom/iris/iris_utils.c @@ -90,18 +90,51 @@ struct iris_inst *iris_get_instance(struct iris_core *c= ore, u32 session_id) return NULL; } =20 -int iris_check_core_mbpf(struct iris_inst *inst) +static u32 iris_get_mbps(struct iris_inst *inst) { - struct iris_core *core =3D inst->core; - struct iris_inst *instance; - u32 total_mbpf =3D 0; + u32 fps =3D max(inst->frame_rate, inst->operating_rate); + + return iris_get_mbpf(inst) * fps; +} + +static void iris_get_core_load(struct iris_core *core, u32 *core_load, boo= l mbpf) +{ + bool dual_core =3D core->iris_platform_data->dual_core; + struct iris_inst *inst; + u32 load; =20 mutex_lock(&core->lock); - list_for_each_entry(instance, &core->instances, list) - total_mbpf +=3D iris_get_mbpf(instance); + list_for_each_entry(inst, &core->instances, list) { + if (mbpf) + load =3D iris_get_mbpf(inst); + else + load =3D iris_get_mbps(inst); + + if (inst->core_id =3D=3D BIT(0)) + core_load[0] +=3D load; + else if (dual_core && inst->core_id =3D=3D BIT(1)) + core_load[1] +=3D load; + } mutex_unlock(&core->lock); +} =20 - if (total_mbpf > core->iris_platform_data->max_core_mbpf) +int iris_check_core_mbpf(struct iris_inst *inst) +{ + struct iris_core *core =3D inst->core; + u32 max_core_mbpf =3D core->iris_platform_data->max_core_mbpf; + bool dual_core =3D core->iris_platform_data->dual_core; + u32 core_mbpf[2] =3D {0, 0}, new_mbpf; + + inst->core_id =3D 0; + iris_get_core_load(core, core_mbpf, true); + new_mbpf =3D iris_get_mbpf(inst); + + if (core_mbpf[0] + new_mbpf <=3D max_core_mbpf) + inst->core_id =3D BIT(0); + else if (dual_core && core_mbpf[1] + new_mbpf <=3D max_core_mbpf) + inst->core_id =3D BIT(1); + + if (!inst->core_id) return -ENOMEM; =20 return 0; @@ -110,17 +143,20 @@ int iris_check_core_mbpf(struct iris_inst *inst) int iris_check_core_mbps(struct iris_inst *inst) { struct iris_core *core =3D inst->core; - struct iris_inst *instance; - u32 total_mbps =3D 0, fps =3D 0; + u32 max_core_mbps =3D core->iris_platform_data->max_core_mbps; + bool dual_core =3D core->iris_platform_data->dual_core; + u32 core_mbps[2] =3D {0, 0}, new_mbps; =20 - mutex_lock(&core->lock); - list_for_each_entry(instance, &core->instances, list) { - fps =3D max(instance->frame_rate, instance->operating_rate); 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Move configuration that differs in a per-SoC platform specific data. Signed-off-by: Vishnu Reddy --- drivers/media/platform/qcom/iris/Makefile | 1 + .../platform/qcom/iris/iris_platform_common.h | 1 + .../media/platform/qcom/iris/iris_platform_gen2.c | 100 +++++++++++++++++= ++++ .../platform/qcom/iris/iris_platform_glymur.c | 93 +++++++++++++++++= ++ .../platform/qcom/iris/iris_platform_glymur.h | 17 ++++ drivers/media/platform/qcom/iris/iris_probe.c | 4 + 6 files changed, 216 insertions(+) diff --git a/drivers/media/platform/qcom/iris/Makefile b/drivers/media/plat= form/qcom/iris/Makefile index 6f4052b98491..677513c7c045 100644 --- a/drivers/media/platform/qcom/iris/Makefile +++ b/drivers/media/platform/qcom/iris/Makefile @@ -11,6 +11,7 @@ qcom-iris-objs +=3D iris_buffer.o \ iris_hfi_gen2_response.o \ iris_hfi_queue.o \ iris_platform_gen2.o \ + iris_platform_glymur.o \ iris_power.o \ iris_probe.o \ iris_resources.o \ diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/driv= ers/media/platform/qcom/iris/iris_platform_common.h index aeb70f54be10..a279ea462ee6 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -41,6 +41,7 @@ enum pipe_type { PIPE_4 =3D 4, }; =20 +extern const struct iris_platform_data glymur_data; extern const struct iris_platform_data qcs8300_data; extern const struct iris_platform_data sc7280_data; extern const struct iris_platform_data sm8250_data; diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/driver= s/media/platform/qcom/iris/iris_platform_gen2.c index 47c6b650f0b4..fa2115092be8 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c @@ -12,6 +12,7 @@ #include "iris_vpu_buffer.h" #include "iris_vpu_common.h" =20 +#include "iris_platform_glymur.h" #include "iris_platform_qcs8300.h" #include "iris_platform_sm8650.h" #include "iris_platform_sm8750.h" @@ -921,6 +922,105 @@ static const u32 sm8550_enc_op_int_buf_tbl[] =3D { BUF_SCRATCH_2, }; =20 +const struct iris_platform_data glymur_data =3D { + .get_instance =3D iris_hfi_gen2_get_instance, + .init_hfi_command_ops =3D iris_hfi_gen2_command_ops_init, + .init_hfi_response_ops =3D iris_hfi_gen2_response_ops_init, + .get_vpu_buffer_size =3D iris_vpu_buf_size, + .vpu_ops =3D &iris_vpu36_ops, + .set_preset_registers =3D iris_set_sm8550_preset_registers, + .init_cb_devs =3D glymur_init_cb_devs, + .deinit_cb_devs =3D glymur_deinit_cb_devs, + .icc_tbl =3D sm8550_icc_table, + .icc_tbl_size =3D ARRAY_SIZE(sm8550_icc_table), + .clk_rst_tbl =3D glymur_clk_reset_table, + .clk_rst_tbl_size =3D ARRAY_SIZE(glymur_clk_reset_table), + .bw_tbl_dec =3D sm8550_bw_table_dec, + .bw_tbl_dec_size =3D ARRAY_SIZE(sm8550_bw_table_dec), + .pmdomain_tbl =3D glymur_pmdomain_table, + .pmdomain_tbl_size =3D ARRAY_SIZE(glymur_pmdomain_table), + .opp_pd_tbl =3D sm8550_opp_pd_table, + .opp_pd_tbl_size =3D ARRAY_SIZE(sm8550_opp_pd_table), + .clk_tbl =3D glymur_clk_table, + .clk_tbl_size =3D ARRAY_SIZE(glymur_clk_table), + .opp_clk_tbl =3D glymur_opp_clk_table, + /* Upper bound of DMA address range */ + .dma_mask =3D 0xffe00000 - 1, + .fwname =3D "qcom/vpu/vpu36_p4_s7.mbn", + .pas_id =3D IRIS_PAS_ID, + .dual_core =3D true, + .inst_iris_fmts =3D platform_fmts_sm8550_dec, + .inst_iris_fmts_size =3D ARRAY_SIZE(platform_fmts_sm8550_dec), + .inst_caps =3D &platform_inst_cap_sm8550, + .inst_fw_caps_dec =3D inst_fw_cap_sm8550_dec, + .inst_fw_caps_dec_size =3D ARRAY_SIZE(inst_fw_cap_sm8550_dec), + .inst_fw_caps_enc =3D inst_fw_cap_sm8550_enc, + .inst_fw_caps_enc_size =3D ARRAY_SIZE(inst_fw_cap_sm8550_enc), + .tz_cp_config_data =3D tz_cp_config_glymur, + .tz_cp_config_data_size =3D ARRAY_SIZE(tz_cp_config_glymur), + .core_arch =3D VIDEO_ARCH_LX, + .hw_response_timeout =3D HW_RESPONSE_TIMEOUT_VALUE, + .ubwc_config =3D &ubwc_config_sm8550, + .num_vpp_pipe =3D 4, + .max_session_count =3D 16, + .max_core_mbpf =3D NUM_MBS_8K * 2, + .max_core_mbps =3D ((8192 * 4320) / 256) * 60, + .dec_input_config_params_default =3D + sm8550_vdec_input_config_params_default, + .dec_input_config_params_default_size =3D + ARRAY_SIZE(sm8550_vdec_input_config_params_default), + .dec_input_config_params_hevc =3D + sm8550_vdec_input_config_param_hevc, + .dec_input_config_params_hevc_size =3D + ARRAY_SIZE(sm8550_vdec_input_config_param_hevc), + .dec_input_config_params_vp9 =3D + sm8550_vdec_input_config_param_vp9, + .dec_input_config_params_vp9_size =3D + ARRAY_SIZE(sm8550_vdec_input_config_param_vp9), + .dec_input_config_params_av1 =3D + sm8550_vdec_input_config_param_av1, + .dec_input_config_params_av1_size =3D + ARRAY_SIZE(sm8550_vdec_input_config_param_av1), + .dec_output_config_params =3D + sm8550_vdec_output_config_params, + .dec_output_config_params_size =3D + ARRAY_SIZE(sm8550_vdec_output_config_params), + + .enc_input_config_params =3D + sm8550_venc_input_config_params, + .enc_input_config_params_size =3D + ARRAY_SIZE(sm8550_venc_input_config_params), + .enc_output_config_params =3D + sm8550_venc_output_config_params, + .enc_output_config_params_size =3D + ARRAY_SIZE(sm8550_venc_output_config_params), + + .dec_input_prop =3D sm8550_vdec_subscribe_input_properties, + .dec_input_prop_size =3D ARRAY_SIZE(sm8550_vdec_subscribe_input_propertie= s), + .dec_output_prop_avc =3D sm8550_vdec_subscribe_output_properties_avc, + .dec_output_prop_avc_size =3D + ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_avc), + .dec_output_prop_hevc =3D sm8550_vdec_subscribe_output_properties_hevc, + .dec_output_prop_hevc_size =3D + ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_hevc), + .dec_output_prop_vp9 =3D sm8550_vdec_subscribe_output_properties_vp9, + .dec_output_prop_vp9_size =3D + ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_vp9), + .dec_output_prop_av1 =3D sm8550_vdec_subscribe_output_properties_av1, + .dec_output_prop_av1_size =3D + ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_av1), + + .dec_ip_int_buf_tbl =3D sm8550_dec_ip_int_buf_tbl, + .dec_ip_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_dec_ip_int_buf_tbl), + .dec_op_int_buf_tbl =3D sm8550_dec_op_int_buf_tbl, + .dec_op_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_dec_op_int_buf_tbl), + + .enc_ip_int_buf_tbl =3D sm8550_enc_ip_int_buf_tbl, + .enc_ip_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_enc_ip_int_buf_tbl), + .enc_op_int_buf_tbl =3D sm8550_enc_op_int_buf_tbl, + .enc_op_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_enc_op_int_buf_tbl), +}; + const struct iris_platform_data sm8550_data =3D { .get_instance =3D iris_hfi_gen2_get_instance, .init_hfi_command_ops =3D iris_hfi_gen2_command_ops_init, diff --git a/drivers/media/platform/qcom/iris/iris_platform_glymur.c b/driv= ers/media/platform/qcom/iris/iris_platform_glymur.c new file mode 100644 index 000000000000..64b150db9f73 --- /dev/null +++ b/drivers/media/platform/qcom/iris/iris_platform_glymur.c @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include "iris_core.h" +#include "iris_platform_common.h" +#include "iris_platform_glymur.h" + +#define VIDEO_REGION_SECURE_FW_REGION_ID 0 +#define VIDEO_REGION_VM0_SECURE_NP_ID 1 +#define VIDEO_REGION_VM0_NONSECURE_NP_ID 5 + +const struct platform_clk_data glymur_clk_table[] =3D { + {IRIS_AXI_VCODEC_CLK, "iface" }, + {IRIS_CTRL_CLK, "core" }, + {IRIS_VCODEC_CLK, "vcodec0_core" }, + {IRIS_AXI_CTRL_CLK, "iface_ctrl" }, + {IRIS_CTRL_FREERUN_CLK, "core_freerun" }, + {IRIS_VCODEC_FREERUN_CLK, "vcodec0_core_freerun" }, + {IRIS_AXI_VCODEC1_CLK, "iface1" }, + {IRIS_VCODEC1_CLK, "vcodec1_core" }, + {IRIS_VCODEC1_FREERUN_CLK, "vcodec1_core_freerun" }, +}; + +const char * const glymur_clk_reset_table[] =3D { + "bus0", + "bus_ctrl", + "core", + "vcodec0_core", + "bus1", + "vcodec1_core", +}; + +const char * const glymur_opp_clk_table[] =3D { + "vcodec0_core", + "vcodec1_core", + "core", + NULL, +}; + +const char * const glymur_pmdomain_table[] =3D { + "venus", + "vcodec0", + "vcodec1", +}; + +const struct tz_cp_config tz_cp_config_glymur[] =3D { + { + .cp_start =3D VIDEO_REGION_SECURE_FW_REGION_ID, + .cp_size =3D 0, + .cp_nonpixel_start =3D 0, + .cp_nonpixel_size =3D 0x1000000, + }, + { + .cp_start =3D VIDEO_REGION_VM0_SECURE_NP_ID, + .cp_size =3D 0, + .cp_nonpixel_start =3D 0x1000000, + .cp_nonpixel_size =3D 0x24800000, + }, + { + .cp_start =3D VIDEO_REGION_VM0_NONSECURE_NP_ID, + .cp_size =3D 0, + .cp_nonpixel_start =3D 0x25800000, + .cp_nonpixel_size =3D 0xda600000, + }, +}; + +int glymur_init_cb_devs(struct iris_core *core) +{ + const u32 f_id =3D IRIS_FIRMWARE; + struct device *dev; + + dev =3D iris_create_cb_dev(core, "iris_firmware", &f_id); + if (IS_ERR(dev)) + return PTR_ERR(dev); + + if (device_iommu_mapped(dev)) + core->dev_fw =3D dev; + else + device_unregister(dev); + + return 0; +} + +void glymur_deinit_cb_devs(struct iris_core *core) +{ + if (core->dev_fw) + device_unregister(core->dev_fw); + + core->dev_fw =3D NULL; +} diff --git a/drivers/media/platform/qcom/iris/iris_platform_glymur.h b/driv= ers/media/platform/qcom/iris/iris_platform_glymur.h new file mode 100644 index 000000000000..03c83922f0d9 --- /dev/null +++ b/drivers/media/platform/qcom/iris/iris_platform_glymur.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef __IRIS_PLATFORM_GLYMUR_H__ +#define __IRIS_PLATFORM_GLYMUR_H__ + +extern const struct platform_clk_data glymur_clk_table[9]; +extern const char * const glymur_clk_reset_table[6]; +extern const char * const glymur_opp_clk_table[4]; +extern const char * const glymur_pmdomain_table[3]; +extern const struct tz_cp_config tz_cp_config_glymur[3]; +int glymur_init_cb_devs(struct iris_core *core); +void glymur_deinit_cb_devs(struct iris_core *core); + +#endif diff --git a/drivers/media/platform/qcom/iris/iris_probe.c b/drivers/media/= platform/qcom/iris/iris_probe.c index 34751912f871..53869d9113d5 100644 --- a/drivers/media/platform/qcom/iris/iris_probe.c +++ b/drivers/media/platform/qcom/iris/iris_probe.c @@ -369,6 +369,10 @@ static const struct dev_pm_ops iris_pm_ops =3D { }; =20 static const struct of_device_id iris_dt_match[] =3D { + { + .compatible =3D "qcom,glymur-iris", + .data =3D &glymur_data, + }, { .compatible =3D "qcom,qcs8300-iris", .data =3D &qcs8300_data, --=20 2.34.1 From nobody Tue Apr 14 14:01:53 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E6B673064B2 for ; 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Signed-off-by: Vishnu Reddy --- arch/arm64/boot/dts/qcom/glymur-crd.dts | 4 ++ arch/arm64/boot/dts/qcom/glymur.dtsi | 118 ++++++++++++++++++++++++++++= ++++ 2 files changed, 122 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dts b/arch/arm64/boot/dts/= qcom/glymur-crd.dts index 35aaf09e4e2b..cbc9856956ff 100644 --- a/arch/arm64/boot/dts/qcom/glymur-crd.dts +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dts @@ -255,6 +255,10 @@ &mdss_dp3_phy { status =3D "okay"; }; =20 +&iris { + status =3D "okay"; +}; + &pmh0110_f_e0_gpios { misc_3p3_reg_en: misc-3p3-reg-en-state { pins =3D "gpio6"; diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qco= m/glymur.dtsi index f23cf81ddb77..e139b2d2e33e 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -4163,6 +4164,123 @@ usb_mp: usb@a400000 { status =3D "disabled"; }; =20 + iris: video-codec@aa00000 { + compatible =3D "qcom,glymur-iris"; + reg =3D <0x0 0xaa00000 0x0 0xf0000>; + + clocks =3D <&gcc GCC_VIDEO_AXI0_CLK>, + <&videocc VIDEO_CC_MVS0C_CLK>, + <&videocc VIDEO_CC_MVS0_CLK>, + <&gcc GCC_VIDEO_AXI0C_CLK>, + <&videocc VIDEO_CC_MVS0C_FREERUN_CLK>, + <&videocc VIDEO_CC_MVS0_FREERUN_CLK>, + <&gcc GCC_VIDEO_AXI1_CLK>, + <&videocc VIDEO_CC_MVS1_CLK>, + <&videocc VIDEO_CC_MVS1_FREERUN_CLK>; + clock-names =3D "iface", + "core", + "vcodec0_core", + "iface_ctrl", + "core_freerun", + "vcodec0_core_freerun", + "iface1", + "vcodec1_core", + "vcodec1_core_freerun"; + + dma-coherent; + + interconnects =3D <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mmss_noc MASTER_VIDEO QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "cpu-cfg", + "video-mem"; + + interrupts =3D ; + + iommus =3D <&apps_smmu 0x1940 0x0>, + <&apps_smmu 0x1943 0x0>, + <&apps_smmu 0x1944 0x0>, + <&apps_smmu 0x19e0 0x0>; + + iommu-map =3D ; + + memory-region =3D <&video_mem>; + + operating-points-v2 =3D <&iris_opp_table>; + + power-domains =3D <&videocc VIDEO_CC_MVS0C_GDSC>, + <&videocc VIDEO_CC_MVS0_GDSC>, + <&rpmhpd RPMHPD_MXC>, + <&rpmhpd RPMHPD_MMCX>, + <&videocc VIDEO_CC_MVS1_GDSC>; + power-domain-names =3D "venus", + "vcodec0", + "mxc", + "mmcx", + "vcodec1"; + + resets =3D <&gcc GCC_VIDEO_AXI0_CLK_ARES>, + <&gcc GCC_VIDEO_AXI0C_CLK_ARES>, + <&videocc VIDEO_CC_MVS0C_FREERUN_CLK_ARES>, + <&videocc VIDEO_CC_MVS0_FREERUN_CLK_ARES>, + <&gcc GCC_VIDEO_AXI1_CLK_ARES>, + <&videocc VIDEO_CC_MVS1_FREERUN_CLK_ARES>; + reset-names =3D "bus0", + "bus_ctrl", + "core", + "vcodec0_core", + "bus1", + "vcodec1_core"; + + /* + * IRIS firmware is signed by vendors, only + * enable on boards where the proper signed firmware + * is available. + */ + status =3D "disabled"; + + iris_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-240000000 { + opp-hz =3D /bits/ 64 <240000000 240000000 360000000>; + required-opps =3D <&rpmhpd_opp_svs>, + <&rpmhpd_opp_low_svs>; + }; + + opp-338000000 { + opp-hz =3D /bits/ 64 <338000000 338000000 507000000>; + required-opps =3D <&rpmhpd_opp_svs>, + <&rpmhpd_opp_svs>; + }; + + opp-366000000 { + opp-hz =3D /bits/ 64 <366000000 366000000 549000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>, + <&rpmhpd_opp_svs_l1>; + }; + + opp-444000000 { + opp-hz =3D /bits/ 64 <444000000 444000000 666000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>, + <&rpmhpd_opp_nom>; + }; + + opp-533333334 { + opp-hz =3D /bits/ 64 <533333334 533333334 800000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>, + <&rpmhpd_opp_turbo>; + }; + + opp-655000000 { + opp-hz =3D /bits/ 64 <655000000 655000000 982000000>; + required-opps =3D <&rpmhpd_opp_nom>, + <&rpmhpd_opp_turbo_l1>; + }; + }; + }; + mdss: display-subsystem@ae00000 { compatible =3D "qcom,glymur-mdss"; reg =3D <0x0 0x0ae00000 0x0 0x1000>; --=20 2.34.1