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charset="utf-8" Convert the LPASS LPI pinctrl driver to use the PM clock framework for runtime power management. This allows the LPASS LPI pinctrl driver to drop clock votes when idle, improves power efficiency on platforms using LPASS LPI island mode, and aligns the driver with common runtime PM patterns used across Qualcomm LPASS subsystems. Signed-off-by: Ajay Kumar Nandam --- drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 36 +++++++++++++------ drivers/pinctrl/qcom/pinctrl-lpass-lpi.h | 2 ++ .../pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c | 5 +++ 3 files changed, 32 insertions(+), 11 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qco= m/pinctrl-lpass-lpi.c index 76aed3296..6d50e06ef 100644 --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c @@ -14,15 +14,16 @@ =20 #include #include +#include #include =20 #include "../pinctrl-utils.h" =20 #include "pinctrl-lpass-lpi.h" +#include =20 #define MAX_NR_GPIO 32 #define GPIO_FUNC 0 -#define MAX_LPI_NUM_CLKS 2 =20 struct lpi_pinctrl { struct device *dev; @@ -31,7 +32,6 @@ struct lpi_pinctrl { struct pinctrl_desc desc; char __iomem *tlmm_base; char __iomem *slew_base; - struct clk_bulk_data clks[MAX_LPI_NUM_CLKS]; /* Protects from concurrent register updates */ struct mutex lock; DECLARE_BITMAP(ever_gpio, MAX_NR_GPIO); @@ -480,9 +480,6 @@ int lpi_pinctrl_probe(struct platform_device *pdev) pctrl->data =3D data; pctrl->dev =3D &pdev->dev; =20 - pctrl->clks[0].id =3D "core"; - pctrl->clks[1].id =3D "audio"; - pctrl->tlmm_base =3D devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(pctrl->tlmm_base)) return dev_err_probe(dev, PTR_ERR(pctrl->tlmm_base), @@ -495,13 +492,17 @@ int lpi_pinctrl_probe(struct platform_device *pdev) "Slew resource not provided\n"); } =20 - ret =3D devm_clk_bulk_get_optional(dev, MAX_LPI_NUM_CLKS, pctrl->clks); + ret =3D devm_pm_clk_create(dev); if (ret) return ret; =20 - ret =3D clk_bulk_prepare_enable(MAX_LPI_NUM_CLKS, pctrl->clks); - if (ret) - return dev_err_probe(dev, ret, "Can't enable clocks\n"); + ret =3D of_pm_clk_add_clks(dev); + if (ret < 0) + return ret; + + pm_runtime_set_autosuspend_delay(dev, 100); + pm_runtime_use_autosuspend(dev); + pm_runtime_enable(dev); =20 pctrl->desc.pctlops =3D &lpi_gpio_pinctrl_ops; pctrl->desc.pmxops =3D &lpi_gpio_pinmux_ops; @@ -539,20 +540,33 @@ int lpi_pinctrl_probe(struct platform_device *pdev) return 0; =20 err_pinctrl: + pm_runtime_disable(dev); mutex_destroy(&pctrl->lock); - clk_bulk_disable_unprepare(MAX_LPI_NUM_CLKS, pctrl->clks); =20 return ret; } EXPORT_SYMBOL_GPL(lpi_pinctrl_probe); =20 +int lpi_pinctrl_runtime_suspend(struct device *dev) +{ + return pm_clk_suspend(dev); +} +EXPORT_SYMBOL_GPL(lpi_pinctrl_runtime_suspend); + +int lpi_pinctrl_runtime_resume(struct device *dev) +{ + return pm_clk_resume(dev); +} +EXPORT_SYMBOL_GPL(lpi_pinctrl_runtime_resume); + void lpi_pinctrl_remove(struct platform_device *pdev) { struct lpi_pinctrl *pctrl =3D platform_get_drvdata(pdev); int i; =20 + pm_runtime_disable(pctrl->dev); + mutex_destroy(&pctrl->lock); - clk_bulk_disable_unprepare(MAX_LPI_NUM_CLKS, pctrl->clks); =20 for (i =3D 0; i < pctrl->data->npins; i++) pinctrl_generic_remove_group(pctrl->ctrl, i); diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h b/drivers/pinctrl/qco= m/pinctrl-lpass-lpi.h index f48368492..ae94ef48d 100644 --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h @@ -107,5 +107,7 @@ struct lpi_pinctrl_variant_data { =20 int lpi_pinctrl_probe(struct platform_device *pdev); void lpi_pinctrl_remove(struct platform_device *pdev); +int lpi_pinctrl_runtime_suspend(struct device *dev); +int lpi_pinctrl_runtime_resume(struct device *dev); =20 #endif /*__PINCTRL_LPASS_LPI_H__*/ diff --git a/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c b/drivers/pinc= trl/qcom/pinctrl-sc7280-lpass-lpi.c index 750f41031..2d955643d 100644 --- a/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c @@ -139,10 +139,15 @@ static const struct of_device_id lpi_pinctrl_of_match= [] =3D { }; MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); =20 +static const struct dev_pm_ops lpi_pinctrl_pm_ops =3D { + RUNTIME_PM_OPS(lpi_pinctrl_runtime_suspend, lpi_pinctrl_runtime_resume, N= ULL) +}; + static struct platform_driver lpi_pinctrl_driver =3D { .driver =3D { .name =3D "qcom-sc7280-lpass-lpi-pinctrl", .of_match_table =3D lpi_pinctrl_of_match, + .pm =3D pm_ptr(&lpi_pinctrl_pm_ops), }, .probe =3D lpi_pinctrl_probe, .remove =3D lpi_pinctrl_remove, --=20 2.34.1 From nobody Sat Jun 20 16:31:06 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6809C3C455B for ; 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charset="utf-8" The LPI GPIO register access helpers previously returned the value from ioread32(), even though their return type was int. This mixes data return with status and is inconsistent with common kernel helper conventions. Rework lpi_gpio_read() and lpi_gpio_write() to return an int status and use output parameters to pass register values. Update all callers to match the new helper interface. This change fixes the helper API and resulting call sites without intending any functional change in GPIO or pinctrl behavior. Signed-off-by: Ajay Kumar Nandam --- drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 66 +++++++++++++++++------- 1 file changed, 47 insertions(+), 19 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qco= m/pinctrl-lpass-lpi.c index 6d50e06ef..d108e7321 100644 --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c @@ -39,22 +39,26 @@ struct lpi_pinctrl { }; =20 static int lpi_gpio_read(struct lpi_pinctrl *state, unsigned int pin, - unsigned int addr) + unsigned int addr, u32 *val) { u32 pin_offset; + int ret; =20 if (state->data->flags & LPI_FLAG_USE_PREDEFINED_PIN_OFFSET) pin_offset =3D state->data->groups[pin].pin_offset; else pin_offset =3D LPI_TLMM_REG_OFFSET * pin; =20 - return ioread32(state->tlmm_base + pin_offset + addr); + *val =3D ioread32(state->tlmm_base + pin_offset + addr); + + return 0; } =20 static int lpi_gpio_write(struct lpi_pinctrl *state, unsigned int pin, unsigned int addr, unsigned int val) { u32 pin_offset; + int ret; =20 if (state->data->flags & LPI_FLAG_USE_PREDEFINED_PIN_OFFSET) pin_offset =3D state->data->groups[pin].pin_offset; @@ -107,7 +111,8 @@ static int lpi_gpio_set_mux(struct pinctrl_dev *pctldev= , unsigned int function, { struct lpi_pinctrl *pctrl =3D pinctrl_dev_get_drvdata(pctldev); const struct lpi_pingroup *g =3D &pctrl->data->groups[group]; - u32 val; + u32 val, io_val; + int ret; int i, pin =3D g->pin; =20 for (i =3D 0; i < g->nfuncs; i++) { @@ -119,7 +124,9 @@ static int lpi_gpio_set_mux(struct pinctrl_dev *pctldev= , unsigned int function, return -EINVAL; =20 mutex_lock(&pctrl->lock); - val =3D lpi_gpio_read(pctrl, pin, LPI_GPIO_CFG_REG); + ret =3D lpi_gpio_read(pctrl, pin, LPI_GPIO_CFG_REG, &val); + if (ret) + goto out_unlock; =20 /* * If this is the first time muxing to GPIO and the direction is @@ -129,24 +136,28 @@ static int lpi_gpio_set_mux(struct pinctrl_dev *pctld= ev, unsigned int function, */ if (i =3D=3D GPIO_FUNC && (val & LPI_GPIO_OE_MASK) && !test_and_set_bit(group, pctrl->ever_gpio)) { - u32 io_val =3D lpi_gpio_read(pctrl, group, LPI_GPIO_VALUE_REG); + ret =3D lpi_gpio_read(pctrl, group, LPI_GPIO_VALUE_REG, &io_val); + if (ret) + goto out_unlock; =20 if (io_val & LPI_GPIO_VALUE_IN_MASK) { if (!(io_val & LPI_GPIO_VALUE_OUT_MASK)) - lpi_gpio_write(pctrl, group, LPI_GPIO_VALUE_REG, - io_val | LPI_GPIO_VALUE_OUT_MASK); + ret =3D lpi_gpio_write(pctrl, group, LPI_GPIO_VALUE_REG, + io_val | LPI_GPIO_VALUE_OUT_MASK); } else { if (io_val & LPI_GPIO_VALUE_OUT_MASK) - lpi_gpio_write(pctrl, group, LPI_GPIO_VALUE_REG, - io_val & ~LPI_GPIO_VALUE_OUT_MASK); + ret =3D lpi_gpio_write(pctrl, group, LPI_GPIO_VALUE_REG, + io_val & ~LPI_GPIO_VALUE_OUT_MASK); } } =20 u32p_replace_bits(&val, i, LPI_GPIO_FUNCTION_MASK); - lpi_gpio_write(pctrl, pin, LPI_GPIO_CFG_REG, val); + ret =3D lpi_gpio_write(pctrl, pin, LPI_GPIO_CFG_REG, val); + +out_unlock: mutex_unlock(&pctrl->lock); =20 - return 0; + return ret; } =20 static const struct pinmux_ops lpi_gpio_pinmux_ops =3D { @@ -165,8 +176,11 @@ static int lpi_config_get(struct pinctrl_dev *pctldev, int is_out; int pull; u32 ctl_reg; + int ret; =20 - ctl_reg =3D lpi_gpio_read(state, pin, LPI_GPIO_CFG_REG); + ret =3D lpi_gpio_read(state, pin, LPI_GPIO_CFG_REG, &ctl_reg); + if (ret) + return ret; is_out =3D ctl_reg & LPI_GPIO_OE_MASK; pull =3D FIELD_GET(LPI_GPIO_PULL_MASK, ctl_reg); =20 @@ -293,17 +307,22 @@ static int lpi_config_set(struct pinctrl_dev *pctldev= , unsigned int group, } =20 mutex_lock(&pctrl->lock); - val =3D lpi_gpio_read(pctrl, group, LPI_GPIO_CFG_REG); + ret =3D lpi_gpio_read(pctrl, group, LPI_GPIO_CFG_REG, &val); + if (ret) { + mutex_unlock(&pctrl->lock); + goto out_unlock; + } =20 u32p_replace_bits(&val, pullup, LPI_GPIO_PULL_MASK); u32p_replace_bits(&val, LPI_GPIO_DS_TO_VAL(strength), LPI_GPIO_OUT_STRENGTH_MASK); u32p_replace_bits(&val, output_enabled, LPI_GPIO_OE_MASK); =20 - lpi_gpio_write(pctrl, group, LPI_GPIO_CFG_REG, val); - mutex_unlock(&pctrl->lock); + ret =3D lpi_gpio_write(pctrl, group, LPI_GPIO_CFG_REG, val); =20 - return 0; +out_unlock: + mutex_unlock(&pctrl->lock); + return ret; } =20 static const struct pinconf_ops lpi_gpio_pinconf_ops =3D { @@ -352,9 +371,13 @@ static int lpi_gpio_direction_output(struct gpio_chip = *chip, static int lpi_gpio_get(struct gpio_chip *chip, unsigned int pin) { struct lpi_pinctrl *state =3D gpiochip_get_data(chip); + u32 val; + int ret; =20 - return lpi_gpio_read(state, pin, LPI_GPIO_VALUE_REG) & - LPI_GPIO_VALUE_IN_MASK; + ret =3D lpi_gpio_read(state, pin, LPI_GPIO_VALUE_REG, &val); + if (ret) + return ret; + return val & LPI_GPIO_VALUE_IN_MASK; } =20 static int lpi_gpio_set(struct gpio_chip *chip, unsigned int pin, int valu= e) @@ -387,6 +410,7 @@ static void lpi_gpio_dbg_show_one(struct seq_file *s, int drive; int pull; u32 ctl_reg; + int ret; =20 static const char * const pulls[] =3D { "no pull", @@ -397,7 +421,11 @@ static void lpi_gpio_dbg_show_one(struct seq_file *s, =20 pctldev =3D pctldev ? : state->ctrl; pindesc =3D pctldev->desc->pins[offset]; - ctl_reg =3D lpi_gpio_read(state, offset, LPI_GPIO_CFG_REG); + ret =3D lpi_gpio_read(state, offset, LPI_GPIO_CFG_REG, &ctl_reg); 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Mon, 13 Apr 2026 05:22:56 -0700 (PDT) Received: from hu-nandam-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 00721157ae682-7af400eb1fasm50781657b3.44.2026.04.13.05.22.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Apr 2026 05:22:56 -0700 (PDT) From: Ajay Kumar Nandam To: Bjorn Andersson , Linus Walleij Cc: linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, srinivas.kandagatla@oss.qualcomm.com Subject: [PATCH v1 3/3] pinctrl: qcom: lpass-lpi: Resume clocks for GPIO access Date: Mon, 13 Apr 2026 17:52:33 +0530 Message-Id: <20260413122233.375945-4-ajay.nandam@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260413122233.375945-1-ajay.nandam@oss.qualcomm.com> References: <20260413122233.375945-1-ajay.nandam@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDEzMDEyMiBTYWx0ZWRfX0rVOLfLEsw8p olEINrZMqVgwd84HsxwLvomGNmb2GPqj23CZc/BMezIbWI+XmYjEsNr+aEdJlm+A4XZArLX5+xE K/jSYNCdKnQVXs34FlcDlbj0z378GPz8tRfJJjdJUuNrHl+yK8NMwS67bmBDI0UF9QjCroSmp2e zzkZzMsKwuupcjtrOKe6pLG2kgbv4jt3OHRMC8Wqx9GNYuPkXfOepVxSTj0vgCANWbR4RISNuo/ XMPX4DPprENaHnsYez12Rqqr2WCHC1gp32yvDUT/D37KI3yAfZqrSL/3hmqejT2DgU2uIqb7UhG d5q3WWLKYaWcJjJ7e8m2U7D+x7osi4IMiMLJK8hyNsPcH3L87+0RZE3yBqWHfgfzPUJO1kUIhku vzK2uLYX80pYk+n45lCyaTNt0bX/KKkr9GkLKQa3ovbutLwdd0T8lBa8TkwOgOmtMB+hGlIHnRi m+r5RACjW3acvepFPKQ== X-Proofpoint-ORIG-GUID: Fh5bXQuwULVWQ1QiDOgFexyuXNScEXcG X-Authority-Analysis: v=2.4 cv=FOkrAeos c=1 sm=1 tr=0 ts=69dce022 cx=c_pps a=0mLRTIufkjop4KoA/9S1MA==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=EUspDBNiAAAA:8 a=f7xhw97bOydz6QRQpsAA:9 a=WgItmB6HBUc_1uVUp3mg:22 X-Proofpoint-GUID: Fh5bXQuwULVWQ1QiDOgFexyuXNScEXcG X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-13_03,2026-04-13_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 malwarescore=0 impostorscore=0 suspectscore=0 priorityscore=1501 clxscore=1015 spamscore=0 phishscore=0 bulkscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604010000 definitions=main-2604130122 Content-Type: text/plain; charset="utf-8" Ensure the LPI pinctrl device clocks are runtime resumed before accessing GPIO registers and autosuspended after the access completes. Guard GPIO register read and write helpers with synchronous runtime PM calls so the device is active during MMIO operations. Signed-off-by: Ajay Kumar Nandam --- drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qco= m/pinctrl-lpass-lpi.c index d108e7321..4275f2734 100644 --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c @@ -49,8 +49,17 @@ static int lpi_gpio_read(struct lpi_pinctrl *state, unsi= gned int pin, else pin_offset =3D LPI_TLMM_REG_OFFSET * pin; =20 + ret =3D pm_runtime_get_sync(state->dev); + if (ret < 0) { + pm_runtime_put_noidle(state->dev); + return ret; + } + *val =3D ioread32(state->tlmm_base + pin_offset + addr); =20 + pm_runtime_mark_last_busy(state->dev); + pm_runtime_put_autosuspend(state->dev); + return 0; } =20 @@ -65,8 +74,17 @@ static int lpi_gpio_write(struct lpi_pinctrl *state, uns= igned int pin, else pin_offset =3D LPI_TLMM_REG_OFFSET * pin; =20 + ret =3D pm_runtime_get_sync(state->dev); + if (ret < 0) { + pm_runtime_put_noidle(state->dev); + return ret; + } + iowrite32(val, state->tlmm_base + pin_offset + addr); =20 + pm_runtime_mark_last_busy(state->dev); + pm_runtime_put_autosuspend(state->dev); + return 0; } =20 --=20 2.34.1