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charset="utf-8" Convert the gpio-mmio accessors to use union gpio_chip_reg instead of the previous MMIO-only register type. This allows the same accessors to operate on both MMIO and PMIO registers and aligns gpio-mmio with the updated gpio_generic_chip API. Move the initialization code shared by MMIO and PMIO devices to a new function gpio_generic_chip_init_common(), leaving gpio_generic_chip_init() with the MMIO-specific initialization. Signed-off-by: Jose Javier Rodriguez Barbarin Reviewed-by: Linus Walleij --- drivers/gpio/gpio-mmio.c | 208 ++++++++++++++++++----------------- include/linux/gpio/generic.h | 37 +++++-- 2 files changed, 138 insertions(+), 107 deletions(-) diff --git a/drivers/gpio/gpio-mmio.c b/drivers/gpio/gpio-mmio.c index edbcaad57d00..39326ab7e494 100644 --- a/drivers/gpio/gpio-mmio.c +++ b/drivers/gpio/gpio-mmio.c @@ -62,66 +62,71 @@ o ` ~~~~\___/~~~~ ` contr= oller in FPGA is ,.` =20 #include "gpiolib.h" =20 -static void gpio_mmio_write8(void __iomem *reg, unsigned long data) +static void gpio_mmio_write8(union gpio_chip_reg *reg, unsigned long data) { - writeb(data, reg); + writeb(data, reg->mmio); } =20 -static unsigned long gpio_mmio_read8(void __iomem *reg) +static unsigned long gpio_mmio_read8(union gpio_chip_reg *reg) { - return readb(reg); + return readb(reg->mmio); } =20 -static void gpio_mmio_write16(void __iomem *reg, unsigned long data) +static void gpio_mmio_write16(union gpio_chip_reg *reg, unsigned long data) { - writew(data, reg); + writew(data, reg->mmio); } =20 -static unsigned long gpio_mmio_read16(void __iomem *reg) +static unsigned long gpio_mmio_read16(union gpio_chip_reg *reg) { - return readw(reg); + return readw(reg->mmio); } =20 -static void gpio_mmio_write32(void __iomem *reg, unsigned long data) +static void gpio_mmio_write32(union gpio_chip_reg *reg, unsigned long data) { - writel(data, reg); + writel(data, reg->mmio); } =20 -static unsigned long gpio_mmio_read32(void __iomem *reg) +static unsigned long gpio_mmio_read32(union gpio_chip_reg *reg) { - return readl(reg); + return readl(reg->mmio); } =20 #if BITS_PER_LONG >=3D 64 -static void gpio_mmio_write64(void __iomem *reg, unsigned long data) +static void gpio_mmio_write64(union gpio_chip_reg *reg, unsigned long data) { - writeq(data, reg); + writeq(data, reg->mmio); } =20 -static unsigned long gpio_mmio_read64(void __iomem *reg) +static unsigned long gpio_mmio_read64(union gpio_chip_reg *reg) { - return readq(reg); + return readq(reg->mmio); } #endif /* BITS_PER_LONG >=3D 64 */ =20 -static void gpio_mmio_write16be(void __iomem *reg, unsigned long data) +static void gpio_mmio_write16be(union gpio_chip_reg *reg, unsigned long da= ta) { - iowrite16be(data, reg); + iowrite16be(data, reg->mmio); } =20 -static unsigned long gpio_mmio_read16be(void __iomem *reg) +static unsigned long gpio_mmio_read16be(union gpio_chip_reg *reg) { - return ioread16be(reg); + return ioread16be(reg->mmio); } =20 -static void gpio_mmio_write32be(void __iomem *reg, unsigned long data) +static void gpio_mmio_write32be(union gpio_chip_reg *reg, unsigned long da= ta) { - iowrite32be(data, reg); + iowrite32be(data, reg->mmio); } =20 -static unsigned long gpio_mmio_read32be(void __iomem *reg) +static unsigned long gpio_mmio_read32be(union gpio_chip_reg *reg) { - return ioread32be(reg); + return ioread32be(reg->mmio); +} + +static inline bool gpio_chip_reg_is_set(union gpio_chip_reg *reg) +{ + return reg->port !=3D 0; } =20 static unsigned long gpio_mmio_line2mask(struct gpio_chip *gc, unsigned in= t line) @@ -140,9 +145,9 @@ static int gpio_mmio_get_set(struct gpio_chip *gc, unsi= gned int gpio) bool dir =3D !!(chip->sdir & pinmask); =20 if (dir) - return !!(chip->read_reg(chip->reg_set) & pinmask); + return !!(chip->read_reg(&chip->reg_set) & pinmask); =20 - return !!(chip->read_reg(chip->reg_dat) & pinmask); + return !!(chip->read_reg(&chip->reg_dat) & pinmask); } =20 /* @@ -162,9 +167,9 @@ static int gpio_mmio_get_set_multiple(struct gpio_chip = *gc, unsigned long *mask, get_mask =3D *mask & ~chip->sdir; =20 if (set_mask) - *bits |=3D chip->read_reg(chip->reg_set) & set_mask; + *bits |=3D chip->read_reg(&chip->reg_set) & set_mask; if (get_mask) - *bits |=3D chip->read_reg(chip->reg_dat) & get_mask; + *bits |=3D chip->read_reg(&chip->reg_dat) & get_mask; =20 return 0; } @@ -173,7 +178,7 @@ static int gpio_mmio_get(struct gpio_chip *gc, unsigned= int gpio) { struct gpio_generic_chip *chip =3D to_gpio_generic_chip(gc); =20 - return !!(chip->read_reg(chip->reg_dat) & gpio_mmio_line2mask(gc, gpio)); + return !!(chip->read_reg(&chip->reg_dat) & gpio_mmio_line2mask(gc, gpio)); } =20 /* @@ -186,7 +191,7 @@ static int gpio_mmio_get_multiple(struct gpio_chip *gc,= unsigned long *mask, =20 /* Make sure we first clear any bits that are zero when we read the regis= ter */ *bits &=3D ~*mask; - *bits |=3D chip->read_reg(chip->reg_dat) & *mask; + *bits |=3D chip->read_reg(&chip->reg_dat) & *mask; return 0; } =20 @@ -209,7 +214,7 @@ static int gpio_mmio_get_multiple_be(struct gpio_chip *= gc, unsigned long *mask, readmask |=3D gpio_mmio_line2mask(gc, bit); =20 /* Read the register */ - val =3D chip->read_reg(chip->reg_dat) & readmask; + val =3D chip->read_reg(&chip->reg_dat) & readmask; =20 /* * Mirror the result into the "bits" result, this will give line 0 @@ -238,7 +243,7 @@ static int gpio_mmio_set(struct gpio_chip *gc, unsigned= int gpio, int val) else chip->sdata &=3D ~mask; =20 - chip->write_reg(chip->reg_dat, chip->sdata); + chip->write_reg(&chip->reg_dat, chip->sdata); =20 return 0; } @@ -250,9 +255,9 @@ static int gpio_mmio_set_with_clear(struct gpio_chip *g= c, unsigned int gpio, unsigned long mask =3D gpio_mmio_line2mask(gc, gpio); =20 if (val) - chip->write_reg(chip->reg_set, mask); + chip->write_reg(&chip->reg_set, mask); else - chip->write_reg(chip->reg_clr, mask); + chip->write_reg(&chip->reg_clr, mask); =20 return 0; } @@ -269,7 +274,7 @@ static int gpio_mmio_set_set(struct gpio_chip *gc, unsi= gned int gpio, int val) else chip->sdata &=3D ~mask; =20 - chip->write_reg(chip->reg_set, chip->sdata); + chip->write_reg(&chip->reg_set, chip->sdata); =20 return 0; } @@ -297,7 +302,7 @@ static void gpio_mmio_multiple_get_masks(struct gpio_ch= ip *gc, static void gpio_mmio_set_multiple_single_reg(struct gpio_chip *gc, unsigned long *mask, unsigned long *bits, - void __iomem *reg) + union gpio_chip_reg *reg) { struct gpio_generic_chip *chip =3D to_gpio_generic_chip(gc); unsigned long set_mask, clear_mask; @@ -317,7 +322,7 @@ static int gpio_mmio_set_multiple(struct gpio_chip *gc,= unsigned long *mask, { struct gpio_generic_chip *chip =3D to_gpio_generic_chip(gc); =20 - gpio_mmio_set_multiple_single_reg(gc, mask, bits, chip->reg_dat); + gpio_mmio_set_multiple_single_reg(gc, mask, bits, &chip->reg_dat); =20 return 0; } @@ -327,7 +332,7 @@ static int gpio_mmio_set_multiple_set(struct gpio_chip = *gc, unsigned long *mask, { struct gpio_generic_chip *chip =3D to_gpio_generic_chip(gc); =20 - gpio_mmio_set_multiple_single_reg(gc, mask, bits, chip->reg_set); + gpio_mmio_set_multiple_single_reg(gc, mask, bits, &chip->reg_set); =20 return 0; } @@ -342,9 +347,9 @@ static int gpio_mmio_set_multiple_with_clear(struct gpi= o_chip *gc, gpio_mmio_multiple_get_masks(gc, mask, bits, &set_mask, &clear_mask); =20 if (set_mask) - chip->write_reg(chip->reg_set, set_mask); + chip->write_reg(&chip->reg_set, set_mask); if (clear_mask) - chip->write_reg(chip->reg_clr, clear_mask); + chip->write_reg(&chip->reg_clr, clear_mask); =20 return 0; } @@ -394,10 +399,10 @@ static int gpio_mmio_dir_in(struct gpio_chip *gc, uns= igned int gpio) scoped_guard(raw_spinlock_irqsave, &chip->lock) { chip->sdir &=3D ~gpio_mmio_line2mask(gc, gpio); =20 - if (chip->reg_dir_in) - chip->write_reg(chip->reg_dir_in, ~chip->sdir); - if (chip->reg_dir_out) - chip->write_reg(chip->reg_dir_out, chip->sdir); + if (gpio_chip_reg_is_set(&chip->reg_dir_in)) + chip->write_reg(&chip->reg_dir_in, ~chip->sdir); + if (gpio_chip_reg_is_set(&chip->reg_dir_out)) + chip->write_reg(&chip->reg_dir_out, chip->sdir); } =20 return gpio_mmio_dir_return(gc, gpio, false); @@ -414,14 +419,14 @@ static int gpio_mmio_get_dir(struct gpio_chip *gc, un= signed int gpio) return GPIO_LINE_DIRECTION_IN; } =20 - if (chip->reg_dir_out) { - if (chip->read_reg(chip->reg_dir_out) & gpio_mmio_line2mask(gc, gpio)) + if (gpio_chip_reg_is_set(&chip->reg_dir_out)) { + if (chip->read_reg(&chip->reg_dir_out) & gpio_mmio_line2mask(gc, gpio)) return GPIO_LINE_DIRECTION_OUT; return GPIO_LINE_DIRECTION_IN; } =20 - if (chip->reg_dir_in) - if (!(chip->read_reg(chip->reg_dir_in) & gpio_mmio_line2mask(gc, gpio))) + if (gpio_chip_reg_is_set(&chip->reg_dir_in)) + if (!(chip->read_reg(&chip->reg_dir_in) & gpio_mmio_line2mask(gc, gpio))) return GPIO_LINE_DIRECTION_OUT; =20 return GPIO_LINE_DIRECTION_IN; @@ -435,10 +440,10 @@ static void gpio_mmio_dir_out(struct gpio_chip *gc, u= nsigned int gpio, int val) =20 chip->sdir |=3D gpio_mmio_line2mask(gc, gpio); =20 - if (chip->reg_dir_in) - chip->write_reg(chip->reg_dir_in, ~chip->sdir); - if (chip->reg_dir_out) - chip->write_reg(chip->reg_dir_out, chip->sdir); + if (gpio_chip_reg_is_set(&chip->reg_dir_in)) + chip->write_reg(&chip->reg_dir_in, ~chip->sdir); + if (gpio_chip_reg_is_set(&chip->reg_dir_out)) + chip->write_reg(&chip->reg_dir_out, chip->sdir); } =20 static int gpio_mmio_dir_out_dir_first(struct gpio_chip *gc, unsigned int = gpio, @@ -526,25 +531,22 @@ static int gpio_mmio_setup_accessors(struct device *d= ev, * - an input direction register (named "dirin") where a 1 bit indicates * the GPIO is an input. */ -static int gpio_mmio_setup_io(struct gpio_generic_chip *chip, - const struct gpio_generic_chip_config *cfg) +static int gpio_mmio_setup_io(struct gpio_generic_chip *chip, int flags) { struct gpio_chip *gc =3D &chip->gc; =20 - chip->reg_dat =3D cfg->dat; - if (!chip->reg_dat) + if (!gpio_chip_reg_is_set(&chip->reg_dat)) return -EINVAL; =20 - if (cfg->set && cfg->clr) { - chip->reg_set =3D cfg->set; - chip->reg_clr =3D cfg->clr; + if (gpio_chip_reg_is_set(&chip->reg_set) && + gpio_chip_reg_is_set(&chip->reg_clr)) { gc->set =3D gpio_mmio_set_with_clear; gc->set_multiple =3D gpio_mmio_set_multiple_with_clear; - } else if (cfg->set && !cfg->clr) { - chip->reg_set =3D cfg->set; + } else if (gpio_chip_reg_is_set(&chip->reg_set) && + !gpio_chip_reg_is_set(&chip->reg_clr)) { gc->set =3D gpio_mmio_set_set; gc->set_multiple =3D gpio_mmio_set_multiple_set; - } else if (cfg->flags & GPIO_GENERIC_NO_OUTPUT) { + } else if (flags & GPIO_GENERIC_NO_OUTPUT) { gc->set =3D gpio_mmio_set_none; gc->set_multiple =3D NULL; } else { @@ -552,8 +554,8 @@ static int gpio_mmio_setup_io(struct gpio_generic_chip = *chip, gc->set_multiple =3D gpio_mmio_set_multiple; } =20 - if (!(cfg->flags & GPIO_GENERIC_UNREADABLE_REG_SET) && - (cfg->flags & GPIO_GENERIC_READ_OUTPUT_REG_SET)) { + if (!(flags & GPIO_GENERIC_UNREADABLE_REG_SET) && + (flags & GPIO_GENERIC_READ_OUTPUT_REG_SET)) { gc->get =3D gpio_mmio_get_set; if (!chip->be_bits) gc->get_multiple =3D gpio_mmio_get_set_multiple; @@ -575,27 +577,24 @@ static int gpio_mmio_setup_io(struct gpio_generic_chi= p *chip, return 0; } =20 -static int gpio_mmio_setup_direction(struct gpio_generic_chip *chip, - const struct gpio_generic_chip_config *cfg) +static int gpio_mmio_setup_direction(struct gpio_generic_chip *chip, int f= lags) { struct gpio_chip *gc =3D &chip->gc; - - if (cfg->dirout || cfg->dirin) { - chip->reg_dir_out =3D cfg->dirout; - chip->reg_dir_in =3D cfg->dirin; - if (cfg->flags & GPIO_GENERIC_NO_SET_ON_INPUT) + if (gpio_chip_reg_is_set(&chip->reg_dir_out) || + gpio_chip_reg_is_set(&chip->reg_dir_in)) { + if (flags & GPIO_GENERIC_NO_SET_ON_INPUT) gc->direction_output =3D gpio_mmio_dir_out_dir_first; else gc->direction_output =3D gpio_mmio_dir_out_val_first; gc->direction_input =3D gpio_mmio_dir_in; gc->get_direction =3D gpio_mmio_get_dir; } else { - if (cfg->flags & GPIO_GENERIC_NO_OUTPUT) + if (flags & GPIO_GENERIC_NO_OUTPUT) gc->direction_output =3D gpio_mmio_dir_out_err; else gc->direction_output =3D gpio_mmio_simple_dir_out; =20 - if (cfg->flags & GPIO_GENERIC_NO_INPUT) + if (flags & GPIO_GENERIC_NO_INPUT) gc->direction_input =3D gpio_mmio_dir_in_err; else gc->direction_input =3D gpio_mmio_simple_dir_in; @@ -617,25 +616,18 @@ static int gpio_mmio_request(struct gpio_chip *gc, un= signed int gpio_pin) return 0; } =20 -/** - * gpio_generic_chip_init() - Initialize a generic GPIO chip. - * @chip: Generic GPIO chip to set up. - * @cfg: Generic GPIO chip configuration. - * - * Returns 0 on success, negative error number on failure. - */ -int gpio_generic_chip_init(struct gpio_generic_chip *chip, - const struct gpio_generic_chip_config *cfg) +static int gpio_generic_chip_init_common(struct gpio_generic_chip *chip, + int sz, + int flags, + struct device *dev) { struct gpio_chip *gc =3D &chip->gc; - unsigned long flags =3D cfg->flags; - struct device *dev =3D cfg->dev; int ret; =20 - if (!is_power_of_2(cfg->sz)) + if (!is_power_of_2(sz)) return -EINVAL; =20 - chip->bits =3D cfg->sz * 8; + chip->bits =3D sz * 8; if (chip->bits > BITS_PER_LONG) return -EINVAL; =20 @@ -650,16 +642,16 @@ int gpio_generic_chip_init(struct gpio_generic_chip *= chip, if (ret) gc->ngpio =3D chip->bits; =20 - ret =3D gpio_mmio_setup_io(chip, cfg); + ret =3D gpio_mmio_setup_io(chip, flags); if (ret) return ret; =20 ret =3D gpio_mmio_setup_accessors(dev, chip, - flags & GPIO_GENERIC_BIG_ENDIAN_BYTE_ORDER); + flags & GPIO_GENERIC_BIG_ENDIAN_BYTE_ORDER); if (ret) return ret; =20 - ret =3D gpio_mmio_setup_direction(chip, cfg); + ret =3D gpio_mmio_setup_direction(chip, flags); if (ret) return ret; =20 @@ -669,10 +661,10 @@ int gpio_generic_chip_init(struct gpio_generic_chip *= chip, gc->free =3D gpiochip_generic_free; } =20 - chip->sdata =3D chip->read_reg(chip->reg_dat); + chip->sdata =3D chip->read_reg(&chip->reg_dat); if (gc->set =3D=3D gpio_mmio_set_set && !(flags & GPIO_GENERIC_UNREADABLE_REG_SET)) - chip->sdata =3D chip->read_reg(chip->reg_set); + chip->sdata =3D chip->read_reg(&chip->reg_set); =20 if (flags & GPIO_GENERIC_UNREADABLE_REG_DIR) chip->dir_unreadable =3D true; @@ -680,24 +672,44 @@ int gpio_generic_chip_init(struct gpio_generic_chip *= chip, /* * Inspect hardware to find initial direction setting. */ - if ((chip->reg_dir_out || chip->reg_dir_in) && + if ((gpio_chip_reg_is_set(&chip->reg_dir_out) || gpio_chip_reg_is_set(&ch= ip->reg_dir_in)) && !(flags & GPIO_GENERIC_UNREADABLE_REG_DIR)) { - if (chip->reg_dir_out) - chip->sdir =3D chip->read_reg(chip->reg_dir_out); - else if (chip->reg_dir_in) - chip->sdir =3D ~chip->read_reg(chip->reg_dir_in); + if (gpio_chip_reg_is_set(&chip->reg_dir_out)) + chip->sdir =3D chip->read_reg(&chip->reg_dir_out); + else if (gpio_chip_reg_is_set(&chip->reg_dir_in)) + chip->sdir =3D ~chip->read_reg(&chip->reg_dir_in); /* * If we have two direction registers, synchronise * input setting to output setting, the library * can not handle a line being input and output at * the same time. */ - if (chip->reg_dir_out && chip->reg_dir_in) - chip->write_reg(chip->reg_dir_in, ~chip->sdir); + if (gpio_chip_reg_is_set(&chip->reg_dir_out) && + gpio_chip_reg_is_set(&chip->reg_dir_in)) + chip->write_reg(&chip->reg_dir_in, ~chip->sdir); } =20 return ret; } + +/** + * gpio_generic_chip_init() - Initialize a generic GPIO chip + * @chip: Generic GPIO chip to set up. + * @cfg: Generic GPIO chip configuration. + * + * Returns 0 on success, negative error number on failure. + */ +int gpio_generic_chip_init(struct gpio_generic_chip *chip, + const struct gpio_generic_chip_config *cfg) +{ + chip->reg_dat.mmio =3D cfg->dat; + chip->reg_set.mmio =3D cfg->set; + chip->reg_clr.mmio =3D cfg->clr; + chip->reg_dir_in.mmio =3D cfg->dirin; + chip->reg_dir_out.mmio =3D cfg->dirout; + + return gpio_generic_chip_init_common(chip, cfg->sz, cfg->flags, cfg->dev); +} EXPORT_SYMBOL_GPL(gpio_generic_chip_init); =20 #if IS_ENABLED(CONFIG_GPIO_GENERIC_PLATFORM) diff --git a/include/linux/gpio/generic.h b/include/linux/gpio/generic.h index ff566dc9c3cb..30f0d87422e9 100644 --- a/include/linux/gpio/generic.h +++ b/include/linux/gpio/generic.h @@ -56,6 +56,19 @@ struct gpio_generic_chip_config { unsigned long flags; }; =20 +/** + * union gpio_chip_reg - Generic GPIO chip register descriptor for MMIO or= port-mapped I/O + * @mmio: MMIO register address. + * @port: I/O Port register address. + * + * Describes a GPIO chip register located either in MMIO space or in + * port-mapped I/O space. + */ +union gpio_chip_reg { + void __iomem *mmio; + unsigned long port; +}; + /** * struct gpio_generic_chip - Generic GPIO chip implementation. * @gc: The underlying struct gpio_chip object, implementing low-level GPIO @@ -84,14 +97,14 @@ struct gpio_generic_chip_config { */ struct gpio_generic_chip { struct gpio_chip gc; - unsigned long (*read_reg)(void __iomem *reg); - void (*write_reg)(void __iomem *reg, unsigned long data); + unsigned long (*read_reg)(union gpio_chip_reg *reg); + void (*write_reg)(union gpio_chip_reg *reg, unsigned long data); bool be_bits; - void __iomem *reg_dat; - void __iomem *reg_set; - void __iomem *reg_clr; - void __iomem *reg_dir_out; - void __iomem *reg_dir_in; + union gpio_chip_reg reg_dat; + union gpio_chip_reg reg_set; + union gpio_chip_reg reg_clr; + union gpio_chip_reg reg_dir_out; + union gpio_chip_reg reg_dir_in; bool dir_unreadable; bool pinctrl; int bits; @@ -143,10 +156,13 @@ gpio_generic_chip_set(struct gpio_generic_chip *chip,= unsigned int offset, static inline unsigned long gpio_generic_read_reg(struct gpio_generic_chip *chip, void __iomem *reg) { + union gpio_chip_reg rg; + if (WARN_ON(!chip->read_reg)) return 0; =20 - return chip->read_reg(reg); + rg.mmio =3D reg; + return chip->read_reg(&rg); } =20 /** @@ -158,10 +174,13 @@ gpio_generic_read_reg(struct gpio_generic_chip *chip,= void __iomem *reg) static inline void gpio_generic_write_reg(struct gpio_generic_chip *chip, void __iomem *reg, unsigned long val) { + union gpio_chip_reg rg; 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charset="utf-8" Implement PMIO read and write callbacks for 8-, 16- and 32-bit register accesses using the corresponding port I/O helpers. Signed-off-by: Jose Javier Rodriguez Barbarin Reviewed-by: Linus Walleij --- drivers/gpio/gpio-mmio.c | 94 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 94 insertions(+) diff --git a/drivers/gpio/gpio-mmio.c b/drivers/gpio/gpio-mmio.c index 39326ab7e494..d23c5d275e6b 100644 --- a/drivers/gpio/gpio-mmio.c +++ b/drivers/gpio/gpio-mmio.c @@ -124,6 +124,60 @@ static unsigned long gpio_mmio_read32be(union gpio_chi= p_reg *reg) return ioread32be(reg->mmio); } =20 +#ifdef CONFIG_HAS_IOPORT + +static void gpio_port_write8(union gpio_chip_reg *reg, unsigned long data) +{ + outb(data, reg->port); +} + +static unsigned long gpio_port_read8(union gpio_chip_reg *reg) +{ + return inb(reg->port); +} + +static void gpio_port_write16(union gpio_chip_reg *reg, unsigned long data) +{ + outw(data, reg->port); +} + +static unsigned long gpio_port_read16(union gpio_chip_reg *reg) +{ + return inw(reg->port); +} + +static void gpio_port_write32(union gpio_chip_reg *reg, unsigned long data) +{ + outl(data, reg->port); +} + +static unsigned long gpio_port_read32(union gpio_chip_reg *reg) +{ + return inl(reg->port); +} + +static void gpio_port_write16be(union gpio_chip_reg *reg, unsigned long da= ta) +{ + outw(swab16(data), reg->port); +} + +static unsigned long gpio_port_read16be(union gpio_chip_reg *reg) +{ + return swab16(inw(reg->port)); +} + +static void gpio_port_write32be(union gpio_chip_reg *reg, unsigned long da= ta) +{ + outl(swab32(data), reg->port); +} + +static unsigned long gpio_port_read32be(union gpio_chip_reg *reg) +{ + return swab32(inl(reg->port)); +} + +#endif /* CONFIG_HAS_IOPORT */ + static inline bool gpio_chip_reg_is_set(union gpio_chip_reg *reg) { return reg->port !=3D 0; @@ -462,6 +516,46 @@ static int gpio_mmio_dir_out_val_first(struct gpio_chi= p *gc, unsigned int gpio, return gpio_mmio_dir_return(gc, gpio, true); } =20 +static int gpio_port_setup_accessors(struct device *dev, + struct gpio_generic_chip *chip, + bool byte_be) +{ +#ifdef CONFIG_HAS_IOPORT + switch (chip->bits) { + case 8: + chip->read_reg =3D gpio_port_read8; + chip->write_reg =3D gpio_port_write8; + break; + case 16: + if (byte_be) { + chip->read_reg =3D gpio_port_read16be; + chip->write_reg =3D gpio_port_write16be; + } else { + chip->read_reg =3D gpio_port_read16; + chip->write_reg =3D gpio_port_write16; + } + break; + case 32: + if (byte_be) { + chip->read_reg =3D gpio_port_read32be; + chip->write_reg =3D gpio_port_write32be; + } else { + chip->read_reg =3D gpio_port_read32; + chip->write_reg =3D gpio_port_write32; + } + break; + default: + dev_err(dev, "unsupported data width %u bits\n", chip->bits); + return -EINVAL; + } + + return 0; +#else + dev_err(dev, "not supported because of missing I/O resource\n"); + return -ENXIO; +#endif /* CONFIG_HAS_IOPORT */ +} + static int gpio_mmio_setup_accessors(struct device *dev, struct gpio_generic_chip *chip, bool byte_be) --=20 2.53.0 From nobody Mon Jun 15 03:55:14 2026 Received: from ZRAP278CU002.outbound.protection.outlook.com (mail-switzerlandnorthazon11020117.outbound.protection.outlook.com [52.101.186.117]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6543935AC0A; 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charset="utf-8" Add a new structure gpio_generic_chip_port_config for configuring PMIO chips. A new function gpio_generic_chip_port_init() allows to configure them. Add an io_port field to struct gpio_generic_chip to distinguish PMIO from MMIO chips during initialization and select the proper register accessors. Signed-off-by: Jose Javier Rodriguez Barbarin Reviewed-by: Linus Walleij --- drivers/gpio/gpio-mmio.c | 30 ++++++++++++++++++++++++-- include/linux/gpio/generic.h | 41 ++++++++++++++++++++++++++++++++++++ 2 files changed, 69 insertions(+), 2 deletions(-) diff --git a/drivers/gpio/gpio-mmio.c b/drivers/gpio/gpio-mmio.c index d23c5d275e6b..01e2afd8d6f1 100644 --- a/drivers/gpio/gpio-mmio.c +++ b/drivers/gpio/gpio-mmio.c @@ -740,8 +740,12 @@ static int gpio_generic_chip_init_common(struct gpio_g= eneric_chip *chip, if (ret) return ret; =20 - ret =3D gpio_mmio_setup_accessors(dev, chip, - flags & GPIO_GENERIC_BIG_ENDIAN_BYTE_ORDER); + if (chip->io_port) + ret =3D gpio_port_setup_accessors(dev, chip, + flags & GPIO_GENERIC_BIG_ENDIAN_BYTE_ORDER); + else + ret =3D gpio_mmio_setup_accessors(dev, chip, + flags & GPIO_GENERIC_BIG_ENDIAN_BYTE_ORDER); if (ret) return ret; =20 @@ -801,11 +805,33 @@ int gpio_generic_chip_init(struct gpio_generic_chip *= chip, chip->reg_clr.mmio =3D cfg->clr; chip->reg_dir_in.mmio =3D cfg->dirin; chip->reg_dir_out.mmio =3D cfg->dirout; + chip->io_port =3D true; =20 return gpio_generic_chip_init_common(chip, cfg->sz, cfg->flags, cfg->dev); } EXPORT_SYMBOL_GPL(gpio_generic_chip_init); =20 +/** + * gpio_generic_chip_port_init() - Initialize a generic GPIO chip for I/O = port devices + * @chip: Generic GPIO chip to set up. + * @cfg: Generic GPIO chip configuration. + * + * Returns 0 on success, negative error number on failure. + */ +int gpio_generic_chip_port_init(struct gpio_generic_chip *chip, + const struct gpio_generic_chip_port_config *cfg) +{ + chip->reg_dat.port =3D cfg->dat; + chip->reg_set.port =3D cfg->set; + chip->reg_clr.port =3D cfg->clr; + chip->reg_dir_in.port =3D cfg->dirin; + chip->reg_dir_out.port =3D cfg->dirout; + chip->io_port =3D true; + + return gpio_generic_chip_init_common(chip, cfg->sz, cfg->flags, cfg->dev); +} +EXPORT_SYMBOL_GPL(gpio_generic_chip_port_init); + #if IS_ENABLED(CONFIG_GPIO_GENERIC_PLATFORM) =20 static void __iomem *gpio_mmio_map(struct platform_device *pdev, diff --git a/include/linux/gpio/generic.h b/include/linux/gpio/generic.h index 30f0d87422e9..93ce5f09c0d3 100644 --- a/include/linux/gpio/generic.h +++ b/include/linux/gpio/generic.h @@ -56,6 +56,43 @@ struct gpio_generic_chip_config { unsigned long flags; }; =20 +/** + * struct gpio_generic_chip_port_config - Generic GPIO chip configuration = data for I/O port devices + * @dev: Parent device of the new GPIO chip (compulsory). + * @sz: Size (width) of the PMIO registers in bytes, typically 1, 2 or 4. + * @dat: PMIO address for the register to READ the value of the GPIO lines= , it + * is expected that a 1 in the corresponding bit in this register me= ans + * the line is asserted. + * @set: PMIO address for the register to SET the value of the GPIO lines,= it + * is expected that we write the line with 1 in this register to dri= ve + * the GPIO line high. + * @clr: PMIO address for the register to CLEAR the value of the GPIO line= s, + * it is expected that we write the line with 1 in this register to + * drive the GPIO line low. It is allowed to leave this address as N= ULL, + * in that case the SET register will be assumed to also clear the G= PIO + * lines, by actively writing the line with 0. + * @dirout: PMIO address for the register to set the line as OUTPUT. It is + * assumed that setting a line to 1 in this register will turn th= at + * line into an output line. Conversely, setting the line to 0 wi= ll + * turn that line into an input. + * @dirin: PMIO address for the register to set this line as INPUT. It is + * assumed that setting a line to 1 in this register will turn that + * line into an input line. Conversely, setting the line to 0 will + * turn that line into an output. + * @flags: Different flags that will affect the behaviour of the device, s= uch + * as endianness etc. + */ +struct gpio_generic_chip_port_config { + struct device *dev; + unsigned long sz; + unsigned long dat; + unsigned long set; + unsigned long clr; + unsigned long dirout; + unsigned long dirin; + unsigned long flags; +}; + /** * union gpio_chip_reg - Generic GPIO chip register descriptor for MMIO or= port-mapped I/O * @mmio: MMIO register address. @@ -79,6 +116,7 @@ union gpio_chip_reg { * representing line 0, bit 30 is line 1 ... bit 0 is line 31) t= his * is set to true by the generic GPIO core. It is for internal * housekeeping only. + * @io_port: indicates that the device is I/O port-mapped * @reg_dat: data (in) register for generic GPIO * @reg_set: output set register (out=3Dhigh) for generic GPIO * @reg_clr: output clear register (out=3Dlow) for generic GPIO @@ -100,6 +138,7 @@ struct gpio_generic_chip { unsigned long (*read_reg)(union gpio_chip_reg *reg); void (*write_reg)(union gpio_chip_reg *reg, unsigned long data); bool be_bits; + bool io_port; union gpio_chip_reg reg_dat; union gpio_chip_reg reg_set; union gpio_chip_reg reg_clr; @@ -122,6 +161,8 @@ to_gpio_generic_chip(struct gpio_chip *gc) int gpio_generic_chip_init(struct gpio_generic_chip *chip, const struct gpio_generic_chip_config *cfg); =20 +int gpio_generic_chip_port_init(struct gpio_generic_chip *chip, + const struct gpio_generic_chip_port_config *cfg); /** * gpio_generic_chip_set() - Set the GPIO line value of the generic GPIO c= hip. * @chip: Generic GPIO chip to use. --=20 2.53.0