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([183.91.15.56]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-82f0c50a8f7sm10232140b3a.56.2026.04.13.03.07.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Apr 2026 03:07:27 -0700 (PDT) From: phucduc.bui@gmail.com To: kuninori.morimoto.gx@renesas.com, broonie@kernel.org Cc: lgirdwood@gmail.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, perex@perex.cz, tiwai@suse.com, linux-sound@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, bui duc phuc Subject: [PATCH v2 1/6] ASoC: renesas: fsi: Add shared SPU clock support Date: Mon, 13 Apr 2026 17:06:55 +0700 Message-ID: <20260413100700.30995-2-phucduc.bui@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260413100700.30995-1-phucduc.bui@gmail.com> References: <20260413100700.30995-1-phucduc.bui@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: bui duc phuc Add SPU clock pointer, reference counter, and locking in fsi_master for shared FSIA/FSIB usage, and initialize them in fsi_probe(). Signed-off-by: bui duc phuc --- Changes in v2: - Add spu_count to track active users of the SPU clock. - Add clk_lock mutex to prevent race conditions during SPU clock enable/disable operations. - Initialize spu_count and clk_lock during driver probe. sound/soc/renesas/fsi.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/sound/soc/renesas/fsi.c b/sound/soc/renesas/fsi.c index 1491c2f2cc96..196ec7bac33d 100644 --- a/sound/soc/renesas/fsi.c +++ b/sound/soc/renesas/fsi.c @@ -292,8 +292,11 @@ struct fsi_master { void __iomem *base; struct fsi_priv fsia; struct fsi_priv fsib; + struct clk *clk_spu; const struct fsi_core *core; + int spu_count; spinlock_t lock; + struct mutex clk_lock; }; =20 static inline int fsi_stream_is_play(struct fsi_priv *fsi, @@ -1961,7 +1964,9 @@ static int fsi_probe(struct platform_device *pdev) =20 /* master setting */ master->core =3D core; + master->spu_count =3D 0; spin_lock_init(&master->lock); + mutex_init(&master->clk_lock); =20 /* FSI A setting */ fsi =3D &master->fsia; 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([183.91.15.56]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-82f0c50a8f7sm10232140b3a.56.2026.04.13.03.07.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Apr 2026 03:07:34 -0700 (PDT) From: phucduc.bui@gmail.com To: kuninori.morimoto.gx@renesas.com, broonie@kernel.org Cc: lgirdwood@gmail.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, perex@perex.cz, tiwai@suse.com, linux-sound@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, bui duc phuc Subject: [PATCH v2 2/6] ASoC: renesas: fsi: Fix hang by enabling SPU clock Date: Mon, 13 Apr 2026 17:06:56 +0700 Message-ID: <20260413100700.30995-3-phucduc.bui@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260413100700.30995-1-phucduc.bui@gmail.com> References: <20260413100700.30995-1-phucduc.bui@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: bui duc phuc Enable/disable the shared SPU clock in hw startup/shutdown. Without this, accessing FSI registers may hang the system. Suggested-by: Kuninori Morimoto Signed-off-by: bui duc phuc --- Changes in v2: - Move SPU clock enable/disable handling from fsi_dai_startup/shutdown=20 to fsi_hw_startup/shutdown sound/soc/renesas/fsi.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/sound/soc/renesas/fsi.c b/sound/soc/renesas/fsi.c index 196ec7bac33d..109e06b5f32d 100644 --- a/sound/soc/renesas/fsi.c +++ b/sound/soc/renesas/fsi.c @@ -1492,6 +1492,18 @@ static int fsi_hw_startup(struct fsi_priv *fsi, struct device *dev) { u32 data =3D 0; + int ret =3D 0; + /* enable spu clock */ + mutex_lock(&fsi->master->clk_lock); + if (fsi->master->clk_spu && fsi->master->spu_count++ =3D=3D 0) { + ret =3D clk_prepare_enable(fsi->master->clk_spu); + if (ret < 0) { + fsi->master->spu_count--; + mutex_unlock(&fsi->master->clk_lock); + return ret; + } + } + mutex_unlock(&fsi->master->clk_lock); =20 /* clock setting */ if (fsi_is_clk_master(fsi)) @@ -1549,6 +1561,11 @@ static int fsi_hw_shutdown(struct fsi_priv *fsi, /* stop master clock */ if (fsi_is_clk_master(fsi)) return fsi_clk_disable(dev, fsi); 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([183.91.15.56]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-82f0c50a8f7sm10232140b3a.56.2026.04.13.03.07.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Apr 2026 03:07:39 -0700 (PDT) From: phucduc.bui@gmail.com To: kuninori.morimoto.gx@renesas.com, broonie@kernel.org Cc: lgirdwood@gmail.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, perex@perex.cz, tiwai@suse.com, linux-sound@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, bui duc phuc Subject: [PATCH v2 3/6] ASoC: renesas: fsi: Fix trigger stop ordering Date: Mon, 13 Apr 2026 17:06:57 +0700 Message-ID: <20260413100700.30995-4-phucduc.bui@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260413100700.30995-1-phucduc.bui@gmail.com> References: <20260413100700.30995-1-phucduc.bui@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: bui duc phuc Reorder calls to execute fsi_stream_stop() before fsi_hw_shutdown(). This ensures that all register accesses are completed before the clock is disabled, preventing the system hang observed on r8a7740. Suggested-by: Kuninori Morimoto Signed-off-by: bui duc phuc --- sound/soc/renesas/fsi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sound/soc/renesas/fsi.c b/sound/soc/renesas/fsi.c index 109e06b5f32d..9df3e91ac79c 100644 --- a/sound/soc/renesas/fsi.c +++ b/sound/soc/renesas/fsi.c @@ -1606,9 +1606,9 @@ static int fsi_dai_trigger(struct snd_pcm_substream *= substream, int cmd, ret =3D fsi_stream_transfer(io); break; case SNDRV_PCM_TRIGGER_STOP: + fsi_stream_stop(fsi, io); if (!ret) ret =3D fsi_hw_shutdown(fsi, dai->dev); - fsi_stream_stop(fsi, io); fsi_stream_quit(fsi, io); break; } --=20 2.43.0 From nobody Mon Jun 15 19:01:34 2026 Received: from mail-pf1-f170.google.com (mail-pf1-f170.google.com [209.85.210.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 863AE3B95E7 for ; Mon, 13 Apr 2026 10:07:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.170 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776074868; cv=none; b=VoLgERQJKD5Cz0cA+YOkHJvmONXmb8T6PP+OlLWd7o9AAOaxNbhLo32igpEDHuCyTuG7IbgexF+jqd+RlZUhVw7pX9fy66scsnbX0cjCSgQCMZFR85PcKI8ASWWBiz5rGaIElnHiVrqmDndmakCa19hLh0EMIB922+8w4SdtYaY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776074868; c=relaxed/simple; bh=0bMg0/W1dHU7kdGDq/bhaGzEZAt+cNePiIeAjdWuL80=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=SxKKn99W9a+B4i9AlsdFeXNmpixcM/izNWkOFuzPGpJAAxcNAtbOzWc+SBmw3lYKTCPbLoW4WCJ4Aa4UYulCRxZBVBAc8wTchMjsNsDQsgUD4zSYhW73aC8r6IUhGYllCQTQJvod5yY/w88dhQhSnPJXFjA27tR+3gCHHcnLZaY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=BtfqG2J0; arc=none smtp.client-ip=209.85.210.170 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="BtfqG2J0" Received: by mail-pf1-f170.google.com with SMTP id d2e1a72fcca58-82cf636dac8so1889853b3a.3 for ; Mon, 13 Apr 2026 03:07:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1776074866; x=1776679666; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=upB10mny2syi2uM1NkkQ56XECtDOY4twgSZ8lGsSufU=; b=BtfqG2J06h+QT15Tt6xfYxbyiS22OCyjOJElqmzOymikx8mWVcTqBzslhAYICFZr5L FvVhwQmn4NB5ZjDHPcYAfZAPPwa6WJaCQHEhvwDVLHuAXV8zOA1kWpfvOYSdgjmE6wUo 0MI8MuRaoEtsEeK4n2JD5g6+d9nf7e4Du4c/uCDbIMB+zJMA+2Q6B+MauG4MnXbEqTg0 wwd1CpbaNOVEg9kFr6JBE5A+Dhyhuvrn2hiv5npGxfcu0sq59IjEUuDXOC+VIayFWxoA bxDC129wjqr3ujRTU3uHfHtmKo4LuN1pk6xGawm6YkJptCSAkeSa5tONal4sqBCzGh/I MA9g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1776074866; x=1776679666; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=upB10mny2syi2uM1NkkQ56XECtDOY4twgSZ8lGsSufU=; b=UDzItE0pxtGdmKwIK+D0DCQnipKB1CL/16/M8FzSgvoRxDqjqF18ddB60FU19Y+5u8 MTsGJq2oPrH/w75dGHOq1cPTtVCzx7JGlqccux1XNLpG0LxHTNDMEJm69gOmz/kjg7Qm dCdpuiwIvWxIvoCq4VCdyUCCvdzDZ/0Aks8+4VyZowRwy2VXH9ui26auZEw63uew1DS2 AsKfcMwbzi1gyesMj9lyvrqOPcBrywJw/YPEiGjJKgQ/zCrmEWh7h+NEmyC3OR22ekZb bFFszJAH0cQp0V0iVXyHyptXlff0/xlRRtzPUYAyf4BZ5j1fs77IAKtFfA1fBeQmbjcn qyTQ== X-Forwarded-Encrypted: i=1; AFNElJ9Bsi4RGKdduem/cESJv/bpDemB8uwPG4GxUvSgK311X7GzPstC40ebGNXiw5uwCyzGKD+nSuXz5higaUQ=@vger.kernel.org X-Gm-Message-State: AOJu0YzmTmpWEX6Z8jqYANK+FiS4P/HoeIZrH0TXZf0CGYXwuR56iF1O KP+ER3hMO689zSaUl1g5z2WxzijDy44g/ieLrAKRFmQh9SBwHB7qWaMv X-Gm-Gg: AeBDievq9NYJHYKBEksiLIIETTnowhMxvua0SXYiV1sEbKGRzJ853K+BkWT/Q5hwZs1 gabgqQuZZqLzhGpuAPQ9cijenmNa2YjCsJ+GAZ3r+xf0R8pyHvzYgChzZ58oqV/RL3ODh0NojQ+ f6M9vViEGb6ihubzUcmUu9ai+hLScrTeD3e26WCXZXl5HluKm2b+U+X2+58Zsd+eUQPEDGVX3Wa 6MQyk+/iSjJ+nUGt1Ms1Gwh7DkcNkO5UsTVPDB59djHl2TJCXHVI5b3OcuX1kmCv6UcUCW10Puy o5YU2A3elgHaRVJ/rM5ugp7RWaYpQwJTz9sBNRRAnsVm7GdQS38zXNyuBeOb90+qM44Nx7ND39Q vp0K0uwji0jRA/VfArB4Bb5Zn4lfHRicU0t6Xp8OWeoWhbMUtYMHRzLUNbeKyBWCT5Hu/42cTb4 D33ZVxMgTTAmbNSjIkOv7hzDYQAYzKeuFQaXBEPy3/JUcYyD4oW58u2Qc0pbB44AxCdAfL X-Received: by 2002:a05:6a00:14c7:b0:82c:9fe1:aa4d with SMTP id d2e1a72fcca58-82f0c28d49amr12758235b3a.13.1776074865962; Mon, 13 Apr 2026 03:07:45 -0700 (PDT) Received: from phuc-desktop.. ([183.91.15.56]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-82f0c50a8f7sm10232140b3a.56.2026.04.13.03.07.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Apr 2026 03:07:45 -0700 (PDT) From: phucduc.bui@gmail.com To: kuninori.morimoto.gx@renesas.com, broonie@kernel.org Cc: lgirdwood@gmail.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, perex@perex.cz, tiwai@suse.com, linux-sound@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, bui duc phuc Subject: [PATCH v2 4/6] ASoC: renesas: fsi: refactor clock initialization Date: Mon, 13 Apr 2026 17:06:58 +0700 Message-ID: <20260413100700.30995-5-phucduc.bui@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260413100700.30995-1-phucduc.bui@gmail.com> References: <20260413100700.30995-1-phucduc.bui@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: bui duc phuc Move fsi_clk_init() out of set_fmt() and handle clock master logic internally. This simplifies the flow and aligns with probe-time initialization. Suggested-by: Kuninori Morimoto Signed-off-by: bui duc phuc --- Note: Due to hardware limitations, only slave mode has been verified. Testing master mode requires resoldering board resistors or developing an HDMI driver, so master mode logic is currently compile-tested only. Full support for fsidiv requires additional DT bindings and a corresponding driver. sound/soc/renesas/fsi.c | 157 +++++++++++++++++++++------------------- 1 file changed, 81 insertions(+), 76 deletions(-) diff --git a/sound/soc/renesas/fsi.c b/sound/soc/renesas/fsi.c index 9df3e91ac79c..db4ddc30f44f 100644 --- a/sound/soc/renesas/fsi.c +++ b/sound/soc/renesas/fsi.c @@ -709,73 +709,6 @@ static void fsi_spdif_clk_ctrl(struct fsi_priv *fsi, i= nt enable) fsi_core_mask_set(master, b_mclk, mask, val); } =20 -/* - * clock function - */ -static int fsi_clk_init(struct device *dev, - struct fsi_priv *fsi, - int xck, - int ick, - int div, - int (*set_rate)(struct device *dev, - struct fsi_priv *fsi)) -{ - struct fsi_clk *clock =3D &fsi->clock; - int is_porta =3D fsi_is_port_a(fsi); - - clock->xck =3D NULL; - clock->ick =3D NULL; - clock->div =3D NULL; - clock->rate =3D 0; - clock->count =3D 0; - clock->set_rate =3D set_rate; - - clock->own =3D devm_clk_get(dev, NULL); - if (IS_ERR(clock->own)) - return -EINVAL; - - /* external clock */ - if (xck) { - clock->xck =3D devm_clk_get(dev, is_porta ? "xcka" : "xckb"); - if (IS_ERR(clock->xck)) { - dev_err(dev, "can't get xck clock\n"); - return -EINVAL; - } - if (clock->xck =3D=3D clock->own) { - dev_err(dev, "cpu doesn't support xck clock\n"); - return -EINVAL; - } - } - - /* FSIACLK/FSIBCLK */ - if (ick) { - clock->ick =3D devm_clk_get(dev, is_porta ? "icka" : "ickb"); - if (IS_ERR(clock->ick)) { - dev_err(dev, "can't get ick clock\n"); - return -EINVAL; - } - if (clock->ick =3D=3D clock->own) { - dev_err(dev, "cpu doesn't support ick clock\n"); - return -EINVAL; - } - } - - /* FSI-DIV */ - if (div) { - clock->div =3D devm_clk_get(dev, is_porta ? "diva" : "divb"); - if (IS_ERR(clock->div)) { - dev_err(dev, "can't get div clock\n"); - return -EINVAL; - } - if (clock->div =3D=3D clock->own) { - dev_err(dev, "cpu doesn't support div clock\n"); - return -EINVAL; - } - } - - return 0; -} - #define fsi_clk_invalid(fsi) fsi_clk_valid(fsi, 0) static void fsi_clk_valid(struct fsi_priv *fsi, unsigned long rate) { @@ -921,6 +854,10 @@ static int fsi_clk_set_rate_external(struct device *de= v, int ackmd, bpfmd; int ret =3D 0; =20 + if (!xck || !ick) { + dev_err(dev, "External (xck) or Internal (ick) clock is missing\n"); + return -EINVAL; + } /* check clock rate */ xrate =3D clk_get_rate(xck); if (xrate % rate) { @@ -957,6 +894,11 @@ static int fsi_clk_set_rate_cpg(struct device *dev, int ackmd, bpfmd; int ret =3D -EINVAL; =20 + if (!ick || !div) { + dev_err(dev, "Internal (ick) or Divider (div) clock is missing\n"); + return -EINVAL; + } + if (!(12288000 % rate)) target =3D 12288000; if (!(11289600 % rate)) @@ -1029,6 +971,76 @@ static int fsi_clk_set_rate_cpg(struct device *dev, return ret; } =20 +/* + * clock function + */ +static int fsi_clk_init(struct device *dev, struct fsi_priv *fsi, int is_c= pg) +{ + struct fsi_clk *clock =3D &fsi->clock; + struct fsi_master *master =3D fsi->master; + int is_porta =3D fsi_is_port_a(fsi); + int xck, ick, div; + + if (is_cpg) { + xck =3D 0; ick =3D 1; div =3D 1; + clock->set_rate =3D fsi_clk_set_rate_cpg; + } else { + xck =3D 1; ick =3D 1; div =3D 0; + clock->set_rate =3D fsi_clk_set_rate_external; + } + + clock->xck =3D NULL; + clock->ick =3D NULL; + clock->div =3D NULL; + clock->rate =3D 0; + clock->count =3D 0; + + clock->own =3D devm_clk_get(dev, NULL); + if (IS_ERR(clock->own)) + return -EINVAL; + + if (!master->clk_spu) { + master->clk_spu =3D devm_clk_get_optional(dev, "spu"); + if (IS_ERR(master->clk_spu)) + return PTR_ERR(master->clk_spu); + } + + /* external clock */ + if (xck) { + clock->xck =3D devm_clk_get_optional(dev, is_porta ? "xcka" : "xckb"); + if (IS_ERR(clock->xck)) + return dev_err_probe(dev, PTR_ERR(clock->xck), "Can't get xck clock\n"); + if (clock->xck =3D=3D clock->own) { + dev_err(dev, "cpu doesn't support xck clock\n"); + return -EINVAL; + } + } + + /* FSIACLK/FSIBCLK */ + if (ick) { + clock->ick =3D devm_clk_get_optional(dev, is_porta ? "icka" : "ickb"); + if (IS_ERR(clock->ick)) + return dev_err_probe(dev, PTR_ERR(clock->ick), "Can't get ick clock\n"); + if (clock->ick =3D=3D clock->own) { + dev_err(dev, "cpu doesn't support ick clock\n"); + return -EINVAL; + } + } + + /* FSI-DIV */ + if (div) { + clock->div =3D devm_clk_get_optional(dev, is_porta ? "diva" : "divb"); + if (IS_ERR(clock->div)) + return dev_err_probe(dev, PTR_ERR(clock->div), "Can't get div clock\n"); + if (clock->div =3D=3D clock->own) { + dev_err(dev, "cpu doesn't support div clock\n"); + return -EINVAL; + } + } + + return 0; +} + static void fsi_pointer_update(struct fsi_stream *io, int size) { io->buff_sample_pos +=3D size; @@ -1684,15 +1696,6 @@ static int fsi_dai_set_fmt(struct snd_soc_dai *dai, = unsigned int fmt) break; } =20 - if (fsi_is_clk_master(fsi)) { - if (fsi->clk_cpg) - fsi_clk_init(dai->dev, fsi, 0, 1, 1, - fsi_clk_set_rate_cpg); - else - fsi_clk_init(dai->dev, fsi, 1, 1, 0, - fsi_clk_set_rate_external); - } - /* set format */ if (fsi_is_spdif(fsi)) ret =3D fsi_set_fmt_spdif(fsi); @@ -1992,6 +1995,7 @@ static int fsi_probe(struct platform_device *pdev) fsi->master =3D master; fsi_port_info_init(fsi, &info.port_a); fsi_handler_init(fsi, &info.port_a); + fsi_clk_init(&pdev->dev, fsi, !!(info.port_a.flags & SH_FSI_CLK_CPG)); ret =3D fsi_stream_probe(fsi, &pdev->dev); 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([183.91.15.56]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-82f0c50a8f7sm10232140b3a.56.2026.04.13.03.07.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Apr 2026 03:07:50 -0700 (PDT) From: phucduc.bui@gmail.com To: kuninori.morimoto.gx@renesas.com, broonie@kernel.org Cc: lgirdwood@gmail.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, perex@perex.cz, tiwai@suse.com, linux-sound@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, bui duc phuc Subject: [PATCH v2 5/6] arm: dts: renesas: r8a7740: Add clocks for FSI Date: Mon, 13 Apr 2026 17:06:59 +0700 Message-ID: <20260413100700.30995-6-phucduc.bui@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260413100700.30995-1-phucduc.bui@gmail.com> References: <20260413100700.30995-1-phucduc.bui@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: bui duc phuc Add the SPU clock to the FSI node to ensure it is enabled before register access, preventing potential system hangs. Also complete the FSI clock tree by adding: - CPG DIV6 clocks (icka/b) as functional parents - External clocks (xcka/b) from the board Define fsib nodes to support the clock hierarchy. Signed-off-by: bui duc phuc --- Changes in v2: - Rename "fsi" clock to "own" to match driver implementation. - Add missing clock names: "icka", "ickb", "xcka", "xckb". arch/arm/boot/dts/renesas/r8a7740.dtsi | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/renesas/r8a7740.dtsi b/arch/arm/boot/dts/ren= esas/r8a7740.dtsi index d13ab86c3ab4..b8d903b711be 100644 --- a/arch/arm/boot/dts/renesas/r8a7740.dtsi +++ b/arch/arm/boot/dts/renesas/r8a7740.dtsi @@ -393,7 +393,11 @@ sh_fsi2: sound@fe1f0000 { compatible =3D "renesas,fsi2-r8a7740", "renesas,sh_fsi2"; reg =3D <0xfe1f0000 0x400>; interrupts =3D ; - clocks =3D <&mstp3_clks R8A7740_CLK_FSI>; + clocks =3D <&mstp3_clks R8A7740_CLK_FSI>, <&spu_clk>, + <&fsia_clk>, <&fsib_clk>, <&fsiack_clk>, + <&fsibck_clk>; + clock-names =3D "own", "spu", "icka", "ickb", "xcka", + "xckb"; power-domains =3D <&pd_a4mp>; status =3D "disabled"; }; @@ -614,6 +618,12 @@ vou_clk: vou@e6150088 { <0>; #clock-cells =3D <0>; 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([183.91.15.56]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-82f0c50a8f7sm10232140b3a.56.2026.04.13.03.07.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Apr 2026 03:07:56 -0700 (PDT) From: phucduc.bui@gmail.com To: kuninori.morimoto.gx@renesas.com, broonie@kernel.org Cc: lgirdwood@gmail.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, perex@perex.cz, tiwai@suse.com, linux-sound@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, bui duc phuc Subject: [PATCH v2 6/6] ASoC: dt-bindings: renesas,fsi: add support for multiple clocks Date: Mon, 13 Apr 2026 17:07:00 +0700 Message-ID: <20260413100700.30995-7-phucduc.bui@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260413100700.30995-1-phucduc.bui@gmail.com> References: <20260413100700.30995-1-phucduc.bui@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: bui duc phuc The FSI on r8a7740 requires the SPU bus/bridge clock to be enabled before accessing its registers. Without this clock, any register access leads to a system hang as the FSI block sits behind the SPU bus. Update the binding to support a flexible positional clock list to properly describe the hardware clock tree, including: - SPU bus/bridge clock (spu) for register access. - CPG DIV6 clocks (icka/b) as functional clock parents. - FSI internal dividers (diva/b) for audio clock generation. - External clock inputs (xcka/b) provided by the board. Signed-off-by: bui duc phuc --- Changes in v2: - Rename FSI module clock to "own" to match driver. - Add "spu", "icka/b", "diva/b", "xcka/b" clock names. - Use YAML anchors to constrain clock-names properly. - Add "if" rule to require "spu" clock for r8a7740. - Update example with full clock configuration. - Clean up schema by moving allOf location. .../bindings/sound/renesas,fsi.yaml | 61 +++++++++++++++++-- 1 file changed, 56 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/sound/renesas,fsi.yaml b/Doc= umentation/devicetree/bindings/sound/renesas,fsi.yaml index df91991699a7..d0ae54f3d321 100644 --- a/Documentation/devicetree/bindings/sound/renesas,fsi.yaml +++ b/Documentation/devicetree/bindings/sound/renesas,fsi.yaml @@ -9,9 +9,6 @@ title: Renesas FIFO-buffered Serial Interface (FSI) maintainers: - Kuninori Morimoto =20 -allOf: - - $ref: dai-common.yaml# - properties: $nodename: pattern: "^sound@.*" @@ -38,7 +35,36 @@ properties: maxItems: 1 =20 clocks: - maxItems: 1 + description: | + Clock driving the FSI Controller. The first clock must be + the module clock ("own"). + minItems: 1 + maxItems: 8 + + clock-names: + description: | + Names of clocks corresponding to entries in "clocks": + - "own": Main FSI module clock (must be first and always present) + - "spu": SPU bus/bridge clock. On R8A7740, this clock must be + enabled to allow register access as the FSI block is connected + behind the SPU bus. + - "icka" / "ickb": CPG DIV6 functional clocks for FSI port A/B + - "diva"/"divb": Internal FSI dividers for port A/B used for + audio clock generation + - "xcka"/"xckb": External clock inputs for FSI port A/B + provided by the board + minItems: 1 + items: + - const: own + - &fsi_all_clks + enum: [spu, icka, ickb, diva, divb, xcka, xckb] + - &fsi_no_spu_clks + enum: [icka, ickb, diva, divb, xcka, xckb] + - *fsi_no_spu_clks + - *fsi_no_spu_clks + - *fsi_no_spu_clks + - *fsi_no_spu_clks + - *fsi_no_spu_clks =20 power-domains: maxItems: 1 @@ -69,6 +95,27 @@ required: =20 unevaluatedProperties: false =20 +allOf: + - $ref: dai-common.yaml# + - if: + properties: + compatible: + contains: + const: renesas,fsi2-r8a7740 + then: + properties: + clock-names: + minItems: 2 + items: + - const: own + - const: spu + - *fsi_no_spu_clks + - *fsi_no_spu_clks + - *fsi_no_spu_clks + - *fsi_no_spu_clks + - *fsi_no_spu_clks + - *fsi_no_spu_clks + examples: - | #include @@ -77,7 +124,11 @@ examples: compatible =3D "renesas,fsi2-r8a7740", "renesas,sh_fsi2"; reg =3D <0xfe1f0000 0x400>; interrupts =3D ; - clocks =3D <&mstp3_clks R8A7740_CLK_FSI>; + clocks =3D <&mstp3_clks R8A7740_CLK_FSI>, <&spu_clk>, + <&fsia_clk>, <&fsib_clk>, <&fsidiva_clk>, + <&fsidivb_clk>,<&fsiack_clk>,<&fsibck_clk>; + clock-names =3D "own", "spu", "icka", "ickb", + "diva", "divb", "xcka", "xckb"; power-domains =3D <&pd_a4mp>; =20 #sound-dai-cells =3D <1>; --=20 2.43.0