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Mon, 13 Apr 2026 03:05:43 -0700 (PDT) From: Khalil X-Google-Original-From: Khalil To: broonie@kernel.org, hansg@kernel.org, ilpo.jarvinen@linux.intel.com Cc: rf@opensource.cirrus.com, linux-spi@vger.kernel.org, platform-driver-x86@vger.kernel.org, linux-kernel@vger.kernel.org, Khalil , Khalil Subject: [PATCH v2 1/3] spi: Preserve preset cs_gpiod in __spi_add_device() Date: Mon, 13 Apr 2026 12:05:28 +0200 Message-ID: <20260413100530.580649-2-khalil@rentman.nl> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260413100530.580649-1-khalil@rentman.nl> References: <20260413100530.580649-1-khalil@rentman.nl> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" __spi_add_device() unconditionally overwrites spi->cs_gpiod[] from ctlr->cs_gpiods[cs], even if the caller has already set a GPIO descriptor on the device. This prevents drivers like serial-multi-instantiate from pre-configuring a GPIO chip select acquired from ACPI before adding the device. Skip the overwrite when the device already has a cs_gpiod set for the given index, allowing callers to preset GPIO chip selects that aren't described in the controller's cs-gpios property. This is useful on platforms where the ACPI _DSD cs-gpios property on the SPI controller is incomplete, but the peripheral's ACPI node does contain the correct GpioIo resource for its chip select. Suggested-by: Richard Fitzgerald Signed-off-by: Khalil --- drivers/spi/spi.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c index a0b2bd3b8..64be99d13 100644 --- a/drivers/spi/spi.c +++ b/drivers/spi/spi.c @@ -734,7 +734,8 @@ static int __spi_add_device(struct spi_device *spi, str= uct spi_device *parent) =20 for (idx =3D 0; idx < spi->num_chipselect; idx++) { cs =3D spi_get_chipselect(spi, idx); - spi_set_csgpiod(spi, idx, ctlr->cs_gpiods[cs]); + if (!spi_get_csgpiod(spi, idx)) + spi_set_csgpiod(spi, idx, ctlr->cs_gpiods[cs]); } } =20 --=20 2.43.0 From nobody Mon Jun 15 16:31:31 2026 Received: from mail-ed1-f53.google.com (mail-ed1-f53.google.com [209.85.208.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 51AD63B6BE4 for ; Mon, 13 Apr 2026 10:05:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.53 ARC-Seal: i=1; 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Mon, 13 Apr 2026 03:05:45 -0700 (PDT) Received: from khalil-hp.home ([62.250.67.33]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b9d6e5c5824sm297805066b.38.2026.04.13.03.05.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Apr 2026 03:05:44 -0700 (PDT) From: Khalil X-Google-Original-From: Khalil To: broonie@kernel.org, hansg@kernel.org, ilpo.jarvinen@linux.intel.com Cc: rf@opensource.cirrus.com, linux-spi@vger.kernel.org, platform-driver-x86@vger.kernel.org, linux-kernel@vger.kernel.org, Khalil , Khalil Subject: [PATCH v2 2/3] platform/x86: serial-multi-instantiate: Fix SPI chip select on platforms with incomplete ACPI cs-gpios Date: Mon, 13 Apr 2026 12:05:29 +0200 Message-ID: <20260413100530.580649-3-khalil@rentman.nl> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260413100530.580649-1-khalil@rentman.nl> References: <20260413100530.580649-1-khalil@rentman.nl> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Some HP laptops with Intel Lunar Lake and dual Cirrus Logic CS35L56 amplifiers over SPI have an incomplete cs-gpios property in the SPI controller's _DSD - it only declares the first chip select. The remaining chip select GPIOs are defined as GpioIo resources in the peripheral's ACPI node but are not referenced by the controller. This causes the SPI framework to reject devices whose chip select exceeds num_chipselect with -EINVAL, preventing the second amplifier from probing. Fix this on known affected platforms by: 1. Adding a DMI quirk table to identify affected systems 2. For devices with chip selects outside the controller's range, acquiring the GPIO from the peripheral's ACPI GpioIo resource 3. Extending num_chipselect and reallocating the controller's cs_gpiods array to install the GPIO descriptor 4. Setting SPI_CONTROLLER_GPIO_SS so the framework calls both the GPIO toggle and controller->set_cs (needed for clock gating on Intel LPSS controllers) Only chip selects beyond the controller's num_chipselect are fixed up. Chip selects within range with a NULL cs_gpiods entry are left alone, as NULL means "native chip select" which is intentional. Tested on HP EliteBook 8 G1i 16 inch (board 8D8A) with 2x CS35L56 Rev B0 amplifiers. Both amplifiers probe and produce audio. Signed-off-by: Khalil --- .../platform/x86/serial-multi-instantiate.c | 168 ++++++++++++++++++ 1 file changed, 168 insertions(+) diff --git a/drivers/platform/x86/serial-multi-instantiate.c b/drivers/plat= form/x86/serial-multi-instantiate.c index 1a369334f..0d30bd0a7 100644 --- a/drivers/platform/x86/serial-multi-instantiate.c +++ b/drivers/platform/x86/serial-multi-instantiate.c @@ -8,6 +8,10 @@ =20 #include #include +#include +#include +#include +#include #include #include #include @@ -46,6 +50,53 @@ struct smi { int spi_num; struct i2c_client **i2c_devs; struct spi_device **spi_devs; + struct gpio_desc *cs_gpio; +}; + +/* + * Quirk data for platforms with broken ACPI SPI chip select descriptions. + * cs_gpio_idx: index of the GpioIo resource in the ACPI _CRS that provides + * the chip select GPIO for devices missing a proper cs-gpios + * entry on the SPI controller. + */ +struct smi_cs_gpio_quirk { + int cs_gpio_idx; +}; + +static const struct smi_cs_gpio_quirk hp_elitebook_8g1i_quirk =3D { + .cs_gpio_idx =3D 0, +}; + +/* + * DMI table of platforms with broken SPI chip select ACPI descriptions. + * + * These systems have multiple SPI peripherals (e.g., dual CS35L56 + * amplifiers) but the SPI controller's _DSD cs-gpios property is + * incomplete - it only declares the first chip select. The remaining + * chip select GPIOs are defined as GpioIo resources in the peripheral's + * ACPI node but are not referenced by the controller. + */ +static const struct dmi_system_id smi_cs_gpio_dmi_table[] =3D { + { + .ident =3D "HP EliteBook 8 G1i 16 inch", + .matches =3D { + DMI_MATCH(DMI_SYS_VENDOR, "HP"), + DMI_MATCH(DMI_BOARD_NAME, "8D8A"), + }, + .driver_data =3D (void *)&hp_elitebook_8g1i_quirk, + }, + { } +}; + +/* + * ACPI GPIO mapping for the chip select GpioIo resource. + * Maps "cs-gpios" to the GpioIo resource at index 0 of the ACPI _CRS. + */ +static const struct acpi_gpio_params smi_cs_gpio_params =3D { 0, 0, false = }; + +static const struct acpi_gpio_mapping smi_cs_gpio_mapping[] =3D { + { "cs-gpios", &smi_cs_gpio_params, 1 }, + { } }; =20 static int smi_get_irq(struct platform_device *pdev, struct acpi_device *a= dev, @@ -99,6 +150,101 @@ static void smi_devs_unregister(struct smi *smi) } } =20 +/* + * smi_spi_setup_cs_gpio - Fix up chip select for a device on a platform + * with broken ACPI cs-gpios description. + * + * On affected platforms, the SPI controller's cs-gpios property is incomp= lete, + * so the framework has no GPIO descriptor for some chip selects. This cau= ses + * __spi_add_device() to reject the device with -EINVAL (cs >=3D num_chips= elect). + * + * This function: + * 1. Extends num_chipselect if the device's CS is out of range + * 2. Reallocates cs_gpiods to match, preventing out-of-bounds access + * in __spi_add_device() + * 3. Installs the GPIO from the peripheral's ACPI node into the + * controller's cs_gpiods array so __spi_add_device() propagates + * it to the device + * 4. Sets SPI_CONTROLLER_GPIO_SS so the framework calls both the GPIO + * toggle and controller->set_cs (needed for clock gating on Intel + * LPSS controllers) + */ +static int smi_spi_setup_cs_gpio(struct device *dev, + struct spi_device *spi_dev, + struct smi *smi, + const struct smi_cs_gpio_quirk *quirk) +{ + struct spi_controller *ctlr =3D spi_dev->controller; + struct gpio_desc **new_gpiods; + u16 cs =3D spi_get_chipselect(spi_dev, 0); + + /* + * Only fix up chip selects that the controller doesn't know about. + * A NULL cs_gpiods[cs] within the controller's num_chipselect range + * means "native chip select" - that's intentional, not broken. + * The broken case is when cs >=3D num_chipselect, meaning the ACPI + * cs-gpios property on the controller was incomplete. + */ + if (cs < ctlr->num_chipselect) + return 0; + + /* Extend num_chipselect to cover this device */ + dev_info(dev, "Extending num_chipselect from %u to %u for CS%u\n", + ctlr->num_chipselect, cs + 1, cs); + ctlr->num_chipselect =3D cs + 1; + + /* Acquire the CS GPIO from the ACPI GpioIo resource if not yet done */ + if (!smi->cs_gpio) { + int ret; + + ret =3D devm_acpi_dev_add_driver_gpios(dev, smi_cs_gpio_mapping); + if (ret) { + dev_warn(dev, "Failed to add CS GPIO mapping: %d\n", ret); + return ret; + } + + smi->cs_gpio =3D devm_gpiod_get(dev, "cs", GPIOD_OUT_HIGH); + if (IS_ERR(smi->cs_gpio)) { + dev_warn(dev, "Failed to get CS GPIO: %ld\n", + PTR_ERR(smi->cs_gpio)); + smi->cs_gpio =3D NULL; + return -ENOENT; + } + dev_info(dev, "Acquired CS GPIO for CS%u from ACPI GpioIo[%d]\n", + cs, quirk->cs_gpio_idx); + } + + /* + * Reallocate the controller's cs_gpiods array to accommodate the + * new num_chipselect, and install the GPIO descriptor. This is + * necessary because __spi_add_device() unconditionally reads + * ctlr->cs_gpiods[cs] to set the device's cs_gpiod. + */ + new_gpiods =3D devm_kcalloc(&ctlr->dev, ctlr->num_chipselect, + sizeof(*new_gpiods), GFP_KERNEL); + if (!new_gpiods) + return -ENOMEM; + + if (ctlr->cs_gpiods) { + unsigned int i; + + for (i =3D 0; i < cs; i++) + new_gpiods[i] =3D ctlr->cs_gpiods[i]; + } + new_gpiods[cs] =3D smi->cs_gpio; + ctlr->cs_gpiods =3D new_gpiods; + + /* + * SPI_CONTROLLER_GPIO_SS ensures the framework calls both the + * GPIO CS toggle and controller->set_cs(). This is required on + * Intel LPSS controllers where set_cs handles clock gating. + */ + ctlr->flags |=3D SPI_CONTROLLER_GPIO_SS; + + dev_info(dev, "Installed GPIO CS on controller for CS%u\n", cs); + return 0; +} + /** * smi_spi_probe - Instantiate multiple SPI devices from inst array * @pdev: Platform device @@ -112,10 +258,19 @@ static int smi_spi_probe(struct platform_device *pdev= , struct smi *smi, { struct device *dev =3D &pdev->dev; struct acpi_device *adev =3D ACPI_COMPANION(dev); + const struct dmi_system_id *dmi_id; + const struct smi_cs_gpio_quirk *quirk =3D NULL; struct spi_controller *ctlr; struct spi_device *spi_dev; char name[50]; int i, ret, count; + u16 cs; + + dmi_id =3D dmi_first_match(smi_cs_gpio_dmi_table); + if (dmi_id) { + quirk =3D dmi_id->driver_data; + dev_info(dev, "Applying CS GPIO quirk for %s\n", dmi_id->ident); + } =20 ret =3D acpi_spi_count_resources(adev); if (ret < 0) @@ -139,6 +294,19 @@ static int smi_spi_probe(struct platform_device *pdev,= struct smi *smi, } =20 ctlr =3D spi_dev->controller; + cs =3D spi_get_chipselect(spi_dev, 0); + + /* + * On quirked platforms, fix up the chip select GPIO for + * devices that would otherwise fail due to incomplete + * ACPI cs-gpios on the SPI controller. + */ + if (quirk) { + ret =3D smi_spi_setup_cs_gpio(dev, spi_dev, smi, quirk); + if (ret) + dev_dbg(dev, "CS GPIO setup returned %d for CS%u\n", + ret, cs); + } =20 strscpy(spi_dev->modalias, inst_array[i].type); =20 --=20 2.43.0 From nobody Mon Jun 15 16:31:31 2026 Received: from mail-ed1-f49.google.com (mail-ed1-f49.google.com [209.85.208.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D79223B7748 for ; Mon, 13 Apr 2026 10:05:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.49 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776074750; cv=none; b=TMlNJcr7Ez8dTFNjWbxP/30WwC77aAVPptHr26Tvjxoot4cVZ7SOCpaAJXXxLL6fNAxLVNwedicIVtXi67jGkaSRyXgrMskuIwGnSjs7NN4Q31qjebEYHYV9o4m2RILJl59VcJaMfQua5ZDhlxP87/WTh0WE6PcozrP4iUTzgKI= ARC-Message-Signature: i=1; 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Mon, 13 Apr 2026 03:05:46 -0700 (PDT) Received: from khalil-hp.home ([62.250.67.33]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b9d6e5c5824sm297805066b.38.2026.04.13.03.05.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Apr 2026 03:05:46 -0700 (PDT) From: Khalil X-Google-Original-From: Khalil To: broonie@kernel.org, hansg@kernel.org, ilpo.jarvinen@linux.intel.com Cc: rf@opensource.cirrus.com, linux-spi@vger.kernel.org, platform-driver-x86@vger.kernel.org, linux-kernel@vger.kernel.org, Khalil , Khalil Subject: [PATCH v2 3/3] spi: pxa2xx: Handle clock gating for GPIO chip select devices Date: Mon, 13 Apr 2026 12:05:30 +0200 Message-ID: <20260413100530.580649-4-khalil@rentman.nl> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260413100530.580649-1-khalil@rentman.nl> References: <20260413100530.580649-1-khalil@rentman.nl> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" On Intel LPSS SPI controllers (Cannon Lake and later) with dynamic clock gating (cs_clk_stays_gated=3Dtrue), the SPI clock is gated when no native chip select is asserted. When using a GPIO chip select (via SPI_CONTROLLER_GPIO_SS), the SPI framework toggles the GPIO and also calls the controller's set_cs callback. Handle this in the pxa2xx cs_assert/cs_deassert functions: when the device uses a GPIO chip select on an LPSS controller, assert native CS in the control register to enable the clock, and force the clock gate on. On deassert, restore both. This is needed on platforms where serial-multi-instantiate installs a GPIO chip select from the peripheral's ACPI GpioIo resource to work around an incomplete cs-gpios property on the SPI controller. Signed-off-by: Khalil --- drivers/spi/spi-pxa2xx.c | 45 ++++++++++++++++++++++++++++++++++++---- 1 file changed, 41 insertions(+), 4 deletions(-) diff --git a/drivers/spi/spi-pxa2xx.c b/drivers/spi/spi-pxa2xx.c index 6291d7c2e..fe5762063 100644 --- a/drivers/spi/spi-pxa2xx.c +++ b/drivers/spi/spi-pxa2xx.c @@ -419,20 +419,43 @@ static void cs_assert(struct spi_device *spi) { struct driver_data *drv_data =3D spi_controller_get_devdata(spi->controller); + const struct lpss_config *config; =20 if (drv_data->ssp_type =3D=3D CE4100_SSP) { pxa2xx_spi_write(drv_data, SSSR, spi_get_chipselect(spi, 0)); return; } =20 - if (is_lpss_ssp(drv_data)) - lpss_ssp_cs_control(spi, true); + if (is_lpss_ssp(drv_data)) { + config =3D lpss_get_config(drv_data); + + if (spi_is_csgpiod(spi)) { + /* + * GPIO handles the actual chip select to the device. + * On LPSS controllers with dynamic clock gating, the + * SPI clock won't run unless the native CS state says + * "asserted" in the CS control register. Assert native + * CS in the register to enable the clock, and force + * the clock gate on. + */ + lpss_ssp_cs_control(spi, true); + if (config->cs_clk_stays_gated) { + __lpss_ssp_update_priv(drv_data, + LPSS_PRIV_CLOCK_GATE, + LPSS_PRIV_CLOCK_GATE_CLK_CTL_MASK, + LPSS_PRIV_CLOCK_GATE_CLK_CTL_FORCE_ON); + } + } else { + lpss_ssp_cs_control(spi, true); + } + } } =20 static void cs_deassert(struct spi_device *spi) { struct driver_data *drv_data =3D spi_controller_get_devdata(spi->controller); + const struct lpss_config *config; unsigned long timeout; =20 if (drv_data->ssp_type =3D=3D CE4100_SSP) @@ -444,8 +467,22 @@ static void cs_deassert(struct spi_device *spi) !time_after(jiffies, timeout)) cpu_relax(); =20 - if (is_lpss_ssp(drv_data)) - lpss_ssp_cs_control(spi, false); + if (is_lpss_ssp(drv_data)) { + config =3D lpss_get_config(drv_data); + + if (spi_is_csgpiod(spi)) { + /* Deassert native CS and restore clock gating */ + lpss_ssp_cs_control(spi, false); + if (config->cs_clk_stays_gated) { + __lpss_ssp_update_priv(drv_data, + LPSS_PRIV_CLOCK_GATE, + LPSS_PRIV_CLOCK_GATE_CLK_CTL_MASK, + LPSS_PRIV_CLOCK_GATE_CLK_CTL_FORCE_OFF); + } + } else { + lpss_ssp_cs_control(spi, false); + } + } } =20 static void pxa2xx_spi_set_cs(struct spi_device *spi, bool level) --=20 2.43.0