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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2d561cd3138sm15260935eec.14.2026.04.12.23.26.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 12 Apr 2026 23:26:18 -0700 (PDT) From: Qiang Yu Date: Sun, 12 Apr 2026 23:25:56 -0700 Subject: [PATCH v3 1/5] dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Add support for glymur Gen5 x8 bifurcation mode Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260412-glymur_gen5x8_phy_0413-v3-1-affcebc16b8b@oss.qualcomm.com> References: <20260412-glymur_gen5x8_phy_0413-v3-0-affcebc16b8b@oss.qualcomm.com> In-Reply-To: <20260412-glymur_gen5x8_phy_0413-v3-0-affcebc16b8b@oss.qualcomm.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Qiang Yu X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1776061577; l=4060; i=qiang.yu@oss.qualcomm.com; s=20250513; h=from:subject:message-id; bh=37ntqnYxbt/tnoGEfVBaNuji1qCkMWieDHTWp7+jFXY=; b=h6UmKLAVvuw2ViAHtaZJ0N1KEw+2AZsfRlJ6f9XTCia8lln/Ov2M9UD4AHf7YtyeyzuSzL85A 4Rk+pFMhoSpDN2CMzdPm2prdQeo1NHPSOE4T/BZqD8B57IpE6RgiG5w X-Developer-Key: i=qiang.yu@oss.qualcomm.com; a=ed25519; pk=Rr94t+fykoieF1ngg/bXxEfr5KoQxeXPtYxM8fBQTAI= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDEzMDA2MCBTYWx0ZWRfXw4eK9iDY3DAb QJcIBe0vszfxhB79YAtR5nTH3sUl+83gX4rZyzXS+ZFiqzPz7YxFHhUkBQ62HwoBA+M/bh4PtOj Ir4WyROmcZyrIfXrbefKWv49Gv/8QhsoqKN8zhW9zsnj+BGjRufib+h3MdR2QRNKagTyQmGa/fi 7Vh/cNjVh15YVz8pVPtusjDnIoj2Yc80gYUaj0cAapwkvvY9Z/PRz/xcSEmno7S4OFvpzV1r65Y VaY3TqxPXiS44pV/6bPvvI80yCXuAvnyp6Gty/rR2WEtpBrTkDkcGuFM6q43F0l55lUexn0MoBU izXJaQuvqVrnlgC7L8jOIIe2v91w6PNvN8KTryLPsx9Wc2Lij/DAvxRKMm66dAbYTu7mWlioRIg 1RXZliMB5GEdPsI79wBOignUpcoelnus17HXxDVxGsC36HnG8Hp2LYGanEaeB1kE0/kr8REWaCJ 3Go4l2FQkscRZHBD7xg== X-Proofpoint-ORIG-GUID: VL3UkU3OakJx-XfDRLj5nPYzyFo41Iqv X-Authority-Analysis: v=2.4 cv=FOkrAeos c=1 sm=1 tr=0 ts=69dc8c8c cx=c_pps a=wEP8DlPgTf/vqF+yE6f9lg==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=EUspDBNiAAAA:8 a=HOj_8Gw7N_1wnwFbGYcA:9 a=QEXdDO2ut3YA:10 a=bBxd6f-gb0O0v-kibOvt:22 X-Proofpoint-GUID: VL3UkU3OakJx-XfDRLj5nPYzyFo41Iqv X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-13_02,2026-04-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 malwarescore=0 impostorscore=0 suspectscore=0 priorityscore=1501 clxscore=1015 spamscore=0 phishscore=0 bulkscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604010000 definitions=main-2604130060 The Glymur SoC has pcie3a and pcie3b PHYs that can operate in two modes: 1. Independent 4-lane mode: Each PHY operates as a separate PCIe Gen5 4-lane interface, compatible with qcom,glymur-qmp-gen5x4-pcie-phy 2. Bifurcation mode (8-lane): pcie3a phy acts as leader and pcie3b phy as follower to form a single 8-lane PCIe Gen5 interface In bifurcation mode, the hardware design requires controlling additional resources beyond the standard pcie3a PHY configuration: - pcie3b's aux_clk (phy_b_aux) - pcie3b's phy_gdsc power domain - pcie3b's bcr/nocsr reset Add qcom,glymur-qmp-gen5x8-pcie-phy compatible string to document this 8-lane bifurcation configuration. The phy_b_aux clock is used as the 6th clock instead of pipediv2, requiring the clock-names enum to be extended to support both [phy_b_aux, pipediv2] options at index 5. This follows the existing pattern used for [rchng, refgen] clocks at index 3. Signed-off-by: Qiang Yu --- .../bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 53 ++++++++++++++++++= ---- 1 file changed, 45 insertions(+), 8 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-p= hy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.= yaml index 3a35120a77ec0ceb814a1cdcacff32fef32b4f7b..14eba5d705b1956c1bb00cc8c95= 171ed6488299b 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml @@ -18,6 +18,7 @@ properties: enum: - qcom,glymur-qmp-gen4x2-pcie-phy - qcom,glymur-qmp-gen5x4-pcie-phy + - qcom,glymur-qmp-gen5x8-pcie-phy - qcom,kaanapali-qmp-gen3x2-pcie-phy - qcom,qcs615-qmp-gen3x1-pcie-phy - qcom,qcs8300-qmp-gen4x2-pcie-phy @@ -68,20 +69,27 @@ properties: - const: ref - enum: [rchng, refgen] - const: pipe - - const: pipediv2 + - enum: [phy_b_aux, pipediv2] =20 power-domains: - maxItems: 1 + minItems: 1 + items: + - description: PCIe PHY power domain. For PHYs supporting + bifurcation mode, this is the leader PHY power domain. + - description: Additional PCIe PHY power domain for PHYs supporting + bifurcation mode, used by the follower PHY. =20 resets: minItems: 1 - maxItems: 2 + maxItems: 4 =20 reset-names: minItems: 1 items: - const: phy - const: phy_nocsr + - const: phy_b + - const: phy_b_nocsr =20 vdda-phy-supply: true =20 @@ -183,6 +191,7 @@ allOf: enum: - qcom,glymur-qmp-gen4x2-pcie-phy - qcom,glymur-qmp-gen5x4-pcie-phy + - qcom,glymur-qmp-gen5x8-pcie-phy - qcom,qcs8300-qmp-gen4x2-pcie-phy - qcom,sa8775p-qmp-gen4x2-pcie-phy - qcom,sa8775p-qmp-gen4x4-pcie-phy @@ -201,6 +210,21 @@ allOf: clock-names: minItems: 6 =20 + - if: + properties: + compatible: + contains: + enum: + - qcom,glymur-qmp-gen5x8-pcie-phy + then: + properties: + power-domains: + minItems: 2 + else: + properties: + power-domains: + maxItems: 1 + - if: properties: compatible: @@ -223,11 +247,24 @@ allOf: reset-names: minItems: 2 else: - properties: - resets: - maxItems: 1 - reset-names: - maxItems: 1 + if: + properties: + compatible: + contains: + enum: + - qcom,glymur-qmp-gen5x8-pcie-phy + then: + properties: + resets: + minItems: 4 + reset-names: + minItems: 4 + else: + properties: + resets: + maxItems: 1 + reset-names: + maxItems: 1 =20 - if: properties: --=20 2.34.1