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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2d561cd3138sm15260935eec.14.2026.04.12.23.26.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 12 Apr 2026 23:26:18 -0700 (PDT) From: Qiang Yu Date: Sun, 12 Apr 2026 23:25:56 -0700 Subject: [PATCH v3 1/5] dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Add support for glymur Gen5 x8 bifurcation mode Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260412-glymur_gen5x8_phy_0413-v3-1-affcebc16b8b@oss.qualcomm.com> References: <20260412-glymur_gen5x8_phy_0413-v3-0-affcebc16b8b@oss.qualcomm.com> In-Reply-To: <20260412-glymur_gen5x8_phy_0413-v3-0-affcebc16b8b@oss.qualcomm.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Qiang Yu X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1776061577; l=4060; i=qiang.yu@oss.qualcomm.com; s=20250513; h=from:subject:message-id; bh=37ntqnYxbt/tnoGEfVBaNuji1qCkMWieDHTWp7+jFXY=; b=h6UmKLAVvuw2ViAHtaZJ0N1KEw+2AZsfRlJ6f9XTCia8lln/Ov2M9UD4AHf7YtyeyzuSzL85A 4Rk+pFMhoSpDN2CMzdPm2prdQeo1NHPSOE4T/BZqD8B57IpE6RgiG5w X-Developer-Key: i=qiang.yu@oss.qualcomm.com; a=ed25519; pk=Rr94t+fykoieF1ngg/bXxEfr5KoQxeXPtYxM8fBQTAI= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDEzMDA2MCBTYWx0ZWRfXw4eK9iDY3DAb QJcIBe0vszfxhB79YAtR5nTH3sUl+83gX4rZyzXS+ZFiqzPz7YxFHhUkBQ62HwoBA+M/bh4PtOj Ir4WyROmcZyrIfXrbefKWv49Gv/8QhsoqKN8zhW9zsnj+BGjRufib+h3MdR2QRNKagTyQmGa/fi 7Vh/cNjVh15YVz8pVPtusjDnIoj2Yc80gYUaj0cAapwkvvY9Z/PRz/xcSEmno7S4OFvpzV1r65Y VaY3TqxPXiS44pV/6bPvvI80yCXuAvnyp6Gty/rR2WEtpBrTkDkcGuFM6q43F0l55lUexn0MoBU izXJaQuvqVrnlgC7L8jOIIe2v91w6PNvN8KTryLPsx9Wc2Lij/DAvxRKMm66dAbYTu7mWlioRIg 1RXZliMB5GEdPsI79wBOignUpcoelnus17HXxDVxGsC36HnG8Hp2LYGanEaeB1kE0/kr8REWaCJ 3Go4l2FQkscRZHBD7xg== X-Proofpoint-ORIG-GUID: VL3UkU3OakJx-XfDRLj5nPYzyFo41Iqv X-Authority-Analysis: v=2.4 cv=FOkrAeos c=1 sm=1 tr=0 ts=69dc8c8c cx=c_pps a=wEP8DlPgTf/vqF+yE6f9lg==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=EUspDBNiAAAA:8 a=HOj_8Gw7N_1wnwFbGYcA:9 a=QEXdDO2ut3YA:10 a=bBxd6f-gb0O0v-kibOvt:22 X-Proofpoint-GUID: VL3UkU3OakJx-XfDRLj5nPYzyFo41Iqv X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-13_02,2026-04-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 malwarescore=0 impostorscore=0 suspectscore=0 priorityscore=1501 clxscore=1015 spamscore=0 phishscore=0 bulkscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604010000 definitions=main-2604130060 The Glymur SoC has pcie3a and pcie3b PHYs that can operate in two modes: 1. Independent 4-lane mode: Each PHY operates as a separate PCIe Gen5 4-lane interface, compatible with qcom,glymur-qmp-gen5x4-pcie-phy 2. Bifurcation mode (8-lane): pcie3a phy acts as leader and pcie3b phy as follower to form a single 8-lane PCIe Gen5 interface In bifurcation mode, the hardware design requires controlling additional resources beyond the standard pcie3a PHY configuration: - pcie3b's aux_clk (phy_b_aux) - pcie3b's phy_gdsc power domain - pcie3b's bcr/nocsr reset Add qcom,glymur-qmp-gen5x8-pcie-phy compatible string to document this 8-lane bifurcation configuration. The phy_b_aux clock is used as the 6th clock instead of pipediv2, requiring the clock-names enum to be extended to support both [phy_b_aux, pipediv2] options at index 5. This follows the existing pattern used for [rchng, refgen] clocks at index 3. Signed-off-by: Qiang Yu --- .../bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 53 ++++++++++++++++++= ---- 1 file changed, 45 insertions(+), 8 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-p= hy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.= yaml index 3a35120a77ec0ceb814a1cdcacff32fef32b4f7b..14eba5d705b1956c1bb00cc8c95= 171ed6488299b 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml @@ -18,6 +18,7 @@ properties: enum: - qcom,glymur-qmp-gen4x2-pcie-phy - qcom,glymur-qmp-gen5x4-pcie-phy + - qcom,glymur-qmp-gen5x8-pcie-phy - qcom,kaanapali-qmp-gen3x2-pcie-phy - qcom,qcs615-qmp-gen3x1-pcie-phy - qcom,qcs8300-qmp-gen4x2-pcie-phy @@ -68,20 +69,27 @@ properties: - const: ref - enum: [rchng, refgen] - const: pipe - - const: pipediv2 + - enum: [phy_b_aux, pipediv2] =20 power-domains: - maxItems: 1 + minItems: 1 + items: + - description: PCIe PHY power domain. For PHYs supporting + bifurcation mode, this is the leader PHY power domain. + - description: Additional PCIe PHY power domain for PHYs supporting + bifurcation mode, used by the follower PHY. =20 resets: minItems: 1 - maxItems: 2 + maxItems: 4 =20 reset-names: minItems: 1 items: - const: phy - const: phy_nocsr + - const: phy_b + - const: phy_b_nocsr =20 vdda-phy-supply: true =20 @@ -183,6 +191,7 @@ allOf: enum: - qcom,glymur-qmp-gen4x2-pcie-phy - qcom,glymur-qmp-gen5x4-pcie-phy + - qcom,glymur-qmp-gen5x8-pcie-phy - qcom,qcs8300-qmp-gen4x2-pcie-phy - qcom,sa8775p-qmp-gen4x2-pcie-phy - qcom,sa8775p-qmp-gen4x4-pcie-phy @@ -201,6 +210,21 @@ allOf: clock-names: minItems: 6 =20 + - if: + properties: + compatible: + contains: + enum: + - qcom,glymur-qmp-gen5x8-pcie-phy + then: + properties: + power-domains: + minItems: 2 + else: + properties: + power-domains: + maxItems: 1 + - if: properties: compatible: @@ -223,11 +247,24 @@ allOf: reset-names: minItems: 2 else: - properties: - resets: - maxItems: 1 - reset-names: - maxItems: 1 + if: + properties: + compatible: + contains: + enum: + - qcom,glymur-qmp-gen5x8-pcie-phy + then: + properties: + resets: + minItems: 4 + reset-names: + minItems: 4 + else: + properties: + resets: + maxItems: 1 + reset-names: + maxItems: 1 =20 - if: properties: --=20 2.34.1 From nobody Mon Apr 13 21:03:16 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2C5353921C1 for ; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2d561cd3138sm15260935eec.14.2026.04.12.23.26.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 12 Apr 2026 23:26:19 -0700 (PDT) From: Qiang Yu Date: Sun, 12 Apr 2026 23:25:57 -0700 Subject: [PATCH v3 2/5] phy: qcom: qmp-pcie: Add multiple power-domains support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260412-glymur_gen5x8_phy_0413-v3-2-affcebc16b8b@oss.qualcomm.com> References: <20260412-glymur_gen5x8_phy_0413-v3-0-affcebc16b8b@oss.qualcomm.com> In-Reply-To: <20260412-glymur_gen5x8_phy_0413-v3-0-affcebc16b8b@oss.qualcomm.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Qiang Yu , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1776061577; l=2571; i=qiang.yu@oss.qualcomm.com; s=20250513; h=from:subject:message-id; bh=WuxD6kGdL+V30CDieIdjcJTNov5dAUcLLKr/2N6fJU4=; b=oIeAAqEG9SEUZcNaYwhRdKHtYtS+diUCf/WWHL1ZhagoSPXt4BK35q/TEcJmwzjJWYyfJOvuO R/LkzvwtIECDN9YfRwvv8LAB50WN4CywYm/PTyFq8z4kB1rhRXMUaJr X-Developer-Key: i=qiang.yu@oss.qualcomm.com; a=ed25519; pk=Rr94t+fykoieF1ngg/bXxEfr5KoQxeXPtYxM8fBQTAI= X-Authority-Analysis: v=2.4 cv=PuijqQM3 c=1 sm=1 tr=0 ts=69dc8c8d cx=c_pps a=Uww141gWH0fZj/3QKPojxA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8 a=eu5IZVYEi8O4nexjJlAA:9 a=QEXdDO2ut3YA:10 a=PxkB5W3o20Ba91AHUih5:22 X-Proofpoint-ORIG-GUID: CGczyK0g4XJMIOca5i3Yb4GKQih-lPUw X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDEzMDA2MCBTYWx0ZWRfX7o6tUSQdnL4V dWcLHH7jVT+mB2DFPpxLB/VVOsQYOxDehdTXlZHx0qwD4b8065xHV0vkvxD0DapHFtDR442HFVh HdGXZVceOMfnoD1mDKL+hW4muCgSpRDZQSZhfX9KH+SnOvhnNT5VGPqRn46A+TE5p817z/+tOE3 VJ6DI6BZw1UuBOEa2At9LUO9amUgeCkijuWb8hHl706eMP3qP1+oM1xpkKotiCfuaBz9jHjREG5 ddYiv1UZ5SZ+F17sNgv4lynRMdiB4tgcrAGOT/vNRk9aeZvTvOnY9QmcSY0YXVPykcyHHcSq/pW yg5KGntKNdvF2HqV+PTiu6qCyABlag9/13SegzbtlA36IScJlgWKECzjVUcZhNoCWFuH5ruY7nA Stg5h9v1a7PuozMU9nl3ykOCDxP5O2D1JoLqqQJTv9rrlUB8jABds4cRrhtcF9H8PHj/QHdFRB+ XiCX09pugh8UcM6zCIw== X-Proofpoint-GUID: CGczyK0g4XJMIOca5i3Yb4GKQih-lPUw X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-13_02,2026-04-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 lowpriorityscore=0 suspectscore=0 spamscore=0 phishscore=0 malwarescore=0 clxscore=1015 impostorscore=0 adultscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604010000 definitions=main-2604130060 The Glymur SoC's 3rd PCIe instance supports 8-lane mode using two PHYs in a bifurcated configuration. Each PHY has its own power domain (phy_gdsc) that must be powered on before initialization per hardware requirements. Current PHY power management assumes a single power domain per PHY, preventing proper setup for this dual-PHY scenario. Add support for multiple power domains by using devm_pm_domain_attach_list() to attach power domains manually, while maintaining compatibility with single power domain PHYs. Enable runtime PM to allow power domain control when the PCIe driver calls phy_power_on/phy_power_off: - Single power domain: QMP PHY platform device directly attaches to power domain and controls it during runtime resume/suspend - Multiple power domains: devm_pm_domain_attach_list() creates virtual devices as power domain suppliers, linked to the QMP PHY platform device as consumer This ensures power domains are properly attached and turned on/off for both single and multiple power domain configurations. Reviewed-by: Dmitry Baryshkov Signed-off-by: Qiang Yu --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcom= m/phy-qcom-qmp-pcie.c index fed2fc9bb31108d51f88d34f3379c7744681f485..424c935e27a8766e1e26762bd3d= 7df527c1520e3 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -5329,6 +5330,7 @@ static int qmp_pcie_parse_dt(struct qmp_pcie *qmp) =20 static int qmp_pcie_probe(struct platform_device *pdev) { + struct dev_pm_domain_list *pd_list; struct device *dev =3D &pdev->dev; struct phy_provider *phy_provider; struct device_node *np; @@ -5348,6 +5350,16 @@ static int qmp_pcie_probe(struct platform_device *pd= ev) WARN_ON_ONCE(!qmp->cfg->pwrdn_ctrl); WARN_ON_ONCE(!qmp->cfg->phy_status); =20 + ret =3D devm_pm_domain_attach_list(dev, NULL, &pd_list); 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The Glymur SoC's 3rd PCIe instance supports 8-lane mode using two PHYs in bifurcation, where each PHY requires its own nocsr reset to be controlled simultaneously. The current implementation only supports a single nocsr reset per PHY configuration. Add num_nocsr and nocsr_list fields to struct qmp_phy_cfg to represent the number and names of a group of nocsr reset names. Initialize these fields for all PHYs that have nocsr resets, allowing the driver to correctly acquire multiple nocsr resets during probe and control them as an array by using reset_control_bulk APIs. The refactoring maintains backward compatibility for existing single nocsr reset configurations while enabling support for multi-PHY scenarios like Glymur's 8-lane bifurcation mode. Additionally, introduces x1e80100_qmp_gen3x2_pciephy_cfg as a separate configuration from sm8550_qmp_gen3x2_pciephy_cfg since the x1e80100 Gen3x2 PHY requires nocsr reset support while the sm8550 Gen3x2 PHY does not. Signed-off-by: Qiang Yu --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 87 ++++++++++++++++++++++++++++= ---- 1 file changed, 77 insertions(+), 10 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcom= m/phy-qcom-qmp-pcie.c index 424c935e27a8766e1e26762bd3d7df527c1520e3..51db9eea41255bad0034bbcfbfd= c36894c2bc95f 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -3281,6 +3281,11 @@ struct qmp_phy_cfg { /* resets to be requested */ const char * const *reset_list; int num_resets; + + /* nocsr resets to be requested */ + const char * const *nocsr_reset_list; + int num_nocsr_resets; + /* regulators to be requested */ const char * const *vreg_list; int num_vregs; @@ -3327,7 +3332,7 @@ struct qmp_pcie { int num_pipe_clks; =20 struct reset_control_bulk_data *resets; - struct reset_control *nocsr_reset; + struct reset_control_bulk_data *nocsr_reset; struct regulator_bulk_data *vregs; =20 struct phy *phy; @@ -3392,6 +3397,10 @@ static const char * const sdm845_pciephy_reset_l[] = =3D { "phy", }; =20 +static const char * const sm8550_pciephy_nocsr_reset_l[] =3D { + "phy_nocsr", +}; + static const struct qmp_pcie_offsets qmp_pcie_offsets_qhp =3D { .serdes =3D 0, .pcs =3D 0x1800, @@ -4348,6 +4357,8 @@ static const struct qmp_phy_cfg sm8550_qmp_gen4x2_pci= ephy_cfg =3D { }, .reset_list =3D sdm845_pciephy_reset_l, .num_resets =3D ARRAY_SIZE(sdm845_pciephy_reset_l), + .nocsr_reset_list =3D sm8550_pciephy_nocsr_reset_l, + .num_nocsr_resets =3D ARRAY_SIZE(sm8550_pciephy_nocsr_reset_l), .vreg_list =3D sm8550_qmp_phy_vreg_l, .num_vregs =3D ARRAY_SIZE(sm8550_qmp_phy_vreg_l), .regs =3D pciephy_v6_regs_layout, @@ -4380,6 +4391,8 @@ static const struct qmp_phy_cfg sm8650_qmp_gen4x2_pci= ephy_cfg =3D { }, .reset_list =3D sdm845_pciephy_reset_l, .num_resets =3D ARRAY_SIZE(sdm845_pciephy_reset_l), + .nocsr_reset_list =3D sm8550_pciephy_nocsr_reset_l, + .num_nocsr_resets =3D ARRAY_SIZE(sm8550_pciephy_nocsr_reset_l), .vreg_list =3D sm8550_qmp_phy_vreg_l, .num_vregs =3D ARRAY_SIZE(sm8550_qmp_phy_vreg_l), .regs =3D pciephy_v6_regs_layout, @@ -4480,6 +4493,35 @@ static const struct qmp_phy_cfg sa8775p_qmp_gen4x4_p= ciephy_cfg =3D { .phy_status =3D PHYSTATUS_4_20, }; =20 +static const struct qmp_phy_cfg x1e80100_qmp_gen3x2_pciephy_cfg =3D { + .lanes =3D 2, + + .offsets =3D &qmp_pcie_offsets_v5, + + .tbls =3D { + .serdes =3D sm8550_qmp_gen3x2_pcie_serdes_tbl, + .serdes_num =3D ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_serdes_tbl), + .tx =3D sm8550_qmp_gen3x2_pcie_tx_tbl, + .tx_num =3D ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_tx_tbl), + .rx =3D sm8550_qmp_gen3x2_pcie_rx_tbl, + .rx_num =3D ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_rx_tbl), + .pcs =3D sm8550_qmp_gen3x2_pcie_pcs_tbl, + .pcs_num =3D ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_pcs_tbl), + .pcs_misc =3D sm8550_qmp_gen3x2_pcie_pcs_misc_tbl, + .pcs_misc_num =3D ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_pcs_misc_tbl), + }, + .reset_list =3D sdm845_pciephy_reset_l, + .num_resets =3D ARRAY_SIZE(sdm845_pciephy_reset_l), + .nocsr_reset_list =3D sm8550_pciephy_nocsr_reset_l, + .num_nocsr_resets =3D ARRAY_SIZE(sm8550_pciephy_nocsr_reset_l), + .vreg_list =3D qmp_phy_vreg_l, + .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), + .regs =3D pciephy_v5_regs_layout, + + .pwrdn_ctrl =3D SW_PWRDN | REFCLK_DRV_DSBL, + .phy_status =3D PHYSTATUS, +}; + static const struct qmp_phy_cfg x1e80100_qmp_gen4x2_pciephy_cfg =3D { .lanes =3D 2, =20 @@ -4502,6 +4544,8 @@ static const struct qmp_phy_cfg x1e80100_qmp_gen4x2_p= ciephy_cfg =3D { =20 .reset_list =3D sdm845_pciephy_reset_l, .num_resets =3D ARRAY_SIZE(sdm845_pciephy_reset_l), + .nocsr_reset_list =3D sm8550_pciephy_nocsr_reset_l, + .num_nocsr_resets =3D ARRAY_SIZE(sm8550_pciephy_nocsr_reset_l), .vreg_list =3D qmp_phy_vreg_l, .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), .regs =3D pciephy_v6_regs_layout, @@ -4535,6 +4579,8 @@ static const struct qmp_phy_cfg x1e80100_qmp_gen4x4_p= ciephy_cfg =3D { =20 .reset_list =3D sdm845_pciephy_reset_l, .num_resets =3D ARRAY_SIZE(sdm845_pciephy_reset_l), + .nocsr_reset_list =3D sm8550_pciephy_nocsr_reset_l, + .num_nocsr_resets =3D ARRAY_SIZE(sm8550_pciephy_nocsr_reset_l), .vreg_list =3D qmp_phy_vreg_l, .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), .regs =3D pciephy_v6_regs_layout, @@ -4566,6 +4612,8 @@ static const struct qmp_phy_cfg x1e80100_qmp_gen4x8_p= ciephy_cfg =3D { =20 .reset_list =3D sdm845_pciephy_reset_l, .num_resets =3D ARRAY_SIZE(sdm845_pciephy_reset_l), + .nocsr_reset_list =3D sm8550_pciephy_nocsr_reset_l, + .num_nocsr_resets =3D ARRAY_SIZE(sm8550_pciephy_nocsr_reset_l), .vreg_list =3D qmp_phy_vreg_l, .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), .regs =3D pciephy_v6_regs_layout, @@ -4581,6 +4629,8 @@ static const struct qmp_phy_cfg qmp_v6_gen4x4_pciephy= _cfg =3D { =20 .reset_list =3D sdm845_pciephy_reset_l, .num_resets =3D ARRAY_SIZE(sdm845_pciephy_reset_l), + .nocsr_reset_list =3D sm8550_pciephy_nocsr_reset_l, + .num_nocsr_resets =3D ARRAY_SIZE(sm8550_pciephy_nocsr_reset_l), .vreg_list =3D qmp_phy_vreg_l, .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), .regs =3D pciephy_v6_regs_layout, @@ -4609,6 +4659,8 @@ static const struct qmp_phy_cfg qmp_v8_gen3x2_pciephy= _cfg =3D { =20 .reset_list =3D sdm845_pciephy_reset_l, .num_resets =3D ARRAY_SIZE(sdm845_pciephy_reset_l), + .nocsr_reset_list =3D sm8550_pciephy_nocsr_reset_l, + .num_nocsr_resets =3D ARRAY_SIZE(sm8550_pciephy_nocsr_reset_l), .vreg_list =3D qmp_phy_vreg_l, .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), .regs =3D pciephy_v8_regs_layout, @@ -4624,6 +4676,8 @@ static const struct qmp_phy_cfg glymur_qmp_gen5x4_pci= ephy_cfg =3D { =20 .reset_list =3D sdm845_pciephy_reset_l, .num_resets =3D ARRAY_SIZE(sdm845_pciephy_reset_l), + .nocsr_reset_list =3D sm8550_pciephy_nocsr_reset_l, + .num_nocsr_resets =3D ARRAY_SIZE(sm8550_pciephy_nocsr_reset_l), .vreg_list =3D qmp_phy_vreg_l, .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), =20 @@ -4640,6 +4694,8 @@ static const struct qmp_phy_cfg glymur_qmp_gen4x2_pci= ephy_cfg =3D { =20 .reset_list =3D sdm845_pciephy_reset_l, .num_resets =3D ARRAY_SIZE(sdm845_pciephy_reset_l), + .nocsr_reset_list =3D sm8550_pciephy_nocsr_reset_l, + .num_nocsr_resets =3D ARRAY_SIZE(sm8550_pciephy_nocsr_reset_l), .vreg_list =3D qmp_phy_vreg_l, .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), =20 @@ -4768,7 +4824,7 @@ static int qmp_pcie_init(struct phy *phy) } } =20 - ret =3D reset_control_assert(qmp->nocsr_reset); + ret =3D reset_control_bulk_assert(cfg->num_nocsr_resets, qmp->nocsr_reset= ); if (ret) { dev_err(qmp->dev, "no-csr reset assert failed\n"); goto err_assert_reset; @@ -4805,7 +4861,7 @@ static int qmp_pcie_exit(struct phy *phy) const struct qmp_phy_cfg *cfg =3D qmp->cfg; =20 if (qmp->nocsr_reset) - reset_control_assert(qmp->nocsr_reset); + reset_control_bulk_assert(cfg->num_nocsr_resets, qmp->nocsr_reset); else reset_control_bulk_assert(cfg->num_resets, qmp->resets); =20 @@ -4849,7 +4905,7 @@ static int qmp_pcie_power_on(struct phy *phy) if (ret) return ret; =20 - ret =3D reset_control_deassert(qmp->nocsr_reset); + ret =3D reset_control_bulk_deassert(cfg->num_nocsr_resets, qmp->nocsr_res= et); if (ret) { dev_err(qmp->dev, "no-csr reset deassert failed\n"); goto err_disable_pipe_clk; @@ -4998,14 +5054,25 @@ static int qmp_pcie_reset_init(struct qmp_pcie *qmp) for (i =3D 0; i < cfg->num_resets; i++) qmp->resets[i].id =3D cfg->reset_list[i]; =20 - ret =3D devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, qmp->= resets); + ret =3D devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, + qmp->resets); if (ret) return dev_err_probe(dev, ret, "failed to get resets\n"); =20 - qmp->nocsr_reset =3D devm_reset_control_get_optional_exclusive(dev, "phy_= nocsr"); - if (IS_ERR(qmp->nocsr_reset)) - return dev_err_probe(dev, PTR_ERR(qmp->nocsr_reset), - "failed to get no-csr reset\n"); + if (!cfg->num_nocsr_resets) + return 0; + qmp->nocsr_reset =3D devm_kcalloc(dev, cfg->num_nocsr_resets, + sizeof(*qmp->nocsr_reset), GFP_KERNEL); + if (!qmp->nocsr_reset) + return -ENOMEM; + + for (i =3D 0; i < cfg->num_nocsr_resets; i++) + qmp->nocsr_reset[i].id =3D cfg->nocsr_reset_list[i]; + + ret =3D devm_reset_control_bulk_get_exclusive(dev, cfg->num_nocsr_resets, + qmp->nocsr_reset); + if (ret) + return dev_err_probe(dev, ret, "failed to get no-csr reset\n"); =20 return 0; } @@ -5520,7 +5587,7 @@ static const struct of_device_id qmp_pcie_of_match_ta= ble[] =3D { .data =3D &sm8750_qmp_gen3x2_pciephy_cfg, }, { .compatible =3D "qcom,x1e80100-qmp-gen3x2-pcie-phy", - .data =3D &sm8550_qmp_gen3x2_pciephy_cfg, + .data =3D &x1e80100_qmp_gen3x2_pciephy_cfg, }, { .compatible =3D "qcom,x1e80100-qmp-gen4x2-pcie-phy", .data =3D &x1e80100_qmp_gen4x2_pciephy_cfg, --=20 2.34.1 From nobody Mon Apr 13 21:03:16 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 31AC7392C3A for ; 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Add dedicated reset/no_csr reset list ("phy_b", "phy_b_nocsr") and clock ("phy_b_aux") required for 8-lane operation. Introduce new glymur_qmp_gen5x8_pciephy_cfg configuration to enable PCIe Gen5 x8 mode. Reviewed-by: Abel Vesa Reviewed-by: Dmitry Baryshkov Signed-off-by: Qiang Yu --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 30 ++++++++++++++++++++++++++++= +- 1 file changed, 29 insertions(+), 1 deletion(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcom= m/phy-qcom-qmp-pcie.c index 51db9eea41255bad0034bbcfbfdc36894c2bc95f..e872b50b11da50e6317ce7e1acf= 6385925f92cdb 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -3376,7 +3376,7 @@ static inline void qphy_clrbits(void __iomem *base, u= 32 offset, u32 val) =20 /* list of clocks required by phy */ static const char * const qmp_pciephy_clk_l[] =3D { - "aux", "cfg_ahb", "ref", "refgen", "rchng", "phy_aux", + "aux", "cfg_ahb", "ref", "refgen", "rchng", "phy_aux", "phy_b_aux", }; =20 /* list of regulators */ @@ -3401,6 +3401,14 @@ static const char * const sm8550_pciephy_nocsr_reset= _l[] =3D { "phy_nocsr", }; =20 +static const char * const glymur_pciephy_reset_l[] =3D { + "phy", "phy_b" +}; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2d561cd3138sm15260935eec.14.2026.04.12.23.26.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 12 Apr 2026 23:26:23 -0700 (PDT) From: Qiang Yu Date: Sun, 12 Apr 2026 23:26:00 -0700 Subject: [PATCH v3 5/5] arch: arm64: dts: qcom: Add support for PCIe3a Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260412-glymur_gen5x8_phy_0413-v3-5-affcebc16b8b@oss.qualcomm.com> References: <20260412-glymur_gen5x8_phy_0413-v3-0-affcebc16b8b@oss.qualcomm.com> In-Reply-To: <20260412-glymur_gen5x8_phy_0413-v3-0-affcebc16b8b@oss.qualcomm.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Qiang Yu X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1776061577; l=9785; i=qiang.yu@oss.qualcomm.com; s=20250513; h=from:subject:message-id; bh=6j3SACKkrYFjJa5AOGKpOr8QZ2eMgNzhp49WGgxvD2U=; b=Eq+D1zI8XyP7EndVlHUisT3hzQ2nCu1TxiSOUFw3E/eD1ssg5FWrAM8AR6eGye22cXONEqljG fwgvFMP7PFeCFLuZIDYJc80Z3baATd3/LP4iemCeYjc/LgAbcusOXMb X-Developer-Key: i=qiang.yu@oss.qualcomm.com; a=ed25519; pk=Rr94t+fykoieF1ngg/bXxEfr5KoQxeXPtYxM8fBQTAI= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDEzMDA2MCBTYWx0ZWRfXykDYzrtiT/gk IveuWsHzTBQyR1Z8z1vBta1w96HC87t1TRmtuRJNIYeNojCZac0KUOB5B+feT0vCSX3kcQh8sHw t8EWHYCY7LW/KQGYPd6Kt8VjbyadU7et+LgTQ+TE+nhtqBghGYbmybAun9d5e2M319La0SUHK8A SKnnPmbwCk6UH+QFmcH1Zh2ULwFEU0/TAkEdGnx2En/NqBqXk7AeN2LiTcuEvW0YuSK6+/knJoL gEblBTb4N6VlwbcYGjNsu3TXoaqEBZNd4bcOwKTgo/phq6gVzfG26hiC+Stn9k7L4sTqU8qJLYl 3nvLDCx7EXw9yVRBcdI1YZ2fKc8Yzo09CKanLMH2bWTlnB+7rdV6If1WUXhcp4Mj/fjoJ1bk+pH Lm1kxKL2Z8L9uAiF8sdSwo0VnId3HWLoPectRm2khF0b0hIGMZyidREP8f1ZRfdOwMeQs4J+r8b O+72aKbQIz0TI1fPpRA== X-Proofpoint-GUID: 3qoxZ3P-2i--XS2L7ZRLILQ1SARXQtsp X-Proofpoint-ORIG-GUID: 3qoxZ3P-2i--XS2L7ZRLILQ1SARXQtsp X-Authority-Analysis: v=2.4 cv=W4gIkxWk c=1 sm=1 tr=0 ts=69dc8c91 cx=c_pps a=PfFC4Oe2JQzmKTvty2cRDw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=EUspDBNiAAAA:8 a=hXbwWmyv05DepBt-Dp8A:9 a=QEXdDO2ut3YA:10 a=6Ab_bkdmUrQuMsNx7PHu:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-13_02,2026-04-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 bulkscore=0 spamscore=0 clxscore=1015 phishscore=0 impostorscore=0 lowpriorityscore=0 priorityscore=1501 malwarescore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604010000 definitions=main-2604130060 Describe PCIe3a controller and PHY. Also add required system resources like regulators, clocks, interrupts and registers configuration for PCIe3a. Signed-off-by: Qiang Yu --- arch/arm64/boot/dts/qcom/glymur.dtsi | 316 +++++++++++++++++++++++++++++++= +++- 1 file changed, 315 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qco= m/glymur.dtsi index f23cf81ddb77a4138deeb4e00dd8b316930a2feb..c15f87c37ecbad72076a6c731f4= 959a1a8bd8425 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -736,7 +736,7 @@ gcc: clock-controller@100000 { <0>, /* USB 2 Phy PCIE PIPEGMUX */ <0>, /* USB 2 Phy PIPEGMUX */ <0>, /* USB 2 Phy SYS PCIE PIPEGMUX */ - <0>, /* PCIe 3a */ + <&pcie3a_phy>, /* PCIe 3a */ <&pcie3b_phy>, /* PCIe 3b */ <&pcie4_phy>, /* PCIe 4 */ <&pcie5_phy>, /* PCIe 5 */ @@ -3640,6 +3640,320 @@ pcie3b_port0: pcie@0 { }; }; =20 + pcie3a: pci@1c10000 { + device_type =3D "pci"; + compatible =3D "qcom,glymur-pcie", "qcom,pcie-x1e80100"; + reg =3D <0x0 0x01c10000 0x0 0x3000>, + <0x0 0x70000000 0x0 0xf20>, + <0x0 0x70000f40 0x0 0xa8>, + <0x0 0x70001000 0x0 0x4000>, + <0x0 0x70100000 0x0 0x100000>, + <0x0 0x01c13000 0x0 0x1000>; + reg-names =3D "parf", + "dbi", + "elbi", + "atu", + "config", + "mhi"; + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges =3D <0x01000000 0x0 0x00000000 0x0 0x70200000 0x0 0x100000>, + <0x02000000 0x0 0x70000000 0x0 0x70300000 0x0 0x3d00000>, + <0x03000000 0x7 0x00000000 0x7 0x00000000 0x0 0x40000000>, + <0x43000000 0x70 0x00000000 0x70 0x00000000 0x10 0x00000000>; + + bus-range =3D <0 0xff>; + + dma-coherent; + + linux,pci-domain =3D <3>; + num-lanes =3D <8>; + + operating-points-v2 =3D <&pcie3a_opp_table>; + + msi-map =3D <0x0 &gic_its 0xb0000 0x10000>; + iommu-map =3D <0x0 &pcie_smmu 0x30000 0x10000>; + + interrupts =3D , + , + , + , + , + , + , + , + ; + interrupt-names =3D "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7", + "global"; + + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &intc 0 0 0 848 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 0 849 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 0 850 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 0 851 IRQ_TYPE_LEVEL_HIGH>; + + clocks =3D <&gcc GCC_PCIE_3A_AUX_CLK>, + <&gcc GCC_PCIE_3A_CFG_AHB_CLK>, + <&gcc GCC_PCIE_3A_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_3A_SLV_AXI_CLK>, + <&gcc GCC_PCIE_3A_SLV_Q2A_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_3A_WEST_SF_AXI_CLK>; + clock-names =3D "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "noc_aggr"; + + assigned-clocks =3D <&gcc GCC_PCIE_3A_AUX_CLK>; + assigned-clock-rates =3D <19200000>; + + interconnects =3D <&pcie_west_anoc MASTER_PCIE_3A QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &pcie_west_slv_noc SLAVE_PCIE_3A QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "pcie-mem", + "cpu-pcie"; + + resets =3D <&gcc GCC_PCIE_3A_BCR>, + <&gcc GCC_PCIE_3A_LINK_DOWN_BCR>; + reset-names =3D "pci", + "link_down"; + + power-domains =3D <&gcc GCC_PCIE_3A_GDSC>; + + eq-presets-8gts =3D /bits/ 16 <0x5555 0x5555 0x5555 0x5555 + 0x5555 0x5555 0x5555 0x5555>; + eq-presets-16gts =3D /bits/ 8 <0x55 0x55 0x55 0x55 0x55 0x55 0x55 0x55>; + eq-presets-32gts =3D /bits/ 8 <0x55 0x55 0x55 0x55 0x55 0x55 0x55 0x55>; + + status =3D "disabled"; + + pcie3a_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + /* GEN 1 x1 */ + opp-2500000-1 { + opp-hz =3D /bits/ 64 <2500000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <250000 1>; + opp-level =3D <1>; + }; + + /* GEN 1 x2 */ + opp-5000000-1 { + opp-hz =3D /bits/ 64 <5000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <500000 1>; + opp-level =3D <1>; + }; + + /* GEN 1 x4 */ + opp-10000000-1 { + opp-hz =3D /bits/ 64 <10000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <1000000 1>; + opp-level =3D <1>; + }; + + /* GEN 1 x8 */ + opp-20000000-1 { + opp-hz =3D /bits/ 64 <20000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <2000000 1>; + opp-level =3D <1>; + }; + + /* GEN 2 x1 */ + opp-5000000-2 { + opp-hz =3D /bits/ 64 <5000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <500000 1>; + opp-level =3D <2>; + }; + + /* GEN 2 x2 */ + opp-10000000-2 { + opp-hz =3D /bits/ 64 <10000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <1000000 1>; + opp-level =3D <2>; + }; + + /* GEN 2 x4 */ + opp-20000000-2 { + opp-hz =3D /bits/ 64 <20000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <2000000 1>; + opp-level =3D <2>; + }; + + /* GEN 2 x8 */ + opp-40000000-2 { + opp-hz =3D /bits/ 64 <40000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <4000000 1>; + opp-level =3D <2>; + }; + + /* GEN 3 x1 */ + opp-8000000-3 { + opp-hz =3D /bits/ 64 <8000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <984500 1>; + opp-level =3D <3>; + }; + + /* GEN 3 x2 */ + opp-16000000-3 { + opp-hz =3D /bits/ 64 <16000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <1969000 1>; + opp-level =3D <3>; + }; + + /* GEN 3 x4 */ + opp-32000000-3 { + opp-hz =3D /bits/ 64 <32000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <3938000 1>; + opp-level =3D <3>; + }; + + /* GEN 3 x8 */ + opp-64000000-3 { + opp-hz =3D /bits/ 64 <64000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <7876000 1>; + opp-level =3D <3>; + }; + + /* GEN 4 x1 */ + opp-16000000-4 { + opp-hz =3D /bits/ 64 <16000000>; + required-opps =3D <&rpmhpd_opp_svs>; + opp-peak-kBps =3D <1969000 1>; + opp-level =3D <4>; + }; + + /* GEN 4 x2 */ + opp-32000000-4 { + opp-hz =3D /bits/ 64 <32000000>; + required-opps =3D <&rpmhpd_opp_svs>; + opp-peak-kBps =3D <3938000 1>; + opp-level =3D <4>; + }; + + /* GEN 4 x4 */ + opp-64000000-4 { + opp-hz =3D /bits/ 64 <64000000>; + required-opps =3D <&rpmhpd_opp_svs>; + opp-peak-kBps =3D <7876000 1>; + opp-level =3D <4>; + }; + + /* GEN 4 x8 */ + opp-128000000-4 { + opp-hz =3D /bits/ 64 <128000000>; + required-opps =3D <&rpmhpd_opp_svs>; + opp-peak-kBps =3D <15753000 1>; + opp-level =3D <4>; + }; + + /* GEN 5 x1 */ + opp-32000000-5 { + opp-hz =3D /bits/ 64 <32000000>; + required-opps =3D <&rpmhpd_opp_nom>; + opp-peak-kBps =3D <3938000 1>; + opp-level =3D <5>; + }; + + /* GEN 5 x2 */ + opp-64000000-5 { + opp-hz =3D /bits/ 64 <64000000>; + required-opps =3D <&rpmhpd_opp_nom>; + opp-peak-kBps =3D <7876000 1>; + opp-level =3D <5>; + }; + + /* GEN 5 x4 */ + opp-128000000-5 { + opp-hz =3D /bits/ 64 <128000000>; + required-opps =3D <&rpmhpd_opp_nom>; + opp-peak-kBps =3D <15753000 1>; + opp-level =3D <5>; + }; + + /* GEN 5 x8 */ + opp-256000000-5 { + opp-hz =3D /bits/ 64 <256000000>; + required-opps =3D <&rpmhpd_opp_nom>; + opp-peak-kBps =3D <31506000 1>; + opp-level =3D <5>; + }; + }; + + pcie3a_port0: pcie@0 { + device_type =3D "pci"; + reg =3D <0x0 0x0 0x0 0x0 0x0>; + bus-range =3D <0x01 0xff>; + + phys =3D <&pcie3a_phy>; + + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges; + }; + }; + + pcie3a_phy: phy@f00000 { + compatible =3D "qcom,glymur-qmp-gen5x8-pcie-phy"; + reg =3D <0 0x00f00000 0 0x10000>; + + clocks =3D <&gcc GCC_PCIE_PHY_3A_AUX_CLK>, + <&gcc GCC_PCIE_3A_CFG_AHB_CLK>, + <&tcsr TCSR_PCIE_3_CLKREF_EN>, + <&gcc GCC_PCIE_3A_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_3A_PIPE_CLK>, + <&gcc GCC_PCIE_PHY_3B_AUX_CLK>; + clock-names =3D "aux", + "cfg_ahb", + "ref", + "rchng", + "pipe", + "phy_b_aux"; + + resets =3D <&gcc GCC_PCIE_3A_PHY_BCR>, + <&gcc GCC_PCIE_3A_NOCSR_COM_PHY_BCR>, + <&gcc GCC_PCIE_3B_PHY_BCR>, + <&gcc GCC_PCIE_3B_NOCSR_COM_PHY_BCR>; + reset-names =3D "phy", + "phy_nocsr", + "phy_b", + "phy_b_nocsr"; + + assigned-clocks =3D <&gcc GCC_PCIE_3A_PHY_RCHNG_CLK>; + assigned-clock-rates =3D <100000000>; + + power-domains =3D <&gcc GCC_PCIE_3A_PHY_GDSC>, + <&gcc GCC_PCIE_3B_PHY_GDSC>; + + #clock-cells =3D <0>; + clock-output-names =3D "pcie3a_pipe_clk"; + + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + pcie3b_phy: phy@f10000 { compatible =3D "qcom,glymur-qmp-gen5x4-pcie-phy"; reg =3D <0x0 0x00f10000 0x0 0x10000>; --=20 2.34.1