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The location of this group of registers is indicated by the MISCOFF register. Each capability has a capability ID to determine which functionality is supported and each capability will point to the next capability supported. Add a basic function to read those capabilities offsets. Signed-off-by: Vivek Pernamitta Signed-off-by: Sivareddy Surasani Signed-off-by: Krishna Chaitanya Chundru --- drivers/bus/mhi/common.h | 11 +++++++++++ drivers/bus/mhi/host/init.c | 32 ++++++++++++++++++++++++++++++++ 2 files changed, 43 insertions(+) diff --git a/drivers/bus/mhi/common.h b/drivers/bus/mhi/common.h index dda340aaed95a5573a2ec776ca712e11a1ed0b52..4c316f3d5a68beb01f15cf575b0= 3747096fdcf2c 100644 --- a/drivers/bus/mhi/common.h +++ b/drivers/bus/mhi/common.h @@ -16,6 +16,7 @@ #define MHICFG 0x10 #define CHDBOFF 0x18 #define ERDBOFF 0x20 +#define MISCOFF 0x24 #define BHIOFF 0x28 #define BHIEOFF 0x2c #define DEBUGOFF 0x30 @@ -113,6 +114,9 @@ #define MHISTATUS_MHISTATE_MASK GENMASK(15, 8) #define MHISTATUS_SYSERR_MASK BIT(2) #define MHISTATUS_READY_MASK BIT(0) +#define MISC_CAP_MASK GENMASK(31, 0) +#define CAP_CAPID_MASK GENMASK(31, 24) +#define CAP_NEXT_CAP_MASK GENMASK(23, 12) =20 /* Command Ring Element macros */ /* No operation command */ @@ -204,6 +208,13 @@ #define MHI_RSCTRE_DATA_DWORD1 cpu_to_le32(FIELD_PREP(GENMASK(23, 16), \ MHI_PKT_TYPE_COALESCING)) =20 +#define MHI_CAP_ID_INTX 0x1 +#define MHI_CAP_ID_TIME_SYNC 0x2 +#define MHI_CAP_ID_BW_SCALE 0x3 +#define MHI_CAP_ID_TSC_TIME_SYNC 0x4 +#define MHI_CAP_ID_MAX_TRB_LEN 0x5 +#define MHI_CAP_ID_MAX 0x6 + enum mhi_pkt_type { MHI_PKT_TYPE_INVALID =3D 0x0, MHI_PKT_TYPE_NOOP_CMD =3D 0x1, diff --git a/drivers/bus/mhi/host/init.c b/drivers/bus/mhi/host/init.c index 0a728ca2c494836b0e0ce4c3f4aea41794c0868b..c2162aa04e810e45ccfbedd20aa= a62f892420d31 100644 --- a/drivers/bus/mhi/host/init.c +++ b/drivers/bus/mhi/host/init.c @@ -466,6 +466,38 @@ static int mhi_init_dev_ctxt(struct mhi_controller *mh= i_cntrl) return ret; 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The host disables low-power link states to minimize latency, reads the local time, issues a MMIO read to the device's TIME register. Add support for initializing this feature and export a function to be used by the drivers which does the time synchronization. MHI reads the device time registers in the MMIO address space pointed to by the capability register after disabling all low power modes and keeping MHI in M0. Before and after MHI reads, the local time is captured and shared for processing. Signed-off-by: Vivek Pernamitta Signed-off-by: Krishna Chaitanya Chundru --- drivers/bus/mhi/common.h | 4 +++ drivers/bus/mhi/host/init.c | 28 ++++++++++++++++ drivers/bus/mhi/host/internal.h | 9 +++++ drivers/bus/mhi/host/main.c | 74 +++++++++++++++++++++++++++++++++++++= ++++ include/linux/mhi.h | 37 +++++++++++++++++++++ 5 files changed, 152 insertions(+) diff --git a/drivers/bus/mhi/common.h b/drivers/bus/mhi/common.h index 4c316f3d5a68beb01f15cf575b03747096fdcf2c..64f9b2b94387a112bb6b5e20c63= 4c3ba8d6bc78e 100644 --- a/drivers/bus/mhi/common.h +++ b/drivers/bus/mhi/common.h @@ -118,6 +118,10 @@ #define CAP_CAPID_MASK GENMASK(31, 24) #define CAP_NEXT_CAP_MASK GENMASK(23, 12) =20 +/* MHI TSC Timesync */ +#define TSC_TIMESYNC_TIME_LOW_OFFSET (0x8) +#define TSC_TIMESYNC_TIME_HIGH_OFFSET (0xC) + /* Command Ring Element macros */ /* No operation command */ #define MHI_TRE_CMD_NOOP_PTR 0 diff --git a/drivers/bus/mhi/host/init.c b/drivers/bus/mhi/host/init.c index c2162aa04e810e45ccfbedd20aaa62f892420d31..eb720f671726d919646cbc450cd= 54bda655a1060 100644 --- a/drivers/bus/mhi/host/init.c +++ b/drivers/bus/mhi/host/init.c @@ -498,6 +498,30 @@ static int mhi_find_capability(struct mhi_controller *= mhi_cntrl, u32 capability) return 0; } =20 +static int mhi_init_tsc_timesync(struct mhi_controller *mhi_cntrl) +{ + struct device *dev =3D &mhi_cntrl->mhi_dev->dev; + struct mhi_timesync *mhi_tsc_tsync; + u32 time_offset; + int ret; + + time_offset =3D mhi_find_capability(mhi_cntrl, MHI_CAP_ID_TSC_TIME_SYNC); + if (!time_offset) + return -ENXIO; + + mhi_tsc_tsync =3D devm_kzalloc(dev, sizeof(*mhi_tsc_tsync), GFP_KERNEL); + if (!mhi_tsc_tsync) + return -ENOMEM; + + mhi_cntrl->tsc_timesync =3D mhi_tsc_tsync; + mutex_init(&mhi_tsc_tsync->ts_mutex); + + /* save time_offset for obtaining time via MMIO register reads */ + mhi_tsc_tsync->time_reg =3D mhi_cntrl->regs + time_offset; + + return 0; +} + int mhi_init_mmio(struct mhi_controller *mhi_cntrl) { u32 val; @@ -635,6 +659,10 @@ int mhi_init_mmio(struct mhi_controller *mhi_cntrl) return ret; } =20 + ret =3D mhi_init_tsc_timesync(mhi_cntrl); + if (ret) + dev_dbg(dev, "TSC Time synchronization init failure\n"); + return 0; } =20 diff --git a/drivers/bus/mhi/host/internal.h b/drivers/bus/mhi/host/interna= l.h index 7b0ee5e3a12dd585064169b7b884750bf4d8c8db..a0e729e7a1198c1b82c70b6bfe3= bc2ee24331229 100644 --- a/drivers/bus/mhi/host/internal.h +++ b/drivers/bus/mhi/host/internal.h @@ -15,6 +15,15 @@ extern const struct bus_type mhi_bus_type; #define MHI_SOC_RESET_REQ_OFFSET 0xb0 #define MHI_SOC_RESET_REQ BIT(0) =20 +/* + * With ASPM enabled, the link may enter a low power state, requiring + * a wake-up sequence. Use a short burst of back-to-back reads to + * transition the link to the active state. Based on testing, + * 4 iterations are necessary to ensure reliable wake-up without + * excess latency. + */ +#define MHI_NUM_BACK_TO_BACK_READS 4 + struct mhi_ctxt { struct mhi_event_ctxt *er_ctxt; struct mhi_chan_ctxt *chan_ctxt; diff --git a/drivers/bus/mhi/host/main.c b/drivers/bus/mhi/host/main.c index 53c0ffe300702bcc3caa8fd9ea8086203c75b186..b7a727b1a5d1f20b570c62707a9= 91ec5b85bfec7 100644 --- a/drivers/bus/mhi/host/main.c +++ b/drivers/bus/mhi/host/main.c @@ -1626,3 +1626,77 @@ int mhi_get_channel_doorbell_offset(struct mhi_contr= oller *mhi_cntrl, u32 *chdb_ return 0; } EXPORT_SYMBOL_GPL(mhi_get_channel_doorbell_offset); + +static int mhi_get_remote_time(struct mhi_controller *mhi_cntrl, struct mh= i_timesync *mhi_tsync, + struct mhi_timesync_info *time) +{ + struct device *dev =3D &mhi_cntrl->mhi_dev->dev; + int ret, i; + + if (!mhi_tsync && !mhi_tsync->time_reg) { + dev_err(dev, "Time sync is not supported\n"); + return -EINVAL; + } + + if (unlikely(MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state))) { + dev_err(dev, "MHI is not in active state, pm_state:%s\n", + to_mhi_pm_state_str(mhi_cntrl->pm_state)); + return -EIO; + } + + /* bring to M0 state */ + ret =3D mhi_device_get_sync(mhi_cntrl->mhi_dev); + if (ret) + return ret; + + guard(mutex)(&mhi_tsync->ts_mutex); + mhi_cntrl->runtime_get(mhi_cntrl); + + /* + * time critical code to fetch device time, delay between these two steps + * should be deterministic as possible. + */ + preempt_disable(); + local_irq_disable(); + + time->t_host_pre =3D ktime_get_real(); + + /* + * To ensure the PCIe link is in L0 when ASPM is enabled, perform series + * of back-to-back reads. This is necessary because the link may be in a + * low-power state (e.g., L1 or L1ss), and need to be forced it to + * transition to L0. + */ + for (i =3D 0; i < MHI_NUM_BACK_TO_BACK_READS; i++) { + ret =3D mhi_read_reg(mhi_cntrl, mhi_tsync->time_reg, + TSC_TIMESYNC_TIME_LOW_OFFSET, &time->t_dev_lo); + + ret =3D mhi_read_reg(mhi_cntrl, mhi_tsync->time_reg, + TSC_TIMESYNC_TIME_HIGH_OFFSET, &time->t_dev_hi); + } + + time->t_host_post =3D ktime_get_real(); + + local_irq_enable(); + preempt_enable(); + + mhi_cntrl->runtime_put(mhi_cntrl); + + mhi_device_put(mhi_cntrl->mhi_dev); + + return 0; +} + +int mhi_get_remote_tsc_time_sync(struct mhi_device *mhi_dev, struct mhi_ti= mesync_info *time) +{ + struct mhi_controller *mhi_cntrl =3D mhi_dev->mhi_cntrl; + struct mhi_timesync *mhi_tsc_tsync =3D mhi_cntrl->tsc_timesync; + int ret; + + ret =3D mhi_get_remote_time(mhi_cntrl, mhi_tsc_tsync, time); + if (ret) + dev_err(&mhi_dev->dev, "Failed to get TSC Time Sync value:%d\n", ret); + + return ret; +} +EXPORT_SYMBOL_GPL(mhi_get_remote_tsc_time_sync); diff --git a/include/linux/mhi.h b/include/linux/mhi.h index 88ccb3e14f481d6b85c2a314eb74ba960c2d4c81..f39c8ca7c251954f2d83c1227d2= 06b600b88c75f 100644 --- a/include/linux/mhi.h +++ b/include/linux/mhi.h @@ -286,6 +286,30 @@ struct mhi_controller_config { bool m2_no_db; }; =20 +/** + * struct mhi_timesync - MHI time synchronization structure + * @time_reg: Points to address of Timesync register + * @ts_mutex: Mutex for synchronization + */ +struct mhi_timesync { + void __iomem *time_reg; + struct mutex ts_mutex; +}; + +/** + * struct mhi_timesync_info - MHI time sync info structure + * @t_host_pre: Pre host soc time + * @t_host_post: Post host soc time + * @t_dev_lo: Mhi device time of lower dword + * @t_dev_hi: Mhi device time of higher dword + */ +struct mhi_timesync_info { + ktime_t t_host_pre; + ktime_t t_host_post; + u32 t_dev_lo; + u32 t_dev_hi; +}; + /** * struct mhi_controller - Master MHI controller structure * @name: Device name of the MHI controller @@ -323,6 +347,7 @@ struct mhi_controller_config { * @mhi_event: MHI event ring configurations table * @mhi_cmd: MHI command ring configurations table * @mhi_ctxt: MHI device context, shared memory between host and device + * @tsc_timesync: MHI TSC timesync * @pm_mutex: Mutex for suspend/resume operation * @pm_lock: Lock for protecting MHI power management state * @timeout_ms: Timeout in ms for state transitions @@ -401,6 +426,8 @@ struct mhi_controller { struct mhi_cmd *mhi_cmd; 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Signed-off-by: Krishna Chaitanya Chundru --- drivers/bus/mhi/host/main.c | 12 ++++++++++++ include/linux/mhi.h | 6 ++++++ 2 files changed, 18 insertions(+) diff --git a/drivers/bus/mhi/host/main.c b/drivers/bus/mhi/host/main.c index b7a727b1a5d1f20b570c62707a991ec5b85bfec7..99917593e1da06f1dece7b5b003= 7c2485953410f 100644 --- a/drivers/bus/mhi/host/main.c +++ b/drivers/bus/mhi/host/main.c @@ -67,6 +67,18 @@ void mhi_write_reg(struct mhi_controller *mhi_cntrl, voi= d __iomem *base, mhi_cntrl->write_reg(mhi_cntrl, base + offset, val); } =20 +static int __must_check mhi_read_reg64(struct mhi_controller *mhi_cntrl, + void __iomem *base, u32 offset, u64 *out) +{ + return mhi_cntrl->read_reg64(mhi_cntrl, base + offset, out); +} + +static void __maybe_unused mhi_write_reg64(struct mhi_controller *mhi_cntr= l, void __iomem *base, + u32 offset, u64 val) +{ + mhi_cntrl->write_reg64(mhi_cntrl, base + offset, val); +} + int __must_check mhi_write_reg_field(struct mhi_controller *mhi_cntrl, void __iomem *base, u32 offset, u32 mask, u32 val) diff --git a/include/linux/mhi.h b/include/linux/mhi.h index f39c8ca7c251954f2d83c1227d206b600b88c75f..8e7257a9c907fb03571a86e29db= 5534f492678c7 100644 --- a/include/linux/mhi.h +++ b/include/linux/mhi.h @@ -376,6 +376,8 @@ struct mhi_timesync_info { * @unmap_single: CB function to destroy TRE buffer * @read_reg: Read a MHI register via the physical link (required) * @write_reg: Write a MHI register via the physical link (required) + * @read_reg64: Read a 64 bit MHI register via the physical link (optional) + * @write_reg64: Write a 64 bit MHI register via the physical link (option= al) * @reset: Controller specific reset function (optional) * @edl_trigger: CB function to trigger EDL mode (optional) * @buffer_len: Bounce buffer length @@ -462,6 +464,10 @@ struct mhi_controller { u32 *out); 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Signed-off-by: Krishna Chaitanya Chundru --- drivers/bus/mhi/host/pci_generic.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/drivers/bus/mhi/host/pci_generic.c b/drivers/bus/mhi/host/pci_= generic.c index 0884a384b77fc3f56fa62a12351933132ffc9293..b1122c7224bdd469406d96af6d3= df342040e1002 100644 --- a/drivers/bus/mhi/host/pci_generic.c +++ b/drivers/bus/mhi/host/pci_generic.c @@ -1046,6 +1046,27 @@ struct mhi_pci_device { bool reset_on_remove; }; =20 +#ifdef readq +static int mhi_pci_read_reg64(struct mhi_controller *mhi_cntrl, + void __iomem *addr, u64 *out) +{ + *out =3D readq(addr); + return 0; +} +#else +#define mhi_pci_read_reg64 NULL +#endif + +#ifdef writeq +static void mhi_pci_write_reg64(struct mhi_controller *mhi_cntrl, + void __iomem *addr, u64 val) +{ + writeq(val, addr); +} +#else +#define mhi_pci_write_reg64 NULL +#endif + static int mhi_pci_read_reg(struct mhi_controller *mhi_cntrl, void __iomem *addr, u32 *out) { @@ -1347,6 +1368,8 @@ static int mhi_pci_probe(struct pci_dev *pdev, const = struct pci_device_id *id) =20 mhi_cntrl->read_reg =3D mhi_pci_read_reg; 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Signed-off-by: Krishna Chaitanya Chundru --- drivers/bus/mhi/host/main.c | 21 ++++++++++++++++----- 1 file changed, 16 insertions(+), 5 deletions(-) diff --git a/drivers/bus/mhi/host/main.c b/drivers/bus/mhi/host/main.c index 99917593e1da06f1dece7b5b0037c2485953410f..e853419a0195dff4a18123631cb= 1f74242ab4428 100644 --- a/drivers/bus/mhi/host/main.c +++ b/drivers/bus/mhi/host/main.c @@ -1643,6 +1643,7 @@ static int mhi_get_remote_time(struct mhi_controller = *mhi_cntrl, struct mhi_time struct mhi_timesync_info *time) { struct device *dev =3D &mhi_cntrl->mhi_dev->dev; + u64 val =3D U64_MAX; int ret, i; =20 if (!mhi_tsync && !mhi_tsync->time_reg) { @@ -1680,15 +1681,25 @@ static int mhi_get_remote_time(struct mhi_controlle= r *mhi_cntrl, struct mhi_time * transition to L0. */ for (i =3D 0; i < MHI_NUM_BACK_TO_BACK_READS; i++) { - ret =3D mhi_read_reg(mhi_cntrl, mhi_tsync->time_reg, - TSC_TIMESYNC_TIME_LOW_OFFSET, &time->t_dev_lo); - - ret =3D mhi_read_reg(mhi_cntrl, mhi_tsync->time_reg, - TSC_TIMESYNC_TIME_HIGH_OFFSET, &time->t_dev_hi); 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a=ed25519-sha256; t=1775895126; l=10454; i=krishna.chundru@oss.qualcomm.com; s=20230907; h=from:subject:message-id; bh=LhDoMll/wWIlDNwH8IZy4kOgBI5XQJ/yC8ie5fx0RPE=; b=bAtw4e0HvRbXp1CYX9AgBteiOgmuA0OHY2qaLoAv6d3MPNFR09XH9VwqjKU1tjMXRZmz7zWTj /C39h4hxuCYBOFVa9Kfvt1bCRjTpyXl7gpAWf3x2sRmXzoYCL/ttCXv X-Developer-Key: i=krishna.chundru@oss.qualcomm.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-Authority-Analysis: v=2.4 cv=bcFbluPB c=1 sm=1 tr=0 ts=69da026f cx=c_pps a=WW5sKcV1LcKqjgzy2JUPuA==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=EUspDBNiAAAA:8 a=iHv4hXetqTYKAj42_78A:9 a=QEXdDO2ut3YA:10 a=OpyuDcXvxspvyRM73sMx:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDExMDA2MiBTYWx0ZWRfX1ZXDlO1AEAta dT2irmzlOOucA/RhelHSYC43llv+PoY92SqsEZHYGShsgR1KxRKczvwqWaz6m0QTxhaWwuZ2a7k 0kZZoikrPJ8f5sKr2jyLOixJFOTy91e4+tUlXmg78b4qgElUS8vPM9X85A5eHHxfJB1X1KvM4mJ IPlATThyTqLd37a/gOEZzMde/sRAJhHbbv8ItHrU+L8wajv1yxQBpmgaHyFqlK4J3iq6LAg6HLJ P5qfW5d3plSX3Ugxi5CjJ53VNYDbQDtkdusf/j6XR1JwnskKUjxXjLsuJoQqcGNQClh3CFabhcJ PNBluueiDTylwpChNrXXum1dTkKFAqf723sUrN1KlcpsvdBms1zosAUhhGGgsTkwaNbHR5eqc4b x2G02NXf0CDleyfxTc3dlQQ5YZQ/Z8oTEf/YV50W/iCvv7wZFx3jnsAJwYbQOSwnV7HFXaPbmSp BQmb7jL/N1Z62qsW/+g== X-Proofpoint-ORIG-GUID: pX-PZTytIOkzMvk_1Ukx0y1lhn7IpOt4 X-Proofpoint-GUID: pX-PZTytIOkzMvk_1Ukx0y1lhn7IpOt4 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-11_02,2026-04-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 clxscore=1015 impostorscore=0 malwarescore=0 suspectscore=0 adultscore=0 bulkscore=0 phishscore=0 priorityscore=1501 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604010000 definitions=main-2604110062 From: Imran Shaik This patch introduces the MHI PHC (PTP Hardware Clock) driver, which registers a PTP (Precision Time Protocol) clock and communicates with the MHI core to get the device side timestamps. These timestamps are then exposed to the PTP subsystem, enabling precise time synchronization between the host and the device. The following diagram illustrates the architecture and data flow: +-------------+ +--------------------+ +--------------+ |Userspace App|<-->|Kernel PTP framework|<-->|MHI PHC Driver| +-------------+ +--------------------+ +--------------+ | v +-------------------------------+ +-----------------+ | MHI Device (Timestamp source) |<------->| MHI Core Driver | +-------------------------------+ +-----------------+ - User space applications use the standard Linux PTP interface. - The PTP subsystem routes IOCTLs to the MHI PHC driver. - The MHI PHC driver communicates with the MHI core to fetch timestamps. - The MHI core interacts with the device to retrieve accurate time data. Co-developed-by: Taniya Das Signed-off-by: Taniya Das Signed-off-by: Imran Shaik --- drivers/bus/mhi/host/Kconfig | 8 ++ drivers/bus/mhi/host/Makefile | 1 + drivers/bus/mhi/host/mhi_phc.c | 150 +++++++++++++++++++++++++++++++++= ++++ drivers/bus/mhi/host/mhi_phc.h | 28 +++++++ drivers/bus/mhi/host/pci_generic.c | 23 ++++++ 5 files changed, 210 insertions(+) diff --git a/drivers/bus/mhi/host/Kconfig b/drivers/bus/mhi/host/Kconfig index da5cd0c9fc620ab595e742c422f1a22a2a84c7b9..b4eabf3e5c56907de93232f0296= 2040e979c3110 100644 --- a/drivers/bus/mhi/host/Kconfig +++ b/drivers/bus/mhi/host/Kconfig @@ -29,3 +29,11 @@ config MHI_BUS_PCI_GENERIC This driver provides MHI PCI controller driver for devices such as Qualcomm SDX55 based PCIe modems. =20 +config MHI_BUS_PHC + bool "MHI PHC driver" + depends on MHI_BUS_PCI_GENERIC + help + This driver provides Precision Time Protocol (PTP) clock and + communicates with MHI PCI driver to get the device side timestamp, + which enables precise time synchronization between the host and + the device. diff --git a/drivers/bus/mhi/host/Makefile b/drivers/bus/mhi/host/Makefile index 859c2f38451c669b3d3014c374b2b957c99a1cfe..5ba244fe7d596834ea535797efd= 3428963ba0ed0 100644 --- a/drivers/bus/mhi/host/Makefile +++ b/drivers/bus/mhi/host/Makefile @@ -4,3 +4,4 @@ mhi-$(CONFIG_MHI_BUS_DEBUG) +=3D debugfs.o =20 obj-$(CONFIG_MHI_BUS_PCI_GENERIC) +=3D mhi_pci_generic.o mhi_pci_generic-y +=3D pci_generic.o +mhi_pci_generic-$(CONFIG_MHI_BUS_PHC) +=3D mhi_phc.o diff --git a/drivers/bus/mhi/host/mhi_phc.c b/drivers/bus/mhi/host/mhi_phc.c new file mode 100644 index 0000000000000000000000000000000000000000..fa04eb7f6025fa281d86c0a45b5= f7d3e61f5ce12 --- /dev/null +++ b/drivers/bus/mhi/host/mhi_phc.c @@ -0,0 +1,150 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2025, Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include +#include "mhi_phc.h" + +#define NSEC 1000000000ULL + +/** + * struct mhi_phc_dev - MHI PHC device + * @ptp_clock: associated PTP clock + * @ptp_clock_info: PTP clock information + * @mhi_dev: associated mhi device object + * @lock: spinlock + * @enabled: Flag to track the state of the MHI device + */ +struct mhi_phc_dev { + struct ptp_clock *ptp_clock; + struct ptp_clock_info ptp_clock_info; + struct mhi_device *mhi_dev; + spinlock_t lock; + bool enabled; +}; + +static int qcom_ptp_gettimex64(struct ptp_clock_info *ptp, struct timespec= 64 *ts, + struct ptp_system_timestamp *sts) +{ + struct mhi_phc_dev *phc_dev =3D container_of(ptp, struct mhi_phc_dev, ptp= _clock_info); + struct mhi_timesync_info time; + ktime_t ktime_cur; + unsigned long flags; + int ret; + + spin_lock_irqsave(&phc_dev->lock, flags); + if (!phc_dev->enabled) { + ret =3D -ENODEV; + goto err; + } + + ret =3D mhi_get_remote_tsc_time_sync(phc_dev->mhi_dev, &time); + if (ret) + goto err; + + ktime_cur =3D time.t_dev_hi * NSEC + time.t_dev_lo; + *ts =3D ktime_to_timespec64(ktime_cur); + + dev_dbg(&phc_dev->mhi_dev->dev, "TSC time stamps sec:%u nsec:%u current:%= lld\n", + time.t_dev_hi, time.t_dev_lo, ktime_cur); + + /* Update pre and post timestamps for PTP_SYS_OFFSET_EXTENDED*/ + if (sts !=3D NULL) { + sts->pre_ts =3D ktime_to_timespec64(time.t_host_pre); + sts->post_ts =3D ktime_to_timespec64(time.t_host_post); + dev_dbg(&phc_dev->mhi_dev->dev, "pre:%lld post:%lld\n", + time.t_host_pre, time.t_host_post); + } + +err: + spin_unlock_irqrestore(&phc_dev->lock, flags); + + return ret; +} + +int mhi_phc_start(struct mhi_controller *mhi_cntrl) +{ + struct mhi_phc_dev *phc_dev =3D dev_get_drvdata(&mhi_cntrl->mhi_dev->dev); + unsigned long flags; + + if (!phc_dev) { + dev_err(&mhi_cntrl->mhi_dev->dev, "Driver data is NULL\n"); + return -ENODEV; + } + + spin_lock_irqsave(&phc_dev->lock, flags); + phc_dev->enabled =3D true; + spin_unlock_irqrestore(&phc_dev->lock, flags); + + return 0; +} + +int mhi_phc_stop(struct mhi_controller *mhi_cntrl) +{ + struct mhi_phc_dev *phc_dev =3D dev_get_drvdata(&mhi_cntrl->mhi_dev->dev); + unsigned long flags; + + if (!phc_dev) { + dev_err(&mhi_cntrl->mhi_dev->dev, "Driver data is NULL\n"); + return -ENODEV; + } + + spin_lock_irqsave(&phc_dev->lock, flags); + phc_dev->enabled =3D false; + spin_unlock_irqrestore(&phc_dev->lock, flags); + + return 0; +} + +static struct ptp_clock_info qcom_ptp_clock_info =3D { + .owner =3D THIS_MODULE, + .gettimex64 =3D qcom_ptp_gettimex64, +}; + +int mhi_phc_init(struct mhi_controller *mhi_cntrl) +{ + struct mhi_device *mhi_dev =3D mhi_cntrl->mhi_dev; + struct mhi_phc_dev *phc_dev; + int ret; + + phc_dev =3D devm_kzalloc(&mhi_dev->dev, sizeof(*phc_dev), GFP_KERNEL); + if (!phc_dev) + return -ENOMEM; + + phc_dev->mhi_dev =3D mhi_dev; + + phc_dev->ptp_clock_info =3D qcom_ptp_clock_info; + strscpy(phc_dev->ptp_clock_info.name, mhi_dev->name, PTP_CLOCK_NAME_LEN); + + spin_lock_init(&phc_dev->lock); + + phc_dev->ptp_clock =3D ptp_clock_register(&phc_dev->ptp_clock_info, &mhi_= dev->dev); + if (IS_ERR(phc_dev->ptp_clock)) { + ret =3D PTR_ERR(phc_dev->ptp_clock); + dev_err(&mhi_dev->dev, "Failed to register PTP clock\n"); + phc_dev->ptp_clock =3D NULL; + return ret; + } + + dev_set_drvdata(&mhi_dev->dev, phc_dev); + + dev_dbg(&mhi_dev->dev, "probed MHI PHC dev: %s\n", mhi_dev->name); + return 0; +}; + +void mhi_phc_exit(struct mhi_controller *mhi_cntrl) +{ + struct mhi_phc_dev *phc_dev =3D dev_get_drvdata(&mhi_cntrl->mhi_dev->dev); + + if (!phc_dev) + return; + + /* disable the node */ + ptp_clock_unregister(phc_dev->ptp_clock); + phc_dev->enabled =3D false; +} diff --git a/drivers/bus/mhi/host/mhi_phc.h b/drivers/bus/mhi/host/mhi_phc.h new file mode 100644 index 0000000000000000000000000000000000000000..e6b0866bc768ba5a8ac3e4c40a9= 9aa2050db1389 --- /dev/null +++ b/drivers/bus/mhi/host/mhi_phc.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2025, Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifdef CONFIG_MHI_BUS_PHC +int mhi_phc_init(struct mhi_controller *mhi_cntrl); +int mhi_phc_start(struct mhi_controller *mhi_cntrl); +int mhi_phc_stop(struct mhi_controller *mhi_cntrl); +void mhi_phc_exit(struct mhi_controller *mhi_cntrl); +#else +static inline int mhi_phc_init(struct mhi_controller *mhi_cntrl) +{ + return 0; +} + +static inline int mhi_phc_start(struct mhi_controller *mhi_cntrl) +{ + return 0; +} + +static inline int mhi_phc_stop(struct mhi_controller *mhi_cntrl) +{ + return 0; +} + +static inline void mhi_phc_exit(struct mhi_controller *mhi_cntrl) {} +#endif diff --git a/drivers/bus/mhi/host/pci_generic.c b/drivers/bus/mhi/host/pci_= generic.c index b1122c7224bdd469406d96af6d3df342040e1002..6cba5cecd1adb40396bba30c9b2= a551898dce871 100644 --- a/drivers/bus/mhi/host/pci_generic.c +++ b/drivers/bus/mhi/host/pci_generic.c @@ -16,6 +16,7 @@ #include #include #include +#include "mhi_phc.h" =20 #define MHI_PCI_DEFAULT_BAR_NUM 0 =20 @@ -1044,6 +1045,7 @@ struct mhi_pci_device { struct timer_list health_check_timer; unsigned long status; bool reset_on_remove; + bool mhi_phc_init_done; }; =20 #ifdef readq @@ -1084,6 +1086,7 @@ static void mhi_pci_status_cb(struct mhi_controller *= mhi_cntrl, enum mhi_callback cb) { struct pci_dev *pdev =3D to_pci_dev(mhi_cntrl->cntrl_dev); + struct mhi_pci_device *mhi_pdev =3D pci_get_drvdata(pdev); =20 /* Nothing to do for now */ switch (cb) { @@ -1091,9 +1094,21 @@ static void mhi_pci_status_cb(struct mhi_controller = *mhi_cntrl, case MHI_CB_SYS_ERROR: dev_warn(&pdev->dev, "firmware crashed (%u)\n", cb); pm_runtime_forbid(&pdev->dev); + /* Stop PHC */ + if (mhi_cntrl->tsc_timesync) + mhi_phc_stop(mhi_cntrl); break; case MHI_CB_EE_MISSION_MODE: pm_runtime_allow(&pdev->dev); + /* Start PHC */ + if (mhi_cntrl->tsc_timesync) { + if (!mhi_pdev->mhi_phc_init_done) { + mhi_phc_init(mhi_cntrl); + mhi_pdev->mhi_phc_init_done =3D true; + } + + mhi_phc_start(mhi_cntrl); + } break; default: break; @@ -1236,6 +1251,10 @@ static void mhi_pci_recovery_work(struct work_struct= *work) =20 pm_runtime_forbid(&pdev->dev); =20 + /* Stop PHC */ + if (mhi_cntrl->tsc_timesync) + mhi_phc_stop(mhi_cntrl); + /* Clean up MHI state */ if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) { mhi_power_down(mhi_cntrl, false); @@ -1457,6 +1476,10 @@ static void mhi_pci_remove(struct pci_dev *pdev) timer_delete_sync(&mhi_pdev->health_check_timer); cancel_work_sync(&mhi_pdev->recovery_work); =20 + /* Remove PHC */ + if (mhi_cntrl->tsc_timesync) + mhi_phc_exit(mhi_cntrl); + if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) { mhi_power_down(mhi_cntrl, true); mhi_unprepare_after_power_down(mhi_cntrl); --=20 2.34.1