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charset="utf-8" From: Nick Hawkins Add the HPE GSC ARM64 BMC SoC compatibles to the existing hpe,gxp.yaml binding. The initial board compatible is hpe,gsc-dl340gen12 for the DL340 Gen12 server platform. Add the arm64 DTS path to the existing ARM/HPE GXP MAINTAINERS entry, renamed to ARM/HPE GXP/GSC ARCHITECTURE. Signed-off-by: Nick Hawkins Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/hpe,gxp.yaml | 7 ++++++- MAINTAINERS | 3 ++- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/hpe,gxp.yaml b/Documenta= tion/devicetree/bindings/arm/hpe,gxp.yaml index 224bbcb93f95..6f057cd58571 100644 --- a/Documentation/devicetree/bindings/arm/hpe,gxp.yaml +++ b/Documentation/devicetree/bindings/arm/hpe,gxp.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/arm/hpe,gxp.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 -title: HPE BMC GXP platforms +title: HPE BMC GXP and GSC platforms =20 maintainers: - Nick Hawkins @@ -15,6 +15,11 @@ properties: oneOf: + - description: GSC Based Boards + items: + - enum: + - hpe,gsc-dl340gen12 + - const: hpe,gsc - description: GXP Based Boards items: - enum: - hpe,gxp-dl360gen10 - const: hpe,gxp =20 required: - compatible diff --git a/MAINTAINERS b/MAINTAINERS index 2265e2c9bfbe..80c66de5e342 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2859,7 +2859,7 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/= kristoffer/linux-hpc.git F: arch/arm/mach-sa1100/include/mach/jornada720.h F: arch/arm/mach-sa1100/jornada720.c =20 -ARM/HPE GXP ARCHITECTURE +ARM/HPE GXP/GSC ARCHITECTURE M: Jean-Marie Verdun M: Nick Hawkins S: Maintained @@ -2870,6 +2870,7 @@ F: Documentation/devicetree/bindings/spi/hpe,gxp-spif= i.yaml F: Documentation/devicetree/bindings/timer/hpe,gxp-timer.yaml F: Documentation/hwmon/gxp-fan-ctrl.rst F: arch/arm/boot/dts/hpe/ +F: arch/arm64/boot/dts/hpe/ F: drivers/clocksource/timer-gxp.c F: drivers/hwmon/gxp-fan-ctrl.c F: drivers/i2c/busses/i2c-gxp.c --=20 2.34.1 From nobody Mon Jun 15 13:57:17 2026 Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8E1473DB63C; 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charset="utf-8" From: Nick Hawkins Add the ARCH_HPE config for HPE ARM64 BMC SoCs to Kconfig.platforms. Signed-off-by: Nick Hawkins Reviewed-by: Krzysztof Kozlowski --- arch/arm64/Kconfig.platforms | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 54eb1d7fd419..b4217809c774 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -168,6 +168,17 @@ config ARCH_HISI help This enables support for Hisilicon ARMv8 SoC family =20 +config ARCH_HPE + bool "HPE SoC Support" + select PINCTRL + select GENERIC_IRQ_CHIP + select CLKSRC_MMIO + help + This enables support for HPE ARM-based SoC chips used + on HPE servers. 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Fri, 10 Apr 2026 17:16:24 +0000 (UTC) Received: from hpe.com (unknown [16.231.227.36]) by p1lg14885.dc01.its.hpecorp.net (Postfix) with ESMTP id 47C3D808530; Fri, 10 Apr 2026 17:16:24 +0000 (UTC) From: nick.hawkins@hpe.com To: catalin.marinas@arm.com, will@kernel.org Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, krzysztof.kozlowski@oss.qualcomm.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Nick Hawkins Subject: [PATCH v5 3/4] arm64: dts: hpe: Add HPE GSC SoC and DL340 Gen12 board DTS Date: Fri, 10 Apr 2026 17:16:10 +0000 Message-ID: <20260410171611.2547255-4-nick.hawkins@hpe.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260410171611.2547255-1-nick.hawkins@hpe.com> References: <20260410171611.2547255-1-nick.hawkins@hpe.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDEwMDE2MiBTYWx0ZWRfX0BAOoDBxs6sA r0F7LzMujNk8BmAclWXfGTlNcbIhvpvrej/P5XnNHt3Dxrm12IUHXY0hn6Rosq7BNkJI2GBVaya wzj/Mv8BIHNCVU8QDVpFg3mm4lpZBskTIGnQapjXb3i3lHLTSE4JOCwcg0gUzg9fL8v3TUOL5jR TNU4/OzUqO9/4n4Euj57hlIOrQW90ioQeE/JmNcQ2sMgibdCVKMnn1lJTk+qMHk0NJXOEx/e1rS Yl2e346uQiAJLivY27nxekPLBAZa60feNsTWNZZtuR3W8331tA2A8ucjzbhcg3Tdmu7ICmp8gVX cVJR63Ah/dS4QgZ916qIbQ7n5Vnqmhu288PXr5UpCHiMOOCOyCKlDifLWRt64DYkjFwyBm/WC0Q yMF7FGaL8Lse6Yv4VeobnYmfkJXd+dUVb5xNujq9EcNX7pKb3gnX2O9AzJenY0/C9Bye5OoVts/ I+pBUseFqnQnJOiPhSg== X-Proofpoint-ORIG-GUID: N05lh3INzBHd0J60Twa_1S2imvFuuJ4J X-Proofpoint-GUID: N05lh3INzBHd0J60Twa_1S2imvFuuJ4J X-Authority-Analysis: v=2.4 cv=At7eGu9P c=1 sm=1 tr=0 ts=69d93069 cx=c_pps a=A+SOMQ4XYIH4HgQ50p3F5Q==:117 a=A+SOMQ4XYIH4HgQ50p3F5Q==:17 a=A5OVakUREuEA:10 a=VkNPw1HP01LnGYTKEx00:22 a=gQcMVamqm3wCPoSYhaRC:22 a=RtSn8ETxjE2H05FtM2s8:22 a=MvuuwTCpAAAA:8 a=KK1IH8HFS8MDNeiM4vUA:9 X-HPE-SCL: -1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-10_05,2026-04-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 impostorscore=0 suspectscore=0 phishscore=0 lowpriorityscore=0 clxscore=1015 spamscore=0 priorityscore=1501 adultscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604010000 definitions=main-2604100162 Content-Type: text/plain; charset="utf-8" From: Nick Hawkins Add SoC-level DTSI for the HPE GSC ARM64 BMC SoC, covering the CPU cluster, GIC v3 interrupt controller, ARM64 generic timer, and console UART. Add the board-level DTS for the HPE DL340 Gen12, which includes gsc.dtsi and adds memory and chosen nodes. Signed-off-by: Nick Hawkins Reviewed-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/hpe/Makefile | 2 + arch/arm64/boot/dts/hpe/gsc-dl340gen12.dts | 18 ++++ arch/arm64/boot/dts/hpe/gsc.dtsi | 104 +++++++++++++++++++++ 3 files changed, 124 insertions(+) create mode 100644 arch/arm64/boot/dts/hpe/Makefile create mode 100644 arch/arm64/boot/dts/hpe/gsc-dl340gen12.dts create mode 100644 arch/arm64/boot/dts/hpe/gsc.dtsi diff --git a/arch/arm64/boot/dts/hpe/Makefile b/arch/arm64/boot/dts/hpe/Mak= efile new file mode 100644 index 000000000000..6b547b8a8154 --- /dev/null +++ b/arch/arm64/boot/dts/hpe/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +dtb-$(CONFIG_ARCH_HPE) +=3D gsc-dl340gen12.dtb diff --git a/arch/arm64/boot/dts/hpe/gsc-dl340gen12.dts b/arch/arm64/boot/d= ts/hpe/gsc-dl340gen12.dts new file mode 100644 index 000000000000..7a3d9f1c4b2e --- /dev/null +++ b/arch/arm64/boot/dts/hpe/gsc-dl340gen12.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "gsc.dtsi" + +/ { + compatible =3D "hpe,gsc-dl340gen12", "hpe,gsc"; + model =3D "HPE ProLiant DL340 Gen12"; + + chosen { + stdout-path =3D &uartc; + }; + + memory@0 { + device_type =3D "memory"; + reg =3D <0x00000000 0x40000000>; + }; +}; diff --git a/arch/arm64/boot/dts/hpe/gsc.dtsi b/arch/arm64/boot/dts/hpe/gsc= .dtsi new file mode 100644 index 000000000000..1f4c2a7b3d91 --- /dev/null +++ b/arch/arm64/boot/dts/hpe/gsc.dtsi @@ -0,0 +1,104 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree file for HPE GSC + */ + +#include + +/ { + #address-cells =3D <1>; + #size-cells =3D <1>; + + osc: clock-33333333 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-output-names =3D "osc"; + clock-frequency =3D <33333333>; + }; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0>; + enable-method =3D "spin-table"; + cpu-release-addr =3D <0 0xa0008048>; + }; + + cpu@1 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <1>; + enable-method =3D "spin-table"; + cpu-release-addr =3D <0 0xa0008048>; + }; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupt-parent =3D <&gic>; + interrupts =3D , + , + , + ; + }; + + soc: soc@80000000 { + compatible =3D "simple-bus"; + reg =3D <0x80000000 0x80000000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + + uarta: serial@c00000e0 { + compatible =3D "ns16550a"; + reg =3D <0xc00000e0 0x8>; + clock-frequency =3D <1846153>; + interrupt-parent =3D <&gic>; + interrupts =3D ; + reg-shift =3D <0>; + }; + + uartb: serial@c00000e8 { + compatible =3D "ns16550a"; + reg =3D <0xc00000e8 0x8>; + clock-frequency =3D <1846153>; + interrupt-parent =3D <&gic>; + interrupts =3D ; + reg-shift =3D <0>; + }; + + uartc: serial@c00000f0 { + compatible =3D "ns16550a"; + reg =3D <0xc00000f0 0x8>; + clock-frequency =3D <1846153>; + interrupt-parent =3D <&gic>; + interrupts =3D ; + reg-shift =3D <0>; + }; + + uarte: serial@c00003e0 { + compatible =3D "ns16550a"; + reg =3D <0xc00003e0 0x8>; + clock-frequency =3D <1846153>; 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charset="utf-8" From: Nick Hawkins Enable ARCH_HPE in the arm64 defconfig to include HPE GSC BMC SoC support in the default build. Signed-off-by: Nick Hawkins Reviewed-by: Krzysztof Kozlowski --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index xxxxxxxxxxxxxxx..xxxxxxxxxxxxxxx 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -xx,6 +xx,7 @@ CONFIG_ARCH_HISI=3Dy +CONFIG_ARCH_HPE=3Dy CONFIG_ARCH_KEEMBAY=3Dy --=20 2.34.1