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Fri, 10 Apr 2026 09:01:15 +0000 From: Changhuang Liang To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Gleixner , Philipp Zabel Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Ley Foon Tan , Changhuang Liang Subject: [PATCH v1 1/5] dt-bindings: interrupt-controller: Convert the word "jh8100" to "jhb100" Date: Fri, 10 Apr 2026 02:01:02 -0700 Message-Id: <20260410090106.622781-2-changhuang.liang@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260410090106.622781-1-changhuang.liang@starfivetech.com> References: <20260410090106.622781-1-changhuang.liang@starfivetech.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: NT0PR01CA0017.CHNPR01.prod.partner.outlook.cn (2406:e500:c510::6) To ZQ4PR01MB1202.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:17::6) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: ZQ4PR01MB1202:EE_|ZQ4PR01MB1218:EE_ X-MS-Office365-Filtering-Correlation-Id: 57f414db-5a46-4653-d279-08de96dfb8d1 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0;ARA:13230040|52116014|376014|1800799024|366016|56012099003|38350700014|22082099003|18002099003; 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charset="utf-8" The StarFive JH8100 SoC was discontinued before production. The newly taped-out JHB100 SoC uses the same interrupt controller IP. Rename the binding file, compatible string, and MAINTAINERS entry from "jh8100" to "jhb100". In JHB100 SoC, The clocks and resets are not operated by users, but they exist in the hardware. Mark them as optional. Signed-off-by: Changhuang Liang Acked-by: Conor Dooley --- ...ve,jh8100-intc.yaml =3D> starfive,jhb100-intc.yaml} | 12 ++++-------- MAINTAINERS | 2 +- 2 files changed, 5 insertions(+), 9 deletions(-) rename Documentation/devicetree/bindings/interrupt-controller/{starfive,jh= 8100-intc.yaml =3D> starfive,jhb100-intc.yaml} (81%) diff --git a/Documentation/devicetree/bindings/interrupt-controller/starfiv= e,jh8100-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller= /starfive,jhb100-intc.yaml similarity index 81% rename from Documentation/devicetree/bindings/interrupt-controller/starfive= ,jh8100-intc.yaml rename to Documentation/devicetree/bindings/interrupt-controller/starfive,j= hb100-intc.yaml index ada5788602d6..576b1d6c7973 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/starfive,jh810= 0-intc.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/starfive,jhb10= 0-intc.yaml @@ -1,13 +1,13 @@ # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause %YAML 1.2 --- -$id: http://devicetree.org/schemas/interrupt-controller/starfive,jh8100-in= tc.yaml# +$id: http://devicetree.org/schemas/interrupt-controller/starfive,jhb100-in= tc.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 title: StarFive External Interrupt Controller =20 description: - StarFive SoC JH8100 contain a external interrupt controller. It can be u= sed + StarFive SoC JHB100 contain a external interrupt controller. It can be u= sed to handle high-level input interrupt signals. It also send the output interrupt signal to RISC-V PLIC. =20 @@ -16,7 +16,7 @@ maintainers: =20 properties: compatible: - const: starfive,jh8100-intc + const: starfive,jhb100-intc =20 reg: maxItems: 1 @@ -40,8 +40,6 @@ properties: required: - compatible - reg - - clocks - - resets - interrupts - interrupt-controller - "#interrupt-cells" @@ -51,10 +49,8 @@ additionalProperties: false examples: - | interrupt-controller@12260000 { - compatible =3D "starfive,jh8100-intc"; + compatible =3D "starfive,jhb100-intc"; reg =3D <0x12260000 0x10000>; - clocks =3D <&syscrg_ne 76>; - resets =3D <&syscrg_ne 13>; interrupts =3D <45>; interrupt-controller; #interrupt-cells =3D <1>; diff --git a/MAINTAINERS b/MAINTAINERS index d238590a31f2..a2961727e3d1 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -25312,7 +25312,7 @@ F: drivers/phy/starfive/phy-jh7110-usb.c STARFIVE JH8100 EXTERNAL INTERRUPT CONTROLLER DRIVER M: Changhuang Liang S: Supported -F: Documentation/devicetree/bindings/interrupt-controller/starfive,jh8100-= intc.yaml +F: Documentation/devicetree/bindings/interrupt-controller/starfive,jhb100-= intc.yaml F: drivers/irqchip/irq-starfive-jh8100-intc.c =20 STATIC BRANCH/CALL --=20 2.25.1 From nobody Mon Jun 15 12:18:50 2026 Received: from CHN02-BJS-obe.outbound.protection.partner.outlook.cn (mail-bjschn02on2109.outbound.protection.partner.outlook.cn [139.219.17.109]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EA8C0223323; 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charset="utf-8" The StarFive JH8100 SoC was discontinued before production. The newly taped-out JHB100 SoC uses the same interrupt controller IP. Rename the driver file, Kconfig symbol, and internal references from "jh8100" to "jhb100" to accurately reflect the supported hardware. Signed-off-by: Changhuang Liang --- MAINTAINERS | 4 ++-- drivers/irqchip/Kconfig | 6 +++--- drivers/irqchip/Makefile | 2 +- ...arfive-jh8100-intc.c =3D> irq-starfive-jhb100-intc.c} | 10 +++++----- 4 files changed, 11 insertions(+), 11 deletions(-) rename drivers/irqchip/{irq-starfive-jh8100-intc.c =3D> irq-starfive-jhb10= 0-intc.c} (94%) diff --git a/MAINTAINERS b/MAINTAINERS index a2961727e3d1..93cbe852ac0b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -25309,11 +25309,11 @@ F: Documentation/devicetree/bindings/phy/starfive= ,jh7110-usb-phy.yaml F: drivers/phy/starfive/phy-jh7110-pcie.c F: drivers/phy/starfive/phy-jh7110-usb.c =20 -STARFIVE JH8100 EXTERNAL INTERRUPT CONTROLLER DRIVER +STARFIVE JHB100 EXTERNAL INTERRUPT CONTROLLER DRIVER M: Changhuang Liang S: Supported F: Documentation/devicetree/bindings/interrupt-controller/starfive,jhb100-= intc.yaml -F: drivers/irqchip/irq-starfive-jh8100-intc.c +F: drivers/irqchip/irq-starfive-jhb100-intc.c =20 STATIC BRANCH/CALL M: Peter Zijlstra diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index f07b00d7fef9..697c6b2e006c 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -651,13 +651,13 @@ config SIFIVE_PLIC select IRQ_DOMAIN_HIERARCHY select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP =20 -config STARFIVE_JH8100_INTC - bool "StarFive JH8100 External Interrupt Controller" +config STARFIVE_JHB100_INTC + bool "StarFive JHB100 External Interrupt Controller" depends on ARCH_STARFIVE || COMPILE_TEST default ARCH_STARFIVE select IRQ_DOMAIN_HIERARCHY help - This enables support for the INTC chip found in StarFive JH8100 + This enables support for the INTC chip found in StarFive JHB100 SoC. =20 If you don't know what to do here, say Y. diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index 26aa3b6ec99f..c686caaa4451 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -108,7 +108,7 @@ obj-$(CONFIG_RISCV_APLIC_MSI) +=3D irq-riscv-aplic-msi= .o obj-$(CONFIG_RISCV_IMSIC) +=3D irq-riscv-imsic-state.o irq-riscv-imsic-ea= rly.o irq-riscv-imsic-platform.o obj-$(CONFIG_RISCV_RPMI_SYSMSI) +=3D irq-riscv-rpmi-sysmsi.o obj-$(CONFIG_SIFIVE_PLIC) +=3D irq-sifive-plic.o -obj-$(CONFIG_STARFIVE_JH8100_INTC) +=3D irq-starfive-jh8100-intc.o +obj-$(CONFIG_STARFIVE_JHB100_INTC) +=3D irq-starfive-jhb100-intc.o obj-$(CONFIG_ACLINT_SSWI) +=3D irq-aclint-sswi.o obj-$(CONFIG_IMX_IRQSTEER) +=3D irq-imx-irqsteer.o obj-$(CONFIG_IMX_INTMUX) +=3D irq-imx-intmux.o diff --git a/drivers/irqchip/irq-starfive-jh8100-intc.c b/drivers/irqchip/i= rq-starfive-jhb100-intc.c similarity index 94% rename from drivers/irqchip/irq-starfive-jh8100-intc.c rename to drivers/irqchip/irq-starfive-jhb100-intc.c index bb62ef363d0b..2c9cdad7f377 100644 --- a/drivers/irqchip/irq-starfive-jh8100-intc.c +++ b/drivers/irqchip/irq-starfive-jhb100-intc.c @@ -1,13 +1,13 @@ // SPDX-License-Identifier: GPL-2.0 /* - * StarFive JH8100 External Interrupt Controller driver + * StarFive JHB100 External Interrupt Controller driver * * Copyright (C) 2023 StarFive Technology Co., Ltd. * * Author: Changhuang Liang */ =20 -#define pr_fmt(fmt) "irq-starfive-jh8100: " fmt +#define pr_fmt(fmt) "irq-starfive-jhb100: " fmt =20 #include #include @@ -71,7 +71,7 @@ static void starfive_intc_mask(struct irq_data *d) } =20 static struct irq_chip intc_dev =3D { - .name =3D "StarFive JH8100 INTC", + .name =3D "StarFive JHB100 INTC", .irq_unmask =3D starfive_intc_unmask, .irq_mask =3D starfive_intc_mask, }; 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charset="utf-8" Use devm_ interfaces to simplify resource release. Make clock and reset get optional as they are not used on the JHB100 SoC. Replace pr_ logging with dev_* logging. Signed-off-by: Changhuang Liang --- drivers/irqchip/irq-starfive-jhb100-intc.c | 44 ++++++++-------------- 1 file changed, 15 insertions(+), 29 deletions(-) diff --git a/drivers/irqchip/irq-starfive-jhb100-intc.c b/drivers/irqchip/i= rq-starfive-jhb100-intc.c index 2c9cdad7f377..312a4634870a 100644 --- a/drivers/irqchip/irq-starfive-jhb100-intc.c +++ b/drivers/irqchip/irq-starfive-jhb100-intc.c @@ -7,16 +7,14 @@ * Author: Changhuang Liang */ =20 -#define pr_fmt(fmt) "irq-starfive-jhb100: " fmt - #include #include #include #include #include #include -#include #include +#include #include #include =20 @@ -127,48 +125,44 @@ static int starfive_intc_probe(struct platform_device= *pdev, struct device_node if (!irqc) return -ENOMEM; =20 - irqc->base =3D of_iomap(intc, 0); + irqc->base =3D devm_platform_ioremap_resource(pdev, 0); if (!irqc->base) { - pr_err("Unable to map registers\n"); + dev_err(&pdev->dev, "unable to map registers\n"); ret =3D -ENXIO; goto err_free; } =20 - rst =3D of_reset_control_get_exclusive(intc, NULL); + rst =3D devm_reset_control_get_optional(&pdev->dev, NULL); if (IS_ERR(rst)) { - pr_err("Unable to get reset control %pe\n", rst); + dev_err(&pdev->dev, "Unable to get reset control %pe\n", rst); ret =3D PTR_ERR(rst); - goto err_unmap; + goto err_free; } =20 - clk =3D of_clk_get(intc, 0); + clk =3D devm_clk_get_optional_enabled(&pdev->dev, NULL); if (IS_ERR(clk)) { - pr_err("Unable to get clock %pe\n", clk); + dev_err(&pdev->dev, "Unable to get and enable clock %pe\n", clk); ret =3D PTR_ERR(clk); - goto err_reset_put; + goto err_free; } =20 ret =3D reset_control_deassert(rst); if (ret) - goto err_clk_put; - - ret =3D clk_prepare_enable(clk); - if (ret) - goto err_reset_assert; + goto err_free; =20 raw_spin_lock_init(&irqc->lock); =20 irqc->domain =3D irq_domain_create_linear(of_fwnode_handle(intc), STARFIV= E_INTC_SRC_IRQ_NUM, &starfive_intc_domain_ops, irqc); if (!irqc->domain) { - pr_err("Unable to create IRQ domain\n"); + dev_err(&pdev->dev, "Unable to create IRQ domain\n"); ret =3D -EINVAL; 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charset="utf-8" From: Mason Huo StarFive JHB100 SoC interrupt controller actually supports 64 interrupt sources, the original code only supported up to 32. now it is extended to 64. Signed-off-by: Mason Huo Signed-off-by: Changhuang Liang --- drivers/irqchip/irq-starfive-jhb100-intc.c | 43 ++++++++++++++-------- 1 file changed, 28 insertions(+), 15 deletions(-) diff --git a/drivers/irqchip/irq-starfive-jhb100-intc.c b/drivers/irqchip/i= rq-starfive-jhb100-intc.c index 312a4634870a..d5ecbb603a58 100644 --- a/drivers/irqchip/irq-starfive-jhb100-intc.c +++ b/drivers/irqchip/irq-starfive-jhb100-intc.c @@ -18,10 +18,11 @@ #include #include =20 -#define STARFIVE_INTC_SRC0_CLEAR 0x10 -#define STARFIVE_INTC_SRC0_MASK 0x14 -#define STARFIVE_INTC_SRC0_INT 0x1c +#define STARFIVE_INTC_SRC_CLEAR(n) (0x10 + ((n) * 0x20)) +#define STARFIVE_INTC_SRC_MASK(n) (0x14 + ((n) * 0x20)) +#define STARFIVE_INTC_SRC_INT(n) (0x1c + ((n) * 0x20)) =20 +#define STARFIVE_INTC_NUM 2 #define STARFIVE_INTC_SRC_IRQ_NUM 32 =20 struct starfive_irq_chip { @@ -53,18 +54,26 @@ static void starfive_intc_bit_clear(struct starfive_irq= _chip *irqc, static void starfive_intc_unmask(struct irq_data *d) { struct starfive_irq_chip *irqc =3D irq_data_get_irq_chip_data(d); + int i, bitpos; + + i =3D d->hwirq / STARFIVE_INTC_SRC_IRQ_NUM; + bitpos =3D d->hwirq % STARFIVE_INTC_SRC_IRQ_NUM; =20 raw_spin_lock(&irqc->lock); - starfive_intc_bit_clear(irqc, STARFIVE_INTC_SRC0_MASK, BIT(d->hwirq)); + starfive_intc_bit_clear(irqc, STARFIVE_INTC_SRC_MASK(i), BIT(bitpos)); raw_spin_unlock(&irqc->lock); } =20 static void starfive_intc_mask(struct irq_data *d) { struct starfive_irq_chip *irqc =3D irq_data_get_irq_chip_data(d); + int i, bitpos; + + i =3D d->hwirq / STARFIVE_INTC_SRC_IRQ_NUM; + bitpos =3D d->hwirq % STARFIVE_INTC_SRC_IRQ_NUM; =20 raw_spin_lock(&irqc->lock); - starfive_intc_bit_set(irqc, STARFIVE_INTC_SRC0_MASK, BIT(d->hwirq)); + starfive_intc_bit_set(irqc, STARFIVE_INTC_SRC_MASK(i), BIT(bitpos)); raw_spin_unlock(&irqc->lock); } =20 @@ -93,20 +102,23 @@ static void starfive_intc_irq_handler(struct irq_desc = *desc) struct starfive_irq_chip *irqc =3D irq_data_get_irq_handler_data(&desc->i= rq_data); struct irq_chip *chip =3D irq_desc_get_chip(desc); unsigned long value; - int hwirq; + int hwirq, i; =20 chained_irq_enter(chip, desc); =20 - value =3D ioread32(irqc->base + STARFIVE_INTC_SRC0_INT); - while (value) { - hwirq =3D ffs(value) - 1; + for (i =3D 0; i < STARFIVE_INTC_NUM; i++) { + value =3D ioread32(irqc->base + STARFIVE_INTC_SRC_INT(i)); + while (value) { + hwirq =3D ffs(value) - 1; =20 - generic_handle_domain_irq(irqc->domain, hwirq); + generic_handle_domain_irq(irqc->domain, + hwirq + i * STARFIVE_INTC_SRC_IRQ_NUM); =20 - starfive_intc_bit_set(irqc, STARFIVE_INTC_SRC0_CLEAR, BIT(hwirq)); - starfive_intc_bit_clear(irqc, STARFIVE_INTC_SRC0_CLEAR, BIT(hwirq)); + starfive_intc_bit_set(irqc, STARFIVE_INTC_SRC_CLEAR(i), BIT(hwirq)); + starfive_intc_bit_clear(irqc, STARFIVE_INTC_SRC_CLEAR(i), BIT(hwirq)); =20 - __clear_bit(hwirq, &value); + __clear_bit(hwirq, &value); + } } =20 chained_irq_exit(chip, desc); @@ -152,7 +164,8 @@ static int starfive_intc_probe(struct platform_device *= pdev, struct device_node =20 raw_spin_lock_init(&irqc->lock); =20 - irqc->domain =3D irq_domain_create_linear(of_fwnode_handle(intc), STARFIV= E_INTC_SRC_IRQ_NUM, + irqc->domain =3D irq_domain_create_linear(of_fwnode_handle(intc), + STARFIVE_INTC_SRC_IRQ_NUM * STARFIVE_INTC_NUM, &starfive_intc_domain_ops, irqc); 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charset="utf-8" Add irq_set_type hook to support configuring interrupt trigger types (level high/low, edge rising/falling) for the JHB100 interrupt controller. Also add irq_ack hook as required by handle_edge_irq. Signed-off-by: Changhuang Liang --- drivers/irqchip/irq-starfive-jhb100-intc.c | 72 ++++++++++++++++++++++ 1 file changed, 72 insertions(+) diff --git a/drivers/irqchip/irq-starfive-jhb100-intc.c b/drivers/irqchip/i= rq-starfive-jhb100-intc.c index d5ecbb603a58..d34f960b0770 100644 --- a/drivers/irqchip/irq-starfive-jhb100-intc.c +++ b/drivers/irqchip/irq-starfive-jhb100-intc.c @@ -9,6 +9,7 @@ =20 #include #include +#include #include #include #include @@ -18,12 +19,20 @@ #include #include =20 +#define STARFIVE_INTC_SRC_TYPE(n) (0x04 + ((n) * 0x20)) #define STARFIVE_INTC_SRC_CLEAR(n) (0x10 + ((n) * 0x20)) #define STARFIVE_INTC_SRC_MASK(n) (0x14 + ((n) * 0x20)) #define STARFIVE_INTC_SRC_INT(n) (0x1c + ((n) * 0x20)) =20 +#define STARFIVE_INTC_TRIGGER_MASK 0x3 +#define STARFIVE_INTC_TRIGGER_HIGH 0 +#define STARFIVE_INTC_TRIGGER_LOW 1 +#define STARFIVE_INTC_TRIGGER_POSEDGE 2 +#define STARFIVE_INTC_TRIGGER_NEGEDGE 3 + #define STARFIVE_INTC_NUM 2 #define STARFIVE_INTC_SRC_IRQ_NUM 32 +#define STARFIVE_INTC_TYPE_NUM 16 =20 struct starfive_irq_chip { void __iomem *base; @@ -31,6 +40,17 @@ struct starfive_irq_chip { raw_spinlock_t lock; }; =20 +static void starfive_intc_mod(struct starfive_irq_chip *irqc, u32 reg, + u32 mask, u32 data) +{ + u32 value; + + value =3D ioread32(irqc->base + reg) & ~mask; + data &=3D mask; + data |=3D value; + iowrite32(data, irqc->base + reg); +} + static void starfive_intc_bit_set(struct starfive_irq_chip *irqc, u32 reg, u32 bit_mask) { @@ -77,10 +97,62 @@ static void starfive_intc_mask(struct irq_data *d) raw_spin_unlock(&irqc->lock); } =20 +static void starfive_intc_ack(struct irq_data *d) +{ + /* for handle_edge_irq, nothing to do */ +} + +static int starfive_intc_set_type(struct irq_data *d, unsigned int type) +{ + struct starfive_irq_chip *irqc =3D irq_data_get_irq_chip_data(d); + u32 i, bitpos, ty_pos, ty_shift, tmp; + + i =3D d->hwirq / STARFIVE_INTC_SRC_IRQ_NUM; + bitpos =3D d->hwirq % STARFIVE_INTC_SRC_IRQ_NUM; + ty_pos =3D bitpos / STARFIVE_INTC_TYPE_NUM; + ty_shift =3D (bitpos % STARFIVE_INTC_TYPE_NUM) * 2; + + switch (type) { + case IRQF_TRIGGER_LOW: + tmp =3D STARFIVE_INTC_TRIGGER_LOW << ty_shift; + irq_set_handler_locked(d, handle_level_irq); + break; + case IRQF_TRIGGER_HIGH: + tmp =3D STARFIVE_INTC_TRIGGER_HIGH << ty_shift; + irq_set_handler_locked(d, handle_level_irq); + break; + case IRQF_TRIGGER_FALLING: + tmp =3D STARFIVE_INTC_TRIGGER_NEGEDGE << ty_shift; + irq_set_handler_locked(d, handle_edge_irq); + break; + case IRQF_TRIGGER_RISING: + tmp =3D STARFIVE_INTC_TRIGGER_POSEDGE << ty_shift; + irq_set_handler_locked(d, handle_edge_irq); + break; + default: + return -EINVAL; + } + + raw_spin_lock(&irqc->lock); + + starfive_intc_mod(irqc, STARFIVE_INTC_SRC_TYPE(i) + 4 * ty_pos, + STARFIVE_INTC_TRIGGER_MASK << ty_shift, tmp); + + /* Once the type is updated, clear interrupt can help to reset the type v= alue */ + starfive_intc_bit_set(irqc, STARFIVE_INTC_SRC_CLEAR(i), BIT(bitpos)); + starfive_intc_bit_clear(irqc, STARFIVE_INTC_SRC_CLEAR(i), BIT(bitpos)); + + raw_spin_unlock(&irqc->lock); + + return 0; +} + static struct irq_chip intc_dev =3D { .name =3D "StarFive JHB100 INTC", .irq_unmask =3D starfive_intc_unmask, .irq_mask =3D starfive_intc_mask, + .irq_ack =3D starfive_intc_ack, + .irq_set_type =3D starfive_intc_set_type, }; =20 static int starfive_intc_map(struct irq_domain *d, unsigned int irq, --=20 2.25.1