From nobody Mon Apr 13 07:45:35 2026 Received: from mout-p-102.mailbox.org (mout-p-102.mailbox.org [80.241.56.152]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C74C93A8723; Fri, 10 Apr 2026 07:59:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=80.241.56.152 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775807984; cv=none; b=I1kNo+8x7+ZBO0T71iln/m9kauv9q7oQLEGcPMANqxL14F+L9qb2dQM7yoxzaeoAWkaS0mUkKT/81ct+T6D+ai3vYaz7Yam6JeBLLxgggtPdBgkWITF43YPaby+n11Jo2NLMTaF+aHTypSMfJz2IpqsiVGWA4NyQ6/t5yPTl/W4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775807984; c=relaxed/simple; bh=tv1SteH5+qLSYwGgTDPHiMVefHL7DAGC9ZjSkpHF5uw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=dQ/rTkYTJiKnxcu6nzSffGTFi4u8EoL2jOtQBlfKEsLp+fqE5sgyYzbcI0cehHUjWNLZuHGq+X36CN1tAiAWQKCd1Vp9rIpjjurHzEF691PCWTc93c536rjEQaO6QryzWbFbXOrIy2xiXbFaz3BkRmexZ9rDErRSggnLQoc8lfc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=mailbox.org; spf=pass smtp.mailfrom=mailbox.org; dkim=pass (2048-bit key) header.d=mailbox.org header.i=@mailbox.org header.b=WeHuFJM4; dkim=pass (2048-bit key) header.d=mailbox.org header.i=@mailbox.org header.b=rAWWtWWl; arc=none smtp.client-ip=80.241.56.152 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=mailbox.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mailbox.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=mailbox.org header.i=@mailbox.org header.b="WeHuFJM4"; dkim=pass (2048-bit key) header.d=mailbox.org header.i=@mailbox.org header.b="rAWWtWWl" Received: from smtp1.mailbox.org (smtp1.mailbox.org [10.196.197.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mout-p-102.mailbox.org (Postfix) with ESMTPS id 4fsTjS5vr1z9sPv; Fri, 10 Apr 2026 09:59:40 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mailbox.org; s=mail20150812; t=1775807980; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=T2dY7nUbucCLtbQPyesJbvvM8gyBSryaljiV7Vdh9ew=; b=WeHuFJM4sHGvsWvSMNhcjGOwXy7+/o5f2NaDK2agyVsZdlcfAMwdDnprp1spOSEj5ZfrGv 0mYtiPcARoQkf4WAMH+5vqPMAktHATJ/sG8F2xAlXiqPFb/d9PT8ZjOn/qJsqKLFkMNH5+ 2bIr+t6e0ETt5ISDpz8piPb/xSGYjBuVDqhHGZJNzp5Ga25KjMeJBkoTYNYPM2DyWUeRwE uAc7ESJV2Ipwf/O7MIMeK0M9NgEuOrjRikjTCaBe5Z+b/1YJlE7+cWRdq2wn8qwoNaT3tP uCcPs2GRd/XeI9ugOtiT/TRUyiQ61vyKgWGDyjd6qWRfsRR0uU552qVynrA4pQ== From: Shuwei Wu DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mailbox.org; s=mail20150812; t=1775807979; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=T2dY7nUbucCLtbQPyesJbvvM8gyBSryaljiV7Vdh9ew=; b=rAWWtWWlvk/gqQBvVd2+IhyqURwuExA7cfgqRYWARoqmJHzmkNxUfOGEvWtttwzAqfhdIP aXucifJADXEvEBlzV/J6zsu3Yh5LzT9B7OdMT49V3OlczPs8HcP7InaptqXm1HxGx6XySc Zs0H1UlEJsNmCwmd1WX3n/wb9Ttup27a0OEKBBcZRTbOBGZIE0b2FLLMlXSxrGTcu1cuSc bkPHMxVj723HRPb9ScxlheUr+rjMMs28k3FUWNpn7D7mO4P2RlQA4TV/lzr7N8Nq5kl1Qv /R+vZKW6o3wi+Ee8kTxFjRG/ETLmx35L7rovcPgYLipY3ZOzSPzpooMNnzvSnQ== Date: Fri, 10 Apr 2026 15:58:22 +0800 Subject: [PATCH v2 1/2] cpufreq: dt-platdev: Add SpacemiT K1 SoC to the allowlist Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260410-shadow-deps-v2-1-4e16b8c0f60e@mailbox.org> References: <20260410-shadow-deps-v2-0-4e16b8c0f60e@mailbox.org> In-Reply-To: <20260410-shadow-deps-v2-0-4e16b8c0f60e@mailbox.org> To: "Rafael J. Wysocki" , Viresh Kumar , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Yixun Lan , Yixun Lan Cc: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, devicetree@vger.kernel.org, Shuwei Wu X-Developer-Signature: v=1; a=ed25519-sha256; t=1775807959; l=808; i=shuwei.wu@mailbox.org; s=20251125; h=from:subject:message-id; bh=tv1SteH5+qLSYwGgTDPHiMVefHL7DAGC9ZjSkpHF5uw=; b=qqGyTe4fFVq3lwPI4KGuZozSKJpFe640d8ae4OBo64XxZLwq54SV6SEqqCDR1ny2RqhgERhWO 4gjknvRMuJqCd7MFYCps1bU18K3RuRQipYSoseKs4uY9Z8pxwLURLpT X-Developer-Key: i=shuwei.wu@mailbox.org; a=ed25519; pk=qZs6i2UZnXkmjUrwO5HJxcfpCvgSNrR4dcU5cjtfTSk= X-MBO-RS-META: pcg4fbn8c83pr3iyabuhitcaqoudsmqs X-MBO-RS-ID: 686342cdb22240db965 The SpacemiT K1 SoC uses standard device tree based CPU frequency scaling. Add it to the allowlist to instantiate the cpufreq-dt driver. Signed-off-by: Shuwei Wu --- drivers/cpufreq/cpufreq-dt-platdev.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq= -dt-platdev.c index 25fd3b191b7e..31a64739df25 100644 --- a/drivers/cpufreq/cpufreq-dt-platdev.c +++ b/drivers/cpufreq/cpufreq-dt-platdev.c @@ -81,6 +81,7 @@ static const struct of_device_id allowlist[] __initconst = =3D { { .have_governor_per_policy =3D true, }, }, =20 + { .compatible =3D "spacemit,k1", }, { .compatible =3D "st-ericsson,u8500", }, { .compatible =3D "st-ericsson,u8540", }, { .compatible =3D "st-ericsson,u9500", }, --=20 2.53.0 From nobody Mon Apr 13 07:45:35 2026 Received: from mout-p-202.mailbox.org (mout-p-202.mailbox.org [80.241.56.172]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 80BF53A75A6; Fri, 10 Apr 2026 07:59:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=80.241.56.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775808000; cv=none; b=XL7w3lz4Zi+AftQ1TTMKY/+w4kADcZrkXmqfpAcELCVxflgnkregUWDYLLsM9+OG3WiMAT/oaF6yBofYRf/AHM/vm3cG/HdP/Ya25kHxpbXhBKCtpJEamSEw/FJ8+kd2NkWV5L4nfRXiAPuZ2cnYUFyUtby7m7ZfNFdxdd3dnBo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775808000; c=relaxed/simple; bh=0VUX7RdGqDoXNiMwU2EZr3QON0J9hCZx8fbGCBgiJcs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=hBRnGjVGpbW5eddbMjtwjszVaFVgbE5DqlJBdcv77BCAqZRHsxFBa7e1i2vjhKnPEzp7pfwW+gfeByByIMJQQ0qGQIVZJWz3KwuLDDcL7HhM2AsdDREu0kixwwfv/6QCD7WRRRDZZ64uvxAuqfO1h5XmDjF5bzJnG8uyyEORV90= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=mailbox.org; spf=pass smtp.mailfrom=mailbox.org; dkim=pass (2048-bit key) header.d=mailbox.org header.i=@mailbox.org header.b=rPjx/5mu; dkim=pass (2048-bit key) header.d=mailbox.org header.i=@mailbox.org header.b=kTvbSN4Q; arc=none smtp.client-ip=80.241.56.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=mailbox.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mailbox.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=mailbox.org header.i=@mailbox.org header.b="rPjx/5mu"; dkim=pass (2048-bit key) header.d=mailbox.org header.i=@mailbox.org header.b="kTvbSN4Q" Received: from smtp1.mailbox.org (smtp1.mailbox.org [10.196.197.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mout-p-202.mailbox.org (Postfix) with ESMTPS id 4fsTjf1fNtz9tnV; Fri, 10 Apr 2026 09:59:50 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mailbox.org; s=mail20150812; t=1775807990; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=C119NIzcOGxwxwzIdJOwlvrD0/jfXj7l51z91Pjq1S8=; b=rPjx/5muFQBLOxM3vdadLL8JZjnkbBY2dZKheizcEhT559SrwDrMSoQd0GKXmf4mOI/GI4 FE78OHWj4iRKq0YbJTyMcM2sWE1K1r4fHZhTW94dWE9YyeCD6uFRaTqF8GByV4SAI4qvcx d5k8nn8UWJaCRBhyP9TBYCSCvQLJ1a6f4Tf6yJoHFZgcCJGksw9KbpwoueR8OZje2LmLAb ag/Xh4PIXTXcZ4dM45RAzNqtscNzNRPmJQYwK73G0akvBtXktNuORQWuMtkQHVTOKDn6XX p+lsh9hBpdui/50yFGfQWgrOS6q5Y0AmD795WGQG5ltxvId3EIeJW7eE4bPojQ== From: Shuwei Wu DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mailbox.org; s=mail20150812; t=1775807988; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=C119NIzcOGxwxwzIdJOwlvrD0/jfXj7l51z91Pjq1S8=; b=kTvbSN4QFgbF9q6zd/+MBOE0VeBlitVZ8nhDfTQVzMRTpSI+aVvgZplEaXnpCa3PkO3Rf4 ZXgRVPVkcvo9gk6hNRcNciT4En8sw4UFry7INyPjZUZu7tr9MTjKyVCErOJ9kqnbn8itut pwBwYN1SGfELGmM8B0zaDblk/yOyefscDmhu4OF7lEyDft9fQ0G+iqr9FQyqiR2Fve3v88 fg2pPmhdL7qxxiE5MFq5314a5Ql8i3qQmXuyIz+w5Kmu097RfBPYg6TqYjrjik9SlU3eGU m/1MiAbETmmlJqfz7d+Oz7FLb72pUtFSwkXrBYVsyA9xf9wZNU5MUQZVZiGF6Q== Date: Fri, 10 Apr 2026 15:58:23 +0800 Subject: [PATCH v2 2/2] riscv: dts: spacemit: Add cpu scaling for K1 SoC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260410-shadow-deps-v2-2-4e16b8c0f60e@mailbox.org> References: <20260410-shadow-deps-v2-0-4e16b8c0f60e@mailbox.org> In-Reply-To: <20260410-shadow-deps-v2-0-4e16b8c0f60e@mailbox.org> To: "Rafael J. Wysocki" , Viresh Kumar , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Yixun Lan , Yixun Lan Cc: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, devicetree@vger.kernel.org, Shuwei Wu X-Developer-Signature: v=1; a=ed25519-sha256; t=1775807959; l=8034; i=shuwei.wu@mailbox.org; s=20251125; h=from:subject:message-id; bh=0VUX7RdGqDoXNiMwU2EZr3QON0J9hCZx8fbGCBgiJcs=; b=3tq5OGveOn8/5bf+tMiV4unxU6gVl3E8eKnwcx6TihxWp0vNd9WfvilcqiQO3ihts5bDqO+GG a5dNX7PNi/BCyPQ6MymUTD+tm+hj/K8VkVCQyEJCzOo9vCMOogmHl0q X-Developer-Key: i=shuwei.wu@mailbox.org; a=ed25519; pk=qZs6i2UZnXkmjUrwO5HJxcfpCvgSNrR4dcU5cjtfTSk= X-MBO-RS-META: 9jff3fkmqxjiun45qgappn1fu8s6jp3q X-MBO-RS-ID: 14cc6a5e871f3b5b420 Add Operating Performance Points (OPP) tables and CPU clock properties for the two clusters in the SpacemiT K1 SoC. Also assign the CPU power supply (cpu-supply) for the Banana Pi BPI-F3 board to fully enable CPU DVFS. Signed-off-by: Shuwei Wu --- Changes in v2: - Add k1-opp.dtsi with OPP tables for both CPU clusters - Assign CPU supplies and include OPP table for Banana Pi BPI-F3 --- arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 35 +++++++- arch/riscv/boot/dts/spacemit/k1-opp.dtsi | 105 ++++++++++++++++++++= ++++ arch/riscv/boot/dts/spacemit/k1.dtsi | 8 ++ 3 files changed, 147 insertions(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/b= oot/dts/spacemit/k1-bananapi-f3.dts index 444c3b1e6f44..3780593f610d 100644 --- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts @@ -5,6 +5,7 @@ =20 #include "k1.dtsi" #include "k1-pinctrl.dtsi" +#include "k1-opp.dtsi" =20 / { model =3D "Banana Pi BPI-F3"; @@ -86,6 +87,38 @@ &combo_phy { status =3D "okay"; }; =20 +&cpu_0 { + cpu-supply =3D <&buck1_3v45>; +}; + +&cpu_1 { + cpu-supply =3D <&buck1_3v45>; +}; + +&cpu_2 { + cpu-supply =3D <&buck1_3v45>; +}; + +&cpu_3 { + cpu-supply =3D <&buck1_3v45>; +}; + +&cpu_4 { + cpu-supply =3D <&buck1_3v45>; +}; + +&cpu_5 { + cpu-supply =3D <&buck1_3v45>; +}; + +&cpu_6 { + cpu-supply =3D <&buck1_3v45>; +}; + +&cpu_7 { + cpu-supply =3D <&buck1_3v45>; +}; + &emmc { bus-width =3D <8>; mmc-hs400-1_8v; @@ -201,7 +234,7 @@ pmic@41 { dldoin2-supply =3D <&buck5>; =20 regulators { - buck1 { + buck1_3v45: buck1 { regulator-min-microvolt =3D <500000>; regulator-max-microvolt =3D <3450000>; regulator-ramp-delay =3D <5000>; diff --git a/arch/riscv/boot/dts/spacemit/k1-opp.dtsi b/arch/riscv/boot/dts= /spacemit/k1-opp.dtsi new file mode 100644 index 000000000000..768ae390686d --- /dev/null +++ b/arch/riscv/boot/dts/spacemit/k1-opp.dtsi @@ -0,0 +1,105 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/ { + cluster0_opp_table: opp-table-cluster0 { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-614400000 { + opp-hz =3D /bits/ 64 <614400000>; + opp-microvolt =3D <950000>; + clock-latency-ns =3D <200000>; + }; + + opp-819000000 { + opp-hz =3D /bits/ 64 <819000000>; + opp-microvolt =3D <950000>; + clock-latency-ns =3D <200000>; + }; + + opp-1000000000 { + opp-hz =3D /bits/ 64 <1000000000>; + opp-microvolt =3D <950000>; + clock-latency-ns =3D <200000>; + }; + + opp-1228800000 { + opp-hz =3D /bits/ 64 <1228800000>; + opp-microvolt =3D <950000>; + clock-latency-ns =3D <200000>; + }; + + opp-1600000000 { + opp-hz =3D /bits/ 64 <1600000000>; + opp-microvolt =3D <1050000>; + clock-latency-ns =3D <200000>; + }; + }; + + cluster1_opp_table: opp-table-cluster1 { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-614400000 { + opp-hz =3D /bits/ 64 <614400000>; + opp-microvolt =3D <950000>; + clock-latency-ns =3D <200000>; + }; + + opp-819000000 { + opp-hz =3D /bits/ 64 <819000000>; + opp-microvolt =3D <950000>; + clock-latency-ns =3D <200000>; + }; + + opp-1000000000 { + opp-hz =3D /bits/ 64 <1000000000>; + opp-microvolt =3D <950000>; + clock-latency-ns =3D <200000>; + }; + + opp-1228800000 { + opp-hz =3D /bits/ 64 <1228800000>; + opp-microvolt =3D <950000>; + clock-latency-ns =3D <200000>; + }; + + opp-1600000000 { + opp-hz =3D /bits/ 64 <1600000000>; + opp-microvolt =3D <1050000>; + clock-latency-ns =3D <200000>; + }; + }; +}; + +&cpu_0 { + operating-points-v2 =3D <&cluster0_opp_table>; +}; + +&cpu_1 { + operating-points-v2 =3D <&cluster0_opp_table>; +}; + +&cpu_2 { + operating-points-v2 =3D <&cluster0_opp_table>; +}; + +&cpu_3 { + operating-points-v2 =3D <&cluster0_opp_table>; +}; + +&cpu_4 { + operating-points-v2 =3D <&cluster1_opp_table>; +}; + +&cpu_5 { + operating-points-v2 =3D <&cluster1_opp_table>; +}; + +&cpu_6 { + operating-points-v2 =3D <&cluster1_opp_table>; +}; + +&cpu_7 { + operating-points-v2 =3D <&cluster1_opp_table>; +}; diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spa= cemit/k1.dtsi index 529ec68e9c23..bdd109b81730 100644 --- a/arch/riscv/boot/dts/spacemit/k1.dtsi +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi @@ -54,6 +54,7 @@ cpu_0: cpu@0 { compatible =3D "spacemit,x60", "riscv"; device_type =3D "cpu"; reg =3D <0>; + clocks =3D <&syscon_apmu CLK_CPU_C0_CORE>; riscv,isa =3D "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zi= fencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_sv= inval_svnapot_svpbmt"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "b", "v", "zicbo= m", @@ -84,6 +85,7 @@ cpu_1: cpu@1 { compatible =3D "spacemit,x60", "riscv"; device_type =3D "cpu"; reg =3D <1>; + clocks =3D <&syscon_apmu CLK_CPU_C0_CORE>; riscv,isa =3D "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zi= fencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_sv= inval_svnapot_svpbmt"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "b", "v", "zicbo= m", @@ -114,6 +116,7 @@ cpu_2: cpu@2 { compatible =3D "spacemit,x60", "riscv"; device_type =3D "cpu"; reg =3D <2>; + clocks =3D <&syscon_apmu CLK_CPU_C0_CORE>; riscv,isa =3D "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zi= fencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_sv= inval_svnapot_svpbmt"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "b", "v", "zicbo= m", @@ -144,6 +147,7 @@ cpu_3: cpu@3 { compatible =3D "spacemit,x60", "riscv"; device_type =3D "cpu"; reg =3D <3>; + clocks =3D <&syscon_apmu CLK_CPU_C0_CORE>; riscv,isa =3D "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zi= fencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_sv= inval_svnapot_svpbmt"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "b", "v", "zicbo= m", @@ -174,6 +178,7 @@ cpu_4: cpu@4 { compatible =3D "spacemit,x60", "riscv"; device_type =3D "cpu"; reg =3D <4>; + clocks =3D <&syscon_apmu CLK_CPU_C1_CORE>; riscv,isa =3D "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zi= fencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_sv= inval_svnapot_svpbmt"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "b", "v", "zicbo= m", @@ -204,6 +209,7 @@ cpu_5: cpu@5 { compatible =3D "spacemit,x60", "riscv"; device_type =3D "cpu"; reg =3D <5>; + clocks =3D <&syscon_apmu CLK_CPU_C1_CORE>; riscv,isa =3D "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zi= fencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_sv= inval_svnapot_svpbmt"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "b", "v", "zicbo= m", @@ -234,6 +240,7 @@ cpu_6: cpu@6 { compatible =3D "spacemit,x60", "riscv"; device_type =3D "cpu"; reg =3D <6>; + clocks =3D <&syscon_apmu CLK_CPU_C1_CORE>; riscv,isa =3D "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zi= fencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_sv= inval_svnapot_svpbmt"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "b", "v", "zicbo= m", @@ -264,6 +271,7 @@ cpu_7: cpu@7 { compatible =3D "spacemit,x60", "riscv"; device_type =3D "cpu"; reg =3D <7>; + clocks =3D <&syscon_apmu CLK_CPU_C1_CORE>; riscv,isa =3D "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zi= fencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_sv= inval_svnapot_svpbmt"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "b", "v", "zicbo= m", --=20 2.53.0