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[129.46.232.65]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-8ac84cb135fsm19223386d6.38.2026.04.10.02.33.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Apr 2026 02:33:58 -0700 (PDT) From: Yongxing Mou Date: Fri, 10 Apr 2026 17:33:36 +0800 Subject: [PATCH v4 01/39] drm/msm/dp: remove cached drm_edid from panel Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260410-msm-dp-mst-v4-1-b20518dea8de@oss.qualcomm.com> References: <20260410-msm-dp-mst-v4-0-b20518dea8de@oss.qualcomm.com> In-Reply-To: <20260410-msm-dp-mst-v4-0-b20518dea8de@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Jessica Zhang Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Yongxing Mou X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1775813628; l=8935; i=yongxing.mou@oss.qualcomm.com; s=20250910; h=from:subject:message-id; bh=uZfqkKsyUuvhDJEMiuMHtPECSA2HOV7I6DmlDJNOZKU=; b=91kwcb+pVceGCT+BXif9ewyCmuomE5R+Bm5lwh4dd2WTN7KEd7DlCtm9Ac15c9VpVBlx+gesc wEG1PwqTFUYDj6HOpApvzyXIl515UCuMeD4AC8b17kAUZP+hXy3msM7 X-Developer-Key: i=yongxing.mou@oss.qualcomm.com; a=ed25519; pk=rAy5J1eP+V7OXqH5FJ7ngMCtUrnHhut30ZTldOj52UM= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDEwMDA4OCBTYWx0ZWRfX21SSptpLlvVy 2XqPDokZxrpgID5sFBfryk36PWUgugYVHtnXQvSivTN7I6gct0U8T+AQuOw446kt0Ydmb85jH/V HHgahj7VnhDAm8+Gi28ikCiYVCLgTgur4pTF3WJ3gQiJfUHw9LkrUKumQ6JDFc6CeSkk8l2ydAo oiyw0g0byYnfwl4nn5IFik5C6jqqBzrXeNhlo42N6NS9Z16p08XbVb3JYNCnclYWvQJAlRyUrOS BM2kDfciy1JyJqVOCoPEYwpdXbxtIo/KbMFXrDlHYSn56vQYu/EhbcAUGZd+1czbHJFSha7v9D/ VbmUItusQyaBCA8GRC2nt0H3lX/1Set8RHA9yLDXEyialpK1ZIDNkgdb7LJi1j8FYa9x2OzPGMv 0FEGZxGcQPsBLCshpyTGO84wQ3eXlRkiO4BmDjk3gJWijf1QDSBZ2G5B1LigiMZQLp+07K7fdbe jDqkol7dWXLAUPGwDuw== X-Authority-Analysis: v=2.4 cv=eOcjSnp1 c=1 sm=1 tr=0 ts=69d8c407 cx=c_pps a=7E5Bxpl4vBhpaufnMqZlrw==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=EUspDBNiAAAA:8 a=Jn5Zs6sXaE638rALQFgA:9 a=QEXdDO2ut3YA:10 a=pJ04lnu7RYOZP9TFuWaZ:22 X-Proofpoint-GUID: 4ek0MD9ynwNSKuMfT107GBInj7PKuin0 X-Proofpoint-ORIG-GUID: 4ek0MD9ynwNSKuMfT107GBInj7PKuin0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-10_03,2026-04-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 adultscore=0 bulkscore=0 suspectscore=0 phishscore=0 impostorscore=0 lowpriorityscore=0 clxscore=1015 priorityscore=1501 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604010000 definitions=main-2604100088 The cached drm_edid seems unnecessary here. Use the drm_edid pointer directly in the plug stage instead of caching it. Remove the cached drm_edid and the corresponding oneliner to simplify the code. Signed-off-by: Yongxing Mou --- drivers/gpu/drm/msm/dp/dp_display.c | 27 +++++++++++------- drivers/gpu/drm/msm/dp/dp_panel.c | 57 ++++-----------------------------= ---- drivers/gpu/drm/msm/dp/dp_panel.h | 13 +++------ 3 files changed, 26 insertions(+), 71 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index 5c6a24ec140d..e28cc1bbb5b1 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -268,6 +268,7 @@ static int msm_dp_display_process_hpd_high(struct msm_d= p_display_private *dp) const struct drm_display_info *info =3D &connector->display_info; int rc =3D 0; u8 dpcd[DP_RECEIVER_CAP_SIZE]; + const struct drm_edid *drm_edid; =20 rc =3D drm_dp_read_dpcd_caps(dp->aux, dpcd); if (rc) @@ -275,10 +276,20 @@ static int msm_dp_display_process_hpd_high(struct msm= _dp_display_private *dp) =20 dp->link->lttpr_count =3D msm_dp_display_lttpr_init(dp, dpcd); =20 - rc =3D msm_dp_panel_read_sink_caps(dp->panel, connector); + rc =3D msm_dp_panel_read_link_caps(dp->panel, connector); if (rc) goto end; =20 + drm_edid =3D drm_edid_read_ddc(connector, &dp->aux->ddc); + drm_edid_connector_update(connector, drm_edid); + + if (!drm_edid) { + DRM_ERROR("panel edid read failed\n"); + /* check edid read fail is due to unplug */ + if (!msm_dp_aux_is_link_connected(dp->aux)) + return -ETIMEDOUT; + } + msm_dp_link_process_request(dp->link); =20 if (!dp->msm_dp_display.is_edp) @@ -290,7 +301,7 @@ static int msm_dp_display_process_hpd_high(struct msm_d= p_display_private *dp) dp->msm_dp_display.psr_supported =3D dp->panel->psr_cap.version && psr_en= abled; =20 dp->audio_supported =3D info->has_audio; - msm_dp_panel_handle_sink_request(dp->panel); + msm_dp_panel_handle_sink_request(dp->panel, drm_edid); =20 /* * set sink to normal operation mode -- D0 @@ -449,7 +460,7 @@ static int msm_dp_hpd_unplug_handle(struct msm_dp_displ= ay_private *dp) =20 /* Don't forget modes for eDP */ if (!dp->msm_dp_display.is_edp) - msm_dp_panel_unplugged(dp->panel, dp->msm_dp_display.connector); + drm_edid_connector_update(dp->msm_dp_display.connector, NULL); =20 /* triggered by irq_hdp with sink_count =3D 0 */ if (dp->link->sink_count =3D=3D 0) @@ -512,7 +523,6 @@ static int msm_dp_irq_hpd_handle(struct msm_dp_display_= private *dp) static void msm_dp_display_deinit_sub_modules(struct msm_dp_display_privat= e *dp) { msm_dp_audio_put(dp->audio); - msm_dp_panel_put(dp->panel); msm_dp_aux_put(dp->aux); } =20 @@ -563,7 +573,7 @@ static int msm_dp_init_sub_modules(struct msm_dp_displa= y_private *dp) rc =3D PTR_ERR(dp->ctrl); DRM_ERROR("failed to initialize ctrl, rc =3D %d\n", rc); dp->ctrl =3D NULL; - goto error_ctrl; + goto error_link; } =20 dp->audio =3D msm_dp_audio_get(dp->msm_dp_display.pdev, dp->link_base); @@ -571,13 +581,11 @@ static int msm_dp_init_sub_modules(struct msm_dp_disp= lay_private *dp) rc =3D PTR_ERR(dp->audio); pr_err("failed to initialize audio, rc =3D %d\n", rc); dp->audio =3D NULL; - goto error_ctrl; + goto error_link; } =20 return rc; =20 -error_ctrl: - msm_dp_panel_put(dp->panel); error_link: msm_dp_aux_put(dp->aux); error: @@ -741,8 +749,7 @@ int msm_dp_display_get_modes(struct msm_dp *dp) =20 msm_dp_display =3D container_of(dp, struct msm_dp_display_private, msm_dp= _display); =20 - return msm_dp_panel_get_modes(msm_dp_display->panel, - dp->connector); + return drm_edid_connector_add_modes(msm_dp_display->panel->connector); } =20 bool msm_dp_display_check_video_test(struct msm_dp *dp) diff --git a/drivers/gpu/drm/msm/dp/dp_panel.c b/drivers/gpu/drm/msm/dp/dp_= panel.c index 6bb021820d7c..bde4a772d22c 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.c +++ b/drivers/gpu/drm/msm/dp/dp_panel.c @@ -232,8 +232,8 @@ static u32 msm_dp_panel_get_supported_bpp(struct msm_dp= _panel *msm_dp_panel, return min_supported_bpp; } =20 -int msm_dp_panel_read_sink_caps(struct msm_dp_panel *msm_dp_panel, - struct drm_connector *connector) +int msm_dp_panel_read_link_caps(struct msm_dp_panel *msm_dp_panel, + struct drm_connector *connector) { int rc, bw_code; int count; @@ -271,36 +271,9 @@ int msm_dp_panel_read_sink_caps(struct msm_dp_panel *m= sm_dp_panel, =20 rc =3D drm_dp_read_downstream_info(panel->aux, msm_dp_panel->dpcd, msm_dp_panel->downstream_ports); - if (rc) - return rc; - - drm_edid_free(msm_dp_panel->drm_edid); - - msm_dp_panel->drm_edid =3D drm_edid_read_ddc(connector, &panel->aux->ddc); - - drm_edid_connector_update(connector, msm_dp_panel->drm_edid); - - if (!msm_dp_panel->drm_edid) { - DRM_ERROR("panel edid read failed\n"); - /* check edid read fail is due to unplug */ - if (!msm_dp_aux_is_link_connected(panel->aux)) { - rc =3D -ETIMEDOUT; - goto end; - } - } - -end: return rc; } =20 -void msm_dp_panel_unplugged(struct msm_dp_panel *msm_dp_panel, - struct drm_connector *connector) -{ - drm_edid_connector_update(connector, NULL); - drm_edid_free(msm_dp_panel->drm_edid); - msm_dp_panel->drm_edid =3D NULL; -} - u32 msm_dp_panel_get_mode_bpp(struct msm_dp_panel *msm_dp_panel, u32 mode_edid_bpp, u32 mode_pclk_khz) { @@ -324,20 +297,6 @@ u32 msm_dp_panel_get_mode_bpp(struct msm_dp_panel *msm= _dp_panel, return bpp; } =20 -int msm_dp_panel_get_modes(struct msm_dp_panel *msm_dp_panel, - struct drm_connector *connector) -{ - if (!msm_dp_panel) { - DRM_ERROR("invalid input\n"); - return -EINVAL; - } - - if (msm_dp_panel->drm_edid) - return drm_edid_connector_add_modes(connector); - - return 0; -} - static u8 msm_dp_panel_get_edid_checksum(const struct edid *edid) { edid +=3D edid->extensions; @@ -345,7 +304,8 @@ static u8 msm_dp_panel_get_edid_checksum(const struct e= did *edid) return edid->checksum; } =20 -void msm_dp_panel_handle_sink_request(struct msm_dp_panel *msm_dp_panel) +void msm_dp_panel_handle_sink_request(struct msm_dp_panel *msm_dp_panel, + const struct drm_edid *drm_edid) { struct msm_dp_panel_private *panel; =20 @@ -358,7 +318,7 @@ void msm_dp_panel_handle_sink_request(struct msm_dp_pan= el *msm_dp_panel) =20 if (panel->link->sink_request & DP_TEST_LINK_EDID_READ) { /* FIXME: get rid of drm_edid_raw() */ - const struct edid *edid =3D drm_edid_raw(msm_dp_panel->drm_edid); + const struct edid *edid =3D drm_edid_raw(drm_edid); u8 checksum; =20 if (edid) @@ -755,10 +715,3 @@ struct msm_dp_panel *msm_dp_panel_get(struct device *d= ev, struct drm_dp_aux *aux return msm_dp_panel; } =20 -void msm_dp_panel_put(struct msm_dp_panel *msm_dp_panel) -{ - if (!msm_dp_panel) - return; - - drm_edid_free(msm_dp_panel->drm_edid); -} diff --git a/drivers/gpu/drm/msm/dp/dp_panel.h b/drivers/gpu/drm/msm/dp/dp_= panel.h index 9173e90a5053..53b7b4463551 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.h +++ b/drivers/gpu/drm/msm/dp/dp_panel.h @@ -33,7 +33,6 @@ struct msm_dp_panel { u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS]; =20 struct msm_dp_link_info link_info; - const struct drm_edid *drm_edid; struct drm_connector *connector; struct msm_dp_display_mode msm_dp_mode; struct msm_dp_panel_psr psr_cap; @@ -47,15 +46,12 @@ struct msm_dp_panel { int msm_dp_panel_init_panel_info(struct msm_dp_panel *msm_dp_panel); int msm_dp_panel_deinit(struct msm_dp_panel *msm_dp_panel); int msm_dp_panel_timing_cfg(struct msm_dp_panel *msm_dp_panel, bool wide_b= us_en); -int msm_dp_panel_read_sink_caps(struct msm_dp_panel *msm_dp_panel, - struct drm_connector *connector); -void msm_dp_panel_unplugged(struct msm_dp_panel *msm_dp_panel, - struct drm_connector *connector); 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Remove it and move all mode setup logic to .atomic_enable(), where the adjusted_mode is available from the atomic CRTC state. Drop msm_dp_mode from msm_dp_display_private and store the mode directly in the panel, as it was only used as a temporary cache. Both changes are limited to msm_dp_display_set_mode and are kept in a single patch. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_display.c | 81 ++++++++++++++-------------------= ---- drivers/gpu/drm/msm/dp/dp_drm.c | 2 - drivers/gpu/drm/msm/dp/dp_drm.h | 3 -- 3 files changed, 31 insertions(+), 55 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index e28cc1bbb5b1..e9f0b96c3ebd 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -63,7 +63,6 @@ struct msm_dp_display_private { struct msm_dp_panel *panel; struct msm_dp_ctrl *ctrl; =20 - struct msm_dp_display_mode msm_dp_mode; struct msm_dp msm_dp_display; =20 /* wait for audio signaling */ @@ -593,16 +592,33 @@ static int msm_dp_init_sub_modules(struct msm_dp_disp= lay_private *dp) } =20 static int msm_dp_display_set_mode(struct msm_dp *msm_dp_display, - struct msm_dp_display_mode *mode) + const struct drm_display_mode *adjusted_mode, + struct msm_dp_panel *msm_dp_panel) { struct msm_dp_display_private *dp; + u32 bpp; =20 dp =3D container_of(msm_dp_display, struct msm_dp_display_private, msm_dp= _display); =20 - drm_mode_copy(&dp->panel->msm_dp_mode.drm_mode, &mode->drm_mode); - dp->panel->msm_dp_mode.bpp =3D mode->bpp; - dp->panel->msm_dp_mode.out_fmt_is_yuv_420 =3D mode->out_fmt_is_yuv_420; - msm_dp_panel_init_panel_info(dp->panel); + drm_mode_copy(&msm_dp_panel->msm_dp_mode.drm_mode, adjusted_mode); + if (msm_dp_display_check_video_test(msm_dp_display)) + bpp =3D msm_dp_display_get_test_bpp(msm_dp_display); + else + bpp =3D msm_dp_panel->connector->display_info.bpc * 3; + + msm_dp_panel->msm_dp_mode.bpp =3D bpp ? bpp : 24; /* Default bpp */ + msm_dp_panel->msm_dp_mode.v_active_low =3D + !!(adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC); + msm_dp_panel->msm_dp_mode.h_active_low =3D + !!(adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC); + msm_dp_panel->msm_dp_mode.out_fmt_is_yuv_420 =3D + drm_mode_is_420_only(&msm_dp_panel->connector->display_info, adjusted_mo= de) && + msm_dp_panel->vsc_sdp_supported; + msm_dp_panel_init_panel_info(msm_dp_panel); + + /* populate wide_bus_support to different layers */ + dp->ctrl->wide_bus_en =3D + msm_dp_panel->msm_dp_mode.out_fmt_is_yuv_420 ? false : dp->wide_bus_supp= orted; return 0; } =20 @@ -1305,7 +1321,7 @@ bool msm_dp_wide_bus_available(const struct msm_dp *m= sm_dp_display) =20 dp =3D container_of(msm_dp_display, struct msm_dp_display_private, msm_dp= _display); =20 - if (dp->msm_dp_mode.out_fmt_is_yuv_420) + if (dp->panel->msm_dp_mode.out_fmt_is_yuv_420) return false; =20 return dp->wide_bus_supported; @@ -1361,15 +1377,19 @@ void msm_dp_bridge_atomic_enable(struct drm_bridge = *drm_bridge, { struct msm_dp_bridge *msm_dp_bridge =3D to_dp_bridge(drm_bridge); struct msm_dp *dp =3D msm_dp_bridge->msm_dp_display; + struct drm_crtc *crtc; + struct drm_crtc_state *crtc_state; int rc =3D 0; struct msm_dp_display_private *msm_dp_display; bool force_link_train =3D false; =20 msm_dp_display =3D container_of(dp, struct msm_dp_display_private, msm_dp= _display); - if (!msm_dp_display->msm_dp_mode.drm_mode.clock) { - DRM_ERROR("invalid params\n"); + + crtc =3D drm_atomic_get_new_crtc_for_encoder(state, + drm_bridge->encoder); + if (!crtc) return; - } + crtc_state =3D drm_atomic_get_new_crtc_state(state, crtc); =20 if (dp->is_edp) msm_dp_hpd_plug_handle(msm_dp_display); @@ -1382,7 +1402,7 @@ void msm_dp_bridge_atomic_enable(struct drm_bridge *d= rm_bridge, if (msm_dp_display->link->sink_count =3D=3D 0) return; =20 - rc =3D msm_dp_display_set_mode(dp, &msm_dp_display->msm_dp_mode); + rc =3D msm_dp_display_set_mode(dp, &crtc_state->adjusted_mode, msm_dp_dis= play->panel); if (rc) { DRM_ERROR("Failed to perform a mode set, rc=3D%d\n", rc); return; @@ -1440,45 +1460,6 @@ void msm_dp_bridge_atomic_post_disable(struct drm_br= idge *drm_bridge, pm_runtime_put_sync(&dp->pdev->dev); } =20 -void msm_dp_bridge_mode_set(struct drm_bridge *drm_bridge, - const struct drm_display_mode *mode, - const struct drm_display_mode *adjusted_mode) -{ - struct msm_dp_bridge *msm_dp_bridge =3D to_dp_bridge(drm_bridge); - struct msm_dp *dp =3D msm_dp_bridge->msm_dp_display; - struct msm_dp_display_private *msm_dp_display; - struct msm_dp_panel *msm_dp_panel; - - msm_dp_display =3D container_of(dp, struct msm_dp_display_private, msm_dp= _display); - msm_dp_panel =3D msm_dp_display->panel; - - memset(&msm_dp_display->msm_dp_mode, 0x0, sizeof(struct msm_dp_display_mo= de)); - - if (msm_dp_display_check_video_test(dp)) - msm_dp_display->msm_dp_mode.bpp =3D msm_dp_display_get_test_bpp(dp); - else /* Default num_components per pixel =3D 3 */ - msm_dp_display->msm_dp_mode.bpp =3D dp->connector->display_info.bpc * 3; - - if (!msm_dp_display->msm_dp_mode.bpp) - msm_dp_display->msm_dp_mode.bpp =3D 24; /* Default bpp */ - - drm_mode_copy(&msm_dp_display->msm_dp_mode.drm_mode, adjusted_mode); - - msm_dp_display->msm_dp_mode.v_active_low =3D - !!(msm_dp_display->msm_dp_mode.drm_mode.flags & DRM_MODE_FLAG_NVSYNC); - - msm_dp_display->msm_dp_mode.h_active_low =3D - !!(msm_dp_display->msm_dp_mode.drm_mode.flags & DRM_MODE_FLAG_NHSYNC); - - msm_dp_display->msm_dp_mode.out_fmt_is_yuv_420 =3D - drm_mode_is_420_only(&dp->connector->display_info, adjusted_mode) && - msm_dp_panel->vsc_sdp_supported; - - /* populate wide_bus_support to different layers */ - msm_dp_display->ctrl->wide_bus_en =3D - msm_dp_display->msm_dp_mode.out_fmt_is_yuv_420 ? false : msm_dp_display-= >wide_bus_supported; -} - void msm_dp_bridge_hpd_enable(struct drm_bridge *bridge) { struct msm_dp_bridge *msm_dp_bridge =3D to_dp_bridge(bridge); diff --git a/drivers/gpu/drm/msm/dp/dp_drm.c b/drivers/gpu/drm/msm/dp/dp_dr= m.c index 8dc0dabd275c..af3d3e3a2d84 100644 --- a/drivers/gpu/drm/msm/dp/dp_drm.c +++ b/drivers/gpu/drm/msm/dp/dp_drm.c @@ -56,7 +56,6 @@ static const struct drm_bridge_funcs msm_dp_bridge_ops = =3D { .atomic_enable =3D msm_dp_bridge_atomic_enable, .atomic_disable =3D msm_dp_bridge_atomic_disable, .atomic_post_disable =3D msm_dp_bridge_atomic_post_disable, - .mode_set =3D msm_dp_bridge_mode_set, .mode_valid =3D msm_dp_bridge_mode_valid, .get_modes =3D msm_dp_bridge_get_modes, .detect =3D msm_dp_bridge_detect, @@ -233,7 +232,6 @@ static const struct drm_bridge_funcs msm_edp_bridge_ops= =3D { .atomic_enable =3D msm_edp_bridge_atomic_enable, .atomic_disable =3D msm_edp_bridge_atomic_disable, .atomic_post_disable =3D msm_edp_bridge_atomic_post_disable, - .mode_set =3D msm_dp_bridge_mode_set, .mode_valid =3D msm_edp_bridge_mode_valid, .atomic_reset =3D drm_atomic_helper_bridge_reset, .atomic_duplicate_state =3D drm_atomic_helper_bridge_duplicate_state, diff --git a/drivers/gpu/drm/msm/dp/dp_drm.h b/drivers/gpu/drm/msm/dp/dp_dr= m.h index 6c0426803d78..6d4cbb9f3918 100644 --- a/drivers/gpu/drm/msm/dp/dp_drm.h +++ b/drivers/gpu/drm/msm/dp/dp_drm.h @@ -36,9 +36,6 @@ void msm_dp_bridge_atomic_post_disable(struct drm_bridge = *drm_bridge, enum drm_mode_status msm_dp_bridge_mode_valid(struct drm_bridge *bridge, const struct drm_display_info *info, const struct drm_display_mode *mode); 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Split these two parts into prepare/enable APIs, to support MST bridges_enable insert the MST payloads funcs between enable stream_clks and program register. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 54 ++++++++++++------- drivers/gpu/drm/msm/dp/dp_ctrl.h | 3 +- drivers/gpu/drm/msm/dp/dp_display.c | 105 +++++++++++++++++++++++---------= ---- 3 files changed, 106 insertions(+), 56 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_c= trl.c index 3bb08c9a020e..0fd4a7b6d931 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -2472,27 +2472,19 @@ static void msm_dp_ctrl_config_msa(struct msm_dp_ct= rl_private *ctrl, msm_dp_write_link(ctrl, REG_DP_SOFTWARE_NVID, nvid); } =20 -int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl, bool force_link= _train) +int msm_dp_ctrl_prepare_stream_on(struct msm_dp_ctrl *msm_dp_ctrl, bool fo= rce_link_train) { int ret =3D 0; - bool mainlink_ready =3D false; struct msm_dp_ctrl_private *ctrl; - unsigned long pixel_rate; - unsigned long pixel_rate_orig; =20 if (!msm_dp_ctrl) return -EINVAL; =20 ctrl =3D container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctr= l); =20 - pixel_rate =3D pixel_rate_orig =3D ctrl->panel->msm_dp_mode.drm_mode.cloc= k; - - if (msm_dp_ctrl->wide_bus_en || ctrl->panel->msm_dp_mode.out_fmt_is_yuv_4= 20) - pixel_rate >>=3D 1; - - drm_dbg_dp(ctrl->drm_dev, "rate=3D%d, num_lanes=3D%d, pixel_rate=3D%lu\n", - ctrl->link->link_params.rate, - ctrl->link->link_params.num_lanes, pixel_rate); + drm_dbg_dp(ctrl->drm_dev, "rate=3D%d, num_lanes=3D%d\n", + ctrl->link->link_params.rate, + ctrl->link->link_params.num_lanes); =20 drm_dbg_dp(ctrl->drm_dev, "core_clk_on=3D%d link_clk_on=3D%d stream_clk_on=3D%d\n", @@ -2502,10 +2494,40 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_d= p_ctrl, bool force_link_train ret =3D msm_dp_ctrl_enable_mainlink_clocks(ctrl); if (ret) { DRM_ERROR("Failed to start link clocks. ret=3D%d\n", ret); - goto end; + return ret; } } =20 + if (force_link_train || !msm_dp_ctrl_channel_eq_ok(ctrl)) + msm_dp_ctrl_link_retrain(ctrl); + + /* stop txing train pattern to end link training */ + msm_dp_ctrl_clear_training_pattern(ctrl, DP_PHY_DPRX); + + return ret; +} + +int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl) +{ + int ret =3D 0; + bool mainlink_ready =3D false; + struct msm_dp_ctrl_private *ctrl; + unsigned long pixel_rate; + unsigned long pixel_rate_orig; + + if (!msm_dp_ctrl) + return -EINVAL; + + ctrl =3D container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctr= l); + + pixel_rate_orig =3D ctrl->panel->msm_dp_mode.drm_mode.clock; + pixel_rate =3D pixel_rate_orig; + + if (msm_dp_ctrl->wide_bus_en || ctrl->panel->msm_dp_mode.out_fmt_is_yuv_4= 20) + pixel_rate >>=3D 1; + + drm_dbg_dp(ctrl->drm_dev, "pixel_rate=3D%lu\n", pixel_rate); + ret =3D clk_set_rate(ctrl->pixel_clk, pixel_rate * 1000); if (ret) { DRM_ERROR("Failed to set pixel clock rate. ret=3D%d\n", ret); @@ -2523,12 +2545,6 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp= _ctrl, bool force_link_train ctrl->stream_clks_on =3D true; } =20 - if (force_link_train || !msm_dp_ctrl_channel_eq_ok(ctrl)) - msm_dp_ctrl_link_retrain(ctrl); - - /* stop txing train pattern to end link training */ - msm_dp_ctrl_clear_training_pattern(ctrl, DP_PHY_DPRX); - /* * Set up transfer unit values and set controller state to send * video. diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.h b/drivers/gpu/drm/msm/dp/dp_c= trl.h index f68bee62713f..1497f1a8fc2f 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.h +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.h @@ -17,7 +17,8 @@ struct msm_dp_ctrl { struct phy; =20 int msm_dp_ctrl_on_link(struct msm_dp_ctrl *msm_dp_ctrl); -int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl, bool force_link= _train); +int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl); +int msm_dp_ctrl_prepare_stream_on(struct msm_dp_ctrl *msm_dp_ctrl, bool fo= rce_link_train); void msm_dp_ctrl_off_link_stream(struct msm_dp_ctrl *msm_dp_ctrl); void msm_dp_ctrl_off(struct msm_dp_ctrl *msm_dp_ctrl); void msm_dp_ctrl_push_idle(struct msm_dp_ctrl *msm_dp_ctrl); diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index e9f0b96c3ebd..5ecbc83c3838 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -622,7 +622,40 @@ static int msm_dp_display_set_mode(struct msm_dp *msm_= dp_display, return 0; } =20 -static int msm_dp_display_enable(struct msm_dp_display_private *dp, bool f= orce_link_train) +static int msm_dp_display_prepare(struct msm_dp_display_private *dp) +{ + struct msm_dp *msm_dp_display =3D &dp->msm_dp_display; + int rc =3D 0; + bool force_link_train =3D false; + + drm_dbg_dp(dp->drm_dev, "sink_count=3D%d\n", dp->link->sink_count); + + if (msm_dp_display->is_edp) + msm_dp_hpd_plug_handle(dp); + + rc =3D pm_runtime_resume_and_get(&msm_dp_display->pdev->dev); + if (rc) { + DRM_ERROR("failed to pm_runtime_resume\n"); + return rc; + } + + if (dp->link->sink_count =3D=3D 0) + return rc; + + if (!msm_dp_display->power_on) { + msm_dp_display_host_phy_init(dp); + force_link_train =3D true; + } + + rc =3D msm_dp_ctrl_on_link(dp->ctrl); + if (rc) + DRM_ERROR("Failed link training (rc=3D%d)\n", rc); + // TODO: schedule drm_connector_set_link_status_property() + + return msm_dp_ctrl_prepare_stream_on(dp->ctrl, force_link_train); +} + +static int msm_dp_display_enable(struct msm_dp_display_private *dp) { int rc =3D 0; struct msm_dp *msm_dp_display =3D &dp->msm_dp_display; @@ -633,7 +666,7 @@ static int msm_dp_display_enable(struct msm_dp_display_= private *dp, bool force_l return 0; } =20 - rc =3D msm_dp_ctrl_on_stream(dp->ctrl, force_link_train); + rc =3D msm_dp_ctrl_on_stream(dp->ctrl); if (!rc) msm_dp_display->power_on =3D true; =20 @@ -663,13 +696,10 @@ static int msm_dp_display_post_enable(struct msm_dp *= msm_dp_display) return 0; } =20 -static int msm_dp_display_disable(struct msm_dp_display_private *dp) +static void msm_dp_display_audio_notify_disable(struct msm_dp_display_priv= ate *dp) { struct msm_dp *msm_dp_display =3D &dp->msm_dp_display; =20 - if (!msm_dp_display->power_on) - return 0; - /* wait only if audio was enabled */ if (msm_dp_display->audio_enabled) { /* signal the disconnect event */ @@ -680,6 +710,14 @@ static int msm_dp_display_disable(struct msm_dp_displa= y_private *dp) } =20 msm_dp_display->audio_enabled =3D false; +} + +static int msm_dp_display_disable(struct msm_dp_display_private *dp) +{ + struct msm_dp *msm_dp_display =3D &dp->msm_dp_display; + + if (!msm_dp_display->power_on) + return 0; =20 if (dp->link->sink_count =3D=3D 0) { /* @@ -1376,14 +1414,13 @@ void msm_dp_bridge_atomic_enable(struct drm_bridge = *drm_bridge, struct drm_atomic_state *state) { struct msm_dp_bridge *msm_dp_bridge =3D to_dp_bridge(drm_bridge); - struct msm_dp *dp =3D msm_dp_bridge->msm_dp_display; + struct msm_dp *msm_dp_display =3D msm_dp_bridge->msm_dp_display; struct drm_crtc *crtc; struct drm_crtc_state *crtc_state; int rc =3D 0; - struct msm_dp_display_private *msm_dp_display; - bool force_link_train =3D false; + struct msm_dp_display_private *dp; =20 - msm_dp_display =3D container_of(dp, struct msm_dp_display_private, msm_dp= _display); + dp =3D container_of(msm_dp_display, struct msm_dp_display_private, msm_dp= _display); =20 crtc =3D drm_atomic_get_new_crtc_for_encoder(state, drm_bridge->encoder); @@ -1391,42 +1428,29 @@ void msm_dp_bridge_atomic_enable(struct drm_bridge = *drm_bridge, return; crtc_state =3D drm_atomic_get_new_crtc_state(state, crtc); =20 - if (dp->is_edp) - msm_dp_hpd_plug_handle(msm_dp_display); - - if (pm_runtime_resume_and_get(&dp->pdev->dev)) { - DRM_ERROR("failed to pm_runtime_resume\n"); - return; - } - - if (msm_dp_display->link->sink_count =3D=3D 0) - return; - - rc =3D msm_dp_display_set_mode(dp, &crtc_state->adjusted_mode, msm_dp_dis= play->panel); + rc =3D msm_dp_display_set_mode(msm_dp_display, &crtc_state->adjusted_mode= , dp->panel); if (rc) { DRM_ERROR("Failed to perform a mode set, rc=3D%d\n", rc); return; } =20 - if (!dp->power_on) { - msm_dp_display_host_phy_init(msm_dp_display); - force_link_train =3D true; + rc =3D msm_dp_display_prepare(dp); + if (rc) { + DRM_ERROR("DP display prepare failed, rc=3D%d\n", rc); + return; } =20 - rc =3D msm_dp_ctrl_on_link(msm_dp_display->ctrl); + rc =3D msm_dp_display_enable(dp); if (rc) - DRM_ERROR("Failed link training (rc=3D%d)\n", rc); - // TODO: schedule drm_connector_set_link_status_property() + DRM_ERROR("DP display enable failed, rc=3D%d\n", rc); =20 - msm_dp_display_enable(msm_dp_display, force_link_train); - - rc =3D msm_dp_display_post_enable(dp); + rc =3D msm_dp_display_post_enable(msm_dp_display); if (rc) { DRM_ERROR("DP display post enable failed, rc=3D%d\n", rc); - msm_dp_display_disable(msm_dp_display); + msm_dp_display_disable(dp); } =20 - drm_dbg_dp(dp->drm_dev, "type=3D%d Done\n", dp->connector_type); + drm_dbg_dp(msm_dp_display->drm_dev, "type=3D%d Done\n", msm_dp_display->c= onnector_type); } =20 void msm_dp_bridge_atomic_disable(struct drm_bridge *drm_bridge, @@ -1441,6 +1465,15 @@ void msm_dp_bridge_atomic_disable(struct drm_bridge = *drm_bridge, msm_dp_ctrl_push_idle(msm_dp_display->ctrl); } =20 +static void msm_dp_display_unprepare(struct msm_dp_display_private *dp) +{ + struct msm_dp *msm_dp_display =3D &dp->msm_dp_display; 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[129.46.232.65]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-8ac84cb135fsm19223386d6.38.2026.04.10.02.34.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Apr 2026 02:34:13 -0700 (PDT) From: Yongxing Mou Date: Fri, 10 Apr 2026 17:33:39 +0800 Subject: [PATCH v4 04/39] drm/msm/dp: re-arrange dp_display_disable() into functional parts Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260410-msm-dp-mst-v4-4-b20518dea8de@oss.qualcomm.com> References: <20260410-msm-dp-mst-v4-0-b20518dea8de@oss.qualcomm.com> In-Reply-To: <20260410-msm-dp-mst-v4-0-b20518dea8de@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Jessica Zhang Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Yongxing Mou , Abhinav Kumar , Dmitry Baryshkov X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1775813628; l=3890; i=yongxing.mou@oss.qualcomm.com; s=20250910; h=from:subject:message-id; bh=jXQCAxCiXUJRF5Hy5TGXsy0zyup8wBHq7tf5RYhaBiU=; b=WGsTo1NHR/4bJtLAXFiYRnBHZTj9PqjbvGytlM2rfB5uHc5KVWe4B1JU8TM6JJaCmRKf6Haro NY/UjH39L99BndgMunlcShYVvNU/wAP5i0xUmW2OYB6CqGXjQY6e4I0 X-Developer-Key: i=yongxing.mou@oss.qualcomm.com; a=ed25519; pk=rAy5J1eP+V7OXqH5FJ7ngMCtUrnHhut30ZTldOj52UM= X-Proofpoint-GUID: 6P0cqjBke3QifABlEd5RFZEMVwBj66P8 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDEwMDA4OCBTYWx0ZWRfXxsYtx6JOo/sh 4OOjqwvJiWeK6oF4h1d9OZabQZqfYI0X9cn0/FREuLJ42iSsTDEt9hxXGoUF+yPLZ02qAxNm5V2 HBXZZBysn2MkuPStVCl/IEx2iKRjE8cEFSvHXcUjKk6y4RhUC+aOZr5VDB/xQcmZnW4VWDXE24c jDKgRD5/jumOmbzYtyPTTLv1zjnufU0PBwm8tlNG6jimqHpoCjR95lr0KtGNkKQKF0UaB5Wy33/ yWweE75wlN7RE32en1672HayfmUz7mmj3PpxD+VwdCT07+m+JUaQ2rq/YBREDcZVxMZ5vdX626u tDRwZzncqYA7JVA66cqThZTD70hu5dD3Zf94tCyvj6pG1zCj8AODkEwyXNPqITKSvwRgA8LDJG6 g2FfRnJ+iCygN4tUZ8/lyn97JOIAUtyLVkTi/ftKRw2kUu1Uks15ymhmg9i2tao8oojpn52JVa9 QUjeVzAZ32mcuCoZk7A== X-Proofpoint-ORIG-GUID: 6P0cqjBke3QifABlEd5RFZEMVwBj66P8 X-Authority-Analysis: v=2.4 cv=DslmPm/+ c=1 sm=1 tr=0 ts=69d8c416 cx=c_pps a=oc9J++0uMp73DTRD5QyR2A==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=We74lq4XQ-Qw3Vo_XYoA:9 a=QEXdDO2ut3YA:10 a=iYH6xdkBrDN1Jqds4HTS:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-10_03,2026-04-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 lowpriorityscore=0 suspectscore=0 adultscore=0 malwarescore=0 clxscore=1015 impostorscore=0 bulkscore=0 priorityscore=1501 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604010000 definitions=main-2604100088 From: Abhinav Kumar dp_display_disable() handles special case of when monitor is disconnected from the dongle while the dongle stays connected thereby needing a separate function dp_ctrl_off_link_stream() for this. However with a slight rework this can still be handled by keeping common paths same for regular and special case. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 19 +------------------ drivers/gpu/drm/msm/dp/dp_ctrl.h | 2 +- drivers/gpu/drm/msm/dp/dp_display.c | 10 +++++++++- 3 files changed, 11 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_c= trl.c index 0fd4a7b6d931..476346e3ac19 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -2576,7 +2576,7 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_= ctrl) return ret; } =20 -void msm_dp_ctrl_off_link_stream(struct msm_dp_ctrl *msm_dp_ctrl) +void msm_dp_ctrl_reinit_phy(struct msm_dp_ctrl *msm_dp_ctrl) { struct msm_dp_ctrl_private *ctrl; struct phy *phy; @@ -2584,23 +2584,6 @@ void msm_dp_ctrl_off_link_stream(struct msm_dp_ctrl = *msm_dp_ctrl) ctrl =3D container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctr= l); phy =3D ctrl->phy; =20 - msm_dp_panel_disable_vsc_sdp(ctrl->panel); - - /* set dongle to D3 (power off) mode */ - msm_dp_link_psm_config(ctrl->link, &ctrl->panel->link_info, true); - - msm_dp_ctrl_mainlink_disable(ctrl); - - if (ctrl->stream_clks_on) { - clk_disable_unprepare(ctrl->pixel_clk); - ctrl->stream_clks_on =3D false; - } - - dev_pm_opp_set_rate(ctrl->dev, 0); - msm_dp_ctrl_link_clk_disable(&ctrl->msm_dp_ctrl); - - phy_power_off(phy); - /* aux channel down, reinit phy */ phy_exit(phy); phy_init(phy); diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.h b/drivers/gpu/drm/msm/dp/dp_c= trl.h index 1497f1a8fc2f..5d615f50d13b 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.h +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.h @@ -19,7 +19,6 @@ struct phy; int msm_dp_ctrl_on_link(struct msm_dp_ctrl *msm_dp_ctrl); int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl); int msm_dp_ctrl_prepare_stream_on(struct msm_dp_ctrl *msm_dp_ctrl, bool fo= rce_link_train); -void msm_dp_ctrl_off_link_stream(struct msm_dp_ctrl *msm_dp_ctrl); void msm_dp_ctrl_off(struct msm_dp_ctrl *msm_dp_ctrl); void msm_dp_ctrl_push_idle(struct msm_dp_ctrl *msm_dp_ctrl); irqreturn_t msm_dp_ctrl_isr(struct msm_dp_ctrl *msm_dp_ctrl); @@ -46,4 +45,5 @@ void msm_dp_ctrl_core_clk_disable(struct msm_dp_ctrl *msm= _dp_ctrl); void msm_dp_ctrl_enable_irq(struct msm_dp_ctrl *msm_dp_ctrl); void msm_dp_ctrl_disable_irq(struct msm_dp_ctrl *msm_dp_ctrl); =20 +void msm_dp_ctrl_reinit_phy(struct msm_dp_ctrl *msm_dp_ctrl); #endif /* _DP_CTRL_H_ */ diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index 5ecbc83c3838..58c46d5ab4d8 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -719,12 +719,20 @@ static int msm_dp_display_disable(struct msm_dp_displ= ay_private *dp) if (!msm_dp_display->power_on) return 0; =20 + msm_dp_panel_disable_vsc_sdp(dp->panel); + + /* dongle is still connected but sinks are disconnected */ if (dp->link->sink_count =3D=3D 0) { /* * irq_hpd with sink_count =3D 0 * hdmi unplugged out of dongle */ - msm_dp_ctrl_off_link_stream(dp->ctrl); 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Currently, msm_dp_ctrl_config_ctrl() configures all of them together. Separates the configuration into link parts and streams part for support MST. Signed-off-by: Yongxing Mou --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 43 ++++++++++++++++++++++++++----------= ---- 1 file changed, 28 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_c= trl.c index 476346e3ac19..85315467b5d0 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -388,26 +388,41 @@ void msm_dp_ctrl_push_idle(struct msm_dp_ctrl *msm_dp= _ctrl) drm_dbg_dp(ctrl->drm_dev, "mainlink off\n"); } =20 -static void msm_dp_ctrl_config_ctrl(struct msm_dp_ctrl_private *ctrl) +static void msm_dp_ctrl_config_ctrl_streams(struct msm_dp_ctrl_private *ct= rl, + struct msm_dp_panel *msm_dp_panel) { u32 config =3D 0, tbd; + + config =3D msm_dp_read_link(ctrl, REG_DP_CONFIGURATION_CTRL); + + if (msm_dp_panel->msm_dp_mode.out_fmt_is_yuv_420) + config |=3D DP_CONFIGURATION_CTRL_RGB_YUV; /* YUV420 */ + + tbd =3D msm_dp_link_get_test_bits_depth(ctrl->link, + msm_dp_panel->msm_dp_mode.bpp); + + config |=3D tbd << DP_CONFIGURATION_CTRL_BPC_SHIFT; + + if (msm_dp_panel->psr_cap.version) + config |=3D DP_CONFIGURATION_CTRL_SEND_VSC; + + drm_dbg_dp(ctrl->drm_dev, "stream DP_CONFIGURATION_CTRL=3D0x%x\n", config= ); + + msm_dp_write_link(ctrl, REG_DP_CONFIGURATION_CTRL, config); +} + +static void msm_dp_ctrl_config_ctrl_link(struct msm_dp_ctrl_private *ctrl) +{ + u32 config =3D 0; const u8 *dpcd =3D ctrl->panel->dpcd; =20 /* Default-> LSCLK DIV: 1/4 LCLK */ config |=3D (2 << DP_CONFIGURATION_CTRL_LSCLK_DIV_SHIFT); =20 - if (ctrl->panel->msm_dp_mode.out_fmt_is_yuv_420) - config |=3D DP_CONFIGURATION_CTRL_RGB_YUV; /* YUV420 */ - /* Scrambler reset enable */ if (drm_dp_alternate_scrambler_reset_cap(dpcd)) config |=3D DP_CONFIGURATION_CTRL_ASSR; =20 - tbd =3D msm_dp_link_get_test_bits_depth(ctrl->link, - ctrl->panel->msm_dp_mode.bpp); - - config |=3D tbd << DP_CONFIGURATION_CTRL_BPC_SHIFT; - /* Num of Lanes */ config |=3D ((ctrl->link->link_params.num_lanes - 1) << DP_CONFIGURATION_CTRL_NUM_OF_LANES_SHIFT); @@ -421,10 +436,7 @@ static void msm_dp_ctrl_config_ctrl(struct msm_dp_ctrl= _private *ctrl) config |=3D DP_CONFIGURATION_CTRL_STATIC_DYNAMIC_CN; config |=3D DP_CONFIGURATION_CTRL_SYNC_ASYNC_CLK; =20 - if (ctrl->panel->psr_cap.version) - config |=3D DP_CONFIGURATION_CTRL_SEND_VSC; - - drm_dbg_dp(ctrl->drm_dev, "DP_CONFIGURATION_CTRL=3D0x%x\n", config); + drm_dbg_dp(ctrl->drm_dev, "link DP_CONFIGURATION_CTRL=3D0x%x\n", config); =20 msm_dp_write_link(ctrl, REG_DP_CONFIGURATION_CTRL, config); } @@ -450,7 +462,8 @@ static void msm_dp_ctrl_configure_source_params(struct = msm_dp_ctrl_private *ctrl msm_dp_ctrl_lane_mapping(ctrl); msm_dp_setup_peripheral_flush(ctrl); =20 - msm_dp_ctrl_config_ctrl(ctrl); + msm_dp_ctrl_config_ctrl_link(ctrl); + msm_dp_ctrl_config_ctrl_streams(ctrl, ctrl->panel); =20 test_bits_depth =3D msm_dp_link_get_test_bits_depth(ctrl->link, ctrl->pan= el->msm_dp_mode.bpp); colorimetry_cfg =3D msm_dp_link_get_colorimetry_config(ctrl->link); @@ -1628,7 +1641,7 @@ static int msm_dp_ctrl_link_train(struct msm_dp_ctrl_= private *ctrl, u8 assr; struct msm_dp_link_info link_info =3D {0}; =20 - msm_dp_ctrl_config_ctrl(ctrl); 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Signed-off-by: Yongxing Mou Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 23 +++++++++++++++-------- 1 file changed, 15 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_c= trl.c index 85315467b5d0..fd6caebae148 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -455,17 +455,13 @@ static void msm_dp_ctrl_lane_mapping(struct msm_dp_ct= rl_private *ctrl) ln_mapping); } =20 -static void msm_dp_ctrl_configure_source_params(struct msm_dp_ctrl_private= *ctrl) +static void msm_dp_ctrl_config_misc1_misc0(struct msm_dp_ctrl_private *ctr= l, + struct msm_dp_panel *msm_dp_panel) { u32 colorimetry_cfg, test_bits_depth, misc_val; =20 - msm_dp_ctrl_lane_mapping(ctrl); - msm_dp_setup_peripheral_flush(ctrl); - - msm_dp_ctrl_config_ctrl_link(ctrl); - msm_dp_ctrl_config_ctrl_streams(ctrl, ctrl->panel); - - test_bits_depth =3D msm_dp_link_get_test_bits_depth(ctrl->link, ctrl->pan= el->msm_dp_mode.bpp); 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[129.46.232.65]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-8ac84cb135fsm19223386d6.38.2026.04.10.02.34.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Apr 2026 02:34:27 -0700 (PDT) From: Yongxing Mou Date: Fri, 10 Apr 2026 17:33:42 +0800 Subject: [PATCH v4 07/39] drm/msm/dp: split link setup from source params Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260410-msm-dp-mst-v4-7-b20518dea8de@oss.qualcomm.com> References: <20260410-msm-dp-mst-v4-0-b20518dea8de@oss.qualcomm.com> In-Reply-To: <20260410-msm-dp-mst-v4-0-b20518dea8de@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Jessica Zhang Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Yongxing Mou X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1775813628; l=1313; i=yongxing.mou@oss.qualcomm.com; s=20250910; h=from:subject:message-id; bh=vaB5TI6vRjLHkdJJHUC0+HLPLyjZuxAcbDY5pvSAxd0=; b=g5dy/hjzpqUBHlCBjit+1XAMpFzbXR2uUyC1CU778OHY7g9h5f7BS1OKg6d5GQ8yCvuSBx+89 jexa4rpk6R6CpOOvw+UYfzVzsgtOokS5vxOsTFBalMToFMTIa8JOWfj X-Developer-Key: i=yongxing.mou@oss.qualcomm.com; a=ed25519; pk=rAy5J1eP+V7OXqH5FJ7ngMCtUrnHhut30ZTldOj52UM= X-Authority-Analysis: v=2.4 cv=X+hi7mTe c=1 sm=1 tr=0 ts=69d8c424 cx=c_pps a=WeENfcodrlLV9YRTxbY/uA==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=EUspDBNiAAAA:8 a=saXSvH3Ee-fMY4W8qR0A:9 a=QEXdDO2ut3YA:10 a=kacYvNCVWA4VmyqE58fU:22 X-Proofpoint-GUID: fGGm2N-QfDfntr1sRRLiJ0WGPw9TYUxe X-Proofpoint-ORIG-GUID: fGGm2N-QfDfntr1sRRLiJ0WGPw9TYUxe X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDEwMDA4OCBTYWx0ZWRfXx+/oSHiYPcJ0 AHVp2/E2iLyIl8K8utgv7q6CyL5tYixViLIkzu0PEy2BH/5921gy9wULKs+3DRs3s/cl2UlUTgo cb1zw1Gxs79vzeLrOryqxxoZQXWYZH4yCqDkyhWENF9vcJ3DcRHWdYQaLd8VTbbaTVMdKnzDqLy GIk3FYubdXWrI4ZhRHMMkLES+iRw+xdwREL1fik4U6tuQx1efD/cRflY9XyX+77uUh7m4BSxmEk 8IkWUHvjcDRBKX9K+7di1ZkYTVoI1R9qxg4UlBpuP97n2LTojhQ/xIZKLM/ztf9lOBbpwpY7qUy 7HIcEu0erPDGJHvGyHfIQ466GBa9LwK9aqLphHKrlWGefQOi/2MwqHeqkyQW9+P4EoLpdIvB+26 etOtelmNfppxI23DHZ7zg7SyMZleOAMOPZDNZoDc0dwemXAV56nW+FAl2bj8eLuJmSGG49FybwX +S6x7pm8n1aQHrn5oeA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-10_03,2026-04-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 malwarescore=0 clxscore=1015 adultscore=0 priorityscore=1501 lowpriorityscore=0 suspectscore=0 spamscore=0 bulkscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604010000 definitions=main-2604100088 msm_dp_ctrl_configure_source_params() should only handle stream-related configuration. Move the link setup out of it so MST can program link and stream settings separately. Signed-off-by: Yongxing Mou Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_c= trl.c index fd6caebae148..cd58968d4e14 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -479,10 +479,6 @@ static void msm_dp_ctrl_config_misc1_misc0(struct msm_= dp_ctrl_private *ctrl, =20 static void msm_dp_ctrl_configure_source_params(struct msm_dp_ctrl_private= *ctrl) { - msm_dp_ctrl_lane_mapping(ctrl); - msm_dp_setup_peripheral_flush(ctrl); - - msm_dp_ctrl_config_ctrl_link(ctrl); msm_dp_ctrl_config_ctrl_streams(ctrl, ctrl->panel); =20 msm_dp_ctrl_config_misc1_misc0(ctrl, ctrl->panel); @@ -2571,6 +2567,10 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp= _ctrl) */ reinit_completion(&ctrl->video_comp); =20 + msm_dp_ctrl_lane_mapping(ctrl); + msm_dp_setup_peripheral_flush(ctrl); + msm_dp_ctrl_config_ctrl_link(ctrl); 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[129.46.232.65]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-8ac84cb135fsm19223386d6.38.2026.04.10.02.34.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Apr 2026 02:34:31 -0700 (PDT) From: Yongxing Mou Date: Fri, 10 Apr 2026 17:33:43 +0800 Subject: [PATCH v4 08/39] drm/msm/dp: allow dp_ctrl stream APIs to use any panel passed to it Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260410-msm-dp-mst-v4-8-b20518dea8de@oss.qualcomm.com> References: <20260410-msm-dp-mst-v4-0-b20518dea8de@oss.qualcomm.com> In-Reply-To: <20260410-msm-dp-mst-v4-0-b20518dea8de@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Jessica Zhang Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Yongxing Mou , Abhinav Kumar X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1775813628; l=4382; i=yongxing.mou@oss.qualcomm.com; s=20250910; h=from:subject:message-id; bh=BkXona5TbnmF2de1k2yc2BT4vzk4O5UWrXuvAHrPtBc=; b=p8UCmpq5XBfAtP50t/F6FDt0RigWiXxicBr6UCmW8ZWVkMnfjZJQawhqlnqHAx9w1xHwzUAg9 BnhX3u/uhRsBZpIBYOrbH170cbtzxIjAqzA4NdvcERnaV5l/G1uySGm X-Developer-Key: i=yongxing.mou@oss.qualcomm.com; a=ed25519; pk=rAy5J1eP+V7OXqH5FJ7ngMCtUrnHhut30ZTldOj52UM= X-Authority-Analysis: v=2.4 cv=PMM/P/qC c=1 sm=1 tr=0 ts=69d8c429 cx=c_pps a=7E5Bxpl4vBhpaufnMqZlrw==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=x41-kvR0HCwjNSFKcS0A:9 a=QEXdDO2ut3YA:10 a=pJ04lnu7RYOZP9TFuWaZ:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: xcVNCgP3XM_bIvdXxEetEPQkxLzXQLQS X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDEwMDA4OCBTYWx0ZWRfX85/EZdr8iadf Rlx/JGL5orbyEHp8F29CwGjzFSCdwrZN0lJqmWgHna8Twl7CLV7vEGoqmPL6xYv+jm4quxSpUhn F0KMR6xtO92Ho7zF2AROJFR0cWVXLm91k8DIo1LJpKhXVAZbA4QQzhMFc33yZ8FsuA1+/+u/rPv cf+gTwP+2c6rQsbxjN8UDLGjuvPbNjbIJPYIsBufbOUXGz0GEOMe782V8cRc4+WxbMUP7g3u8nK hMtaP1t3V+78Paoa3PlRjzD8/r3ajPHbuGuMe0kvcn+ydWDVxhvgly+iYb4sWdZ2oex6a9NHvD/ XEDHYDfPnkuvafFARFeZ/8EawrZjb8Tx5RspovR4pT1yfjr7XWrPIOt2byXsYxnBu/YOkIy5z9p +TZZVqm2P8V1pTNwXnwHqWsaULXUyLId8mmf4+3GWtH2VT8r9NaPKn6fCEQSrQj+L42WMkGyZXD aoqz/U2bjInBmIdwOrQ== X-Proofpoint-GUID: xcVNCgP3XM_bIvdXxEetEPQkxLzXQLQS X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-10_03,2026-04-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 suspectscore=0 priorityscore=1501 adultscore=0 lowpriorityscore=0 bulkscore=0 phishscore=0 clxscore=1015 malwarescore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604010000 definitions=main-2604100088 From: Abhinav Kumar Currently, the dp_ctrl stream APIs operate on their own dp_panel which is stored inside the dp_ctrl's private struct. However with MST, the stored panel represents the fixed link and not the sinks which are hotplugged. Allow the stream related APIs to work on the panel which is passed to them rather than the stored one. For SST cases, this shall continue to use the stored dp_panel. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 21 +++++++++++---------- drivers/gpu/drm/msm/dp/dp_ctrl.h | 2 +- drivers/gpu/drm/msm/dp/dp_display.c | 2 +- 3 files changed, 13 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_c= trl.c index cd58968d4e14..d0eed8c7df45 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -477,13 +477,14 @@ static void msm_dp_ctrl_config_misc1_misc0(struct msm= _dp_ctrl_private *ctrl, msm_dp_write_link(ctrl, REG_DP_MISC1_MISC0, misc_val); } =20 -static void msm_dp_ctrl_configure_source_params(struct msm_dp_ctrl_private= *ctrl) +static void msm_dp_ctrl_configure_source_params(struct msm_dp_ctrl_private= *ctrl, + struct msm_dp_panel *msm_dp_panel) { - msm_dp_ctrl_config_ctrl_streams(ctrl, ctrl->panel); + msm_dp_ctrl_config_ctrl_streams(ctrl, msm_dp_panel); =20 - msm_dp_ctrl_config_misc1_misc0(ctrl, ctrl->panel); + msm_dp_ctrl_config_misc1_misc0(ctrl, msm_dp_panel); =20 - msm_dp_panel_timing_cfg(ctrl->panel, ctrl->msm_dp_ctrl.wide_bus_en); + msm_dp_panel_timing_cfg(msm_dp_panel, ctrl->msm_dp_ctrl.wide_bus_en); } =20 /* @@ -2523,7 +2524,7 @@ int msm_dp_ctrl_prepare_stream_on(struct msm_dp_ctrl = *msm_dp_ctrl, bool force_li return ret; } =20 -int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl) +int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl, struct msm_dp_p= anel *msm_dp_panel) { int ret =3D 0; bool mainlink_ready =3D false; @@ -2536,10 +2537,10 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_d= p_ctrl) =20 ctrl =3D container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctr= l); =20 - pixel_rate_orig =3D ctrl->panel->msm_dp_mode.drm_mode.clock; + pixel_rate_orig =3D msm_dp_panel->msm_dp_mode.drm_mode.clock; pixel_rate =3D pixel_rate_orig; =20 - if (msm_dp_ctrl->wide_bus_en || ctrl->panel->msm_dp_mode.out_fmt_is_yuv_4= 20) + if (msm_dp_ctrl->wide_bus_en || msm_dp_panel->msm_dp_mode.out_fmt_is_yuv_= 420) pixel_rate >>=3D 1; =20 drm_dbg_dp(ctrl->drm_dev, "pixel_rate=3D%lu\n", pixel_rate); @@ -2571,14 +2572,14 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_d= p_ctrl) msm_dp_setup_peripheral_flush(ctrl); msm_dp_ctrl_config_ctrl_link(ctrl); =20 - msm_dp_ctrl_configure_source_params(ctrl); + msm_dp_ctrl_configure_source_params(ctrl, msm_dp_panel); =20 msm_dp_ctrl_config_msa(ctrl, ctrl->link->link_params.rate, pixel_rate_orig, - ctrl->panel->msm_dp_mode.out_fmt_is_yuv_420); + msm_dp_panel->msm_dp_mode.out_fmt_is_yuv_420); =20 - msm_dp_panel_clear_dsc_dto(ctrl->panel); + msm_dp_panel_clear_dsc_dto(msm_dp_panel); =20 msm_dp_ctrl_setup_tr_unit(ctrl); =20 diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.h b/drivers/gpu/drm/msm/dp/dp_c= trl.h index 5d615f50d13b..32196e97cbe9 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.h +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.h @@ -17,7 +17,7 @@ struct msm_dp_ctrl { struct phy; =20 int msm_dp_ctrl_on_link(struct msm_dp_ctrl *msm_dp_ctrl); -int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl); 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Move it into individual helpers so that the helpers can be called wherever necessary. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 79 +++++++++++++++++++++---------------= ---- 1 file changed, 41 insertions(+), 38 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_c= trl.c index d0eed8c7df45..fa62f8f91189 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -2176,6 +2176,42 @@ static bool msm_dp_ctrl_send_phy_test_pattern(struct= msm_dp_ctrl_private *ctrl) return success; } =20 +static int msm_dp_ctrl_on_pixel_clk(struct msm_dp_ctrl_private *ctrl, unsi= gned long pixel_rate) +{ + int ret; + + ret =3D clk_set_rate(ctrl->pixel_clk, pixel_rate * 1000); + if (ret) { + DRM_ERROR("Failed to set pixel clock rate. ret=3D%d\n", ret); + return ret; + } + + if (ctrl->stream_clks_on) { + drm_dbg_dp(ctrl->drm_dev, "pixel clks already enabled\n"); + } else { + ret =3D clk_prepare_enable(ctrl->pixel_clk); + if (ret) { + DRM_ERROR("Failed to start pixel clocks. ret=3D%d\n", ret); + return ret; + } + ctrl->stream_clks_on =3D true; + } + + return ret; +} + +static void msm_dp_ctrl_off_pixel_clk(struct msm_dp_ctrl *msm_dp_ctrl) +{ + struct msm_dp_ctrl_private *ctrl; + + ctrl =3D container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctr= l); + + if (ctrl->stream_clks_on) { + clk_disable_unprepare(ctrl->pixel_clk); + ctrl->stream_clks_on =3D false; + } +} + static int msm_dp_ctrl_process_phy_test_request(struct msm_dp_ctrl_private= *ctrl) { int ret; @@ -2201,22 +2237,7 @@ static int msm_dp_ctrl_process_phy_test_request(stru= ct msm_dp_ctrl_private *ctrl } =20 pixel_rate =3D ctrl->panel->msm_dp_mode.drm_mode.clock; - ret =3D clk_set_rate(ctrl->pixel_clk, pixel_rate * 1000); - if (ret) { - DRM_ERROR("Failed to set pixel clock rate. ret=3D%d\n", ret); - return ret; - } - - if (ctrl->stream_clks_on) { - drm_dbg_dp(ctrl->drm_dev, "pixel clks already enabled\n"); - } else { - ret =3D clk_prepare_enable(ctrl->pixel_clk); - if (ret) { - DRM_ERROR("Failed to start pixel clocks. ret=3D%d\n", ret); - return ret; - } - ctrl->stream_clks_on =3D true; - } + ret =3D msm_dp_ctrl_on_pixel_clk(ctrl, pixel_rate); =20 msm_dp_ctrl_send_phy_test_pattern(ctrl); =20 @@ -2545,22 +2566,9 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp= _ctrl, struct msm_dp_panel * =20 drm_dbg_dp(ctrl->drm_dev, "pixel_rate=3D%lu\n", pixel_rate); =20 - ret =3D clk_set_rate(ctrl->pixel_clk, pixel_rate * 1000); - if (ret) { - DRM_ERROR("Failed to set pixel clock rate. ret=3D%d\n", ret); - goto end; - } - - if (ctrl->stream_clks_on) { - drm_dbg_dp(ctrl->drm_dev, "pixel clks already enabled\n"); - } else { - ret =3D clk_prepare_enable(ctrl->pixel_clk); - if (ret) { - DRM_ERROR("Failed to start pixel clocks. ret=3D%d\n", ret); - goto end; - } - ctrl->stream_clks_on =3D true; - } + ret =3D msm_dp_ctrl_on_pixel_clk(ctrl, pixel_rate); + if (ret) + return ret; =20 /* * Set up transfer unit values and set controller state to send @@ -2593,7 +2601,6 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_= ctrl, struct msm_dp_panel * drm_dbg_dp(ctrl->drm_dev, "mainlink %s\n", mainlink_ready ? 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Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 8 ++++---- drivers/gpu/drm/msm/dp/dp_ctrl.h | 3 ++- drivers/gpu/drm/msm/dp/dp_display.c | 6 ++++-- 3 files changed, 10 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_c= trl.c index fa62f8f91189..120ec00884e5 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -2200,7 +2200,7 @@ static int msm_dp_ctrl_on_pixel_clk(struct msm_dp_ctr= l_private *ctrl, unsigned l return ret; } =20 -static void msm_dp_ctrl_off_pixel_clk(struct msm_dp_ctrl *msm_dp_ctrl) +void msm_dp_ctrl_off_pixel_clk(struct msm_dp_ctrl *msm_dp_ctrl) { struct msm_dp_ctrl_private *ctrl; =20 @@ -2228,7 +2228,8 @@ static int msm_dp_ctrl_process_phy_test_request(struc= t msm_dp_ctrl_private *ctrl * running. Add the global reset just before disabling the * link clocks and core clocks. */ - msm_dp_ctrl_off(&ctrl->msm_dp_ctrl); + msm_dp_ctrl_off_pixel_clk(&ctrl->msm_dp_ctrl); + msm_dp_ctrl_off_link(&ctrl->msm_dp_ctrl); =20 ret =3D msm_dp_ctrl_on_link(&ctrl->msm_dp_ctrl); if (ret) { @@ -2620,7 +2621,7 @@ void msm_dp_ctrl_reinit_phy(struct msm_dp_ctrl *msm_d= p_ctrl) phy, phy->init_count, phy->power_count); } =20 -void msm_dp_ctrl_off(struct msm_dp_ctrl *msm_dp_ctrl) +void msm_dp_ctrl_off_link(struct msm_dp_ctrl *msm_dp_ctrl) { struct msm_dp_ctrl_private *ctrl; struct phy *phy; @@ -2634,7 +2635,6 @@ void msm_dp_ctrl_off(struct msm_dp_ctrl *msm_dp_ctrl) =20 msm_dp_ctrl_reset(&ctrl->msm_dp_ctrl); =20 - msm_dp_ctrl_off_pixel_clk(msm_dp_ctrl); dev_pm_opp_set_rate(ctrl->dev, 0); msm_dp_ctrl_link_clk_disable(&ctrl->msm_dp_ctrl); =20 diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.h b/drivers/gpu/drm/msm/dp/dp_c= trl.h index 32196e97cbe9..b83be2252a9b 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.h +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.h @@ -19,7 +19,8 @@ struct phy; int msm_dp_ctrl_on_link(struct msm_dp_ctrl *msm_dp_ctrl); int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl, struct msm_dp_p= anel *msm_dp_panel); int msm_dp_ctrl_prepare_stream_on(struct msm_dp_ctrl *msm_dp_ctrl, bool fo= rce_link_train); -void msm_dp_ctrl_off(struct msm_dp_ctrl *msm_dp_ctrl); +void msm_dp_ctrl_off_link(struct msm_dp_ctrl *msm_dp_ctrl); +void msm_dp_ctrl_off_pixel_clk(struct msm_dp_ctrl *msm_dp_ctrl); void msm_dp_ctrl_push_idle(struct msm_dp_ctrl *msm_dp_ctrl); irqreturn_t msm_dp_ctrl_isr(struct msm_dp_ctrl *msm_dp_ctrl); void msm_dp_ctrl_handle_sink_request(struct msm_dp_ctrl *msm_dp_ctrl); diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index 1bf1335712bc..31e229ac2393 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -730,7 +730,8 @@ static int msm_dp_display_disable(struct msm_dp_display= _private *dp) =20 /* set dongle to D3 (power off) mode */ msm_dp_link_psm_config(dp->link, &dp->panel->link_info, true); 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[129.46.232.65]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-8ac84cb135fsm19223386d6.38.2026.04.10.02.34.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Apr 2026 02:34:47 -0700 (PDT) From: Yongxing Mou Date: Fri, 10 Apr 2026 17:33:46 +0800 Subject: [PATCH v4 11/39] drm/msm/dp: make bridge helpers use dp_display to allow re-use Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260410-msm-dp-mst-v4-11-b20518dea8de@oss.qualcomm.com> References: <20260410-msm-dp-mst-v4-0-b20518dea8de@oss.qualcomm.com> In-Reply-To: <20260410-msm-dp-mst-v4-0-b20518dea8de@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Jessica Zhang Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Yongxing Mou , Abhinav Kumar X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1775813628; l=8431; i=yongxing.mou@oss.qualcomm.com; s=20250910; h=from:subject:message-id; bh=jzeTvQi7vuc6cxW8UWUPZDTFedkNgRaHOSc8OQfHLhw=; b=aOI7bMWddL63zn1zjtqswK/6/E+CznKH+N2JZ04tDdLJgvwf1b3DcGgEqsNpoXW6QoJNI1LwP FQWP59qg7xPDfbPZdsWAIDvnAKqaP+tO4CQOY8DyYife9nWC9wrRWOj X-Developer-Key: i=yongxing.mou@oss.qualcomm.com; a=ed25519; pk=rAy5J1eP+V7OXqH5FJ7ngMCtUrnHhut30ZTldOj52UM= X-Proofpoint-GUID: 7hVBjALrBx3c1UEfqEWgbIsq3e5bVwq_ X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDEwMDA4OCBTYWx0ZWRfXxo8moaKdh3Gu R8U+gpz0TB4wN+EbikEjYECzYVD5j/Xmod+TqC0V84bVYOR1S0/W/GEoM5YjmGHXkn6dNRV2P2p LTqHxcyGN1nNQIZxFfy8p5F8iLD3TkbtGxnUxkcJIUrKWk/OQCQXTqWO1mrm6Ny9sub3YtGQcV5 eSSH5vomwq3ok58NDs3NFmsi9dx4uaOx7lEA1xoE88fad4fCzFoN04hbqrX/2TlcjKFs1z3ESwS 59VEwKj3O5SRj4hbegpMKCMPl9jSKPQHrwIuXbYWrpNCmC5VQTxKQGyhwi5OCfM8pqTGDVNazuT iKJOuS7T/rjqq7MBpLtUUDAckPFcndKPU3YmSk33YruzM1LU19DDFMhiqFbNjkF3fsf6YUu7Fe4 S57UoV154h+mMQOgoVgXa0lAMmBAAQEopHZiwvrd9XQbiMKbWrZ4QguFjMkcYNi+sJRZaHVUQ+Y S/Xvye+PdApTBcppT0Q== X-Proofpoint-ORIG-GUID: 7hVBjALrBx3c1UEfqEWgbIsq3e5bVwq_ X-Authority-Analysis: v=2.4 cv=DslmPm/+ c=1 sm=1 tr=0 ts=69d8c438 cx=c_pps a=HLyN3IcIa5EE8TELMZ618Q==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=LmD7BKvqrCyCckpIDn8A:9 a=QEXdDO2ut3YA:10 a=bTQJ7kPSJx9SKPbeHEYW:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-10_03,2026-04-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 lowpriorityscore=0 suspectscore=0 adultscore=0 malwarescore=0 clxscore=1015 impostorscore=0 bulkscore=0 priorityscore=1501 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604010000 definitions=main-2604100088 From: Abhinav Kumar dp_bridge helpers take drm_bridge as an input and extract the dp_display object to be used in the dp_display module. Rather than doing it in a roundabout way, directly pass the dp_display object to these helpers so that the MST bridge can also re-use the same helpers. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_display.c | 29 +++++++++------------------ drivers/gpu/drm/msm/dp/dp_display.h | 7 +++++++ drivers/gpu/drm/msm/dp/dp_drm.c | 39 +++++++++++++++++++++++++++++++++= +++- drivers/gpu/drm/msm/dp/dp_drm.h | 9 --------- 4 files changed, 54 insertions(+), 30 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index 31e229ac2393..c7dc861301de 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -752,24 +752,21 @@ static int msm_dp_display_disable(struct msm_dp_displ= ay_private *dp) =20 /** * msm_dp_bridge_mode_valid - callback to determine if specified mode is v= alid - * @bridge: Pointer to drm bridge structure + * @dp: Pointer to dp display structure * @info: display info * @mode: Pointer to drm mode structure * Returns: Validity status for specified mode */ -enum drm_mode_status msm_dp_bridge_mode_valid(struct drm_bridge *bridge, - const struct drm_display_info *info, - const struct drm_display_mode *mode) +enum drm_mode_status msm_dp_display_mode_valid(struct msm_dp *dp, + const struct drm_display_info *info, + const struct drm_display_mode *mode) { const u32 num_components =3D 3, default_bpp =3D 24; struct msm_dp_display_private *msm_dp_display; struct msm_dp_link_info *link_info; u32 mode_rate_khz =3D 0, supported_rate_khz =3D 0, mode_bpp =3D 0; - struct msm_dp *dp; int mode_pclk_khz =3D mode->clock; =20 - dp =3D to_dp_bridge(bridge)->msm_dp_display; - if (!dp || !mode_pclk_khz || !dp->connector) { DRM_ERROR("invalid params\n"); return -EINVAL; @@ -1420,11 +1417,9 @@ int msm_dp_modeset_init(struct msm_dp *msm_dp_displa= y, struct drm_device *dev, return 0; } =20 -void msm_dp_bridge_atomic_enable(struct drm_bridge *drm_bridge, - struct drm_atomic_state *state) +void msm_dp_display_atomic_enable(struct msm_dp *msm_dp_display, + struct drm_atomic_state *state) { - struct msm_dp_bridge *msm_dp_bridge =3D to_dp_bridge(drm_bridge); - struct msm_dp *msm_dp_display =3D msm_dp_bridge->msm_dp_display; struct drm_crtc *crtc; struct drm_crtc_state *crtc_state; int rc =3D 0; @@ -1433,7 +1428,7 @@ void msm_dp_bridge_atomic_enable(struct drm_bridge *d= rm_bridge, dp =3D container_of(msm_dp_display, struct msm_dp_display_private, msm_dp= _display); =20 crtc =3D drm_atomic_get_new_crtc_for_encoder(state, - drm_bridge->encoder); + msm_dp_display->bridge->encoder); if (!crtc) return; crtc_state =3D drm_atomic_get_new_crtc_state(state, crtc); @@ -1463,11 +1458,8 @@ void msm_dp_bridge_atomic_enable(struct drm_bridge *= drm_bridge, drm_dbg_dp(msm_dp_display->drm_dev, "type=3D%d Done\n", msm_dp_display->c= onnector_type); } =20 -void msm_dp_bridge_atomic_disable(struct drm_bridge *drm_bridge, - struct drm_atomic_state *state) +void msm_dp_display_atomic_disable(struct msm_dp *dp) { - struct msm_dp_bridge *msm_dp_bridge =3D to_dp_bridge(drm_bridge); - struct msm_dp *dp =3D msm_dp_bridge->msm_dp_display; struct msm_dp_display_private *msm_dp_display; =20 msm_dp_display =3D container_of(dp, struct msm_dp_display_private, msm_dp= _display); @@ -1484,11 +1476,8 @@ static void msm_dp_display_unprepare(struct msm_dp_d= isplay_private *dp) drm_dbg_dp(dp->drm_dev, "type=3D%d Done\n", msm_dp_display->connector_typ= e); } =20 -void msm_dp_bridge_atomic_post_disable(struct drm_bridge *drm_bridge, - struct drm_atomic_state *state) +void msm_dp_display_atomic_post_disable(struct msm_dp *dp) { - struct msm_dp_bridge *msm_dp_bridge =3D to_dp_bridge(drm_bridge); - struct msm_dp *dp =3D msm_dp_bridge->msm_dp_display; struct msm_dp_display_private *msm_dp_display; =20 msm_dp_display =3D container_of(dp, struct msm_dp_display_private, msm_dp= _display); diff --git a/drivers/gpu/drm/msm/dp/dp_display.h b/drivers/gpu/drm/msm/dp/d= p_display.h index 0b65e16c790d..1a697fb305a7 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.h +++ b/drivers/gpu/drm/msm/dp/dp_display.h @@ -33,5 +33,12 @@ void msm_dp_display_signal_audio_start(struct msm_dp *ms= m_dp_display); void msm_dp_display_signal_audio_complete(struct msm_dp *msm_dp_display); void msm_dp_display_set_psr(struct msm_dp *dp, bool enter); void msm_dp_display_debugfs_init(struct msm_dp *msm_dp_display, struct den= try *dentry, bool is_edp); +void msm_dp_display_atomic_post_disable(struct msm_dp *dp_display); +void msm_dp_display_atomic_disable(struct msm_dp *dp_display); +void msm_dp_display_atomic_enable(struct msm_dp *dp_display, + struct drm_atomic_state *state); +enum drm_mode_status msm_dp_display_mode_valid(struct msm_dp *dp, + const struct drm_display_info *info, + const struct drm_display_mode *mode); =20 #endif /* _DP_DISPLAY_H_ */ diff --git a/drivers/gpu/drm/msm/dp/dp_drm.c b/drivers/gpu/drm/msm/dp/dp_dr= m.c index af3d3e3a2d84..cb54d7e71f8e 100644 --- a/drivers/gpu/drm/msm/dp/dp_drm.c +++ b/drivers/gpu/drm/msm/dp/dp_drm.c @@ -49,6 +49,43 @@ static void msm_dp_bridge_debugfs_init(struct drm_bridge= *bridge, struct dentry msm_dp_display_debugfs_init(dp, root, false); } =20 +static void msm_dp_bridge_atomic_enable(struct drm_bridge *drm_bridge, + struct drm_atomic_state *state) +{ + struct msm_dp_bridge *dp_bridge =3D to_dp_bridge(drm_bridge); + struct msm_dp *dp =3D dp_bridge->msm_dp_display; + + msm_dp_display_atomic_enable(dp, state); +} + +static void msm_dp_bridge_atomic_disable(struct drm_bridge *drm_bridge, + struct drm_atomic_state *state) +{ + struct msm_dp_bridge *dp_bridge =3D to_dp_bridge(drm_bridge); + struct msm_dp *dp =3D dp_bridge->msm_dp_display; + + msm_dp_display_atomic_disable(dp); +} + +static void msm_dp_bridge_atomic_post_disable(struct drm_bridge *drm_bridg= e, + struct drm_atomic_state *state) +{ + struct msm_dp_bridge *dp_bridge =3D to_dp_bridge(drm_bridge); + struct msm_dp *dp =3D dp_bridge->msm_dp_display; + + msm_dp_display_atomic_post_disable(dp); +} + +static enum drm_mode_status msm_dp_bridge_mode_valid(struct drm_bridge *dr= m_bridge, + const struct drm_display_info *info, + const struct drm_display_mode *mode) +{ + struct msm_dp_bridge *dp_bridge =3D to_dp_bridge(drm_bridge); + struct msm_dp *dp =3D dp_bridge->msm_dp_display; + + return msm_dp_display_mode_valid(dp, info, mode); +} + static const struct drm_bridge_funcs msm_dp_bridge_ops =3D { .atomic_duplicate_state =3D drm_atomic_helper_bridge_duplicate_state, .atomic_destroy_state =3D drm_atomic_helper_bridge_destroy_state, @@ -115,7 +152,7 @@ static void msm_edp_bridge_atomic_enable(struct drm_bri= dge *drm_bridge, return; } =20 - msm_dp_bridge_atomic_enable(drm_bridge, state); + msm_dp_display_atomic_enable(dp, state); } =20 static void msm_edp_bridge_atomic_disable(struct drm_bridge *drm_bridge, diff --git a/drivers/gpu/drm/msm/dp/dp_drm.h b/drivers/gpu/drm/msm/dp/dp_dr= m.h index 6d4cbb9f3918..da412c788503 100644 --- a/drivers/gpu/drm/msm/dp/dp_drm.h +++ b/drivers/gpu/drm/msm/dp/dp_drm.h @@ -27,15 +27,6 @@ int msm_dp_bridge_init(struct msm_dp *msm_dp_display, st= ruct drm_device *dev, =20 enum drm_connector_status msm_dp_bridge_detect(struct drm_bridge *bridge, struct drm_connector *connector); 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Split the link-related preparation out of msm_dp_display_atomic_enable() so it can be called separately before the per-stream enable path. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_display.c | 16 +++++++++++----- drivers/gpu/drm/msm/dp/dp_display.h | 5 +++-- drivers/gpu/drm/msm/dp/dp_drm.c | 6 ++++-- 3 files changed, 18 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index c7dc861301de..32ad00e326ba 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -1417,8 +1417,8 @@ int msm_dp_modeset_init(struct msm_dp *msm_dp_display= , struct drm_device *dev, return 0; } =20 -void msm_dp_display_atomic_enable(struct msm_dp *msm_dp_display, - struct drm_atomic_state *state) +void msm_dp_display_atomic_prepare(struct msm_dp *msm_dp_display, + struct drm_atomic_state *state) { struct drm_crtc *crtc; struct drm_crtc_state *crtc_state; @@ -1440,10 +1440,16 @@ void msm_dp_display_atomic_enable(struct msm_dp *ms= m_dp_display, } =20 rc =3D msm_dp_display_prepare(dp); - if (rc) { + if (rc) DRM_ERROR("DP display prepare failed, rc=3D%d\n", rc); - return; - } +} + +void msm_dp_display_atomic_enable(struct msm_dp *msm_dp_display) +{ + struct msm_dp_display_private *dp; + int rc =3D 0; + + dp =3D container_of(msm_dp_display, struct msm_dp_display_private, msm_dp= _display); =20 rc =3D msm_dp_display_enable(dp); if (rc) diff --git a/drivers/gpu/drm/msm/dp/dp_display.h b/drivers/gpu/drm/msm/dp/d= p_display.h index 1a697fb305a7..295da7ae0047 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.h +++ b/drivers/gpu/drm/msm/dp/dp_display.h @@ -35,8 +35,9 @@ void msm_dp_display_set_psr(struct msm_dp *dp, bool enter= ); void msm_dp_display_debugfs_init(struct msm_dp *msm_dp_display, struct den= try *dentry, bool is_edp); void msm_dp_display_atomic_post_disable(struct msm_dp *dp_display); void msm_dp_display_atomic_disable(struct msm_dp *dp_display); -void msm_dp_display_atomic_enable(struct msm_dp *dp_display, - struct drm_atomic_state *state); +void msm_dp_display_atomic_prepare(struct msm_dp *dp_display, + struct drm_atomic_state *state); +void msm_dp_display_atomic_enable(struct msm_dp *dp_display); enum drm_mode_status msm_dp_display_mode_valid(struct msm_dp *dp, const struct drm_display_info *info, const struct drm_display_mode *mode); diff --git a/drivers/gpu/drm/msm/dp/dp_drm.c b/drivers/gpu/drm/msm/dp/dp_dr= m.c index cb54d7e71f8e..0feb757e2db9 100644 --- a/drivers/gpu/drm/msm/dp/dp_drm.c +++ b/drivers/gpu/drm/msm/dp/dp_drm.c @@ -55,7 +55,8 @@ static void msm_dp_bridge_atomic_enable(struct drm_bridge= *drm_bridge, struct msm_dp_bridge *dp_bridge =3D to_dp_bridge(drm_bridge); struct msm_dp *dp =3D dp_bridge->msm_dp_display; =20 - msm_dp_display_atomic_enable(dp, state); + msm_dp_display_atomic_prepare(dp, state); + msm_dp_display_atomic_enable(dp); } =20 static void msm_dp_bridge_atomic_disable(struct drm_bridge *drm_bridge, @@ -152,7 +153,8 @@ static void msm_edp_bridge_atomic_enable(struct drm_bri= dge *drm_bridge, return; } =20 - msm_dp_display_atomic_enable(dp, state); + msm_dp_display_atomic_prepare(dp, state); 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[129.46.232.65]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-8ac84cb135fsm19223386d6.38.2026.04.10.02.34.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Apr 2026 02:34:57 -0700 (PDT) From: Yongxing Mou Date: Fri, 10 Apr 2026 17:33:48 +0800 Subject: [PATCH v4 13/39] drm/msm/dp: introduce stream_id for each DP panel Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260410-msm-dp-mst-v4-13-b20518dea8de@oss.qualcomm.com> References: <20260410-msm-dp-mst-v4-0-b20518dea8de@oss.qualcomm.com> In-Reply-To: <20260410-msm-dp-mst-v4-0-b20518dea8de@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Jessica Zhang Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Yongxing Mou , Abhinav Kumar X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1775813628; l=10441; i=yongxing.mou@oss.qualcomm.com; s=20250910; h=from:subject:message-id; bh=0zZ5Z749us2wPfXjM1qRY1pgMrkJ7eOESMVd1J1iOOk=; b=mWQhlZFthxzZPoshK9EMaGep5PpowHqrQGvmpZYLR6lyrLndre+4uvwZ3P+tuhbK4HHAYmiMM I5X3n5eA3GkAO6wBqoYx3jeE+fCHWC57XYlvgLhh7o7tE+DiISwzzK7 X-Developer-Key: i=yongxing.mou@oss.qualcomm.com; a=ed25519; pk=rAy5J1eP+V7OXqH5FJ7ngMCtUrnHhut30ZTldOj52UM= X-Authority-Analysis: v=2.4 cv=X+hi7mTe c=1 sm=1 tr=0 ts=69d8c444 cx=c_pps a=mPf7EqFMSY9/WdsSgAYMbA==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=3p9S9wXb_X6dsqCEsbEA:9 a=QEXdDO2ut3YA:10 a=dawVfQjAaf238kedN5IG:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: OMzgSBWMet71qCGpfqNlnRI7QELi2Xe9 X-Proofpoint-ORIG-GUID: OMzgSBWMet71qCGpfqNlnRI7QELi2Xe9 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDEwMDA4OCBTYWx0ZWRfX5BJaqSglytZj 8UpKX+hsNcJw6Xc6UaNuD1nat5/4fiSeeGe7K7boJto18uo/yyUqcu1x4XWYNAsTOVxp8KeAsp2 4b8gQ/VimfvbDbnVq6iEa/nqIKs64CB6zjTc/wfYrSJXbIfDRgEtYegleEQeqoX2qz1TQAa2iSY RTvd9blNMF3d/XpzJC7MuUxsNOyF4eOY3xa4ROJ9iTt4O0JFhY8Riv+aFLK/dwtszd4AfMSwdnE e6hbClUShF2XN62oer63G+vLDZqpfzViKKsU6uBZotUyiAUZs9Dh43nP1SbcMaf6N/82gQsAR/z 4eKk8yiyZ1MxLugalKF6ZUJTfdPk1ux+LHHw9n5OmKYCyzyWRwmOa/15mDaOpUUHcPiwotOLQMx H1W3IB9TBRqvelIyyp+0v7Htny3nZb8y4RMWADL6+1Wmfg1VraYtvpjnRvYI7MeXF6m2NPP1JHL LrD/9mLPEyGGaKB+OxQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-10_03,2026-04-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 malwarescore=0 clxscore=1015 adultscore=0 priorityscore=1501 lowpriorityscore=0 suspectscore=0 spamscore=0 bulkscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604010000 definitions=main-2604100088 From: Abhinav Kumar With MST, each DP controller can handle multiple streams. There shall be one dp_panel for each stream but the dp_display object shall be shared among them. To represent this abstraction, create a stream_id for each DP panel which shall be set by the MST stream. For SST, default this to stream 0. Use the stream ID to control the pixel clock of that respective stream by extending the clock handles and state tracking of the DP pixel clock to an array of max supported streams. The maximum streams currently is 4. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 57 +++++++++++++++++++++++----------= ---- drivers/gpu/drm/msm/dp/dp_ctrl.h | 2 +- drivers/gpu/drm/msm/dp/dp_display.c | 24 ++++++++++++++-- drivers/gpu/drm/msm/dp/dp_display.h | 2 ++ drivers/gpu/drm/msm/dp/dp_panel.h | 11 +++++++ 5 files changed, 71 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_c= trl.c index 120ec00884e5..fb6396727628 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -127,7 +127,7 @@ struct msm_dp_ctrl_private { unsigned int num_link_clks; struct clk_bulk_data *link_clks; =20 - struct clk *pixel_clk; + struct clk *pixel_clk[DP_STREAM_MAX]; =20 union phy_configure_opts phy_opts; =20 @@ -139,7 +139,7 @@ struct msm_dp_ctrl_private { =20 bool core_clks_on; bool link_clks_on; - bool stream_clks_on; + bool stream_clks_on[DP_STREAM_MAX]; }; =20 static inline u32 msm_dp_read_ahb(const struct msm_dp_ctrl_private *ctrl, = u32 offset) @@ -2176,39 +2176,40 @@ static bool msm_dp_ctrl_send_phy_test_pattern(struc= t msm_dp_ctrl_private *ctrl) return success; } =20 -static int msm_dp_ctrl_on_pixel_clk(struct msm_dp_ctrl_private *ctrl, unsi= gned long pixel_rate) +static int msm_dp_ctrl_on_pixel_clk(struct msm_dp_ctrl_private *ctrl, unsi= gned long pixel_rate, + enum msm_dp_stream_id stream_id) { int ret; =20 - ret =3D clk_set_rate(ctrl->pixel_clk, pixel_rate * 1000); + ret =3D clk_set_rate(ctrl->pixel_clk[stream_id], pixel_rate * 1000); if (ret) { DRM_ERROR("Failed to set pixel clock rate. ret=3D%d\n", ret); return ret; } =20 - if (ctrl->stream_clks_on) { + if (ctrl->stream_clks_on[stream_id]) { drm_dbg_dp(ctrl->drm_dev, "pixel clks already enabled\n"); } else { - ret =3D clk_prepare_enable(ctrl->pixel_clk); + ret =3D clk_prepare_enable(ctrl->pixel_clk[stream_id]); if (ret) { DRM_ERROR("Failed to start pixel clocks. ret=3D%d\n", ret); return ret; } - ctrl->stream_clks_on =3D true; + ctrl->stream_clks_on[stream_id] =3D true; } =20 return ret; } =20 -void msm_dp_ctrl_off_pixel_clk(struct msm_dp_ctrl *msm_dp_ctrl) +void msm_dp_ctrl_off_pixel_clk(struct msm_dp_ctrl *msm_dp_ctrl, enum msm_d= p_stream_id stream_id) { struct msm_dp_ctrl_private *ctrl; =20 ctrl =3D container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctr= l); =20 - if (ctrl->stream_clks_on) { - clk_disable_unprepare(ctrl->pixel_clk); - ctrl->stream_clks_on =3D false; + if (ctrl->stream_clks_on[stream_id]) { + clk_disable_unprepare(ctrl->pixel_clk[stream_id]); + ctrl->stream_clks_on[stream_id] =3D false; } } =20 @@ -2228,7 +2229,7 @@ static int msm_dp_ctrl_process_phy_test_request(struc= t msm_dp_ctrl_private *ctrl * running. Add the global reset just before disabling the * link clocks and core clocks. */ - msm_dp_ctrl_off_pixel_clk(&ctrl->msm_dp_ctrl); + msm_dp_ctrl_off_pixel_clk(&ctrl->msm_dp_ctrl, ctrl->panel->stream_id); msm_dp_ctrl_off_link(&ctrl->msm_dp_ctrl); =20 ret =3D msm_dp_ctrl_on_link(&ctrl->msm_dp_ctrl); @@ -2238,7 +2239,7 @@ static int msm_dp_ctrl_process_phy_test_request(struc= t msm_dp_ctrl_private *ctrl } =20 pixel_rate =3D ctrl->panel->msm_dp_mode.drm_mode.clock; - ret =3D msm_dp_ctrl_on_pixel_clk(ctrl, pixel_rate); + ret =3D msm_dp_ctrl_on_pixel_clk(ctrl, pixel_rate, ctrl->panel->stream_id= ); =20 msm_dp_ctrl_send_phy_test_pattern(ctrl); =20 @@ -2525,9 +2526,8 @@ int msm_dp_ctrl_prepare_stream_on(struct msm_dp_ctrl = *msm_dp_ctrl, bool force_li ctrl->link->link_params.rate, ctrl->link->link_params.num_lanes); =20 - drm_dbg_dp(ctrl->drm_dev, - "core_clk_on=3D%d link_clk_on=3D%d stream_clk_on=3D%d\n", - ctrl->core_clks_on, ctrl->link_clks_on, ctrl->stream_clks_on); + drm_dbg_dp(ctrl->drm_dev, "core_clk_on=3D%d link_clk_on=3D%d\n", + ctrl->core_clks_on, ctrl->link_clks_on); =20 if (!ctrl->link_clks_on) { /* link clk is off */ ret =3D msm_dp_ctrl_enable_mainlink_clocks(ctrl); @@ -2567,7 +2567,7 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_= ctrl, struct msm_dp_panel * =20 drm_dbg_dp(ctrl->drm_dev, "pixel_rate=3D%lu\n", pixel_rate); =20 - ret =3D msm_dp_ctrl_on_pixel_clk(ctrl, pixel_rate); + ret =3D msm_dp_ctrl_on_pixel_clk(ctrl, pixel_rate, msm_dp_panel->stream_i= d); if (ret) return ret; =20 @@ -2629,8 +2629,6 @@ void msm_dp_ctrl_off_link(struct msm_dp_ctrl *msm_dp_= ctrl) ctrl =3D container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctr= l); phy =3D ctrl->phy; =20 - msm_dp_panel_disable_vsc_sdp(ctrl->panel); - msm_dp_ctrl_mainlink_disable(ctrl); =20 msm_dp_ctrl_reset(&ctrl->msm_dp_ctrl); @@ -2702,6 +2700,13 @@ static const char *ctrl_clks[] =3D { "ctrl_link_iface", }; =20 +static const char * const pixel_clks[] =3D { + "stream_pixel", + "stream_1_pixel", + "stream_2_pixel", + "stream_3_pixel", +}; + static int msm_dp_ctrl_clk_init(struct msm_dp_ctrl *msm_dp_ctrl) { struct msm_dp_ctrl_private *ctrl; @@ -2735,9 +2740,17 @@ static int msm_dp_ctrl_clk_init(struct msm_dp_ctrl *= msm_dp_ctrl) if (rc) return rc; =20 - ctrl->pixel_clk =3D devm_clk_get(dev, "stream_pixel"); - if (IS_ERR(ctrl->pixel_clk)) - return PTR_ERR(ctrl->pixel_clk); + for (i =3D DP_STREAM_0; i < DP_STREAM_MAX; i++) { + ctrl->pixel_clk[i] =3D devm_clk_get(dev, pixel_clks[i]); + + if (i =3D=3D 0 && IS_ERR(ctrl->pixel_clk[i])) + return PTR_ERR(ctrl->pixel_clk[i]); + + if (IS_ERR(ctrl->pixel_clk[i])) { + DRM_DEBUG_DP("stream %d pixel clock not exist", i); + break; + } + } =20 return 0; } diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.h b/drivers/gpu/drm/msm/dp/dp_c= trl.h index b83be2252a9b..b9f0705b03ba 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.h +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.h @@ -20,7 +20,7 @@ int msm_dp_ctrl_on_link(struct msm_dp_ctrl *msm_dp_ctrl); int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl, struct msm_dp_p= anel *msm_dp_panel); int msm_dp_ctrl_prepare_stream_on(struct msm_dp_ctrl *msm_dp_ctrl, bool fo= rce_link_train); void msm_dp_ctrl_off_link(struct msm_dp_ctrl *msm_dp_ctrl); -void msm_dp_ctrl_off_pixel_clk(struct msm_dp_ctrl *msm_dp_ctrl); +void msm_dp_ctrl_off_pixel_clk(struct msm_dp_ctrl *msm_dp_ctrl, enum msm_d= p_stream_id stream_id); void msm_dp_ctrl_push_idle(struct msm_dp_ctrl *msm_dp_ctrl); irqreturn_t msm_dp_ctrl_isr(struct msm_dp_ctrl *msm_dp_ctrl); void msm_dp_ctrl_handle_sink_request(struct msm_dp_ctrl *msm_dp_ctrl); diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index 32ad00e326ba..736b621c0531 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -730,7 +730,7 @@ static int msm_dp_display_disable(struct msm_dp_display= _private *dp) =20 /* set dongle to D3 (power off) mode */ msm_dp_link_psm_config(dp->link, &dp->panel->link_info, true); - msm_dp_ctrl_off_pixel_clk(dp->ctrl); + msm_dp_ctrl_off_pixel_clk(dp->ctrl, dp->panel->stream_id); msm_dp_ctrl_off_link(dp->ctrl); /* re-init the PHY so that we can listen to Dongle disconnect */ msm_dp_ctrl_reinit_phy(dp->ctrl); @@ -739,7 +739,7 @@ static int msm_dp_display_disable(struct msm_dp_display= _private *dp) * unplugged interrupt * dongle unplugged out of DUT */ - msm_dp_ctrl_off_pixel_clk(dp->ctrl); + msm_dp_ctrl_off_pixel_clk(dp->ctrl, dp->panel->stream_id); msm_dp_ctrl_off_link(dp->ctrl); msm_dp_display_host_phy_exit(dp); } @@ -750,6 +750,24 @@ static int msm_dp_display_disable(struct msm_dp_displa= y_private *dp) return 0; } =20 +int msm_dp_display_set_stream_info(struct msm_dp *msm_dp_display, + struct msm_dp_panel *panel, enum msm_dp_stream_id stream_id) +{ + int rc =3D 0; + struct msm_dp_display_private *dp; + + dp =3D container_of(msm_dp_display, struct msm_dp_display_private, msm_dp= _display); + + if (!dp) { + DRM_ERROR("invalid input\n"); + return -EINVAL; + } + + panel->stream_id =3D stream_id; + + return rc; +} + /** * msm_dp_bridge_mode_valid - callback to determine if specified mode is v= alid * @dp: Pointer to dp display structure @@ -1451,6 +1469,8 @@ void msm_dp_display_atomic_enable(struct msm_dp *msm_= dp_display) =20 dp =3D container_of(msm_dp_display, struct msm_dp_display_private, msm_dp= _display); =20 + msm_dp_display_set_stream_info(msm_dp_display, dp->panel, 0); + rc =3D msm_dp_display_enable(dp); if (rc) DRM_ERROR("DP display enable failed, rc=3D%d\n", rc); diff --git a/drivers/gpu/drm/msm/dp/dp_display.h b/drivers/gpu/drm/msm/dp/d= p_display.h index 295da7ae0047..a5c6ed5b18e4 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.h +++ b/drivers/gpu/drm/msm/dp/dp_display.h @@ -41,5 +41,7 @@ void msm_dp_display_atomic_enable(struct msm_dp *dp_displ= ay); enum drm_mode_status msm_dp_display_mode_valid(struct msm_dp *dp, const struct drm_display_info *info, const struct drm_display_mode *mode); +int msm_dp_display_set_stream_info(struct msm_dp *msm_dp_display, + struct msm_dp_panel *panel, enum msm_dp_stream_id stream_id); =20 #endif /* _DP_DISPLAY_H_ */ diff --git a/drivers/gpu/drm/msm/dp/dp_panel.h b/drivers/gpu/drm/msm/dp/dp_= panel.h index 53b7b4463551..21f7f30e6dfd 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.h +++ b/drivers/gpu/drm/msm/dp/dp_panel.h @@ -27,6 +27,15 @@ struct msm_dp_panel_psr { u8 capabilities; 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[129.46.232.65]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-8ac84cb135fsm19223386d6.38.2026.04.10.02.34.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Apr 2026 02:35:02 -0700 (PDT) From: Yongxing Mou Date: Fri, 10 Apr 2026 17:33:49 +0800 Subject: [PATCH v4 14/39] drm/msm/dp: introduce max_streams for DP controller MST support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260410-msm-dp-mst-v4-14-b20518dea8de@oss.qualcomm.com> References: <20260410-msm-dp-mst-v4-0-b20518dea8de@oss.qualcomm.com> In-Reply-To: <20260410-msm-dp-mst-v4-0-b20518dea8de@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Jessica Zhang Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Yongxing Mou , Abhinav Kumar X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1775813628; l=6181; i=yongxing.mou@oss.qualcomm.com; s=20250910; h=from:subject:message-id; bh=plU7Urx0kW/l+Yq+gBI/qNvhT/6gNugtooXNAjfVfZs=; b=Gg3H2ELuh9AzuIzDB66IMGb489kZ2605TppVgxDeuy1g4Nr7k69mz7TAQtt6Txer8Heq7mYbL JOMF3iXz7ZtARwpnkcRp9CU6AfOFZv30ENs4bgHHiI/mqSikvRkfLPY X-Developer-Key: i=yongxing.mou@oss.qualcomm.com; a=ed25519; pk=rAy5J1eP+V7OXqH5FJ7ngMCtUrnHhut30ZTldOj52UM= X-Authority-Analysis: v=2.4 cv=PMM/P/qC c=1 sm=1 tr=0 ts=69d8c448 cx=c_pps a=7E5Bxpl4vBhpaufnMqZlrw==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=Zlm8kRnIXfIeTuhDwTwA:9 a=QEXdDO2ut3YA:10 a=pJ04lnu7RYOZP9TFuWaZ:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: bXhtmS-fsW_AfVfoe-1xDByQ8sJP8ino X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDEwMDA4OCBTYWx0ZWRfX3x1wOEkTqzbd C0jyz5ji03t4RQdJ89ZA/nl51Z4yYzeD2uyEWrSSd/z9Glm+C9Grvt9TrpYj9eFX8lRSWILuirJ jAGkHD8Rfn5wIrUwM98vawx+i2SJdov7bwvc1WuZI3oeOfGv2QWi3vTggswX4P2fYPSzA/rS1Bw LoaEateQGxDEz8by5DVaeKK+0kSqbb7KcviZ+KJX3lNePip6V5GTEjBUivGhg3bR/w9DV64gql3 4VOIxCJqx6vjaadTxgOXnmihr7oj7m83pnryvIYqllkUsqai6Fc9MKShSEXIOwYVBKMpHHNWlnS DmoXZTSDGOnspcEIZH2M6sW8SwccTfPuD0l9dwmLXArwk4Da2Ryo77v6JhUMXDszzV/4P/5vW6K vlaqeybYma3kzIedxMAZjTSQyqLsqaWqqk0DcPAtcTaVHpgzX/D+zvtsnstIhMheUEGNZaKCOhp j1isjIbjlTkQ8F06AeQ== X-Proofpoint-GUID: bXhtmS-fsW_AfVfoe-1xDByQ8sJP8ino X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-10_03,2026-04-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 suspectscore=0 priorityscore=1501 adultscore=0 lowpriorityscore=0 bulkscore=0 phishscore=0 clxscore=1015 malwarescore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604010000 definitions=main-2604100088 From: Abhinav Kumar Introduce the `mst_streams` field in each DP controller descriptor to specify the number of supported MST streams. Most platforms support 2 or 4 MST streams, while platforms without MST support default to a single stream (`DEFAULT_STREAM_COUNT =3D 1`). Also accounts for platforms with asymmetric stream support, e.g., DP0 supporting 4 streams and DP1 supporting 2. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 20 +++++++++++++++++--- drivers/gpu/drm/msm/dp/dp_ctrl.h | 2 ++ drivers/gpu/drm/msm/dp/dp_display.c | 20 +++++++++++++++++++- drivers/gpu/drm/msm/dp/dp_display.h | 1 + 4 files changed, 39 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_c= trl.c index fb6396727628..1e80d6fc7bda 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -128,6 +128,7 @@ struct msm_dp_ctrl_private { struct clk_bulk_data *link_clks; =20 struct clk *pixel_clk[DP_STREAM_MAX]; + unsigned int num_pixel_clks; =20 union phy_configure_opts phy_opts; =20 @@ -2707,7 +2708,7 @@ static const char * const pixel_clks[] =3D { "stream_3_pixel", }; =20 -static int msm_dp_ctrl_clk_init(struct msm_dp_ctrl *msm_dp_ctrl) +static int msm_dp_ctrl_clk_init(struct msm_dp_ctrl *msm_dp_ctrl, int max_s= tream) { struct msm_dp_ctrl_private *ctrl; struct device *dev; @@ -2740,7 +2741,8 @@ static int msm_dp_ctrl_clk_init(struct msm_dp_ctrl *m= sm_dp_ctrl) if (rc) return rc; =20 - for (i =3D DP_STREAM_0; i < DP_STREAM_MAX; i++) { + ctrl->num_pixel_clks =3D 0; + for (i =3D DP_STREAM_0; i < max_stream; i++) { ctrl->pixel_clk[i] =3D devm_clk_get(dev, pixel_clks[i]); =20 if (i =3D=3D 0 && IS_ERR(ctrl->pixel_clk[i])) @@ -2750,14 +2752,26 @@ static int msm_dp_ctrl_clk_init(struct msm_dp_ctrl = *msm_dp_ctrl) DRM_DEBUG_DP("stream %d pixel clock not exist", i); break; } + + ctrl->num_pixel_clks++; } =20 return 0; } =20 +int msm_dp_ctrl_get_stream_cnt(struct msm_dp_ctrl *msm_dp_ctrl) +{ + struct msm_dp_ctrl_private *ctrl; + + ctrl =3D container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctr= l); + + return ctrl->num_pixel_clks; +} + struct msm_dp_ctrl *msm_dp_ctrl_get(struct device *dev, struct msm_dp_link= *link, struct msm_dp_panel *panel, struct drm_dp_aux *aux, struct phy *phy, + int max_stream, void __iomem *ahb_base, void __iomem *link_base) { @@ -2800,7 +2814,7 @@ struct msm_dp_ctrl *msm_dp_ctrl_get(struct device *de= v, struct msm_dp_link *link ctrl->ahb_base =3D ahb_base; ctrl->link_base =3D link_base; =20 - ret =3D msm_dp_ctrl_clk_init(&ctrl->msm_dp_ctrl); + ret =3D msm_dp_ctrl_clk_init(&ctrl->msm_dp_ctrl, max_stream); if (ret) { dev_err(dev, "failed to init clocks\n"); return ERR_PTR(ret); diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.h b/drivers/gpu/drm/msm/dp/dp_c= trl.h index b9f0705b03ba..6fed3ff3a72d 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.h +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.h @@ -29,6 +29,7 @@ struct msm_dp_ctrl *msm_dp_ctrl_get(struct device *dev, struct msm_dp_panel *panel, struct drm_dp_aux *aux, struct phy *phy, + int max_stream, void __iomem *ahb_base, void __iomem *link_base); =20 @@ -47,4 +48,5 @@ void msm_dp_ctrl_enable_irq(struct msm_dp_ctrl *msm_dp_ct= rl); void msm_dp_ctrl_disable_irq(struct msm_dp_ctrl *msm_dp_ctrl); =20 void msm_dp_ctrl_reinit_phy(struct msm_dp_ctrl *msm_dp_ctrl); +int msm_dp_ctrl_get_stream_cnt(struct msm_dp_ctrl *dp_ctrl); #endif /* _DP_CTRL_H_ */ diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index 736b621c0531..7984a0f9e938 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -87,12 +87,15 @@ struct msm_dp_display_private { =20 void __iomem *p0_base; size_t p0_len; + + int max_stream; }; =20 struct msm_dp_desc { phys_addr_t io_start; unsigned int id; bool wide_bus_supported; + int mst_streams; }; =20 static const struct msm_dp_desc msm_dp_desc_glymur[] =3D { @@ -567,13 +570,15 @@ static int msm_dp_init_sub_modules(struct msm_dp_disp= lay_private *dp) } =20 dp->ctrl =3D msm_dp_ctrl_get(dev, dp->link, dp->panel, dp->aux, - phy, dp->ahb_base, dp->link_base); + phy, dp->max_stream, dp->ahb_base, dp->link_base); if (IS_ERR(dp->ctrl)) { rc =3D PTR_ERR(dp->ctrl); DRM_ERROR("failed to initialize ctrl, rc =3D %d\n", rc); dp->ctrl =3D NULL; goto error_link; } + if (dp->max_stream !=3D msm_dp_ctrl_get_stream_cnt(dp->ctrl)) + dp->max_stream =3D 1; =20 dp->audio =3D msm_dp_audio_get(dp->msm_dp_display.pdev, dp->link_base); if (IS_ERR(dp->audio)) { @@ -1208,6 +1213,15 @@ static int msm_dp_display_get_io(struct msm_dp_displ= ay_private *display) return 0; } =20 +int msm_dp_get_mst_max_stream(struct msm_dp *msm_dp_display) +{ + struct msm_dp_display_private *dp; + + dp =3D container_of(msm_dp_display, struct msm_dp_display_private, msm_dp= _display); + + return dp->max_stream; +} + static int msm_dp_display_probe(struct platform_device *pdev) { int rc =3D 0; @@ -1234,6 +1248,10 @@ static int msm_dp_display_probe(struct platform_devi= ce *pdev) dp->msm_dp_display.is_edp =3D (dp->msm_dp_display.connector_type =3D=3D DRM_MODE_CONNECTOR_eDP); dp->hpd_isr_status =3D 0; + dp->max_stream =3D 1; + + if (desc->mst_streams > 1) + dp->max_stream =3D desc->mst_streams; =20 mutex_init(&dp->plugged_lock); =20 diff --git a/drivers/gpu/drm/msm/dp/dp_display.h b/drivers/gpu/drm/msm/dp/d= p_display.h index a5c6ed5b18e4..b0cfdf215970 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.h +++ b/drivers/gpu/drm/msm/dp/dp_display.h @@ -26,6 +26,7 @@ struct msm_dp { bool psr_supported; }; =20 +int msm_dp_get_mst_max_stream(struct msm_dp *msm_dp_display); int msm_dp_display_get_modes(struct msm_dp *msm_dp_display); bool msm_dp_display_check_video_test(struct msm_dp *msm_dp_display); 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[129.46.232.65]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-8ac84cb135fsm19223386d6.38.2026.04.10.02.35.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Apr 2026 02:35:07 -0700 (PDT) From: Yongxing Mou Date: Fri, 10 Apr 2026 17:33:50 +0800 Subject: [PATCH v4 15/39] drm/msm/dp: Add support for programming p1/p2/p3 register blocks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260410-msm-dp-mst-v4-15-b20518dea8de@oss.qualcomm.com> References: <20260410-msm-dp-mst-v4-0-b20518dea8de@oss.qualcomm.com> In-Reply-To: <20260410-msm-dp-mst-v4-0-b20518dea8de@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Jessica Zhang Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Yongxing Mou , Abhinav Kumar X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1775813628; l=13269; i=yongxing.mou@oss.qualcomm.com; s=20250910; h=from:subject:message-id; bh=MOCjL1zm0UGvp3PTvJVzajVWQ2DVszPdta0rj5MJPMQ=; b=FuyO6ioRMH0q6faTAV3Lte+PDjYcPt71lyEUM5KOri/pHm3yrEQDwRlr8XR/NVJBXc5GEKPCB qUol2d+J1p8DRy7J9gIIaf2FEK5tJ9N8iEEAZM9XTH7lkK/ie1ecWIw X-Developer-Key: i=yongxing.mou@oss.qualcomm.com; a=ed25519; pk=rAy5J1eP+V7OXqH5FJ7ngMCtUrnHhut30ZTldOj52UM= X-Proofpoint-ORIG-GUID: 5bUSGK64Lt5Ijcfcc5-BwoT_lx1i7Kak X-Proofpoint-GUID: 5bUSGK64Lt5Ijcfcc5-BwoT_lx1i7Kak X-Authority-Analysis: v=2.4 cv=H/brBeYi c=1 sm=1 tr=0 ts=69d8c44d cx=c_pps a=wEM5vcRIz55oU/E2lInRtA==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=NUdAJ6xLEXsWjxoEJnsA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=OIgjcC2v60KrkQgK7BGD:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDEwMDA4OCBTYWx0ZWRfX2YYnwhl+i8q8 EsCfGkmQCw85mkTakOWprlFuNjxWuhZ1dXMTQpGpGu/BAemEdCBsYlbHGnnceKJvJ2GwYPdIgq4 pdkDP68Y/aO4L48aX8R13CqUnCyri5yYE0wH+Wni8lF3tmEdcUvNNzaOoDzY8LWMObh7Wa1DyXq DvBvimMD3hsl37oeNgt+GMGZP7oHlpM9rckpzDhvH5q6YVlW0K3drlk7sV7c4yE0ALQU0pGjLsq Zboo4O4VPDWC9VoazPDo2eoPdl36zrcCeEyuX4Quz9zJQGJTHW2QQv2bo69qqd712ZwoaFjpE9p WDFYA2NUDbUFS+EwR8fbWf8vUHNTFlnX2MRsPWew00E8vkbxX3mQDqupelzR2O43HB6ODBjelNI Ej6ue8oAsn46ZTMFVTlMPpzOEbSF+BGMljNBn/F66G2um5fQ9Ubx9A1Gn1wUHsT9euQYdjni1zv vnm20/SOGu1NQ3pWdBA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-10_03,2026-04-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 phishscore=0 adultscore=0 spamscore=0 lowpriorityscore=0 suspectscore=0 malwarescore=0 bulkscore=0 impostorscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604010000 definitions=main-2604100088 From: Abhinav Kumar Add support for additional pixel register blocks (p1, p2, p3) to enable 4=E2=80=91stream MST pixel clocks. Introduce the helper functions msm_dp_re= ad_pn and msm_dp_write_pn for pixel register programming. All pixel clocks share the same register layout but use different base addresses. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou --- drivers/gpu/drm/msm/dp/dp_display.c | 40 ++++++++++++----- drivers/gpu/drm/msm/dp/dp_panel.c | 89 ++++++++++++++++++++-------------= ---- drivers/gpu/drm/msm/dp/dp_panel.h | 3 +- 3 files changed, 79 insertions(+), 53 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index 7984a0f9e938..ff506064a3fa 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -85,8 +85,8 @@ struct msm_dp_display_private { void __iomem *link_base; size_t link_len; =20 - void __iomem *p0_base; - size_t p0_len; + void __iomem *pixel_base[DP_STREAM_MAX]; + size_t pixel_len; =20 int max_stream; }; @@ -561,7 +561,7 @@ static int msm_dp_init_sub_modules(struct msm_dp_displa= y_private *dp) goto error_link; } =20 - dp->panel =3D msm_dp_panel_get(dev, dp->aux, dp->link, dp->link_base, dp-= >p0_base); + dp->panel =3D msm_dp_panel_get(dev, dp->aux, dp->link, dp->link_base, dp-= >pixel_base[0]); if (IS_ERR(dp->panel)) { rc =3D PTR_ERR(dp->panel); DRM_ERROR("failed to initialize panel, rc =3D %d\n", rc); @@ -769,6 +769,7 @@ int msm_dp_display_set_stream_info(struct msm_dp *msm_d= p_display, } =20 panel->stream_id =3D stream_id; + msm_dp_panel_set_pixel_base(panel, dp->pixel_base[stream_id]); =20 return rc; } @@ -882,8 +883,14 @@ void msm_dp_snapshot(struct msm_disp_state *disp_state= , struct msm_dp *dp) msm_dp_display->aux_base, "dp_aux"); msm_disp_snapshot_add_block(disp_state, msm_dp_display->link_len, msm_dp_display->link_base, "dp_link"); - msm_disp_snapshot_add_block(disp_state, msm_dp_display->p0_len, - msm_dp_display->p0_base, "dp_p0"); + msm_disp_snapshot_add_block(disp_state, msm_dp_display->pixel_len, + msm_dp_display->pixel_base[0], "dp_p0"); + msm_disp_snapshot_add_block(disp_state, msm_dp_display->pixel_len, + msm_dp_display->pixel_base[1], "dp_p1"); + msm_disp_snapshot_add_block(disp_state, msm_dp_display->pixel_len, + msm_dp_display->pixel_base[2], "dp_p2"); + msm_disp_snapshot_add_block(disp_state, msm_dp_display->pixel_len, + msm_dp_display->pixel_base[3], "dp_p3"); } =20 void msm_dp_display_set_psr(struct msm_dp *msm_dp_display, bool enter) @@ -1163,6 +1170,7 @@ static void __iomem *msm_dp_ioremap(struct platform_d= evice *pdev, int idx, size_ static int msm_dp_display_get_io(struct msm_dp_display_private *display) { struct platform_device *pdev =3D display->msm_dp_display.pdev; + int i; =20 display->ahb_base =3D msm_dp_ioremap(pdev, 0, &display->ahb_len); if (IS_ERR(display->ahb_base)) @@ -1192,8 +1200,8 @@ static int msm_dp_display_get_io(struct msm_dp_displa= y_private *display) display->aux_len =3D DP_DEFAULT_AUX_SIZE; display->link_base =3D display->ahb_base + DP_DEFAULT_LINK_OFFSET; display->link_len =3D DP_DEFAULT_LINK_SIZE; - display->p0_base =3D display->ahb_base + DP_DEFAULT_P0_OFFSET; - display->p0_len =3D DP_DEFAULT_P0_SIZE; + display->pixel_base[0] =3D display->ahb_base + DP_DEFAULT_P0_OFFSET; + display->pixel_len =3D DP_DEFAULT_P0_SIZE; =20 return 0; } @@ -1204,10 +1212,20 @@ static int msm_dp_display_get_io(struct msm_dp_disp= lay_private *display) return PTR_ERR(display->link_base); } =20 - display->p0_base =3D msm_dp_ioremap(pdev, 3, &display->p0_len); - if (IS_ERR(display->p0_base)) { - DRM_ERROR("unable to remap p0 region: %pe\n", display->p0_base); - return PTR_ERR(display->p0_base); + display->pixel_base[0] =3D msm_dp_ioremap(pdev, 3, &display->pixel_len); + if (IS_ERR(display->pixel_base[0])) { + DRM_ERROR("unable to remap p0 region: %pe\n", display->pixel_base[0]); + return PTR_ERR(display->pixel_base[0]); + } + + for (i =3D DP_STREAM_1; i < display->max_stream; i++) { + /* pixels clk reg index start from 3*/ + display->pixel_base[i] =3D msm_dp_ioremap(pdev, i + 3, &display->pixel_l= en); + if (IS_ERR(display->pixel_base[i])) { + DRM_DEBUG_DP("unable to remap p%d region: %pe\n", i, + display->pixel_base[i]); + break; + } } =20 return 0; diff --git a/drivers/gpu/drm/msm/dp/dp_panel.c b/drivers/gpu/drm/msm/dp/dp_= panel.c index bde4a772d22c..c17b87353d1a 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.c +++ b/drivers/gpu/drm/msm/dp/dp_panel.c @@ -25,7 +25,7 @@ struct msm_dp_panel_private { struct drm_dp_aux *aux; struct msm_dp_link *link; void __iomem *link_base; - void __iomem *p0_base; + void __iomem *pixel_base; bool panel_on; }; =20 @@ -44,24 +44,24 @@ static inline void msm_dp_write_link(struct msm_dp_pane= l_private *panel, writel(data, panel->link_base + offset); } =20 -static inline void msm_dp_write_p0(struct msm_dp_panel_private *panel, - u32 offset, u32 data) +static inline void msm_dp_write_pn(struct msm_dp_panel_private *panel, + u32 offset, u32 data) { /* * To make sure interface reg writes happens before any other operation, * this function uses writel() instread of writel_relaxed() */ - writel(data, panel->p0_base + offset); + writel(data, panel->pixel_base + offset); } =20 -static inline u32 msm_dp_read_p0(struct msm_dp_panel_private *panel, - u32 offset) +static inline u32 msm_dp_read_pn(struct msm_dp_panel_private *panel, + u32 offset) { /* * To make sure interface reg writes happens before any other operation, * this function uses writel() instread of writel_relaxed() */ - return readl_relaxed(panel->p0_base + offset); + return readl_relaxed(panel->pixel_base + offset); } =20 static void msm_dp_panel_read_psr_cap(struct msm_dp_panel_private *panel) @@ -367,34 +367,34 @@ static void msm_dp_panel_tpg_enable(struct msm_dp_pan= el *msm_dp_panel, display_hctl =3D (hsync_end_x << 16) | hsync_start_x; =20 =20 - msm_dp_write_p0(panel, MMSS_DP_INTF_HSYNC_CTL, hsync_ctl); - msm_dp_write_p0(panel, MMSS_DP_INTF_VSYNC_PERIOD_F0, vsync_period * + msm_dp_write_pn(panel, MMSS_DP_INTF_HSYNC_CTL, hsync_ctl); + msm_dp_write_pn(panel, MMSS_DP_INTF_VSYNC_PERIOD_F0, vsync_period * hsync_period); - msm_dp_write_p0(panel, MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F0, v_sync_width * + msm_dp_write_pn(panel, MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F0, v_sync_width * hsync_period); - msm_dp_write_p0(panel, MMSS_DP_INTF_VSYNC_PERIOD_F1, 0); - msm_dp_write_p0(panel, MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F1, 0); - msm_dp_write_p0(panel, MMSS_DP_INTF_DISPLAY_HCTL, display_hctl); - msm_dp_write_p0(panel, MMSS_DP_INTF_ACTIVE_HCTL, 0); - msm_dp_write_p0(panel, MMSS_INTF_DISPLAY_V_START_F0, display_v_start); - msm_dp_write_p0(panel, MMSS_DP_INTF_DISPLAY_V_END_F0, display_v_end); - msm_dp_write_p0(panel, MMSS_INTF_DISPLAY_V_START_F1, 0); - msm_dp_write_p0(panel, MMSS_DP_INTF_DISPLAY_V_END_F1, 0); - msm_dp_write_p0(panel, MMSS_DP_INTF_ACTIVE_V_START_F0, 0); - msm_dp_write_p0(panel, MMSS_DP_INTF_ACTIVE_V_END_F0, 0); - msm_dp_write_p0(panel, MMSS_DP_INTF_ACTIVE_V_START_F1, 0); - msm_dp_write_p0(panel, MMSS_DP_INTF_ACTIVE_V_END_F1, 0); - msm_dp_write_p0(panel, MMSS_DP_INTF_POLARITY_CTL, 0); - - msm_dp_write_p0(panel, MMSS_DP_TPG_MAIN_CONTROL, - DP_TPG_CHECKERED_RECT_PATTERN); - msm_dp_write_p0(panel, MMSS_DP_TPG_VIDEO_CONFIG, - DP_TPG_VIDEO_CONFIG_BPP_8BIT | - DP_TPG_VIDEO_CONFIG_RGB); - msm_dp_write_p0(panel, MMSS_DP_BIST_ENABLE, - DP_BIST_ENABLE_DPBIST_EN); - msm_dp_write_p0(panel, MMSS_DP_TIMING_ENGINE_EN, - DP_TIMING_ENGINE_EN_EN); + msm_dp_write_pn(panel, MMSS_DP_INTF_VSYNC_PERIOD_F1, 0); + msm_dp_write_pn(panel, MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F1, 0); + msm_dp_write_pn(panel, MMSS_DP_INTF_DISPLAY_HCTL, display_hctl); + msm_dp_write_pn(panel, MMSS_DP_INTF_ACTIVE_HCTL, 0); + msm_dp_write_pn(panel, MMSS_INTF_DISPLAY_V_START_F0, display_v_start); + msm_dp_write_pn(panel, MMSS_DP_INTF_DISPLAY_V_END_F0, display_v_end); + msm_dp_write_pn(panel, MMSS_INTF_DISPLAY_V_START_F1, 0); + msm_dp_write_pn(panel, MMSS_DP_INTF_DISPLAY_V_END_F1, 0); + msm_dp_write_pn(panel, MMSS_DP_INTF_ACTIVE_V_START_F0, 0); + msm_dp_write_pn(panel, MMSS_DP_INTF_ACTIVE_V_END_F0, 0); + msm_dp_write_pn(panel, MMSS_DP_INTF_ACTIVE_V_START_F1, 0); + msm_dp_write_pn(panel, MMSS_DP_INTF_ACTIVE_V_END_F1, 0); + msm_dp_write_pn(panel, MMSS_DP_INTF_POLARITY_CTL, 0); + + msm_dp_write_pn(panel, MMSS_DP_TPG_MAIN_CONTROL, + DP_TPG_CHECKERED_RECT_PATTERN); + msm_dp_write_pn(panel, MMSS_DP_TPG_VIDEO_CONFIG, + DP_TPG_VIDEO_CONFIG_BPP_8BIT | + DP_TPG_VIDEO_CONFIG_RGB); + msm_dp_write_pn(panel, MMSS_DP_BIST_ENABLE, + DP_BIST_ENABLE_DPBIST_EN); + msm_dp_write_pn(panel, MMSS_DP_TIMING_ENGINE_EN, + DP_TIMING_ENGINE_EN_EN); drm_dbg_dp(panel->drm_dev, "%s: enabled tpg\n", __func__); } =20 @@ -403,9 +403,9 @@ static void msm_dp_panel_tpg_disable(struct msm_dp_pane= l *msm_dp_panel) struct msm_dp_panel_private *panel =3D container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); =20 - msm_dp_write_p0(panel, MMSS_DP_TPG_MAIN_CONTROL, 0x0); - msm_dp_write_p0(panel, MMSS_DP_BIST_ENABLE, 0x0); - msm_dp_write_p0(panel, MMSS_DP_TIMING_ENGINE_EN, 0x0); + msm_dp_write_pn(panel, MMSS_DP_TPG_MAIN_CONTROL, 0x0); + msm_dp_write_pn(panel, MMSS_DP_BIST_ENABLE, 0x0); + msm_dp_write_pn(panel, MMSS_DP_TIMING_ENGINE_EN, 0x0); } =20 void msm_dp_panel_tpg_config(struct msm_dp_panel *msm_dp_panel, bool enabl= e) @@ -439,7 +439,7 @@ void msm_dp_panel_clear_dsc_dto(struct msm_dp_panel *ms= m_dp_panel) struct msm_dp_panel_private *panel =3D container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); =20 - msm_dp_write_p0(panel, MMSS_DP_DSC_DTO, 0x0); + msm_dp_write_pn(panel, MMSS_DP_DSC_DTO, 0x0); } =20 static void msm_dp_panel_send_vsc_sdp(struct msm_dp_panel_private *panel, = struct dp_sdp *vsc_sdp) @@ -629,7 +629,7 @@ int msm_dp_panel_timing_cfg(struct msm_dp_panel *msm_dp= _panel, bool wide_bus_en) msm_dp_write_link(panel, REG_DP_HSYNC_VSYNC_WIDTH_POLARITY, width_blankin= g); msm_dp_write_link(panel, REG_DP_ACTIVE_HOR_VER, msm_dp_active); =20 - reg =3D msm_dp_read_p0(panel, MMSS_DP_INTF_CONFIG); + reg =3D msm_dp_read_pn(panel, MMSS_DP_INTF_CONFIG); if (wide_bus_en) reg |=3D DP_INTF_CONFIG_DATABUS_WIDEN; else @@ -637,7 +637,7 @@ int msm_dp_panel_timing_cfg(struct msm_dp_panel *msm_dp= _panel, bool wide_bus_en) =20 drm_dbg_dp(panel->drm_dev, "wide_bus_en=3D%d reg=3D%#x\n", wide_bus_en, r= eg); =20 - msm_dp_write_p0(panel, MMSS_DP_INTF_CONFIG, reg); + msm_dp_write_pn(panel, MMSS_DP_INTF_CONFIG, reg); =20 if (msm_dp_panel->msm_dp_mode.out_fmt_is_yuv_420) msm_dp_panel_setup_vsc_sdp_yuv_420(msm_dp_panel); @@ -647,6 +647,13 @@ int msm_dp_panel_timing_cfg(struct msm_dp_panel *msm_d= p_panel, bool wide_bus_en) return 0; } =20 +void msm_dp_panel_set_pixel_base(struct msm_dp_panel *msm_dp_panel, void _= _iomem *pixel_base) +{ + struct msm_dp_panel_private *panel =3D + container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); + panel->pixel_base =3D pixel_base; +} + int msm_dp_panel_init_panel_info(struct msm_dp_panel *msm_dp_panel) { struct drm_display_mode *drm_mode; @@ -689,7 +696,7 @@ int msm_dp_panel_init_panel_info(struct msm_dp_panel *m= sm_dp_panel) struct msm_dp_panel *msm_dp_panel_get(struct device *dev, struct drm_dp_au= x *aux, struct msm_dp_link *link, void __iomem *link_base, - void __iomem *p0_base) + void __iomem *pixel_base) { struct msm_dp_panel_private *panel; struct msm_dp_panel *msm_dp_panel; @@ -707,7 +714,7 @@ struct msm_dp_panel *msm_dp_panel_get(struct device *de= v, struct drm_dp_aux *aux panel->aux =3D aux; panel->link =3D link; panel->link_base =3D link_base; - panel->p0_base =3D p0_base; + panel->pixel_base =3D pixel_base; =20 msm_dp_panel =3D &panel->msm_dp_panel; msm_dp_panel->max_bw_code =3D DP_LINK_BW_8_1; diff --git a/drivers/gpu/drm/msm/dp/dp_panel.h b/drivers/gpu/drm/msm/dp/dp_= panel.h index 21f7f30e6dfd..fe4ac3e47e17 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.h +++ b/drivers/gpu/drm/msm/dp/dp_panel.h @@ -66,6 +66,7 @@ void msm_dp_panel_handle_sink_request(struct msm_dp_panel= *msm_dp_panel, void msm_dp_panel_tpg_config(struct msm_dp_panel *msm_dp_panel, bool enabl= e); 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Stream 1 share the same link clk with stream 0 with different reg offset. Also add additional register defines for stream 1. Streams 2 and 3 are not covered here, as they use separate link clocks and require separate handling. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 24 ++++++++++--- drivers/gpu/drm/msm/dp/dp_panel.c | 72 +++++++++++++++++++++++++++--------= ---- drivers/gpu/drm/msm/dp/dp_reg.h | 11 ++++++ 3 files changed, 81 insertions(+), 26 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_c= trl.c index 1e80d6fc7bda..a52bcd9ea2a3 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -393,6 +393,7 @@ static void msm_dp_ctrl_config_ctrl_streams(struct msm_= dp_ctrl_private *ctrl, struct msm_dp_panel *msm_dp_panel) { u32 config =3D 0, tbd; + u32 reg_offset =3D 0; =20 config =3D msm_dp_read_link(ctrl, REG_DP_CONFIGURATION_CTRL); =20 @@ -409,7 +410,8 @@ static void msm_dp_ctrl_config_ctrl_streams(struct msm_= dp_ctrl_private *ctrl, =20 drm_dbg_dp(ctrl->drm_dev, "stream DP_CONFIGURATION_CTRL=3D0x%x\n", config= ); =20 - msm_dp_write_link(ctrl, REG_DP_CONFIGURATION_CTRL, config); + if (msm_dp_panel->stream_id =3D=3D DP_STREAM_1) + reg_offset =3D REG_DP1_CONFIGURATION_CTRL - REG_DP_CONFIGURATION_CTRL; } =20 static void msm_dp_ctrl_config_ctrl_link(struct msm_dp_ctrl_private *ctrl) @@ -460,12 +462,16 @@ static void msm_dp_ctrl_config_misc1_misc0(struct msm= _dp_ctrl_private *ctrl, struct msm_dp_panel *msm_dp_panel) { u32 colorimetry_cfg, test_bits_depth, misc_val; + u32 reg_offset =3D 0; =20 test_bits_depth =3D msm_dp_link_get_test_bits_depth(ctrl->link, msm_dp_panel->msm_dp_mode.bpp); colorimetry_cfg =3D msm_dp_link_get_colorimetry_config(ctrl->link); =20 - misc_val =3D msm_dp_read_link(ctrl, REG_DP_MISC1_MISC0); + if (msm_dp_panel->stream_id =3D=3D DP_STREAM_1) + reg_offset =3D REG_DP1_MISC1_MISC0 - REG_DP_MISC1_MISC0; + + misc_val =3D msm_dp_read_link(ctrl, REG_DP_MISC1_MISC0 + reg_offset); =20 /* clear bpp bits */ misc_val &=3D ~(0x07 << DP_MISC0_TEST_BITS_DEPTH_SHIFT); @@ -475,7 +481,7 @@ static void msm_dp_ctrl_config_misc1_misc0(struct msm_d= p_ctrl_private *ctrl, misc_val |=3D DP_MISC0_SYNCHRONOUS_CLK; =20 drm_dbg_dp(ctrl->drm_dev, "misc settings =3D 0x%x\n", misc_val); - msm_dp_write_link(ctrl, REG_DP_MISC1_MISC0, misc_val); + msm_dp_write_link(ctrl, REG_DP_MISC1_MISC0 + reg_offset, misc_val); } =20 static void msm_dp_ctrl_configure_source_params(struct msm_dp_ctrl_private= *ctrl, @@ -2446,6 +2452,7 @@ static int msm_dp_ctrl_link_retrain(struct msm_dp_ctr= l_private *ctrl) } =20 static void msm_dp_ctrl_config_msa(struct msm_dp_ctrl_private *ctrl, + struct msm_dp_panel *msm_dp_panel, u32 rate, u32 stream_rate_khz, bool is_ycbcr_420) { @@ -2455,6 +2462,12 @@ static void msm_dp_ctrl_config_msa(struct msm_dp_ctr= l_private *ctrl, u32 const link_rate_hbr2 =3D 540000; u32 const link_rate_hbr3 =3D 810000; unsigned long den, num; + u32 mvid_reg_off =3D 0, nvid_reg_off =3D 0; + + if (msm_dp_panel->stream_id =3D=3D DP_STREAM_1) { + mvid_reg_off =3D REG_DP1_SOFTWARE_MVID - REG_DP_SOFTWARE_MVID; + nvid_reg_off =3D REG_DP1_SOFTWARE_NVID - REG_DP_SOFTWARE_NVID; + } =20 switch (rate) { case link_rate_hbr3: @@ -2509,8 +2522,8 @@ static void msm_dp_ctrl_config_msa(struct msm_dp_ctrl= _private *ctrl, nvid *=3D 3; =20 drm_dbg_dp(ctrl->drm_dev, "mvid=3D0x%x, nvid=3D0x%x\n", mvid, nvid); - msm_dp_write_link(ctrl, REG_DP_SOFTWARE_MVID, mvid); - msm_dp_write_link(ctrl, REG_DP_SOFTWARE_NVID, nvid); + msm_dp_write_link(ctrl, REG_DP_SOFTWARE_MVID + mvid_reg_off, mvid); + msm_dp_write_link(ctrl, REG_DP_SOFTWARE_NVID + nvid_reg_off, nvid); } =20 int msm_dp_ctrl_prepare_stream_on(struct msm_dp_ctrl *msm_dp_ctrl, bool fo= rce_link_train) @@ -2585,6 +2598,7 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_= ctrl, struct msm_dp_panel * msm_dp_ctrl_configure_source_params(ctrl, msm_dp_panel); =20 msm_dp_ctrl_config_msa(ctrl, + msm_dp_panel, ctrl->link->link_params.rate, pixel_rate_orig, msm_dp_panel->msm_dp_mode.out_fmt_is_yuv_420); diff --git a/drivers/gpu/drm/msm/dp/dp_panel.c b/drivers/gpu/drm/msm/dp/dp_= panel.c index c17b87353d1a..6c88cc7e3037 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.c +++ b/drivers/gpu/drm/msm/dp/dp_panel.c @@ -447,27 +447,35 @@ static void msm_dp_panel_send_vsc_sdp(struct msm_dp_p= anel_private *panel, struct u32 header[2]; u32 val; int i; + u32 offset =3D 0; + + if (panel->msm_dp_panel.stream_id =3D=3D DP_STREAM_1) + offset =3D MMSS_DP1_GENERIC0_0 - MMSS_DP_GENERIC0_0; =20 msm_dp_utils_pack_sdp_header(&vsc_sdp->sdp_header, header); =20 - msm_dp_write_link(panel, MMSS_DP_GENERIC0_0, header[0]); - msm_dp_write_link(panel, MMSS_DP_GENERIC0_1, header[1]); + msm_dp_write_link(panel, MMSS_DP_GENERIC0_0 + offset, header[0]); + msm_dp_write_link(panel, MMSS_DP_GENERIC0_1 + offset, header[1]); =20 for (i =3D 0; i < sizeof(vsc_sdp->db); i +=3D 4) { val =3D ((vsc_sdp->db[i]) | (vsc_sdp->db[i + 1] << 8) | (vsc_sdp->db[i += 2] << 16) | (vsc_sdp->db[i + 3] << 24)); - msm_dp_write_link(panel, MMSS_DP_GENERIC0_2 + i, val); + msm_dp_write_link(panel, MMSS_DP_GENERIC0_2 + i + offset, val); } } =20 static void msm_dp_panel_update_sdp(struct msm_dp_panel_private *panel) { u32 hw_revision =3D panel->msm_dp_panel.hw_revision; + u32 offset =3D 0; + + if (panel->msm_dp_panel.stream_id =3D=3D DP_STREAM_1) + offset =3D MMSS_DP1_SDP_CFG3 - MMSS_DP_SDP_CFG3; =20 if (hw_revision >=3D DP_HW_VERSION_1_0 && hw_revision < DP_HW_VERSION_1_2) { - msm_dp_write_link(panel, MMSS_DP_SDP_CFG3, UPDATE_SDP); - msm_dp_write_link(panel, MMSS_DP_SDP_CFG3, 0x0); + msm_dp_write_link(panel, MMSS_DP_SDP_CFG3 + offset, UPDATE_SDP); + msm_dp_write_link(panel, MMSS_DP_SDP_CFG3 + offset, 0x0); } } =20 @@ -476,16 +484,25 @@ void msm_dp_panel_enable_vsc_sdp(struct msm_dp_panel = *msm_dp_panel, struct dp_sd struct msm_dp_panel_private *panel =3D container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); u32 cfg, cfg2, misc; + u32 misc_reg_offset =3D 0; + u32 sdp_cfg_offset =3D 0; + u32 sdp_cfg2_offset =3D 0; + + if (msm_dp_panel->stream_id =3D=3D DP_STREAM_1) { + misc_reg_offset =3D REG_DP1_MISC1_MISC0 - REG_DP_MISC1_MISC0; + sdp_cfg_offset =3D MMSS_DP1_SDP_CFG - MMSS_DP_SDP_CFG; + sdp_cfg2_offset =3D MMSS_DP1_SDP_CFG2 - MMSS_DP_SDP_CFG2; + } =20 - cfg =3D msm_dp_read_link(panel, MMSS_DP_SDP_CFG); - cfg2 =3D msm_dp_read_link(panel, MMSS_DP_SDP_CFG2); - misc =3D msm_dp_read_link(panel, REG_DP_MISC1_MISC0); + cfg =3D msm_dp_read_link(panel, MMSS_DP_SDP_CFG + sdp_cfg_offset); + cfg2 =3D msm_dp_read_link(panel, MMSS_DP_SDP_CFG2 + sdp_cfg2_offset); + misc =3D msm_dp_read_link(panel, REG_DP_MISC1_MISC0 + misc_reg_offset); =20 cfg |=3D GEN0_SDP_EN; - msm_dp_write_link(panel, MMSS_DP_SDP_CFG, cfg); + msm_dp_write_link(panel, MMSS_DP_SDP_CFG + sdp_cfg_offset, cfg); =20 cfg2 |=3D GENERIC0_SDPSIZE_VALID; - msm_dp_write_link(panel, MMSS_DP_SDP_CFG2, cfg2); + msm_dp_write_link(panel, MMSS_DP_SDP_CFG2 + sdp_cfg2_offset, cfg2); =20 msm_dp_panel_send_vsc_sdp(panel, vsc_sdp); =20 @@ -495,7 +512,7 @@ void msm_dp_panel_enable_vsc_sdp(struct msm_dp_panel *m= sm_dp_panel, struct dp_sd drm_dbg_dp(panel->drm_dev, "vsc sdp enable=3D1\n"); =20 pr_debug("misc settings =3D 0x%x\n", misc); - msm_dp_write_link(panel, REG_DP_MISC1_MISC0, misc); + msm_dp_write_link(panel, REG_DP_MISC1_MISC0 + misc_reg_offset, misc); =20 msm_dp_panel_update_sdp(panel); } @@ -505,16 +522,25 @@ void msm_dp_panel_disable_vsc_sdp(struct msm_dp_panel= *msm_dp_panel) struct msm_dp_panel_private *panel =3D container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); u32 cfg, cfg2, misc; + u32 misc_reg_offset =3D 0; + u32 sdp_cfg_offset =3D 0; + u32 sdp_cfg2_offset =3D 0; + + if (msm_dp_panel->stream_id =3D=3D DP_STREAM_1) { + misc_reg_offset =3D REG_DP1_MISC1_MISC0 - REG_DP_MISC1_MISC0; + sdp_cfg_offset =3D MMSS_DP1_SDP_CFG - MMSS_DP_SDP_CFG; + sdp_cfg2_offset =3D MMSS_DP1_SDP_CFG2 - MMSS_DP_SDP_CFG2; + } =20 - cfg =3D msm_dp_read_link(panel, MMSS_DP_SDP_CFG); - cfg2 =3D msm_dp_read_link(panel, MMSS_DP_SDP_CFG2); - misc =3D msm_dp_read_link(panel, REG_DP_MISC1_MISC0); + cfg =3D msm_dp_read_link(panel, MMSS_DP_SDP_CFG + sdp_cfg_offset); + cfg2 =3D msm_dp_read_link(panel, MMSS_DP_SDP_CFG2 + sdp_cfg2_offset); + misc =3D msm_dp_read_link(panel, REG_DP_MISC1_MISC0 + misc_reg_offset); =20 cfg &=3D ~GEN0_SDP_EN; - msm_dp_write_link(panel, MMSS_DP_SDP_CFG, cfg); + msm_dp_write_link(panel, MMSS_DP_SDP_CFG + sdp_cfg_offset, cfg); =20 cfg2 &=3D ~GENERIC0_SDPSIZE_VALID; - msm_dp_write_link(panel, MMSS_DP_SDP_CFG2, cfg2); + msm_dp_write_link(panel, MMSS_DP_SDP_CFG2 + sdp_cfg2_offset, cfg2); =20 /* switch back to MSA */ misc &=3D ~DP_MISC1_VSC_SDP; @@ -522,7 +548,7 @@ void msm_dp_panel_disable_vsc_sdp(struct msm_dp_panel *= msm_dp_panel) drm_dbg_dp(panel->drm_dev, "vsc sdp enable=3D0\n"); =20 pr_debug("misc settings =3D 0x%x\n", misc); - msm_dp_write_link(panel, REG_DP_MISC1_MISC0, misc); + msm_dp_write_link(panel, REG_DP_MISC1_MISC0 + misc_reg_offset, misc); =20 msm_dp_panel_update_sdp(panel); } @@ -580,6 +606,7 @@ int msm_dp_panel_timing_cfg(struct msm_dp_panel *msm_dp= _panel, bool wide_bus_en) u32 msm_dp_active; u32 total; u32 reg; + u32 offset =3D 0; =20 panel =3D container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_= panel); drm_mode =3D &panel->msm_dp_panel.msm_dp_mode.drm_mode; @@ -594,6 +621,9 @@ int msm_dp_panel_timing_cfg(struct msm_dp_panel *msm_dp= _panel, bool wide_bus_en) drm_mode->vsync_start - drm_mode->vdisplay, drm_mode->vsync_end - drm_mode->vsync_start); =20 + if (msm_dp_panel->stream_id =3D=3D DP_STREAM_1) + offset =3D REG_DP1_TOTAL_HOR_VER - REG_DP_TOTAL_HOR_VER; + total_hor =3D drm_mode->htotal; =20 total_ver =3D drm_mode->vtotal; @@ -624,10 +654,10 @@ int msm_dp_panel_timing_cfg(struct msm_dp_panel *msm_= dp_panel, bool wide_bus_en) =20 msm_dp_active =3D data; =20 - msm_dp_write_link(panel, REG_DP_TOTAL_HOR_VER, total); - msm_dp_write_link(panel, REG_DP_START_HOR_VER_FROM_SYNC, sync_start); - msm_dp_write_link(panel, REG_DP_HSYNC_VSYNC_WIDTH_POLARITY, width_blankin= g); - msm_dp_write_link(panel, REG_DP_ACTIVE_HOR_VER, msm_dp_active); + msm_dp_write_link(panel, REG_DP_TOTAL_HOR_VER + offset, total); + msm_dp_write_link(panel, REG_DP_START_HOR_VER_FROM_SYNC + offset, sync_s= tart); + msm_dp_write_link(panel, REG_DP_HSYNC_VSYNC_WIDTH_POLARITY + offset, widt= h_blanking); + msm_dp_write_link(panel, REG_DP_ACTIVE_HOR_VER + offset, msm_dp_active); =20 reg =3D msm_dp_read_pn(panel, MMSS_DP_INTF_CONFIG); if (wide_bus_en) diff --git a/drivers/gpu/drm/msm/dp/dp_reg.h b/drivers/gpu/drm/msm/dp/dp_re= g.h index 3689642b7fc0..295c1161e6b7 100644 --- a/drivers/gpu/drm/msm/dp/dp_reg.h +++ b/drivers/gpu/drm/msm/dp/dp_reg.h @@ -332,6 +332,17 @@ #define DP_TPG_VIDEO_CONFIG_BPP_8BIT (0x00000001) #define DP_TPG_VIDEO_CONFIG_RGB (0x00000004) =20 +/* DP MST registers */ +#define REG_DP1_CONFIGURATION_CTRL (0x00000400) +#define REG_DP1_SOFTWARE_MVID (0x00000414) +#define REG_DP1_SOFTWARE_NVID (0x00000418) +#define REG_DP1_TOTAL_HOR_VER (0x0000041C) +#define REG_DP1_MISC1_MISC0 (0x0000042C) +#define MMSS_DP1_GENERIC0_0 (0x00000490) +#define MMSS_DP1_SDP_CFG (0x000004E0) +#define MMSS_DP1_SDP_CFG2 (0x000004E4) +#define MMSS_DP1_SDP_CFG3 (0x000004E8) + #define MMSS_DP_ASYNC_FIFO_CONFIG (0x00000088) =20 #define REG_DP_PHY_AUX_INTERRUPT_CLEAR (0x0000004C) --=20 2.43.0 From nobody Sat Apr 18 10:45:33 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C86E734CFC2 for ; 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Signed-off-by: Yongxing Mou --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 225 ++++++++++++++++++++++----------= ---- drivers/gpu/drm/msm/dp/dp_ctrl.h | 4 +- drivers/gpu/drm/msm/dp/dp_display.c | 24 +++- drivers/gpu/drm/msm/dp/dp_panel.c | 135 +++++++++++++++++----- drivers/gpu/drm/msm/dp/dp_panel.h | 2 + drivers/gpu/drm/msm/dp/dp_reg.h | 16 ++- 6 files changed, 283 insertions(+), 123 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_c= trl.c index a52bcd9ea2a3..1109b2df21be 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -118,6 +118,8 @@ struct msm_dp_ctrl_private { struct msm_dp_link *link; void __iomem *ahb_base; void __iomem *link_base; + void __iomem *mst2link_base; + void __iomem *mst3link_base; =20 struct phy *phy; =20 @@ -158,19 +160,45 @@ static inline void msm_dp_write_ahb(struct msm_dp_ctr= l_private *ctrl, writel(data, ctrl->ahb_base + offset); } =20 -static inline u32 msm_dp_read_link(struct msm_dp_ctrl_private *ctrl, u32 o= ffset) +static inline u32 msm_dp_read_link(struct msm_dp_ctrl_private *ctrl, + enum msm_dp_stream_id stream_id, u32 offset) { - return readl_relaxed(ctrl->link_base + offset); + switch (stream_id) { + case DP_STREAM_0: + case DP_STREAM_1: + return readl_relaxed(ctrl->link_base + offset); + case DP_STREAM_2: + return readl_relaxed(ctrl->mst2link_base + offset); + case DP_STREAM_3: + return readl_relaxed(ctrl->mst3link_base + offset); + default: + DRM_ERROR("error stream_id\n"); + return 0; + } } =20 static inline void msm_dp_write_link(struct msm_dp_ctrl_private *ctrl, - u32 offset, u32 data) + enum msm_dp_stream_id stream_id, u32 offset, u32 data) { /* * To make sure link reg writes happens before any other operation, * this function uses writel() instread of writel_relaxed() */ - writel(data, ctrl->link_base + offset); + switch (stream_id) { + case DP_STREAM_0: + case DP_STREAM_1: + writel(data, ctrl->link_base + offset); + break; + case DP_STREAM_2: + writel(data, ctrl->mst2link_base + offset); + break; + case DP_STREAM_3: + writel(data, ctrl->mst3link_base + offset); + break; + default: + DRM_ERROR("error stream_id\n"); + break; + } } =20 static int msm_dp_aux_link_configure(struct drm_dp_aux *aux, @@ -294,18 +322,18 @@ static void msm_dp_ctrl_psr_mainlink_enable(struct ms= m_dp_ctrl_private *ctrl) { u32 val; =20 - val =3D msm_dp_read_link(ctrl, REG_DP_MAINLINK_CTRL); + val =3D msm_dp_read_link(ctrl, 0, REG_DP_MAINLINK_CTRL); val |=3D DP_MAINLINK_CTRL_ENABLE; - msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, val); + msm_dp_write_link(ctrl, 0, REG_DP_MAINLINK_CTRL, val); } =20 static void msm_dp_ctrl_psr_mainlink_disable(struct msm_dp_ctrl_private *c= trl) { u32 val; =20 - val =3D msm_dp_read_link(ctrl, REG_DP_MAINLINK_CTRL); + val =3D msm_dp_read_link(ctrl, 0, REG_DP_MAINLINK_CTRL); val &=3D ~DP_MAINLINK_CTRL_ENABLE; - msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, val); + msm_dp_write_link(ctrl, 0, REG_DP_MAINLINK_CTRL, val); } =20 static void msm_dp_ctrl_mainlink_enable(struct msm_dp_ctrl_private *ctrl) @@ -314,21 +342,21 @@ static void msm_dp_ctrl_mainlink_enable(struct msm_dp= _ctrl_private *ctrl) =20 drm_dbg_dp(ctrl->drm_dev, "enable\n"); =20 - mainlink_ctrl =3D msm_dp_read_link(ctrl, REG_DP_MAINLINK_CTRL); + mainlink_ctrl =3D msm_dp_read_link(ctrl, 0, REG_DP_MAINLINK_CTRL); =20 mainlink_ctrl &=3D ~(DP_MAINLINK_CTRL_RESET | DP_MAINLINK_CTRL_ENABLE); - msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, mainlink_ctrl); + msm_dp_write_link(ctrl, 0, REG_DP_MAINLINK_CTRL, mainlink_ctrl); =20 mainlink_ctrl |=3D DP_MAINLINK_CTRL_RESET; - msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, mainlink_ctrl); + msm_dp_write_link(ctrl, 0, REG_DP_MAINLINK_CTRL, mainlink_ctrl); =20 mainlink_ctrl &=3D ~DP_MAINLINK_CTRL_RESET; - msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, mainlink_ctrl); + msm_dp_write_link(ctrl, 0, REG_DP_MAINLINK_CTRL, mainlink_ctrl); =20 mainlink_ctrl |=3D (DP_MAINLINK_CTRL_ENABLE | DP_MAINLINK_FB_BOUNDARY_SEL); - msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, mainlink_ctrl); + msm_dp_write_link(ctrl, 0, REG_DP_MAINLINK_CTRL, mainlink_ctrl); } =20 static void msm_dp_ctrl_mainlink_disable(struct msm_dp_ctrl_private *ctrl) @@ -337,23 +365,23 @@ static void msm_dp_ctrl_mainlink_disable(struct msm_d= p_ctrl_private *ctrl) =20 drm_dbg_dp(ctrl->drm_dev, "disable\n"); =20 - mainlink_ctrl =3D msm_dp_read_link(ctrl, REG_DP_MAINLINK_CTRL); + mainlink_ctrl =3D msm_dp_read_link(ctrl, 0, REG_DP_MAINLINK_CTRL); mainlink_ctrl &=3D ~DP_MAINLINK_CTRL_ENABLE; - msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, mainlink_ctrl); + msm_dp_write_link(ctrl, 0, REG_DP_MAINLINK_CTRL, mainlink_ctrl); } =20 static void msm_dp_setup_peripheral_flush(struct msm_dp_ctrl_private *ctrl) { u32 mainlink_ctrl; =20 - mainlink_ctrl =3D msm_dp_read_link(ctrl, REG_DP_MAINLINK_CTRL); + mainlink_ctrl =3D msm_dp_read_link(ctrl, 0, REG_DP_MAINLINK_CTRL); =20 if (ctrl->hw_revision >=3D DP_HW_VERSION_1_2) mainlink_ctrl |=3D DP_MAINLINK_FLUSH_MODE_SDE_PERIPH_UPDATE; else mainlink_ctrl |=3D DP_MAINLINK_FLUSH_MODE_UPDATE_SDP; =20 - msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, mainlink_ctrl); + msm_dp_write_link(ctrl, 0, REG_DP_MAINLINK_CTRL, mainlink_ctrl); } =20 static bool msm_dp_ctrl_mainlink_ready(struct msm_dp_ctrl_private *ctrl) @@ -380,7 +408,7 @@ void msm_dp_ctrl_push_idle(struct msm_dp_ctrl *msm_dp_c= trl) ctrl =3D container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctr= l); =20 reinit_completion(&ctrl->idle_comp); - msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, DP_STATE_CTRL_PUSH_IDLE); + msm_dp_write_link(ctrl, 0, REG_DP_STATE_CTRL, DP_STATE_CTRL_PUSH_IDLE); =20 if (!wait_for_completion_timeout(&ctrl->idle_comp, IDLE_PATTERN_COMPLETION_TIMEOUT_JIFFIES)) @@ -395,7 +423,11 @@ static void msm_dp_ctrl_config_ctrl_streams(struct msm= _dp_ctrl_private *ctrl, u32 config =3D 0, tbd; u32 reg_offset =3D 0; =20 - config =3D msm_dp_read_link(ctrl, REG_DP_CONFIGURATION_CTRL); + if (msm_dp_panel->stream_id =3D=3D DP_STREAM_0) + config =3D msm_dp_read_link(ctrl, 0, REG_DP_CONFIGURATION_CTRL); + + if (msm_dp_panel->stream_id =3D=3D DP_STREAM_1) + reg_offset =3D REG_DP1_CONFIGURATION_CTRL - REG_DP_CONFIGURATION_CTRL; =20 if (msm_dp_panel->msm_dp_mode.out_fmt_is_yuv_420) config |=3D DP_CONFIGURATION_CTRL_RGB_YUV; /* YUV420 */ @@ -410,8 +442,10 @@ static void msm_dp_ctrl_config_ctrl_streams(struct msm= _dp_ctrl_private *ctrl, =20 drm_dbg_dp(ctrl->drm_dev, "stream DP_CONFIGURATION_CTRL=3D0x%x\n", config= ); =20 - if (msm_dp_panel->stream_id =3D=3D DP_STREAM_1) - reg_offset =3D REG_DP1_CONFIGURATION_CTRL - REG_DP_CONFIGURATION_CTRL; + msm_dp_write_link(ctrl, msm_dp_panel->stream_id, msm_dp_panel->stream_id = > 1 ? + REG_DP_MSTLINK_CONFIGURATION_CTRL : + REG_DP_CONFIGURATION_CTRL + reg_offset, config); + } =20 static void msm_dp_ctrl_config_ctrl_link(struct msm_dp_ctrl_private *ctrl) @@ -441,7 +475,7 @@ static void msm_dp_ctrl_config_ctrl_link(struct msm_dp_= ctrl_private *ctrl) =20 drm_dbg_dp(ctrl->drm_dev, "link DP_CONFIGURATION_CTRL=3D0x%x\n", config); =20 - msm_dp_write_link(ctrl, REG_DP_CONFIGURATION_CTRL, config); + msm_dp_write_link(ctrl, 0, REG_DP_CONFIGURATION_CTRL, config); } =20 static void msm_dp_ctrl_lane_mapping(struct msm_dp_ctrl_private *ctrl) @@ -454,8 +488,8 @@ static void msm_dp_ctrl_lane_mapping(struct msm_dp_ctrl= _private *ctrl) ln_mapping |=3D lane_map[2] << LANE2_MAPPING_SHIFT; ln_mapping |=3D lane_map[3] << LANE3_MAPPING_SHIFT; =20 - msm_dp_write_link(ctrl, REG_DP_LOGICAL2PHYSICAL_LANE_MAPPING, - ln_mapping); + msm_dp_write_link(ctrl, 0, REG_DP_LOGICAL2PHYSICAL_LANE_MAPPING, + ln_mapping); } =20 static void msm_dp_ctrl_config_misc1_misc0(struct msm_dp_ctrl_private *ctr= l, @@ -471,7 +505,8 @@ static void msm_dp_ctrl_config_misc1_misc0(struct msm_d= p_ctrl_private *ctrl, if (msm_dp_panel->stream_id =3D=3D DP_STREAM_1) reg_offset =3D REG_DP1_MISC1_MISC0 - REG_DP_MISC1_MISC0; =20 - misc_val =3D msm_dp_read_link(ctrl, REG_DP_MISC1_MISC0 + reg_offset); + misc_val =3D msm_dp_read_link(ctrl, msm_dp_panel->stream_id, msm_dp_panel= ->stream_id > 1 ? + REG_DP_MSTLINK_MISC1_MISC0 : REG_DP_MISC1_MISC0 + reg_offset); =20 /* clear bpp bits */ misc_val &=3D ~(0x07 << DP_MISC0_TEST_BITS_DEPTH_SHIFT); @@ -481,7 +516,10 @@ static void msm_dp_ctrl_config_misc1_misc0(struct msm_= dp_ctrl_private *ctrl, misc_val |=3D DP_MISC0_SYNCHRONOUS_CLK; =20 drm_dbg_dp(ctrl->drm_dev, "misc settings =3D 0x%x\n", misc_val); - msm_dp_write_link(ctrl, REG_DP_MISC1_MISC0 + reg_offset, misc_val); + msm_dp_write_link(ctrl, msm_dp_panel->stream_id, + msm_dp_panel->stream_id > 1 ? + REG_DP_MSTLINK_MISC1_MISC0 : REG_DP_MISC1_MISC0 + reg_offset, + misc_val); } =20 static void msm_dp_ctrl_configure_source_params(struct msm_dp_ctrl_private= *ctrl, @@ -1307,9 +1345,9 @@ static void msm_dp_ctrl_setup_tr_unit(struct msm_dp_c= trl_private *ctrl) pr_debug("dp_tu=3D0x%x, valid_boundary=3D0x%x, valid_boundary2=3D0x%x\n", msm_dp_tu, valid_boundary, valid_boundary2); =20 - msm_dp_write_link(ctrl, REG_DP_VALID_BOUNDARY, valid_boundary); - msm_dp_write_link(ctrl, REG_DP_TU, msm_dp_tu); - msm_dp_write_link(ctrl, REG_DP_VALID_BOUNDARY_2, valid_boundary2); + msm_dp_write_link(ctrl, 0, REG_DP_VALID_BOUNDARY, valid_boundary); + msm_dp_write_link(ctrl, 0, REG_DP_TU, msm_dp_tu); + msm_dp_write_link(ctrl, 0, REG_DP_VALID_BOUNDARY_2, valid_boundary2); } =20 static int msm_dp_ctrl_wait4video_ready(struct msm_dp_ctrl_private *ctrl) @@ -1426,7 +1464,7 @@ static int msm_dp_ctrl_set_pattern_state_bit(struct m= sm_dp_ctrl_private *ctrl, =20 bit =3D BIT(state_bit - 1); drm_dbg_dp(ctrl->drm_dev, "hw: bit=3D%d train=3D%d\n", bit, state_bit); - msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, bit); + msm_dp_write_link(ctrl, 0, REG_DP_STATE_CTRL, bit); =20 bit =3D BIT(state_bit - 1) << DP_MAINLINK_READY_LINK_TRAINING_SHIFT; =20 @@ -1453,7 +1491,7 @@ static int msm_dp_ctrl_link_train_1(struct msm_dp_ctr= l_private *ctrl, delay_us =3D drm_dp_read_clock_recovery_delay(ctrl->aux, ctrl->panel->dpcd, dp_phy, false); =20 - msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, 0); + msm_dp_write_link(ctrl, 0, REG_DP_STATE_CTRL, 0); =20 *training_step =3D DP_TRAINING_1; =20 @@ -1577,7 +1615,7 @@ static int msm_dp_ctrl_link_train_2(struct msm_dp_ctr= l_private *ctrl, delay_us =3D drm_dp_read_channel_eq_delay(ctrl->aux, ctrl->panel->dpcd, dp_phy, false); =20 - msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, 0); + msm_dp_write_link(ctrl, 0, REG_DP_STATE_CTRL, 0); =20 *training_step =3D DP_TRAINING_2; =20 @@ -1694,7 +1732,7 @@ static int msm_dp_ctrl_link_train(struct msm_dp_ctrl_= private *ctrl, } =20 end: - msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, 0); + msm_dp_write_link(ctrl, 0, REG_DP_STATE_CTRL, 0); =20 return ret; } @@ -1840,34 +1878,34 @@ static int msm_dp_ctrl_enable_mainlink_clocks(struc= t msm_dp_ctrl_private *ctrl) static void msm_dp_ctrl_enable_sdp(struct msm_dp_ctrl_private *ctrl) { /* trigger sdp */ - msm_dp_write_link(ctrl, MMSS_DP_SDP_CFG3, UPDATE_SDP); - msm_dp_write_link(ctrl, MMSS_DP_SDP_CFG3, 0x0); + msm_dp_write_link(ctrl, 0, MMSS_DP_SDP_CFG3, UPDATE_SDP); + msm_dp_write_link(ctrl, 0, MMSS_DP_SDP_CFG3, 0x0); } =20 static void msm_dp_ctrl_psr_enter(struct msm_dp_ctrl_private *ctrl) { u32 cmd; =20 - cmd =3D msm_dp_read_link(ctrl, REG_PSR_CMD); + cmd =3D msm_dp_read_link(ctrl, 0, REG_PSR_CMD); =20 cmd &=3D ~(PSR_ENTER | PSR_EXIT); cmd |=3D PSR_ENTER; =20 msm_dp_ctrl_enable_sdp(ctrl); - msm_dp_write_link(ctrl, REG_PSR_CMD, cmd); + msm_dp_write_link(ctrl, 0, REG_PSR_CMD, cmd); } =20 static void msm_dp_ctrl_psr_exit(struct msm_dp_ctrl_private *ctrl) { u32 cmd; =20 - cmd =3D msm_dp_read_link(ctrl, REG_PSR_CMD); + cmd =3D msm_dp_read_link(ctrl, 0, REG_PSR_CMD); =20 cmd &=3D ~(PSR_ENTER | PSR_EXIT); cmd |=3D PSR_EXIT; =20 msm_dp_ctrl_enable_sdp(ctrl); - msm_dp_write_link(ctrl, REG_PSR_CMD, cmd); + msm_dp_write_link(ctrl, 0, REG_PSR_CMD, cmd); } =20 void msm_dp_ctrl_config_psr(struct msm_dp_ctrl *msm_dp_ctrl) @@ -1880,9 +1918,9 @@ void msm_dp_ctrl_config_psr(struct msm_dp_ctrl *msm_d= p_ctrl) return; =20 /* enable PSR1 function */ - cfg =3D msm_dp_read_link(ctrl, REG_PSR_CONFIG); + cfg =3D msm_dp_read_link(ctrl, 0, REG_PSR_CONFIG); cfg |=3D PSR1_SUPPORTED; - msm_dp_write_link(ctrl, REG_PSR_CONFIG, cfg); + msm_dp_write_link(ctrl, 0, REG_PSR_CONFIG, cfg); =20 msm_dp_ctrl_config_psr_interrupt(ctrl); msm_dp_ctrl_enable_sdp(ctrl); @@ -1921,16 +1959,16 @@ void msm_dp_ctrl_set_psr(struct msm_dp_ctrl *msm_dp= _ctrl, bool enter) } =20 msm_dp_ctrl_push_idle(msm_dp_ctrl); - msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, 0); + msm_dp_write_link(ctrl, 0, REG_DP_STATE_CTRL, 0); =20 msm_dp_ctrl_psr_mainlink_disable(ctrl); } else { msm_dp_ctrl_psr_mainlink_enable(ctrl); =20 msm_dp_ctrl_psr_exit(ctrl); - msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, DP_STATE_CTRL_SEND_VIDEO); + msm_dp_write_link(ctrl, 0, REG_DP_STATE_CTRL, DP_STATE_CTRL_SEND_VIDEO); msm_dp_ctrl_wait4video_ready(ctrl); - msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, 0); + msm_dp_write_link(ctrl, 0, REG_DP_STATE_CTRL, 0); } } =20 @@ -2041,7 +2079,7 @@ static int msm_dp_ctrl_link_maintenance(struct msm_dp= _ctrl_private *ctrl) =20 msm_dp_ctrl_clear_training_pattern(ctrl, DP_PHY_DPRX); =20 - msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, DP_STATE_CTRL_SEND_VIDEO); + msm_dp_write_link(ctrl, 0, REG_DP_STATE_CTRL, DP_STATE_CTRL_SEND_VIDEO); =20 ret =3D msm_dp_ctrl_wait4video_ready(ctrl); end: @@ -2056,72 +2094,72 @@ static void msm_dp_ctrl_send_phy_pattern(struct msm= _dp_ctrl_private *ctrl, u32 value =3D 0x0; =20 /* Make sure to clear the current pattern before starting a new one */ - msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, 0x0); + msm_dp_write_link(ctrl, 0, REG_DP_STATE_CTRL, 0x0); =20 drm_dbg_dp(ctrl->drm_dev, "pattern: %#x\n", pattern); switch (pattern) { case DP_PHY_TEST_PATTERN_D10_2: - msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, - DP_STATE_CTRL_LINK_TRAINING_PATTERN1); + msm_dp_write_link(ctrl, 0, REG_DP_STATE_CTRL, + DP_STATE_CTRL_LINK_TRAINING_PATTERN1); break; =20 case DP_PHY_TEST_PATTERN_ERROR_COUNT: value &=3D ~(1 << 16); - msm_dp_write_link(ctrl, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, - value); + msm_dp_write_link(ctrl, 0, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, + value); value |=3D SCRAMBLER_RESET_COUNT_VALUE; - msm_dp_write_link(ctrl, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, - value); - msm_dp_write_link(ctrl, REG_DP_MAINLINK_LEVELS, - DP_MAINLINK_SAFE_TO_EXIT_LEVEL_2); - msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, - DP_STATE_CTRL_LINK_SYMBOL_ERR_MEASURE); + msm_dp_write_link(ctrl, 0, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, + value); + msm_dp_write_link(ctrl, 0, REG_DP_MAINLINK_LEVELS, + DP_MAINLINK_SAFE_TO_EXIT_LEVEL_2); + msm_dp_write_link(ctrl, 0, REG_DP_STATE_CTRL, + DP_STATE_CTRL_LINK_SYMBOL_ERR_MEASURE); break; =20 case DP_PHY_TEST_PATTERN_PRBS7: - msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, - DP_STATE_CTRL_LINK_PRBS7); + msm_dp_write_link(ctrl, 0, REG_DP_STATE_CTRL, + DP_STATE_CTRL_LINK_PRBS7); break; =20 case DP_PHY_TEST_PATTERN_80BIT_CUSTOM: - msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, - DP_STATE_CTRL_LINK_TEST_CUSTOM_PATTERN); + msm_dp_write_link(ctrl, 0, REG_DP_STATE_CTRL, + DP_STATE_CTRL_LINK_TEST_CUSTOM_PATTERN); /* 00111110000011111000001111100000 */ - msm_dp_write_link(ctrl, REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG0, - 0x3E0F83E0); + msm_dp_write_link(ctrl, 0, REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG0, + 0x3E0F83E0); /* 00001111100000111110000011111000 */ - msm_dp_write_link(ctrl, REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG1, - 0x0F83E0F8); + msm_dp_write_link(ctrl, 0, REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG1, + 0x0F83E0F8); /* 1111100000111110 */ - msm_dp_write_link(ctrl, REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG2, - 0x0000F83E); + msm_dp_write_link(ctrl, 0, REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG2, + 0x0000F83E); break; =20 case DP_PHY_TEST_PATTERN_CP2520: - value =3D msm_dp_read_link(ctrl, REG_DP_MAINLINK_CTRL); + value =3D msm_dp_read_link(ctrl, 0, REG_DP_MAINLINK_CTRL); value &=3D ~DP_MAINLINK_CTRL_SW_BYPASS_SCRAMBLER; - msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, value); + msm_dp_write_link(ctrl, 0, REG_DP_MAINLINK_CTRL, value); =20 value =3D DP_HBR2_ERM_PATTERN; - msm_dp_write_link(ctrl, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, - value); + msm_dp_write_link(ctrl, 0, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, + value); value |=3D SCRAMBLER_RESET_COUNT_VALUE; - msm_dp_write_link(ctrl, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, - value); - msm_dp_write_link(ctrl, REG_DP_MAINLINK_LEVELS, - DP_MAINLINK_SAFE_TO_EXIT_LEVEL_2); - msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, - DP_STATE_CTRL_LINK_SYMBOL_ERR_MEASURE); - value =3D msm_dp_read_link(ctrl, REG_DP_MAINLINK_CTRL); + msm_dp_write_link(ctrl, 0, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, + value); + msm_dp_write_link(ctrl, 0, REG_DP_MAINLINK_LEVELS, + DP_MAINLINK_SAFE_TO_EXIT_LEVEL_2); + msm_dp_write_link(ctrl, 0, REG_DP_STATE_CTRL, + DP_STATE_CTRL_LINK_SYMBOL_ERR_MEASURE); + value =3D msm_dp_read_link(ctrl, 0, REG_DP_MAINLINK_CTRL); value |=3D DP_MAINLINK_CTRL_ENABLE; - msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, value); + msm_dp_write_link(ctrl, 0, REG_DP_MAINLINK_CTRL, value); break; =20 case DP_PHY_TEST_PATTERN_SEL_MASK: - msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, - DP_MAINLINK_CTRL_ENABLE); - msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, - DP_STATE_CTRL_LINK_TRAINING_PATTERN4); + msm_dp_write_link(ctrl, 0, REG_DP_MAINLINK_CTRL, + DP_MAINLINK_CTRL_ENABLE); + msm_dp_write_link(ctrl, 0, REG_DP_STATE_CTRL, + DP_STATE_CTRL_LINK_TRAINING_PATTERN4); break; =20 default: @@ -2149,7 +2187,7 @@ static bool msm_dp_ctrl_send_phy_test_pattern(struct = msm_dp_ctrl_private *ctrl) msm_dp_ctrl_update_phy_vx_px(ctrl, DP_PHY_DPRX); msm_dp_link_send_test_response(ctrl->link); =20 - pattern_sent =3D msm_dp_read_link(ctrl, REG_DP_MAINLINK_READY); + pattern_sent =3D msm_dp_read_link(ctrl, 0, REG_DP_MAINLINK_READY); =20 switch (pattern_sent) { case MR_LINK_TRAINING1: @@ -2522,8 +2560,14 @@ static void msm_dp_ctrl_config_msa(struct msm_dp_ctr= l_private *ctrl, nvid *=3D 3; =20 drm_dbg_dp(ctrl->drm_dev, "mvid=3D0x%x, nvid=3D0x%x\n", mvid, nvid); - msm_dp_write_link(ctrl, REG_DP_SOFTWARE_MVID + mvid_reg_off, mvid); - msm_dp_write_link(ctrl, REG_DP_SOFTWARE_NVID + nvid_reg_off, nvid); + msm_dp_write_link(ctrl, msm_dp_panel->stream_id, + msm_dp_panel->stream_id > 1 ? + REG_MSTLINK_SOFTWARE_MVID : REG_DP_SOFTWARE_MVID + mvid_reg_off, + mvid); + msm_dp_write_link(ctrl, msm_dp_panel->stream_id, + msm_dp_panel->stream_id > 1 ? + REG_MSTLINK_SOFTWARE_NVID : REG_DP_SOFTWARE_NVID + nvid_reg_off, + nvid); } =20 int msm_dp_ctrl_prepare_stream_on(struct msm_dp_ctrl *msm_dp_ctrl, bool fo= rce_link_train) @@ -2593,7 +2637,8 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_= ctrl, struct msm_dp_panel * =20 msm_dp_ctrl_lane_mapping(ctrl); msm_dp_setup_peripheral_flush(ctrl); - msm_dp_ctrl_config_ctrl_link(ctrl); + if (msm_dp_panel->stream_id =3D=3D DP_STREAM_0) + msm_dp_ctrl_config_ctrl_link(ctrl); =20 msm_dp_ctrl_configure_source_params(ctrl, msm_dp_panel); =20 @@ -2607,7 +2652,7 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_= ctrl, struct msm_dp_panel * =20 msm_dp_ctrl_setup_tr_unit(ctrl); =20 - msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, DP_STATE_CTRL_SEND_VIDEO); + msm_dp_write_link(ctrl, 0, REG_DP_STATE_CTRL, DP_STATE_CTRL_SEND_VIDEO); =20 ret =3D msm_dp_ctrl_wait4video_ready(ctrl); if (ret) @@ -2787,7 +2832,9 @@ struct msm_dp_ctrl *msm_dp_ctrl_get(struct device *de= v, struct msm_dp_link *link struct phy *phy, int max_stream, void __iomem *ahb_base, - void __iomem *link_base) + void __iomem *link_base, + void __iomem *mst2link_base, + void __iomem *mst3link_base) { struct msm_dp_ctrl_private *ctrl; int ret; @@ -2827,6 +2874,8 @@ struct msm_dp_ctrl *msm_dp_ctrl_get(struct device *de= v, struct msm_dp_link *link ctrl->phy =3D phy; ctrl->ahb_base =3D ahb_base; ctrl->link_base =3D link_base; + ctrl->mst2link_base =3D mst2link_base; + ctrl->mst3link_base =3D mst3link_base; =20 ret =3D msm_dp_ctrl_clk_init(&ctrl->msm_dp_ctrl, max_stream); if (ret) { diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.h b/drivers/gpu/drm/msm/dp/dp_c= trl.h index 6fed3ff3a72d..e72d501ac1ce 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.h +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.h @@ -31,7 +31,9 @@ struct msm_dp_ctrl *msm_dp_ctrl_get(struct device *dev, struct phy *phy, int max_stream, void __iomem *ahb_base, - void __iomem *link_base); + void __iomem *link_base, + void __iomem *mst2link_base, + void __iomem *mst3link_base); =20 void msm_dp_ctrl_reset(struct msm_dp_ctrl *msm_dp_ctrl); void msm_dp_ctrl_phy_init(struct msm_dp_ctrl *msm_dp_ctrl); diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index ff506064a3fa..a924fbd825f7 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -85,6 +85,12 @@ struct msm_dp_display_private { void __iomem *link_base; size_t link_len; =20 + void __iomem *mst2link_base; + size_t mst2link_len; + + void __iomem *mst3link_base; + size_t mst3link_len; + void __iomem *pixel_base[DP_STREAM_MAX]; size_t pixel_len; =20 @@ -561,7 +567,8 @@ static int msm_dp_init_sub_modules(struct msm_dp_displa= y_private *dp) goto error_link; } =20 - dp->panel =3D msm_dp_panel_get(dev, dp->aux, dp->link, dp->link_base, dp-= >pixel_base[0]); + dp->panel =3D msm_dp_panel_get(dev, dp->aux, dp->link, dp->link_base, + dp->mst2link_base, dp->mst3link_base, dp->pixel_base[0]); if (IS_ERR(dp->panel)) { rc =3D PTR_ERR(dp->panel); DRM_ERROR("failed to initialize panel, rc =3D %d\n", rc); @@ -570,7 +577,8 @@ static int msm_dp_init_sub_modules(struct msm_dp_displa= y_private *dp) } =20 dp->ctrl =3D msm_dp_ctrl_get(dev, dp->link, dp->panel, dp->aux, - phy, dp->max_stream, dp->ahb_base, dp->link_base); + phy, dp->max_stream, dp->ahb_base, + dp->link_base, dp->mst2link_base, dp->mst3link_base); if (IS_ERR(dp->ctrl)) { rc =3D PTR_ERR(dp->ctrl); DRM_ERROR("failed to initialize ctrl, rc =3D %d\n", rc); @@ -883,6 +891,10 @@ void msm_dp_snapshot(struct msm_disp_state *disp_state= , struct msm_dp *dp) msm_dp_display->aux_base, "dp_aux"); msm_disp_snapshot_add_block(disp_state, msm_dp_display->link_len, msm_dp_display->link_base, "dp_link"); + msm_disp_snapshot_add_block(disp_state, msm_dp_display->mst2link_len, + msm_dp_display->mst2link_base, "dp_mst2link"); + msm_disp_snapshot_add_block(disp_state, msm_dp_display->mst3link_len, + msm_dp_display->mst3link_base, "dp_mst3link"); msm_disp_snapshot_add_block(disp_state, msm_dp_display->pixel_len, msm_dp_display->pixel_base[0], "dp_p0"); msm_disp_snapshot_add_block(disp_state, msm_dp_display->pixel_len, @@ -1228,6 +1240,14 @@ static int msm_dp_display_get_io(struct msm_dp_displ= ay_private *display) } } =20 + display->mst2link_base =3D msm_dp_ioremap(pdev, 7, &display->mst2link_len= ); + if (IS_ERR(display->mst2link_base)) + DRM_DEBUG_DP("unable to remap link region: %pe\n", display->mst2link_bas= e); + + display->mst3link_base =3D msm_dp_ioremap(pdev, 8, &display->mst3link_len= ); + if (IS_ERR(display->mst3link_base)) + DRM_DEBUG_DP("unable to remap link region: %pe\n", display->mst3link_bas= e); + return 0; } =20 diff --git a/drivers/gpu/drm/msm/dp/dp_panel.c b/drivers/gpu/drm/msm/dp/dp_= panel.c index 6c88cc7e3037..a8a6297b37e3 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.c +++ b/drivers/gpu/drm/msm/dp/dp_panel.c @@ -25,23 +25,50 @@ struct msm_dp_panel_private { struct drm_dp_aux *aux; struct msm_dp_link *link; void __iomem *link_base; + void __iomem *mst2link_base; + void __iomem *mst3link_base; void __iomem *pixel_base; bool panel_on; }; =20 static inline u32 msm_dp_read_link(struct msm_dp_panel_private *panel, u32= offset) { - return readl_relaxed(panel->link_base + offset); + switch (panel->msm_dp_panel.stream_id) { + case DP_STREAM_0: + case DP_STREAM_1: + return readl_relaxed(panel->link_base + offset); + case DP_STREAM_2: + return readl_relaxed(panel->mst2link_base + offset); + case DP_STREAM_3: + return readl_relaxed(panel->mst3link_base + offset); + default: + DRM_ERROR("error stream_id\n"); + return 0; + } } =20 static inline void msm_dp_write_link(struct msm_dp_panel_private *panel, - u32 offset, u32 data) + u32 offset, u32 data) { /* * To make sure link reg writes happens before any other operation, * this function uses writel() instread of writel_relaxed() */ - writel(data, panel->link_base + offset); + switch (panel->msm_dp_panel.stream_id) { + case DP_STREAM_0: + case DP_STREAM_1: + writel(data, panel->link_base + offset); + break; + case DP_STREAM_2: + writel(data, panel->mst2link_base + offset); + break; + case DP_STREAM_3: + writel(data, panel->mst3link_base + offset); + break; + default: + DRM_ERROR("error stream_id\n"); + break; + } } =20 static inline void msm_dp_write_pn(struct msm_dp_panel_private *panel, @@ -444,38 +471,51 @@ void msm_dp_panel_clear_dsc_dto(struct msm_dp_panel *= msm_dp_panel) =20 static void msm_dp_panel_send_vsc_sdp(struct msm_dp_panel_private *panel, = struct dp_sdp *vsc_sdp) { + u32 id =3D panel->msm_dp_panel.stream_id; u32 header[2]; u32 val; int i; u32 offset =3D 0; =20 - if (panel->msm_dp_panel.stream_id =3D=3D DP_STREAM_1) + if (id =3D=3D DP_STREAM_1) offset =3D MMSS_DP1_GENERIC0_0 - MMSS_DP_GENERIC0_0; =20 msm_dp_utils_pack_sdp_header(&vsc_sdp->sdp_header, header); =20 - msm_dp_write_link(panel, MMSS_DP_GENERIC0_0 + offset, header[0]); - msm_dp_write_link(panel, MMSS_DP_GENERIC0_1 + offset, header[1]); + msm_dp_write_link(panel, id > 1 ? + MMSS_DP_MSTLINK_GENERIC0_0 : MMSS_DP_GENERIC0_0 + offset, + header[0]); + msm_dp_write_link(panel, id > 1 ? + MMSS_DP_MSTLINK_GENERIC0_1 : MMSS_DP_GENERIC0_1 + offset, + header[1]); =20 for (i =3D 0; i < sizeof(vsc_sdp->db); i +=3D 4) { val =3D ((vsc_sdp->db[i]) | (vsc_sdp->db[i + 1] << 8) | (vsc_sdp->db[i += 2] << 16) | (vsc_sdp->db[i + 3] << 24)); - msm_dp_write_link(panel, MMSS_DP_GENERIC0_2 + i + offset, val); + + msm_dp_write_link(panel, id > 1 ? + MMSS_DP_MSTLINK_GENERIC0_2 + i : MMSS_DP_GENERIC0_2 + i + offset, + val); } } =20 static void msm_dp_panel_update_sdp(struct msm_dp_panel_private *panel) { + u32 id =3D panel->msm_dp_panel.stream_id; u32 hw_revision =3D panel->msm_dp_panel.hw_revision; u32 offset =3D 0; =20 - if (panel->msm_dp_panel.stream_id =3D=3D DP_STREAM_1) + if (id =3D=3D DP_STREAM_1) offset =3D MMSS_DP1_SDP_CFG3 - MMSS_DP_SDP_CFG3; =20 if (hw_revision >=3D DP_HW_VERSION_1_0 && hw_revision < DP_HW_VERSION_1_2) { - msm_dp_write_link(panel, MMSS_DP_SDP_CFG3 + offset, UPDATE_SDP); - msm_dp_write_link(panel, MMSS_DP_SDP_CFG3 + offset, 0x0); + msm_dp_write_link(panel, id > 1 ? + MMSS_DP_MSTLINK_SDP_CFG3 : MMSS_DP_SDP_CFG3 + offset, + UPDATE_SDP); + msm_dp_write_link(panel, id > 1 ? + MMSS_DP_MSTLINK_SDP_CFG3 : MMSS_DP_SDP_CFG3 + offset, + 0x0); } } =20 @@ -483,26 +523,34 @@ void msm_dp_panel_enable_vsc_sdp(struct msm_dp_panel = *msm_dp_panel, struct dp_sd { struct msm_dp_panel_private *panel =3D container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); + u32 id =3D msm_dp_panel->stream_id; u32 cfg, cfg2, misc; u32 misc_reg_offset =3D 0; u32 sdp_cfg_offset =3D 0; u32 sdp_cfg2_offset =3D 0; =20 - if (msm_dp_panel->stream_id =3D=3D DP_STREAM_1) { + if (id =3D=3D DP_STREAM_1) { misc_reg_offset =3D REG_DP1_MISC1_MISC0 - REG_DP_MISC1_MISC0; sdp_cfg_offset =3D MMSS_DP1_SDP_CFG - MMSS_DP_SDP_CFG; sdp_cfg2_offset =3D MMSS_DP1_SDP_CFG2 - MMSS_DP_SDP_CFG2; } =20 - cfg =3D msm_dp_read_link(panel, MMSS_DP_SDP_CFG + sdp_cfg_offset); - cfg2 =3D msm_dp_read_link(panel, MMSS_DP_SDP_CFG2 + sdp_cfg2_offset); - misc =3D msm_dp_read_link(panel, REG_DP_MISC1_MISC0 + misc_reg_offset); + cfg =3D msm_dp_read_link(panel, id > 1 ? + MMSS_DP_MSTLINK_SDP_CFG : MMSS_DP_SDP_CFG + sdp_cfg_offset); + cfg2 =3D msm_dp_read_link(panel, id > 1 ? + MMSS_DP_MSTLINK_SDP_CFG2 : MMSS_DP_SDP_CFG2 + sdp_cfg2_offset); + misc =3D msm_dp_read_link(panel, id > 1 ? + REG_DP_MSTLINK_MISC1_MISC0 : REG_DP_MISC1_MISC0 + misc_reg_offset); =20 cfg |=3D GEN0_SDP_EN; - msm_dp_write_link(panel, MMSS_DP_SDP_CFG + sdp_cfg_offset, cfg); - cfg2 |=3D GENERIC0_SDPSIZE_VALID; - msm_dp_write_link(panel, MMSS_DP_SDP_CFG2 + sdp_cfg2_offset, cfg2); + + msm_dp_write_link(panel, id > 1 ? + MMSS_DP_MSTLINK_SDP_CFG : MMSS_DP_SDP_CFG + sdp_cfg_offset, + cfg); + msm_dp_write_link(panel, id > 1 ? + MMSS_DP_MSTLINK_SDP_CFG2 : MMSS_DP_SDP_CFG2 + sdp_cfg2_offset, + cfg2); =20 msm_dp_panel_send_vsc_sdp(panel, vsc_sdp); =20 @@ -512,7 +560,9 @@ void msm_dp_panel_enable_vsc_sdp(struct msm_dp_panel *m= sm_dp_panel, struct dp_sd drm_dbg_dp(panel->drm_dev, "vsc sdp enable=3D1\n"); =20 pr_debug("misc settings =3D 0x%x\n", misc); - msm_dp_write_link(panel, REG_DP_MISC1_MISC0 + misc_reg_offset, misc); + msm_dp_write_link(panel, id > 1 ? + REG_DP_MSTLINK_MISC1_MISC0 : REG_DP_MISC1_MISC0 + misc_reg_offset, + misc); =20 msm_dp_panel_update_sdp(panel); } @@ -521,26 +571,34 @@ void msm_dp_panel_disable_vsc_sdp(struct msm_dp_panel= *msm_dp_panel) { struct msm_dp_panel_private *panel =3D container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); + u32 id =3D msm_dp_panel->stream_id; u32 cfg, cfg2, misc; u32 misc_reg_offset =3D 0; u32 sdp_cfg_offset =3D 0; u32 sdp_cfg2_offset =3D 0; =20 - if (msm_dp_panel->stream_id =3D=3D DP_STREAM_1) { + if (id =3D=3D DP_STREAM_1) { misc_reg_offset =3D REG_DP1_MISC1_MISC0 - REG_DP_MISC1_MISC0; sdp_cfg_offset =3D MMSS_DP1_SDP_CFG - MMSS_DP_SDP_CFG; sdp_cfg2_offset =3D MMSS_DP1_SDP_CFG2 - MMSS_DP_SDP_CFG2; } =20 - cfg =3D msm_dp_read_link(panel, MMSS_DP_SDP_CFG + sdp_cfg_offset); - cfg2 =3D msm_dp_read_link(panel, MMSS_DP_SDP_CFG2 + sdp_cfg2_offset); - misc =3D msm_dp_read_link(panel, REG_DP_MISC1_MISC0 + misc_reg_offset); + cfg =3D msm_dp_read_link(panel, id > 1 ? + MMSS_DP_MSTLINK_SDP_CFG : MMSS_DP_SDP_CFG + sdp_cfg_offset); + cfg2 =3D msm_dp_read_link(panel, id > 1 ? + MMSS_DP_MSTLINK_SDP_CFG2 : MMSS_DP_SDP_CFG2 + sdp_cfg2_offset); + misc =3D msm_dp_read_link(panel, id > 1 ? + REG_DP_MSTLINK_MISC1_MISC0 : REG_DP_MISC1_MISC0 + misc_reg_offset); =20 cfg &=3D ~GEN0_SDP_EN; - msm_dp_write_link(panel, MMSS_DP_SDP_CFG + sdp_cfg_offset, cfg); - cfg2 &=3D ~GENERIC0_SDPSIZE_VALID; - msm_dp_write_link(panel, MMSS_DP_SDP_CFG2 + sdp_cfg2_offset, cfg2); + + msm_dp_write_link(panel, id > 1 ? + MMSS_DP_MSTLINK_SDP_CFG : MMSS_DP_SDP_CFG + sdp_cfg_offset, + cfg); + msm_dp_write_link(panel, id > 1 ? + MMSS_DP_MSTLINK_SDP_CFG2 : MMSS_DP_SDP_CFG2 + sdp_cfg2_offset, + cfg2); =20 /* switch back to MSA */ misc &=3D ~DP_MISC1_VSC_SDP; @@ -548,7 +606,9 @@ void msm_dp_panel_disable_vsc_sdp(struct msm_dp_panel *= msm_dp_panel) drm_dbg_dp(panel->drm_dev, "vsc sdp enable=3D0\n"); =20 pr_debug("misc settings =3D 0x%x\n", misc); - msm_dp_write_link(panel, REG_DP_MISC1_MISC0 + misc_reg_offset, misc); + msm_dp_write_link(panel, id > 1 ? + REG_DP_MSTLINK_MISC1_MISC0 : REG_DP_MISC1_MISC0 + misc_reg_offset, + misc); =20 msm_dp_panel_update_sdp(panel); } @@ -598,6 +658,7 @@ static int msm_dp_panel_setup_vsc_sdp_yuv_420(struct ms= m_dp_panel *msm_dp_panel) =20 int msm_dp_panel_timing_cfg(struct msm_dp_panel *msm_dp_panel, bool wide_b= us_en) { + u32 id =3D msm_dp_panel->stream_id; u32 data, total_ver, total_hor; struct msm_dp_panel_private *panel; struct drm_display_mode *drm_mode; @@ -621,7 +682,7 @@ int msm_dp_panel_timing_cfg(struct msm_dp_panel *msm_dp= _panel, bool wide_bus_en) drm_mode->vsync_start - drm_mode->vdisplay, drm_mode->vsync_end - drm_mode->vsync_start); =20 - if (msm_dp_panel->stream_id =3D=3D DP_STREAM_1) + if (id =3D=3D DP_STREAM_1) offset =3D REG_DP1_TOTAL_HOR_VER - REG_DP_TOTAL_HOR_VER; =20 total_hor =3D drm_mode->htotal; @@ -654,10 +715,18 @@ int msm_dp_panel_timing_cfg(struct msm_dp_panel *msm_= dp_panel, bool wide_bus_en) =20 msm_dp_active =3D data; =20 - msm_dp_write_link(panel, REG_DP_TOTAL_HOR_VER + offset, total); - msm_dp_write_link(panel, REG_DP_START_HOR_VER_FROM_SYNC + offset, sync_s= tart); - msm_dp_write_link(panel, REG_DP_HSYNC_VSYNC_WIDTH_POLARITY + offset, widt= h_blanking); - msm_dp_write_link(panel, REG_DP_ACTIVE_HOR_VER + offset, msm_dp_active); + msm_dp_write_link(panel, + id > 1 ? REG_DP_MSTLINK_TOTAL_HOR_VER : + REG_DP_TOTAL_HOR_VER + offset, total); + msm_dp_write_link(panel, + id > 1 ? REG_DP_MSTLINK_START_HOR_VER_FROM_SYNC : + REG_DP_START_HOR_VER_FROM_SYNC + offset, sync_start); + msm_dp_write_link(panel, + id > 1 ? REG_DP_MSTLINK_HSYNC_VSYNC_WIDTH_POLARITY : + REG_DP_HSYNC_VSYNC_WIDTH_POLARITY + offset, width_blanking); + msm_dp_write_link(panel, + id > 1 ? REG_DP_MSTLINK_ACTIVE_HOR_VER : + REG_DP_ACTIVE_HOR_VER + offset, msm_dp_active); =20 reg =3D msm_dp_read_pn(panel, MMSS_DP_INTF_CONFIG); if (wide_bus_en) @@ -726,6 +795,8 @@ int msm_dp_panel_init_panel_info(struct msm_dp_panel *m= sm_dp_panel) struct msm_dp_panel *msm_dp_panel_get(struct device *dev, struct drm_dp_au= x *aux, struct msm_dp_link *link, void __iomem *link_base, + void __iomem *mst2link_base, + void __iomem *mst3link_base, void __iomem *pixel_base) { struct msm_dp_panel_private *panel; @@ -745,6 +816,8 @@ struct msm_dp_panel *msm_dp_panel_get(struct device *de= v, struct drm_dp_aux *aux panel->link =3D link; panel->link_base =3D link_base; panel->pixel_base =3D pixel_base; + panel->mst2link_base =3D mst2link_base; + panel->mst3link_base =3D mst3link_base; =20 msm_dp_panel =3D &panel->msm_dp_panel; msm_dp_panel->max_bw_code =3D DP_LINK_BW_8_1; diff --git a/drivers/gpu/drm/msm/dp/dp_panel.h b/drivers/gpu/drm/msm/dp/dp_= panel.h index fe4ac3e47e17..4873c55bd693 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.h +++ b/drivers/gpu/drm/msm/dp/dp_panel.h @@ -101,5 +101,7 @@ static inline bool is_lane_count_valid(u32 lane_count) struct msm_dp_panel *msm_dp_panel_get(struct device *dev, struct drm_dp_au= x *aux, struct msm_dp_link *link, void __iomem *link_base, + void __iomem *mst2link_base, + void __iomem *mst3link_base, void __iomem *pixel_base); #endif /* _DP_PANEL_H_ */ diff --git a/drivers/gpu/drm/msm/dp/dp_reg.h b/drivers/gpu/drm/msm/dp/dp_re= g.h index 295c1161e6b7..1c2d3d8d029d 100644 --- a/drivers/gpu/drm/msm/dp/dp_reg.h +++ b/drivers/gpu/drm/msm/dp/dp_reg.h @@ -162,7 +162,6 @@ #define REG_DP_START_HOR_VER_FROM_SYNC (0x00000020) #define REG_DP_HSYNC_VSYNC_WIDTH_POLARITY (0x00000024) #define REG_DP_ACTIVE_HOR_VER (0x00000028) - #define REG_DP_MISC1_MISC0 (0x0000002C) #define DP_MISC0_SYNCHRONOUS_CLK (0x00000001) #define DP_MISC0_COLORIMETRY_CFG_SHIFT (0x00000001) @@ -343,6 +342,21 @@ #define MMSS_DP1_SDP_CFG2 (0x000004E4) #define MMSS_DP1_SDP_CFG3 (0x000004E8) =20 +#define REG_DP_MSTLINK_CONFIGURATION_CTRL (0x00000034) +#define REG_MSTLINK_SOFTWARE_MVID (0x00000040) +#define REG_MSTLINK_SOFTWARE_NVID (0x00000044) +#define REG_DP_MSTLINK_TOTAL_HOR_VER (0x00000048) +#define REG_DP_MSTLINK_START_HOR_VER_FROM_SYNC (0x0000004C) +#define REG_DP_MSTLINK_HSYNC_VSYNC_WIDTH_POLARITY (0x00000050) +#define REG_DP_MSTLINK_ACTIVE_HOR_VER (0x00000054) +#define REG_DP_MSTLINK_MISC1_MISC0 (0x00000058) +#define MMSS_DP_MSTLINK_GENERIC0_0 (0x000000BC) +#define MMSS_DP_MSTLINK_GENERIC0_1 (0x000000C0) +#define MMSS_DP_MSTLINK_GENERIC0_2 (0x000000C4) +#define MMSS_DP_MSTLINK_SDP_CFG (0x0000010c) +#define MMSS_DP_MSTLINK_SDP_CFG2 (0x0000011c) +#define MMSS_DP_MSTLINK_SDP_CFG3 (0x00000114) + #define MMSS_DP_ASYNC_FIFO_CONFIG (0x00000088) =20 #define REG_DP_PHY_AUX_INTERRUPT_CLEAR (0x0000004C) --=20 2.43.0 From nobody Sat Apr 18 10:45:33 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AFEBE3BBA0E for ; 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This would be applicable during the start and stop of the pixel stream. Add the infrastructure to be able to send ACT packets for the DP controller when operating in MST mode. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 43 +++++++++++++++++++++++++++++++++= ++-- drivers/gpu/drm/msm/dp/dp_ctrl.h | 3 ++- drivers/gpu/drm/msm/dp/dp_display.c | 3 ++- drivers/gpu/drm/msm/dp/dp_display.h | 1 + drivers/gpu/drm/msm/dp/dp_reg.h | 2 ++ 5 files changed, 48 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_c= trl.c index 1109b2df21be..6f25145ef214 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -143,6 +143,7 @@ struct msm_dp_ctrl_private { bool core_clks_on; bool link_clks_on; bool stream_clks_on[DP_STREAM_MAX]; + bool mst_active; }; =20 static inline u32 msm_dp_read_ahb(const struct msm_dp_ctrl_private *ctrl, = u32 offset) @@ -228,6 +229,32 @@ static int msm_dp_aux_link_configure(struct drm_dp_aux= *aux, return err; } =20 +int msm_dp_ctrl_mst_send_act(struct msm_dp_ctrl *msm_dp_ctrl) +{ + struct msm_dp_ctrl_private *ctrl; + bool act_complete; + + ctrl =3D container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctr= l); + + if (!ctrl->mst_active) + return 0; + + msm_dp_write_link(ctrl, 0, REG_DP_MST_ACT, 0x1); + /* make sure ACT signal is performed */ + wmb(); + + msleep(20); /* needs 1 frame time */ + + act_complete =3D msm_dp_read_link(ctrl, 0, REG_DP_MST_ACT); + + if (!act_complete) { + drm_dbg_dp(ctrl->drm_dev, "MST ACT trigger complete failed\n"); + return -EINVAL; + } + + return 0; +} + /* * NOTE: resetting DP controller will also clear any pending HPD related i= nterrupts */ @@ -2081,6 +2108,10 @@ static int msm_dp_ctrl_link_maintenance(struct msm_d= p_ctrl_private *ctrl) =20 msm_dp_write_link(ctrl, 0, REG_DP_STATE_CTRL, DP_STATE_CTRL_SEND_VIDEO); =20 + ret =3D msm_dp_ctrl_mst_send_act(&ctrl->msm_dp_ctrl); + if (ret) + return ret; + ret =3D msm_dp_ctrl_wait4video_ready(ctrl); end: return ret; @@ -2277,7 +2308,7 @@ static int msm_dp_ctrl_process_phy_test_request(struc= t msm_dp_ctrl_private *ctrl msm_dp_ctrl_off_pixel_clk(&ctrl->msm_dp_ctrl, ctrl->panel->stream_id); msm_dp_ctrl_off_link(&ctrl->msm_dp_ctrl); =20 - ret =3D msm_dp_ctrl_on_link(&ctrl->msm_dp_ctrl); + ret =3D msm_dp_ctrl_on_link(&ctrl->msm_dp_ctrl, false); if (ret) { DRM_ERROR("failed to enable DP link controller\n"); return ret; @@ -2357,7 +2388,7 @@ static bool msm_dp_ctrl_channel_eq_ok(struct msm_dp_c= trl_private *ctrl) return drm_dp_channel_eq_ok(link_status, num_lanes); } =20 -int msm_dp_ctrl_on_link(struct msm_dp_ctrl *msm_dp_ctrl) +int msm_dp_ctrl_on_link(struct msm_dp_ctrl *msm_dp_ctrl, bool mst_active) { int rc =3D 0; struct msm_dp_ctrl_private *ctrl; @@ -2375,6 +2406,7 @@ int msm_dp_ctrl_on_link(struct msm_dp_ctrl *msm_dp_ct= rl) =20 rate =3D ctrl->panel->link_info.rate; pixel_rate =3D ctrl->panel->msm_dp_mode.drm_mode.clock; + ctrl->mst_active =3D mst_active; =20 msm_dp_ctrl_core_clk_enable(&ctrl->msm_dp_ctrl); =20 @@ -2654,6 +2686,10 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp= _ctrl, struct msm_dp_panel * =20 msm_dp_write_link(ctrl, 0, REG_DP_STATE_CTRL, DP_STATE_CTRL_SEND_VIDEO); =20 + ret =3D msm_dp_ctrl_mst_send_act(msm_dp_ctrl); + if (ret) + return ret; + ret =3D msm_dp_ctrl_wait4video_ready(ctrl); if (ret) return ret; @@ -2693,6 +2729,8 @@ void msm_dp_ctrl_off_link(struct msm_dp_ctrl *msm_dp_= ctrl) =20 msm_dp_ctrl_reset(&ctrl->msm_dp_ctrl); =20 + ctrl->mst_active =3D false; + dev_pm_opp_set_rate(ctrl->dev, 0); msm_dp_ctrl_link_clk_disable(&ctrl->msm_dp_ctrl); =20 @@ -2876,6 +2914,7 @@ struct msm_dp_ctrl *msm_dp_ctrl_get(struct device *de= v, struct msm_dp_link *link ctrl->link_base =3D link_base; ctrl->mst2link_base =3D mst2link_base; ctrl->mst3link_base =3D mst3link_base; + ctrl->mst_active =3D false; =20 ret =3D msm_dp_ctrl_clk_init(&ctrl->msm_dp_ctrl, max_stream); if (ret) { diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.h b/drivers/gpu/drm/msm/dp/dp_c= trl.h index e72d501ac1ce..f82fd96e412a 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.h +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.h @@ -16,7 +16,7 @@ struct msm_dp_ctrl { =20 struct phy; =20 -int msm_dp_ctrl_on_link(struct msm_dp_ctrl *msm_dp_ctrl); +int msm_dp_ctrl_on_link(struct msm_dp_ctrl *msm_dp_ctrl, bool mst_active); int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl, struct msm_dp_p= anel *msm_dp_panel); int msm_dp_ctrl_prepare_stream_on(struct msm_dp_ctrl *msm_dp_ctrl, bool fo= rce_link_train); void msm_dp_ctrl_off_link(struct msm_dp_ctrl *msm_dp_ctrl); @@ -51,4 +51,5 @@ void msm_dp_ctrl_disable_irq(struct msm_dp_ctrl *msm_dp_c= trl); =20 void msm_dp_ctrl_reinit_phy(struct msm_dp_ctrl *msm_dp_ctrl); int msm_dp_ctrl_get_stream_cnt(struct msm_dp_ctrl *dp_ctrl); +int msm_dp_ctrl_mst_send_act(struct msm_dp_ctrl *msm_dp_ctrl); #endif /* _DP_CTRL_H_ */ diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index a924fbd825f7..80bb5fc4003f 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -660,7 +660,7 @@ static int msm_dp_display_prepare(struct msm_dp_display= _private *dp) force_link_train =3D true; } =20 - rc =3D msm_dp_ctrl_on_link(dp->ctrl); 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[129.46.232.65]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-8ac84cb135fsm19223386d6.38.2026.04.10.02.35.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Apr 2026 02:35:27 -0700 (PDT) From: Yongxing Mou Date: Fri, 10 Apr 2026 17:33:54 +0800 Subject: [PATCH v4 19/39] drm/msm/dp: Add support to enable MST in mainlink control Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260410-msm-dp-mst-v4-19-b20518dea8de@oss.qualcomm.com> References: <20260410-msm-dp-mst-v4-0-b20518dea8de@oss.qualcomm.com> In-Reply-To: <20260410-msm-dp-mst-v4-0-b20518dea8de@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Jessica Zhang Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Yongxing Mou , Abhinav Kumar X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1775813628; l=2524; i=yongxing.mou@oss.qualcomm.com; s=20250910; h=from:subject:message-id; bh=K5vgfTfdCI4P5kMd92t6oN5BdOo9qMx4WD+42FN4rPU=; b=xE4kYondk9JUlsE03aUn3L62AYCt/ATKX+EV9mZLBM27CYYnwrk0Lz+9gycIw3ZKS57a1vCiB gLO/pK1Aci0C6N/rTE00I9+m1K0+R+25JzjUUbpF7eGq5Yua5Gw8bKq X-Developer-Key: i=yongxing.mou@oss.qualcomm.com; a=ed25519; pk=rAy5J1eP+V7OXqH5FJ7ngMCtUrnHhut30ZTldOj52UM= X-Proofpoint-ORIG-GUID: 8-vS53BoOrkzJPkxPApGfw8YAmSN42ev X-Proofpoint-GUID: 8-vS53BoOrkzJPkxPApGfw8YAmSN42ev X-Authority-Analysis: v=2.4 cv=Ko59H2WN c=1 sm=1 tr=0 ts=69d8c461 cx=c_pps a=7E5Bxpl4vBhpaufnMqZlrw==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=GJT6Fafo9oTAj6z5dyEA:9 a=QEXdDO2ut3YA:10 a=pJ04lnu7RYOZP9TFuWaZ:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDEwMDA4OSBTYWx0ZWRfX92HQsHPNMjUb x6oCKE9L/6w39MuflYvgajknBYdebVH907cwH0kFLrJ1ul8MnDMf0ZP2HocDzLGuncIgWAmtYa9 ZVQdTNmEkZ9Y+l/AhIBbAwe0q1EDZ3M9NpYUYwSsM9GTddntS4pjd/jufYdJvSpJ9OG6KmxTYaL qBMCeAnTqX3IM9V5vzow0SDwYQcnfyE3pFDYtKEIjNTPJ3zpSzbvvbFwupcPPWzgCxK0qCXcYrJ tT4hqv4j4VsVZH/EKVlmCGVEfaWkyW8HSj6g0u8WVIyGm7WCUquR6jI8KWiB+bVEg2Krax/ZpS7 anEqEZ8YhAy44HlvkZzvZiiRWSjw2lzdr7SwdxvHmJGnr8x2tPBAKdg5Wr77kdRfBi2hXdhbjRz OBBAK99ZaSB5cVm5TquoLjoZZgX2DDAM7aU9K01nAuYkrrGm2MBfQp2E7GAfS7tzlOPJt8AY+BZ 0rMyqfWDoe411qYNcKA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-10_03,2026-04-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 lowpriorityscore=0 clxscore=1015 priorityscore=1501 phishscore=0 bulkscore=0 spamscore=0 suspectscore=0 impostorscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604010000 definitions=main-2604100089 From: Abhinav Kumar Add support to program the MST enable bit in the mainlink control register when an MST session is active or being disabled. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 17 +++++++++++++++++ drivers/gpu/drm/msm/dp/dp_reg.h | 4 ++++ 2 files changed, 21 insertions(+) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_c= trl.c index 6f25145ef214..9513de81abc4 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -255,6 +255,19 @@ int msm_dp_ctrl_mst_send_act(struct msm_dp_ctrl *msm_d= p_ctrl) return 0; } =20 +static void msm_dp_ctrl_mst_config(struct msm_dp_ctrl_private *ctrl, bool = enable) +{ + u32 mainlink_ctrl; + + mainlink_ctrl =3D msm_dp_read_link(ctrl, 0, REG_DP_MAINLINK_CTRL); + if (enable) + mainlink_ctrl |=3D DP_MAINLINK_CTRL_MST_EN; + else + mainlink_ctrl &=3D ~DP_MAINLINK_CTRL_MST_EN; + + msm_dp_write_link(ctrl, 0, REG_DP_MAINLINK_CTRL, mainlink_ctrl); +} + /* * NOTE: resetting DP controller will also clear any pending HPD related i= nterrupts */ @@ -2669,6 +2682,9 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_= ctrl, struct msm_dp_panel * =20 msm_dp_ctrl_lane_mapping(ctrl); msm_dp_setup_peripheral_flush(ctrl); + if (ctrl->mst_active) + msm_dp_ctrl_mst_config(ctrl, true); + if (msm_dp_panel->stream_id =3D=3D DP_STREAM_0) msm_dp_ctrl_config_ctrl_link(ctrl); =20 @@ -2726,6 +2742,7 @@ void msm_dp_ctrl_off_link(struct msm_dp_ctrl *msm_dp_= ctrl) phy =3D ctrl->phy; =20 msm_dp_ctrl_mainlink_disable(ctrl); + msm_dp_ctrl_mst_config(ctrl, false); =20 msm_dp_ctrl_reset(&ctrl->msm_dp_ctrl); =20 diff --git a/drivers/gpu/drm/msm/dp/dp_reg.h b/drivers/gpu/drm/msm/dp/dp_re= g.h index 237325d52dbd..87eaaefa014d 100644 --- a/drivers/gpu/drm/msm/dp/dp_reg.h +++ b/drivers/gpu/drm/msm/dp/dp_reg.h @@ -128,6 +128,10 @@ #define DP_MAINLINK_FLUSH_MODE_UPDATE_SDP FIELD_PREP(DP_MAINLINK_CTRL_FLUS= H_MODE_MASK, 1) #define DP_MAINLINK_FLUSH_MODE_SDE_PERIPH_UPDATE FIELD_PREP(DP_MAINLINK_CT= RL_FLUSH_MODE_MASK, 3) #define DP_MAINLINK_FB_BOUNDARY_SEL (0x02000000) +#define DP_MAINLINK_CTRL_ECF_MODE BIT(26) +#define DP_MAINLINK_CTRL_MST_ACTIVE BIT(8) +#define DP_MAINLINK_CTRL_MST_EN (DP_MAINLINK_CTRL_ECF_MODE | \ + DP_MAINLINK_CTRL_MST_ACTIVE) =20 #define REG_DP_STATE_CTRL (0x00000004) #define DP_STATE_CTRL_LINK_TRAINING_PATTERN1 (0x00000001) --=20 2.43.0 From nobody Sat Apr 18 10:45:33 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2AC523BE175 for ; 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Skip the TU programming for MST cases. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_c= trl.c index 9513de81abc4..98316892eccd 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -2698,7 +2698,8 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_= ctrl, struct msm_dp_panel * =20 msm_dp_panel_clear_dsc_dto(msm_dp_panel); =20 - msm_dp_ctrl_setup_tr_unit(ctrl); + if (!ctrl->mst_active) + msm_dp_ctrl_setup_tr_unit(ctrl); =20 msm_dp_write_link(ctrl, 0, REG_DP_STATE_CTRL, DP_STATE_CTRL_SEND_VIDEO); =20 --=20 2.43.0 From nobody Sat Apr 18 10:45:33 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EDE8B33A70E for ; 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[129.46.232.65]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-8ac84cb135fsm19223386d6.38.2026.04.10.02.35.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Apr 2026 02:35:37 -0700 (PDT) From: Yongxing Mou Date: Fri, 10 Apr 2026 17:33:56 +0800 Subject: [PATCH v4 21/39] drm/msm/dp: Add support for MST channel slot allocation Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260410-msm-dp-mst-v4-21-b20518dea8de@oss.qualcomm.com> References: <20260410-msm-dp-mst-v4-0-b20518dea8de@oss.qualcomm.com> In-Reply-To: <20260410-msm-dp-mst-v4-0-b20518dea8de@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Jessica Zhang Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Yongxing Mou , Abhinav Kumar X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1775813628; l=15414; i=yongxing.mou@oss.qualcomm.com; s=20250910; h=from:subject:message-id; bh=/Z1eXht6ut+VWY+LRmTgoTtTXhFrx17GU4z2meq4QT4=; b=tuF+XMDWsjo0yeGWLXL06E+qmDQvMWzsjqw/j6zHmviK5A4zxBqpOfue+mgp7jDEx281ss2xa H8CNLHQ9pBaDq2Kln3/ctHljP/1M5Hm6OJrre0piWq9FwNQtGQUTC2s X-Developer-Key: i=yongxing.mou@oss.qualcomm.com; a=ed25519; pk=rAy5J1eP+V7OXqH5FJ7ngMCtUrnHhut30ZTldOj52UM= X-Authority-Analysis: v=2.4 cv=XtnK/1F9 c=1 sm=1 tr=0 ts=69d8c46c cx=c_pps a=7E5Bxpl4vBhpaufnMqZlrw==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=dHIZ7lCY0nX3Y9ypm_0A:9 a=QEXdDO2ut3YA:10 a=pJ04lnu7RYOZP9TFuWaZ:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDEwMDA4OSBTYWx0ZWRfX9dtwwWnGy5mG 1Hug4buD4f91tPtd8Rn2rnhwLFCajqr+KF+j/H70TG9bg9LLKOOyYUVGqoecvaD5RYddXJaPIEb Ws/0SmR1SHZCbdhaNQODJgB2IIWeQ/Kuxw24EL2oiw2Og8JsptwP8l57pCPszaob4YxzGOwGOoq oMzyI/s34BI5lapgoqdQPUZ9eP6+5HjTVlxyfwU5rZQ5opfCzKOR/0QaR3I3kGBqpNobP0E1lW9 AYNNLVURakzdnP1qYA2vzxx2WHAKjm8Nl7NJVrE460k8ZIc77TctQex9YJuCKNXZQh/Egf8bh8+ RLAb61N6uQvh3x3s3Wb8MD41dmhncBzwoQwk9GZ8eoI7xOyhSDNplK164/sytxnGk2XMzRq8b8i qXCZnHJlcnttZtElQV0AJBK2jcRgYYiZqFD4a0+vrz02NvP6cTzX+4GT/lWUZvNiL7EovyM1Jq7 JNrX1a1DUXZXrNQSQzw== X-Proofpoint-GUID: 7aJFBnsS1mGSUQkoZV4wF-23jtWxTs_l X-Proofpoint-ORIG-GUID: 7aJFBnsS1mGSUQkoZV4wF-23jtWxTs_l X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-10_03,2026-04-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 lowpriorityscore=0 clxscore=1015 malwarescore=0 priorityscore=1501 bulkscore=0 phishscore=0 impostorscore=0 adultscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604010000 definitions=main-2604100089 From: Abhinav Kumar DP MST streams share 64 MTP slots in a time-multiplexed manner. This patch adds support for calculating the rate governor, slot allocation, and slot reservation in the DP controller. Each MST stream can reserve its slots by calling dp_display_set_stream_info() from its bridge callbacks. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 207 ++++++++++++++++++++++++++++++++= ++++ drivers/gpu/drm/msm/dp/dp_ctrl.h | 7 +- drivers/gpu/drm/msm/dp/dp_display.c | 28 +++-- drivers/gpu/drm/msm/dp/dp_display.h | 5 +- drivers/gpu/drm/msm/dp/dp_panel.h | 1 + drivers/gpu/drm/msm/dp/dp_reg.h | 10 ++ 6 files changed, 247 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_c= trl.c index 98316892eccd..e64f81bc8c36 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -73,6 +73,7 @@ #define MR_LINK_PRBS7 0x100 #define MR_LINK_CUSTOM80 0x200 #define MR_LINK_TRAINING4 0x40 +#define DP_MAX_TIME_SLOTS 64 =20 enum { DP_TRAINING_NONE, @@ -109,6 +110,11 @@ struct msm_dp_vc_tu_mapping_table { u8 tu_size_minus1; }; =20 +struct msm_dp_mst_ch_slot_info { + u32 start_slot; + u32 tot_slots; +}; + struct msm_dp_ctrl_private { struct msm_dp_ctrl msm_dp_ctrl; struct drm_device *drm_dev; @@ -144,6 +150,8 @@ struct msm_dp_ctrl_private { bool link_clks_on; bool stream_clks_on[DP_STREAM_MAX]; bool mst_active; + + struct msm_dp_mst_ch_slot_info mst_ch_info[DP_STREAM_MAX]; }; =20 static inline u32 msm_dp_read_ahb(const struct msm_dp_ctrl_private *ctrl, = u32 offset) @@ -268,6 +276,73 @@ static void msm_dp_ctrl_mst_config(struct msm_dp_ctrl_= private *ctrl, bool enable msm_dp_write_link(ctrl, 0, REG_DP_MAINLINK_CTRL, mainlink_ctrl); } =20 +static void msm_dp_ctrl_mst_channel_alloc(struct msm_dp_ctrl_private *ctrl, + enum msm_dp_stream_id stream_id, u32 ch_start_slot, + u32 tot_slot_cnt) +{ + u32 i, slot; + u32 slot_reg_1, slot_reg_2; + u32 reg_off =3D 0; + int const num_slots_per_reg =3D 32; + + if (ch_start_slot > DP_MAX_TIME_SLOTS || + (ch_start_slot + tot_slot_cnt > DP_MAX_TIME_SLOTS)) { + DRM_ERROR("invalid slots start %d, tot %d\n", + ch_start_slot, tot_slot_cnt); + return; + } + + drm_dbg_dp(ctrl->drm_dev, "stream_id %d, start_slot %d, tot_slot %d\n", + stream_id, ch_start_slot, tot_slot_cnt); + + if (stream_id =3D=3D DP_STREAM_1) + reg_off =3D REG_DP_DP1_TIMESLOT_1_32 - REG_DP_DP0_TIMESLOT_1_32; + + slot_reg_1 =3D 0; + slot_reg_2 =3D 0; + + if (ch_start_slot && tot_slot_cnt) { + ch_start_slot--; + for (i =3D 0; i < tot_slot_cnt; i++) { + if (ch_start_slot < num_slots_per_reg) { + slot_reg_1 |=3D BIT(ch_start_slot); + } else { + slot =3D ch_start_slot - num_slots_per_reg; + slot_reg_2 |=3D BIT(slot); + } + ch_start_slot++; + } + } + + drm_dbg_dp(ctrl->drm_dev, "stream_id:%d slot_reg_1:%d, slot_reg_2:%d\n", = stream_id, + slot_reg_1, slot_reg_2); + + msm_dp_write_link(ctrl, stream_id, stream_id > DP_STREAM_1 ? + REG_DP_MSTLINK_TIMESLOT_1_32 : REG_DP_DP0_TIMESLOT_1_32 + reg_off, + slot_reg_1); + msm_dp_write_link(ctrl, stream_id, stream_id > DP_STREAM_1 ? + REG_DP_MSTLINK_TIMESLOT_33_63 : REG_DP_DP0_TIMESLOT_33_63 + reg_off, + slot_reg_2); +} + +static void msm_dp_ctrl_update_rg(struct msm_dp_ctrl_private *ctrl, + enum msm_dp_stream_id stream_id, u32 x_int, u32 y_frac_enum) +{ + u32 rg, reg_off =3D 0; + + rg =3D y_frac_enum; + rg |=3D (x_int << 16); + + drm_dbg_dp(ctrl->drm_dev, "stream_id: %d x_int:%d y_frac_enum:%d rg:%d\n", + stream_id, x_int, y_frac_enum, rg); + + if (stream_id =3D=3D DP_STREAM_1) + reg_off =3D REG_DP_DP1_RG - REG_DP_DP0_RG; + + msm_dp_write_link(ctrl, stream_id, stream_id > 1 ? + REG_DP_MSTLINK_DP_RG : REG_DP_DP0_RG + reg_off, rg); +} + /* * NOTE: resetting DP controller will also clear any pending HPD related i= nterrupts */ @@ -2615,6 +2690,103 @@ static void msm_dp_ctrl_config_msa(struct msm_dp_ct= rl_private *ctrl, nvid); } =20 +/* TODO: comments here. */ +static void msm_dp_ctrl_mst_calculate_rg(struct msm_dp_ctrl_private *ctrl, + struct msm_dp_panel *panel, + u32 *p_x_int, u32 *p_y_frac_enum) +{ + u64 min_slot_cnt, max_slot_cnt; + u64 raw_target_sc, target_sc_fixp; + u64 ts_denom, ts_enum, ts_int; + u64 pclk =3D panel->msm_dp_mode.drm_mode.clock; + u64 lclk =3D 0; + u64 lanes =3D ctrl->link->link_params.num_lanes; + u64 bpp =3D panel->msm_dp_mode.bpp; + u64 pbn =3D panel->pbn; + u64 numerator, denominator, temp, temp1, temp2; + u32 x_int =3D 0, y_frac_enum =3D 0; + u64 target_strm_sym, ts_int_fixp, ts_frac_fixp, y_frac_enum_fixp; + + lclk =3D ctrl->link->link_params.rate; + + /* min_slot_cnt */ + numerator =3D pclk * bpp * 64 * 1000; + denominator =3D lclk * lanes * 8 * 1000; + min_slot_cnt =3D drm_fixp_from_fraction(numerator, denominator); + + /* max_slot_cnt */ + numerator =3D pbn * 54 * 1000; + denominator =3D lclk * lanes; + max_slot_cnt =3D drm_fixp_from_fraction(numerator, denominator); + + /* raw_target_sc */ + numerator =3D max_slot_cnt + min_slot_cnt; + denominator =3D drm_fixp_from_fraction(2, 1); + raw_target_sc =3D drm_fixp_div(numerator, denominator); + + /* target_sc */ + temp =3D drm_fixp_from_fraction(256 * lanes, 1); + numerator =3D drm_fixp_mul(raw_target_sc, temp); + denominator =3D drm_fixp_from_fraction(256 * lanes, 1); + target_sc_fixp =3D drm_fixp_div(numerator, denominator); + + ts_enum =3D 256 * lanes; + ts_denom =3D drm_fixp_from_fraction(256 * lanes, 1); + ts_int =3D drm_fixp2int(target_sc_fixp); + + temp =3D drm_fixp2int_ceil(raw_target_sc); + if (temp !=3D ts_int) { + temp =3D drm_fixp_from_fraction(ts_int, 1); + temp1 =3D raw_target_sc - temp; + temp2 =3D drm_fixp_mul(temp1, ts_denom); + ts_enum =3D drm_fixp2int(temp2); + } + + /* target_strm_sym */ + ts_int_fixp =3D drm_fixp_from_fraction(ts_int, 1); + ts_frac_fixp =3D drm_fixp_from_fraction(ts_enum, drm_fixp2int(ts_denom)); + temp =3D ts_int_fixp + ts_frac_fixp; + temp1 =3D drm_fixp_from_fraction(lanes, 1); + target_strm_sym =3D drm_fixp_mul(temp, temp1); + + /* x_int */ + x_int =3D drm_fixp2int(target_strm_sym); + + /* y_enum_frac */ + temp =3D drm_fixp_from_fraction(x_int, 1); + temp1 =3D target_strm_sym - temp; + temp2 =3D drm_fixp_from_fraction(256, 1); + y_frac_enum_fixp =3D drm_fixp_mul(temp1, temp2); + + temp1 =3D drm_fixp2int(y_frac_enum_fixp); + temp2 =3D drm_fixp2int_ceil(y_frac_enum_fixp); + + y_frac_enum =3D (u32)((temp1 =3D=3D temp2) ? temp1 : temp1 + 1); + + *p_x_int =3D x_int; + *p_y_frac_enum =3D y_frac_enum; + + drm_dbg_dp(ctrl->drm_dev, "MST lane_cnt:%llu, rate:%llu x_int:%d, y_frac:= %d\n", + lanes, lclk, x_int, y_frac_enum); +} + +static void msm_dp_ctrl_mst_stream_setup(struct msm_dp_ctrl_private *ctrl, + struct msm_dp_panel *panel) +{ + u32 x_int, y_frac_enum; + + if (!ctrl->mst_active) + return; + + drm_dbg_dp(ctrl->drm_dev, "MST stream channel allocation\n"); + + msm_dp_ctrl_mst_stream_channel_slot_setup(&ctrl->msm_dp_ctrl); + + msm_dp_ctrl_mst_calculate_rg(ctrl, panel, &x_int, &y_frac_enum); + + msm_dp_ctrl_update_rg(ctrl, panel->stream_id, x_int, y_frac_enum); +} + int msm_dp_ctrl_prepare_stream_on(struct msm_dp_ctrl *msm_dp_ctrl, bool fo= rce_link_train) { int ret =3D 0; @@ -2701,6 +2873,8 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_= ctrl, struct msm_dp_panel * if (!ctrl->mst_active) msm_dp_ctrl_setup_tr_unit(ctrl); =20 + msm_dp_ctrl_mst_stream_setup(ctrl, msm_dp_panel); + msm_dp_write_link(ctrl, 0, REG_DP_STATE_CTRL, DP_STATE_CTRL_SEND_VIDEO); =20 ret =3D msm_dp_ctrl_mst_send_act(msm_dp_ctrl); @@ -2757,6 +2931,39 @@ void msm_dp_ctrl_off_link(struct msm_dp_ctrl *msm_dp= _ctrl) phy, phy->init_count, phy->power_count); } =20 +void msm_dp_ctrl_set_mst_channel_info(struct msm_dp_ctrl *msm_dp_ctrl, + enum msm_dp_stream_id stream_id, + u32 start_slot, u32 tot_slots) +{ + struct msm_dp_ctrl_private *ctrl; + + if (!msm_dp_ctrl || stream_id >=3D DP_STREAM_MAX) { + DRM_ERROR("invalid input\n"); + return; + } + + ctrl =3D container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctr= l); + + ctrl->mst_ch_info[stream_id].start_slot =3D start_slot; + ctrl->mst_ch_info[stream_id].tot_slots =3D tot_slots; +} + +void msm_dp_ctrl_mst_stream_channel_slot_setup(struct msm_dp_ctrl *msm_dp_= ctrl) +{ + struct msm_dp_ctrl_private *ctrl; + int i; + + ctrl =3D container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctr= l); + + if (!ctrl->mst_active) + return; + + for (i =3D DP_STREAM_0; i < ctrl->num_pixel_clks; i++) { + msm_dp_ctrl_mst_channel_alloc(ctrl, i, ctrl->mst_ch_info[i].start_slot, + ctrl->mst_ch_info[i].tot_slots); + } +} + irqreturn_t msm_dp_ctrl_isr(struct msm_dp_ctrl *msm_dp_ctrl) { struct msm_dp_ctrl_private *ctrl; diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.h b/drivers/gpu/drm/msm/dp/dp_c= trl.h index f82fd96e412a..c59338199399 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.h +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.h @@ -17,7 +17,8 @@ struct msm_dp_ctrl { struct phy; =20 int msm_dp_ctrl_on_link(struct msm_dp_ctrl *msm_dp_ctrl, bool mst_active); -int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl, struct msm_dp_p= anel *msm_dp_panel); +int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl, + struct msm_dp_panel *msm_dp_panel); int msm_dp_ctrl_prepare_stream_on(struct msm_dp_ctrl *msm_dp_ctrl, bool fo= rce_link_train); void msm_dp_ctrl_off_link(struct msm_dp_ctrl *msm_dp_ctrl); void msm_dp_ctrl_off_pixel_clk(struct msm_dp_ctrl *msm_dp_ctrl, enum msm_d= p_stream_id stream_id); @@ -52,4 +53,8 @@ void msm_dp_ctrl_disable_irq(struct msm_dp_ctrl *msm_dp_c= trl); void msm_dp_ctrl_reinit_phy(struct msm_dp_ctrl *msm_dp_ctrl); int msm_dp_ctrl_get_stream_cnt(struct msm_dp_ctrl *dp_ctrl); int msm_dp_ctrl_mst_send_act(struct msm_dp_ctrl *msm_dp_ctrl); +void msm_dp_ctrl_mst_stream_channel_slot_setup(struct msm_dp_ctrl *msm_dp_= ctrl); +void msm_dp_ctrl_set_mst_channel_info(struct msm_dp_ctrl *msm_dp_ctrl, + enum msm_dp_stream_id stream_id, + u32 start_slot, u32 tot_slots); #endif /* _DP_CTRL_H_ */ diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index 80bb5fc4003f..e0bf4dffa6af 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -763,11 +763,13 @@ static int msm_dp_display_disable(struct msm_dp_displ= ay_private *dp) return 0; } =20 -int msm_dp_display_set_stream_info(struct msm_dp *msm_dp_display, - struct msm_dp_panel *panel, enum msm_dp_stream_id stream_id) +int msm_dp_display_set_stream_info(struct msm_dp *msm_dp_display, struct m= sm_dp_panel *panel, + enum msm_dp_stream_id stream_id, u32 start_slot, + u32 num_slots, u32 pbn) { int rc =3D 0; struct msm_dp_display_private *dp; + const int max_slots =3D 64; =20 dp =3D container_of(msm_dp_display, struct msm_dp_display_private, msm_dp= _display); =20 @@ -776,7 +778,16 @@ int msm_dp_display_set_stream_info(struct msm_dp *msm_= dp_display, return -EINVAL; } =20 + if (start_slot + num_slots > max_slots) { + DRM_ERROR("invalid channel info received. start:%d, slots:%d\n", + start_slot, num_slots); + return -EINVAL; + } + + msm_dp_ctrl_set_mst_channel_info(dp->ctrl, stream_id, start_slot, num_slo= ts); + panel->stream_id =3D stream_id; + panel->pbn =3D pbn; msm_dp_panel_set_pixel_base(panel, dp->pixel_base[stream_id]); =20 return rc; @@ -1525,7 +1536,7 @@ void msm_dp_display_atomic_enable(struct msm_dp *msm_= dp_display) =20 dp =3D container_of(msm_dp_display, struct msm_dp_display_private, msm_dp= _display); =20 - msm_dp_display_set_stream_info(msm_dp_display, dp->panel, 0); + msm_dp_display_set_stream_info(msm_dp_display, dp->panel, 0, 0, 0, 0); =20 rc =3D msm_dp_display_enable(dp); if (rc) @@ -1540,14 +1551,15 @@ void msm_dp_display_atomic_enable(struct msm_dp *ms= m_dp_display) drm_dbg_dp(msm_dp_display->drm_dev, "type=3D%d Done\n", msm_dp_display->c= onnector_type); } =20 -void msm_dp_display_atomic_disable(struct msm_dp *dp) +void msm_dp_display_atomic_disable(struct msm_dp *msm_dp_display) { - struct msm_dp_display_private *msm_dp_display; + struct msm_dp_display_private *dp; =20 - msm_dp_display =3D container_of(dp, struct msm_dp_display_private, msm_dp= _display); + dp =3D container_of(msm_dp_display, struct msm_dp_display_private, msm_dp= _display); =20 - msm_dp_ctrl_push_idle(msm_dp_display->ctrl); - msm_dp_ctrl_mst_send_act(msm_dp_display->ctrl); + msm_dp_ctrl_push_idle(dp->ctrl); + msm_dp_ctrl_mst_stream_channel_slot_setup(dp->ctrl); + msm_dp_ctrl_mst_send_act(dp->ctrl); } =20 static void msm_dp_display_unprepare(struct msm_dp_display_private *dp) diff --git a/drivers/gpu/drm/msm/dp/dp_display.h b/drivers/gpu/drm/msm/dp/d= p_display.h index fdbe6e4871d9..0ccdddb223c8 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.h +++ b/drivers/gpu/drm/msm/dp/dp_display.h @@ -43,7 +43,8 @@ void msm_dp_display_atomic_enable(struct msm_dp *dp_displ= ay); enum drm_mode_status msm_dp_display_mode_valid(struct msm_dp *dp, const struct drm_display_info *info, const struct drm_display_mode *mode); -int msm_dp_display_set_stream_info(struct msm_dp *msm_dp_display, - struct msm_dp_panel *panel, enum msm_dp_stream_id stream_id); +int msm_dp_display_set_stream_info(struct msm_dp *msm_dp_display, struct m= sm_dp_panel *panel, + enum msm_dp_stream_id stream_id, + u32 start_slot, u32 num_slots, u32 pbn); =20 #endif /* _DP_DISPLAY_H_ */ diff --git a/drivers/gpu/drm/msm/dp/dp_panel.h b/drivers/gpu/drm/msm/dp/dp_= panel.h index 4873c55bd693..8e7374de90eb 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.h +++ b/drivers/gpu/drm/msm/dp/dp_panel.h @@ -50,6 +50,7 @@ struct msm_dp_panel { u32 hw_revision; =20 enum msm_dp_stream_id stream_id; + u32 pbn; =20 u32 max_bw_code; }; diff --git a/drivers/gpu/drm/msm/dp/dp_reg.h b/drivers/gpu/drm/msm/dp/dp_re= g.h index 87eaaefa014d..835a55446868 100644 --- a/drivers/gpu/drm/msm/dp/dp_reg.h +++ b/drivers/gpu/drm/msm/dp/dp_reg.h @@ -338,7 +338,13 @@ #define DP_TPG_VIDEO_CONFIG_RGB (0x00000004) =20 /* DP MST registers */ + +#define REG_DP_MSTLINK_DP_RG (0X0000011C) #define REG_DP1_CONFIGURATION_CTRL (0x00000400) +#define REG_DP_DP0_TIMESLOT_1_32 (0x00000404) +#define REG_DP_DP0_TIMESLOT_33_63 (0x00000408) +#define REG_DP_DP1_TIMESLOT_1_32 (0x0000040C) +#define REG_DP_DP1_TIMESLOT_33_63 (0x00000410) #define REG_DP1_SOFTWARE_MVID (0x00000414) #define REG_DP1_SOFTWARE_NVID (0x00000418) #define REG_DP1_TOTAL_HOR_VER (0x0000041C) @@ -347,8 +353,12 @@ #define MMSS_DP1_SDP_CFG (0x000004E0) #define MMSS_DP1_SDP_CFG2 (0x000004E4) #define MMSS_DP1_SDP_CFG3 (0x000004E8) +#define REG_DP_DP0_RG (0x000004F8) +#define REG_DP_DP1_RG (0x000004FC) =20 #define REG_DP_MSTLINK_CONFIGURATION_CTRL (0x00000034) +#define REG_DP_MSTLINK_TIMESLOT_1_32 (0x00000038) +#define REG_DP_MSTLINK_TIMESLOT_33_63 (0x0000003C) #define REG_MSTLINK_SOFTWARE_MVID (0x00000040) #define REG_MSTLINK_SOFTWARE_NVID (0x00000044) #define REG_DP_MSTLINK_TOTAL_HOR_VER (0x00000048) --=20 2.43.0 From nobody Sat Apr 18 10:45:33 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EA3AF346770 for ; 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This patch adds support for triggering the VCPF sequence in the MSM DP controller. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 55 +++++++++++++++++++++++++++++++++= +--- drivers/gpu/drm/msm/dp/dp_ctrl.h | 2 +- drivers/gpu/drm/msm/dp/dp_display.c | 2 +- drivers/gpu/drm/msm/dp/dp_reg.h | 5 ++++ 4 files changed, 58 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_c= trl.c index e64f81bc8c36..9907f2e56e65 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -65,9 +65,18 @@ (PSR_UPDATE_MASK | PSR_CAPTURE_MASK | PSR_EXIT_MASK | \ PSR_UPDATE_ERROR_MASK | PSR_WAKE_ERROR_MASK) =20 +#define DP_INTERRUPT_STATUS5 \ + (DP_INTR_DP0_VCPF_SENT | DP_INTR_DP1_VCPF_SENT) +#define DP_INTERRUPT_STATUS5_MASK \ + (DP_INTERRUPT_STATUS5 << DP_INTERRUPT_STATUS_MASK_SHIFT) + #define DP_CTRL_INTR_READY_FOR_VIDEO BIT(0) #define DP_CTRL_INTR_IDLE_PATTERN_SENT BIT(3) =20 +#define DP_DP0_PUSH_VCPF BIT(12) +#define DP_DP1_PUSH_VCPF BIT(14) +#define DP_MSTLINK_PUSH_VCPF BIT(12) + #define MR_LINK_TRAINING1 0x8 #define MR_LINK_SYMBOL_ERM 0x80 #define MR_LINK_PRBS7 0x100 @@ -405,6 +414,8 @@ void msm_dp_ctrl_enable_irq(struct msm_dp_ctrl *msm_dp_= ctrl) DP_INTERRUPT_STATUS1_MASK); msm_dp_write_ahb(ctrl, REG_DP_INTR_STATUS2, DP_INTERRUPT_STATUS2_MASK); + msm_dp_write_ahb(ctrl, REG_DP_INTR_STATUS5, + DP_INTERRUPT_STATUS5_MASK); } =20 void msm_dp_ctrl_disable_irq(struct msm_dp_ctrl *msm_dp_ctrl) @@ -414,6 +425,7 @@ void msm_dp_ctrl_disable_irq(struct msm_dp_ctrl *msm_dp= _ctrl) =20 msm_dp_write_ahb(ctrl, REG_DP_INTR_STATUS, 0x00); msm_dp_write_ahb(ctrl, REG_DP_INTR_STATUS2, 0x00); + msm_dp_write_ahb(ctrl, REG_DP_INTR_STATUS5, 0x00); } =20 static u32 msm_dp_ctrl_get_psr_interrupt(struct msm_dp_ctrl_private *ctrl) @@ -433,6 +445,20 @@ static void msm_dp_ctrl_config_psr_interrupt(struct ms= m_dp_ctrl_private *ctrl) msm_dp_write_ahb(ctrl, REG_DP_INTR_MASK4, DP_INTERRUPT_MASK4); } =20 +static u32 msm_dp_ctrl_get_mst_interrupt(struct msm_dp_ctrl_private *ctrl) +{ + u32 intr, intr_ack; + + intr =3D msm_dp_read_ahb(ctrl, REG_DP_INTR_STATUS5); + intr &=3D ~DP_INTERRUPT_STATUS5_MASK; + intr_ack =3D (intr & DP_INTERRUPT_STATUS5) + << DP_INTERRUPT_STATUS_ACK_SHIFT; + msm_dp_write_ahb(ctrl, REG_DP_INTR_STATUS5, + intr_ack | DP_INTERRUPT_STATUS5_MASK); + + return intr; +} + static void msm_dp_ctrl_psr_mainlink_enable(struct msm_dp_ctrl_private *ct= rl) { u32 val; @@ -516,14 +542,28 @@ static bool msm_dp_ctrl_mainlink_ready(struct msm_dp_= ctrl_private *ctrl) return true; } =20 -void msm_dp_ctrl_push_idle(struct msm_dp_ctrl *msm_dp_ctrl) +void msm_dp_ctrl_push_idle(struct msm_dp_ctrl *msm_dp_ctrl, struct msm_dp_= panel *msm_dp_panel) { struct msm_dp_ctrl_private *ctrl; + u32 state =3D 0x0; =20 ctrl =3D container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctr= l); =20 + if (!ctrl->mst_active) + state |=3D DP_STATE_CTRL_PUSH_IDLE; + else if (msm_dp_panel->stream_id =3D=3D DP_STREAM_0) + state |=3D DP_DP0_PUSH_VCPF; + else if (msm_dp_panel->stream_id =3D=3D DP_STREAM_1) + state |=3D DP_DP1_PUSH_VCPF; + else + state |=3D DP_MSTLINK_PUSH_VCPF; + reinit_completion(&ctrl->idle_comp); - msm_dp_write_link(ctrl, 0, REG_DP_STATE_CTRL, DP_STATE_CTRL_PUSH_IDLE); + + msm_dp_write_link(ctrl, msm_dp_panel->stream_id, + msm_dp_panel->stream_id > 1 ? + REG_DP_MSTLINK_STATE_CTRL : REG_DP_STATE_CTRL, + state); =20 if (!wait_for_completion_timeout(&ctrl->idle_comp, IDLE_PATTERN_COMPLETION_TIMEOUT_JIFFIES)) @@ -2073,7 +2113,7 @@ void msm_dp_ctrl_set_psr(struct msm_dp_ctrl *msm_dp_c= trl, bool enter) return; } =20 - msm_dp_ctrl_push_idle(msm_dp_ctrl); + msm_dp_ctrl_push_idle(msm_dp_ctrl, ctrl->panel); msm_dp_write_link(ctrl, 0, REG_DP_STATE_CTRL, 0); =20 msm_dp_ctrl_psr_mainlink_disable(ctrl); @@ -2183,7 +2223,7 @@ static int msm_dp_ctrl_link_maintenance(struct msm_dp= _ctrl_private *ctrl) int ret =3D 0; int training_step =3D DP_TRAINING_NONE; =20 - msm_dp_ctrl_push_idle(&ctrl->msm_dp_ctrl); + msm_dp_ctrl_push_idle(&ctrl->msm_dp_ctrl, ctrl->panel); =20 ctrl->link->phy_params.p_level =3D 0; ctrl->link->phy_params.v_level =3D 0; @@ -3005,6 +3045,13 @@ irqreturn_t msm_dp_ctrl_isr(struct msm_dp_ctrl *msm_= dp_ctrl) ret =3D IRQ_HANDLED; } =20 + isr =3D msm_dp_ctrl_get_mst_interrupt(ctrl); + if (isr & (DP_INTR_DP0_VCPF_SENT | DP_INTR_DP1_VCPF_SENT)) { + drm_dbg_dp(ctrl->drm_dev, "vcpf sent\n"); + complete(&ctrl->idle_comp); + ret =3D IRQ_HANDLED; + } + /* DP aux isr */ isr =3D msm_dp_ctrl_get_aux_interrupt(ctrl); if (isr) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.h b/drivers/gpu/drm/msm/dp/dp_c= trl.h index c59338199399..cfe7e4496943 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.h +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.h @@ -22,7 +22,7 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl, int msm_dp_ctrl_prepare_stream_on(struct msm_dp_ctrl *msm_dp_ctrl, bool fo= rce_link_train); void msm_dp_ctrl_off_link(struct msm_dp_ctrl *msm_dp_ctrl); void msm_dp_ctrl_off_pixel_clk(struct msm_dp_ctrl *msm_dp_ctrl, enum msm_d= p_stream_id stream_id); -void msm_dp_ctrl_push_idle(struct msm_dp_ctrl *msm_dp_ctrl); +void msm_dp_ctrl_push_idle(struct msm_dp_ctrl *msm_dp_ctrl, struct msm_dp_= panel *msm_dp_panel); irqreturn_t msm_dp_ctrl_isr(struct msm_dp_ctrl *msm_dp_ctrl); void msm_dp_ctrl_handle_sink_request(struct msm_dp_ctrl *msm_dp_ctrl); struct msm_dp_ctrl *msm_dp_ctrl_get(struct device *dev, diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index e0bf4dffa6af..e8028402f748 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -1557,7 +1557,7 @@ void msm_dp_display_atomic_disable(struct msm_dp *msm= _dp_display) =20 dp =3D container_of(msm_dp_display, struct msm_dp_display_private, msm_dp= _display); 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[129.46.232.65]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-8ac84cb135fsm19223386d6.38.2026.04.10.02.35.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Apr 2026 02:35:48 -0700 (PDT) From: Yongxing Mou Date: Fri, 10 Apr 2026 17:33:58 +0800 Subject: [PATCH v4 23/39] drm/msm/dp: Always program MST_FIFO_CONSTANT_FILL for MST use cases Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260410-msm-dp-mst-v4-23-b20518dea8de@oss.qualcomm.com> References: <20260410-msm-dp-mst-v4-0-b20518dea8de@oss.qualcomm.com> In-Reply-To: <20260410-msm-dp-mst-v4-0-b20518dea8de@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Jessica Zhang Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Yongxing Mou , Abhinav Kumar , Dmitry Baryshkov X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1775813628; l=2580; i=yongxing.mou@oss.qualcomm.com; s=20250910; h=from:subject:message-id; bh=jH0cVfAtP120hSC87AlhdrymlK41cuTeQOw2p6hhzug=; b=TtbOcGnnVswOiKEFrkl2fRDSQNtLGseH0eo6Qi9FfVVeScNHdeQbh+Kebi1069Ykexg/gfjI4 uQhj74dlbysB7fpOEiHFemwt11gXJQVSUyJkUHRGbh0HTUo+lbJWssh X-Developer-Key: i=yongxing.mou@oss.qualcomm.com; a=ed25519; pk=rAy5J1eP+V7OXqH5FJ7ngMCtUrnHhut30ZTldOj52UM= X-Authority-Analysis: v=2.4 cv=X+hi7mTe c=1 sm=1 tr=0 ts=69d8c476 cx=c_pps a=UgVkIMxJMSkC9lv97toC5g==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=HaeL3RsyjvW3zFWBFcMA:9 a=QEXdDO2ut3YA:10 a=1HOtulTD9v-eNWfpl4qZ:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: yF9swJZrSwD6KnC3y3zzFlE2Yd51vsre X-Proofpoint-ORIG-GUID: yF9swJZrSwD6KnC3y3zzFlE2Yd51vsre X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDEwMDA4OSBTYWx0ZWRfXzry09PELnNRw JgmkzMXWAQXTDPS64sVNFKxG5qXPD6PlpoyEE4/K9Pe0bC/J/sUuHlDf+y6fyx15lviREl6JfPX pWjNbGC0EDFBVuUNuKkCkKA7jFWSS5DO4eCU4Er/ksxvQgrlLOZHGJy01WhfsOygz2uuUC6lAU+ INuTPAiYgVFvNlG/NJvO9MuQgoW98dqjd6vL2AvhlPoG7TvA0senNHoyQw6RFPQo5MksxaUtskK kI4uilxgp4xrRvwGCjU/w7q6dmX/NjlwS+/QLCQ3spJsP8uu/QWu/z46A7+IlnndoadV1B6gU7p vmWuBrvW05eVITZ3VGBqaIe6s2PWJa6R/VWOHym0EDMwwfBN2hObcFvKxzA2LLPCukP8QerQRNp rH4OcHVfXb125UELcsxWxVWGkFvHup/0+b2NWv+f0u2GuaCY4g74szlcJDmAOxvUTOGG4UC1Byo cvJyqMhmEZPz6sktnIg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-10_03,2026-04-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 malwarescore=0 clxscore=1015 adultscore=0 priorityscore=1501 lowpriorityscore=0 suspectscore=0 spamscore=0 bulkscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604010000 definitions=main-2604100089 From: Abhinav Kumar As per the hardware programming guide, MST_FIFO_CONSTANT_FILL must always be programmed when operating in MST mode. This patch ensures the register is configured accordingly. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 2 ++ drivers/gpu/drm/msm/dp/dp_panel.c | 12 ++++++++++++ drivers/gpu/drm/msm/dp/dp_panel.h | 2 ++ 3 files changed, 16 insertions(+) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_c= trl.c index 9907f2e56e65..199c2806aaa2 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -685,6 +685,8 @@ static void msm_dp_ctrl_configure_source_params(struct = msm_dp_ctrl_private *ctrl msm_dp_ctrl_config_misc1_misc0(ctrl, msm_dp_panel); =20 msm_dp_panel_timing_cfg(msm_dp_panel, ctrl->msm_dp_ctrl.wide_bus_en); + + msm_dp_panel_mst_async_fifo(msm_dp_panel, ctrl->mst_active); } =20 /* diff --git a/drivers/gpu/drm/msm/dp/dp_panel.c b/drivers/gpu/drm/msm/dp/dp_= panel.c index a8a6297b37e3..e05d96f33c43 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.c +++ b/drivers/gpu/drm/msm/dp/dp_panel.c @@ -753,6 +753,18 @@ void msm_dp_panel_set_pixel_base(struct msm_dp_panel *= msm_dp_panel, void __iomem panel->pixel_base =3D pixel_base; } =20 +void msm_dp_panel_mst_async_fifo(struct msm_dp_panel *msm_dp_panel, bool m= st_en) +{ + struct msm_dp_panel_private *panel; + + panel =3D container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_= panel); + + if (mst_en) + msm_dp_write_pn(panel, MMSS_DP_ASYNC_FIFO_CONFIG, 0x01); + else + msm_dp_write_pn(panel, MMSS_DP_ASYNC_FIFO_CONFIG, 0x00); +} + int msm_dp_panel_init_panel_info(struct msm_dp_panel *msm_dp_panel) { struct drm_display_mode *drm_mode; diff --git a/drivers/gpu/drm/msm/dp/dp_panel.h b/drivers/gpu/drm/msm/dp/dp_= panel.h index 8e7374de90eb..8bab27520439 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.h +++ b/drivers/gpu/drm/msm/dp/dp_panel.h @@ -72,6 +72,8 @@ void msm_dp_panel_set_pixel_base(struct msm_dp_panel *msm= _dp_panel, void __iomem void msm_dp_panel_enable_vsc_sdp(struct msm_dp_panel *msm_dp_panel, struct= dp_sdp *vsc_sdp); void msm_dp_panel_disable_vsc_sdp(struct msm_dp_panel *msm_dp_panel); =20 +void msm_dp_panel_mst_async_fifo(struct msm_dp_panel *msm_dp_panel, bool m= st_en); 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No functional change intended. Signed-off-by: Yongxing Mou Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_display.c | 25 ++++++++----------------- 1 file changed, 8 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index e8028402f748..7b3b9160e005 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -734,28 +734,19 @@ static int msm_dp_display_disable(struct msm_dp_displ= ay_private *dp) =20 msm_dp_panel_disable_vsc_sdp(dp->panel); =20 - /* dongle is still connected but sinks are disconnected */ - if (dp->link->sink_count =3D=3D 0) { - /* - * irq_hpd with sink_count =3D 0 - * hdmi unplugged out of dongle - */ + msm_dp_ctrl_off_pixel_clk(dp->ctrl, dp->panel->stream_id); =20 - /* set dongle to D3 (power off) mode */ + /* dongle is still connected but sinks are disconnected */ + if (dp->link->sink_count =3D=3D 0) msm_dp_link_psm_config(dp->link, &dp->panel->link_info, true); - msm_dp_ctrl_off_pixel_clk(dp->ctrl, dp->panel->stream_id); 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Signed-off-by: Yongxing Mou --- drivers/gpu/drm/msm/dp/dp_display.c | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index 7b3b9160e005..88a078e53dc1 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -668,7 +668,8 @@ static int msm_dp_display_prepare(struct msm_dp_display= _private *dp) return msm_dp_ctrl_prepare_stream_on(dp->ctrl, force_link_train); } =20 -static int msm_dp_display_enable(struct msm_dp_display_private *dp) +static int msm_dp_display_enable(struct msm_dp_display_private *dp, + struct msm_dp_panel *msm_dp_panel) { int rc =3D 0; struct msm_dp *msm_dp_display =3D &dp->msm_dp_display; @@ -725,20 +726,21 @@ static void msm_dp_display_audio_notify_disable(struc= t msm_dp_display_private *d msm_dp_display->audio_enabled =3D false; } =20 -static int msm_dp_display_disable(struct msm_dp_display_private *dp) +static int msm_dp_display_disable(struct msm_dp_display_private *dp, + struct msm_dp_panel *msm_dp_panel) { struct msm_dp *msm_dp_display =3D &dp->msm_dp_display; =20 if (!msm_dp_display->power_on) return 0; =20 - msm_dp_panel_disable_vsc_sdp(dp->panel); + msm_dp_panel_disable_vsc_sdp(msm_dp_panel); =20 - msm_dp_ctrl_off_pixel_clk(dp->ctrl, dp->panel->stream_id); + msm_dp_ctrl_off_pixel_clk(dp->ctrl, msm_dp_panel->stream_id); =20 /* dongle is still connected but sinks are disconnected */ if (dp->link->sink_count =3D=3D 0) - msm_dp_link_psm_config(dp->link, &dp->panel->link_info, true); + msm_dp_link_psm_config(dp->link, &msm_dp_panel->link_info, true); =20 msm_dp_ctrl_off_link(dp->ctrl); =20 @@ -1529,14 +1531,14 @@ void msm_dp_display_atomic_enable(struct msm_dp *ms= m_dp_display) =20 msm_dp_display_set_stream_info(msm_dp_display, dp->panel, 0, 0, 0, 0); =20 - rc =3D msm_dp_display_enable(dp); + rc =3D msm_dp_display_enable(dp, dp->panel); if (rc) DRM_ERROR("DP display enable failed, rc=3D%d\n", rc); =20 rc =3D msm_dp_display_post_enable(msm_dp_display); if (rc) { DRM_ERROR("DP display post enable failed, rc=3D%d\n", rc); - msm_dp_display_disable(dp); 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To be able to re-use these helpers for MST use-case abstract the helpers to use the panel which is passed in to them. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou --- drivers/gpu/drm/msm/dp/dp_display.c | 117 ++++++++++++++++++++++++--------= ---- drivers/gpu/drm/msm/dp/dp_display.h | 12 ++++ 2 files changed, 91 insertions(+), 38 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index 88a078e53dc1..33d8539afee7 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -635,12 +635,14 @@ static int msm_dp_display_set_mode(struct msm_dp *msm= _dp_display, return 0; } =20 -static int msm_dp_display_prepare(struct msm_dp_display_private *dp) +int msm_dp_display_prepare(struct msm_dp *msm_dp_display) { - struct msm_dp *msm_dp_display =3D &dp->msm_dp_display; + struct msm_dp_display_private *dp; int rc =3D 0; bool force_link_train =3D false; =20 + dp =3D container_of(msm_dp_display, struct msm_dp_display_private, msm_dp= _display); + drm_dbg_dp(dp->drm_dev, "sink_count=3D%d\n", dp->link->sink_count); =20 if (msm_dp_display->is_edp) @@ -680,7 +682,7 @@ static int msm_dp_display_enable(struct msm_dp_display_= private *dp, return 0; } =20 - rc =3D msm_dp_ctrl_on_stream(dp->ctrl, dp->panel); + rc =3D msm_dp_ctrl_on_stream(dp->ctrl, msm_dp_panel); if (!rc) msm_dp_display->power_on =3D true; =20 @@ -738,18 +740,6 @@ static int msm_dp_display_disable(struct msm_dp_displa= y_private *dp, =20 msm_dp_ctrl_off_pixel_clk(dp->ctrl, msm_dp_panel->stream_id); =20 - /* dongle is still connected but sinks are disconnected */ - if (dp->link->sink_count =3D=3D 0) - msm_dp_link_psm_config(dp->link, &msm_dp_panel->link_info, true); - - msm_dp_ctrl_off_link(dp->ctrl); - - if (dp->link->sink_count =3D=3D 0) - /* re-init the PHY so that we can listen to Dongle disconnect */ - msm_dp_ctrl_reinit_phy(dp->ctrl); - else - msm_dp_display_host_phy_exit(dp); - msm_dp_display->power_on =3D false; =20 drm_dbg_dp(dp->drm_dev, "sink count: %d\n", dp->link->sink_count); @@ -1495,76 +1485,116 @@ int msm_dp_modeset_init(struct msm_dp *msm_dp_disp= lay, struct drm_device *dev, return 0; } =20 -void msm_dp_display_atomic_prepare(struct msm_dp *msm_dp_display, - struct drm_atomic_state *state) +int msm_dp_display_set_mode_helper(struct msm_dp *msm_dp_display, + struct drm_atomic_state *state, + struct drm_encoder *drm_encoder, + struct msm_dp_panel *msm_dp_panel) { struct drm_crtc *crtc; struct drm_crtc_state *crtc_state; + + crtc =3D drm_atomic_get_new_crtc_for_encoder(state, drm_encoder); + if (!crtc) + return 0; + crtc_state =3D drm_atomic_get_new_crtc_state(state, crtc); + + return msm_dp_display_set_mode(msm_dp_display, &crtc_state->adjusted_mode= , msm_dp_panel); +} + +void msm_dp_display_atomic_prepare(struct msm_dp *msm_dp_display, + struct drm_atomic_state *state) +{ int rc =3D 0; struct msm_dp_display_private *dp; =20 dp =3D container_of(msm_dp_display, struct msm_dp_display_private, msm_dp= _display); =20 - crtc =3D drm_atomic_get_new_crtc_for_encoder(state, - msm_dp_display->bridge->encoder); - if (!crtc) - return; - crtc_state =3D drm_atomic_get_new_crtc_state(state, crtc); - - rc =3D msm_dp_display_set_mode(msm_dp_display, &crtc_state->adjusted_mode= , dp->panel); + rc =3D msm_dp_display_set_mode_helper(msm_dp_display, state, + msm_dp_display->bridge->encoder, dp->panel); if (rc) { DRM_ERROR("Failed to perform a mode set, rc=3D%d\n", rc); return; } =20 - rc =3D msm_dp_display_prepare(dp); + rc =3D msm_dp_display_prepare(msm_dp_display); if (rc) DRM_ERROR("DP display prepare failed, rc=3D%d\n", rc); } =20 -void msm_dp_display_atomic_enable(struct msm_dp *msm_dp_display) +void msm_dp_display_enable_helper(struct msm_dp *msm_dp_display, struct ms= m_dp_panel *msm_dp_panel) { struct msm_dp_display_private *dp; int rc =3D 0; =20 dp =3D container_of(msm_dp_display, struct msm_dp_display_private, msm_dp= _display); =20 - msm_dp_display_set_stream_info(msm_dp_display, dp->panel, 0, 0, 0, 0); - - rc =3D msm_dp_display_enable(dp, dp->panel); + rc =3D msm_dp_display_enable(dp, msm_dp_panel); if (rc) DRM_ERROR("DP display enable failed, rc=3D%d\n", rc); =20 rc =3D msm_dp_display_post_enable(msm_dp_display); if (rc) { DRM_ERROR("DP display post enable failed, rc=3D%d\n", rc); - msm_dp_display_disable(dp, dp->panel); + msm_dp_display_disable(dp, msm_dp_panel); } =20 drm_dbg_dp(msm_dp_display->drm_dev, "type=3D%d Done\n", msm_dp_display->c= onnector_type); } =20 -void msm_dp_display_atomic_disable(struct msm_dp *msm_dp_display) +void msm_dp_display_atomic_enable(struct msm_dp *msm_dp_display) { struct msm_dp_display_private *dp; =20 dp =3D container_of(msm_dp_display, struct msm_dp_display_private, msm_dp= _display); =20 - msm_dp_ctrl_push_idle(dp->ctrl, dp->panel); + msm_dp_display_set_stream_info(msm_dp_display, dp->panel, 0, 0, 0, 0); + + msm_dp_display_enable_helper(msm_dp_display, dp->panel); +} + +void msm_dp_display_disable_helper(struct msm_dp *msm_dp_display, + struct msm_dp_panel *msm_dp_panel) +{ + struct msm_dp_display_private *dp; + + dp =3D container_of(msm_dp_display, struct msm_dp_display_private, msm_dp= _display); + + msm_dp_ctrl_push_idle(dp->ctrl, msm_dp_panel); msm_dp_ctrl_mst_stream_channel_slot_setup(dp->ctrl); msm_dp_ctrl_mst_send_act(dp->ctrl); } =20 -static void msm_dp_display_unprepare(struct msm_dp_display_private *dp) +void msm_dp_display_atomic_disable(struct msm_dp *msm_dp_display) { - struct msm_dp *msm_dp_display =3D &dp->msm_dp_display; + struct msm_dp_display_private *dp; =20 - pm_runtime_put_sync(&msm_dp_display->pdev->dev); + dp =3D container_of(msm_dp_display, struct msm_dp_display_private, msm_dp= _display); + + msm_dp_display_disable_helper(msm_dp_display, dp->panel); +} + +void msm_dp_display_unprepare(struct msm_dp *msm_dp_display) +{ + struct msm_dp_display_private *dp; + + dp =3D container_of(msm_dp_display, struct msm_dp_display_private, msm_dp= _display); =20 - drm_dbg_dp(dp->drm_dev, "type=3D%d Done\n", msm_dp_display->connector_typ= e); + /* dongle is still connected but sinks are disconnected */ + if (dp->link->sink_count =3D=3D 0) + msm_dp_link_psm_config(dp->link, &dp->panel->link_info, true); + + msm_dp_ctrl_off_link(dp->ctrl); + + /* re-init the PHY so that we can listen to Dongle disconnect */ + if (dp->link->sink_count =3D=3D 0) + msm_dp_ctrl_reinit_phy(dp->ctrl); + else + msm_dp_display_host_phy_exit(dp); + + pm_runtime_put_sync(&msm_dp_display->pdev->dev); } =20 -void msm_dp_display_atomic_post_disable(struct msm_dp *dp) +void msm_dp_display_atomic_post_disable_helper(struct msm_dp *dp, struct m= sm_dp_panel *msm_dp_panel) { struct msm_dp_display_private *msm_dp_display; =20 @@ -1575,7 +1605,18 @@ void msm_dp_display_atomic_post_disable(struct msm_d= p *dp) =20 msm_dp_display_audio_notify_disable(msm_dp_display); =20 - msm_dp_display_disable(msm_dp_display, msm_dp_display->panel); + msm_dp_display_disable(msm_dp_display, msm_dp_panel); + + drm_dbg_dp(dp->drm_dev, "type=3D%d Done\n", dp->connector_type); +} + +void msm_dp_display_atomic_post_disable(struct msm_dp *msm_dp_display) +{ + struct msm_dp_display_private *dp; + + dp =3D container_of(msm_dp_display, struct msm_dp_display_private, msm_dp= _display); + + msm_dp_display_atomic_post_disable_helper(msm_dp_display, dp->panel); =20 msm_dp_display_unprepare(msm_dp_display); } diff --git a/drivers/gpu/drm/msm/dp/dp_display.h b/drivers/gpu/drm/msm/dp/d= p_display.h index 0ccdddb223c8..0ede5505be58 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.h +++ b/drivers/gpu/drm/msm/dp/dp_display.h @@ -46,5 +46,17 @@ enum drm_mode_status msm_dp_display_mode_valid(struct ms= m_dp *dp, int msm_dp_display_set_stream_info(struct msm_dp *msm_dp_display, struct m= sm_dp_panel *panel, enum msm_dp_stream_id stream_id, u32 start_slot, u32 num_slots, u32 pbn); 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Introduce an active_stream_cnt to track the number of active streams and necessary state handling. Replace the power_on variable with active_stream_cnt as power_on boolean works only for a single stream. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou --- drivers/gpu/drm/msm/dp/dp_audio.c | 2 +- drivers/gpu/drm/msm/dp/dp_display.c | 38 +++++++++++++++++++--------------= ---- drivers/gpu/drm/msm/dp/dp_display.h | 2 +- 3 files changed, 22 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_audio.c b/drivers/gpu/drm/msm/dp/dp_= audio.c index 41018e82efa1..035e230201fd 100644 --- a/drivers/gpu/drm/msm/dp/dp_audio.c +++ b/drivers/gpu/drm/msm/dp/dp_audio.c @@ -284,7 +284,7 @@ int msm_dp_audio_prepare(struct drm_bridge *bridge, * such cases check for connection status and bail out if not * connected. */ - if (!msm_dp_display->power_on) { + if (!msm_dp_display->active_stream_cnt) { rc =3D -EINVAL; goto end; } diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index 33d8539afee7..e6ecbb3a688e 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -657,15 +657,15 @@ int msm_dp_display_prepare(struct msm_dp *msm_dp_disp= lay) if (dp->link->sink_count =3D=3D 0) return rc; =20 - if (!msm_dp_display->power_on) { + if (!msm_dp_display->active_stream_cnt) { msm_dp_display_host_phy_init(dp); force_link_train =3D true; - } =20 - rc =3D msm_dp_ctrl_on_link(dp->ctrl, msm_dp_display->mst_active); - if (rc) - DRM_ERROR("Failed link training (rc=3D%d)\n", rc); - // TODO: schedule drm_connector_set_link_status_property() + rc =3D msm_dp_ctrl_on_link(dp->ctrl, msm_dp_display->mst_active); + if (rc) + DRM_ERROR("Failed link training (rc=3D%d)\n", rc); + // TODO: schedule drm_connector_set_link_status_property() + } =20 return msm_dp_ctrl_prepare_stream_on(dp->ctrl, force_link_train); } @@ -674,18 +674,12 @@ static int msm_dp_display_enable(struct msm_dp_displa= y_private *dp, struct msm_dp_panel *msm_dp_panel) { int rc =3D 0; - struct msm_dp *msm_dp_display =3D &dp->msm_dp_display; =20 drm_dbg_dp(dp->drm_dev, "sink_count=3D%d\n", dp->link->sink_count); - if (msm_dp_display->power_on) { - drm_dbg_dp(dp->drm_dev, "Link already setup, return\n"); - return 0; - } =20 rc =3D msm_dp_ctrl_on_stream(dp->ctrl, msm_dp_panel); - if (!rc) - msm_dp_display->power_on =3D true; =20 + dp->msm_dp_display.active_stream_cnt++; return rc; } =20 @@ -731,16 +725,14 @@ static void msm_dp_display_audio_notify_disable(struc= t msm_dp_display_private *d static int msm_dp_display_disable(struct msm_dp_display_private *dp, struct msm_dp_panel *msm_dp_panel) { - struct msm_dp *msm_dp_display =3D &dp->msm_dp_display; - - if (!msm_dp_display->power_on) + if (!dp->msm_dp_display.active_stream_cnt) return 0; =20 msm_dp_panel_disable_vsc_sdp(msm_dp_panel); =20 msm_dp_ctrl_off_pixel_clk(dp->ctrl, msm_dp_panel->stream_id); =20 - msm_dp_display->power_on =3D false; + dp->msm_dp_display.active_stream_cnt--; =20 drm_dbg_dp(dp->drm_dev, "sink count: %d\n", dp->link->sink_count); return 0; @@ -876,7 +868,7 @@ void msm_dp_snapshot(struct msm_disp_state *disp_state,= struct msm_dp *dp) * power_on status before dumping DP registers to avoid crash due * to unclocked access */ - if (!dp->power_on) + if (!dp->active_stream_cnt) return; =20 msm_disp_snapshot_add_block(disp_state, msm_dp_display->ahb_len, @@ -1559,6 +1551,11 @@ void msm_dp_display_disable_helper(struct msm_dp *ms= m_dp_display, =20 dp =3D container_of(msm_dp_display, struct msm_dp_display_private, msm_dp= _display); =20 + if (!msm_dp_display->active_stream_cnt) { + drm_dbg_dp(dp->drm_dev, "no active streams\n"); + return; + } + msm_dp_ctrl_push_idle(dp->ctrl, msm_dp_panel); msm_dp_ctrl_mst_stream_channel_slot_setup(dp->ctrl); msm_dp_ctrl_mst_send_act(dp->ctrl); @@ -1579,6 +1576,11 @@ void msm_dp_display_unprepare(struct msm_dp *msm_dp_= display) =20 dp =3D container_of(msm_dp_display, struct msm_dp_display_private, msm_dp= _display); =20 + if (msm_dp_display->active_stream_cnt) { + drm_dbg_dp(dp->drm_dev, "stream still active, return\n"); + return; + } + /* dongle is still connected but sinks are disconnected */ if (dp->link->sink_count =3D=3D 0) msm_dp_link_psm_config(dp->link, &dp->panel->link_info, true); diff --git a/drivers/gpu/drm/msm/dp/dp_display.h b/drivers/gpu/drm/msm/dp/d= p_display.h index 0ede5505be58..2548f67cd441 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.h +++ b/drivers/gpu/drm/msm/dp/dp_display.h @@ -18,7 +18,7 @@ struct msm_dp { struct drm_bridge *next_bridge; struct drm_bridge *bridge; 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In MST mode, connector detection is handled by MST bridges. This patch skips detection for the SST bridge when MST is active. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_display.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index e6ecbb3a688e..8ae690ce2b9f 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -926,6 +926,9 @@ enum drm_connector_status msm_dp_bridge_detect(struct d= rm_bridge *bridge, =20 priv =3D container_of(dp, struct msm_dp_display_private, msm_dp_display); =20 + if (dp->mst_active) + return status; + mutex_lock(&priv->plugged_lock); ret =3D pm_runtime_resume_and_get(&dp->pdev->dev); if (ret) { --=20 2.43.0 From nobody Sat Apr 18 10:45:33 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1571433E351 for ; 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Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou --- drivers/gpu/drm/msm/dp/dp_display.c | 57 ++++++++++++++++++++++++++++++++-= ---- 1 file changed, 50 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index 8ae690ce2b9f..abf26951819a 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -14,6 +14,7 @@ #include #include #include +#include #include =20 #include "msm_drv.h" @@ -270,6 +271,40 @@ static int msm_dp_display_lttpr_init(struct msm_dp_dis= play_private *dp, u8 *dpcd return lttpr_count; } =20 +static void msm_dp_display_mst_init(struct msm_dp_display_private *dp) +{ + const unsigned long clear_mstm_ctrl_timeout_us =3D 100000; + u8 old_mstm_ctrl; + struct msm_dp *msm_dp =3D &dp->msm_dp_display; + int ret; + + /* clear sink MST state */ + drm_dp_dpcd_read_byte(dp->aux, DP_MSTM_CTRL, &old_mstm_ctrl); + + ret =3D drm_dp_dpcd_write_byte(dp->aux, DP_MSTM_CTRL, 0); + if (ret < 0) { + DRM_ERROR("failed to clear DP_MSTM_CTRL, ret=3D%d\n", ret); + return; + } + + /* add extra delay if MST old state is on*/ + if (old_mstm_ctrl) { + drm_dbg_dp(dp->drm_dev, "wait %luus to set DP_MSTM_CTRL set 0\n", + clear_mstm_ctrl_timeout_us); + usleep_range(clear_mstm_ctrl_timeout_us, + clear_mstm_ctrl_timeout_us + 1000); + } + + ret =3D drm_dp_dpcd_write_byte(dp->aux, DP_MSTM_CTRL, + DP_MST_EN | DP_UP_REQ_EN | DP_UPSTREAM_IS_SRC); + if (ret < 0) { + DRM_ERROR("sink MST enablement failed\n"); + return; + } + + msm_dp->mst_active =3D true; +} + static int msm_dp_display_process_hpd_high(struct msm_dp_display_private *= dp) { struct drm_connector *connector =3D dp->msm_dp_display.connector; @@ -288,14 +323,19 @@ static int msm_dp_display_process_hpd_high(struct msm= _dp_display_private *dp) if (rc) goto end; =20 - drm_edid =3D drm_edid_read_ddc(connector, &dp->aux->ddc); - drm_edid_connector_update(connector, drm_edid); + if (!(dp->max_stream > 1) || !drm_dp_read_mst_cap(dp->aux, dp->panel->dpc= d)) { + drm_edid =3D drm_edid_read_ddc(connector, &dp->aux->ddc); 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Since some of the fields of DP panel are private, dp_display module needs to initialize these parts and return the panel back. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou --- drivers/gpu/drm/msm/dp/dp_display.c | 24 ++++++++++++++++++++++++ drivers/gpu/drm/msm/dp/dp_display.h | 1 + 2 files changed, 25 insertions(+) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index abf26951819a..1f26283b2dee 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -571,6 +571,30 @@ static int msm_dp_irq_hpd_handle(struct msm_dp_display= _private *dp) return rc; } =20 +struct msm_dp_panel *msm_dp_display_get_panel(struct msm_dp *msm_dp_displa= y) +{ + struct msm_dp_display_private *dp; + struct msm_dp_panel *dp_panel; + + dp =3D container_of(msm_dp_display, struct msm_dp_display_private, msm_dp= _display); + + dp_panel =3D msm_dp_panel_get(&dp->msm_dp_display.pdev->dev, dp->aux, dp-= >link, + dp->link_base, dp->mst2link_base, dp->mst3link_base, + dp->pixel_base[0]); + + if (IS_ERR(dp->panel)) { + DRM_ERROR("failed to initialize panel\n"); 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[129.46.232.65]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-8ac84cb135fsm19223386d6.38.2026.04.10.02.36.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Apr 2026 02:36:27 -0700 (PDT) From: Yongxing Mou Date: Fri, 10 Apr 2026 17:34:06 +0800 Subject: [PATCH v4 31/39] drm/msm/dp: add prepared to manage link-level operations Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260410-msm-dp-mst-v4-31-b20518dea8de@oss.qualcomm.com> References: <20260410-msm-dp-mst-v4-0-b20518dea8de@oss.qualcomm.com> In-Reply-To: <20260410-msm-dp-mst-v4-0-b20518dea8de@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Jessica Zhang Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Yongxing Mou , Abhinav Kumar X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1775813628; l=3575; i=yongxing.mou@oss.qualcomm.com; s=20250910; h=from:subject:message-id; bh=0SRrv+FxL8qkWFHKN4JQjVFRw38qXcyyamUUeTeLiXQ=; b=6d5c41YJLaWP774PXbiRUaSi6hpDLZVBF9fp3dCvVjbBoHJ6jCxZ05GuXV7ZHazoEe4vypBTO Z0Xo2DMhypUA+vdt+2phn6uLryBin0XvB5YMh0bhYXzseoaHpiy4STj X-Developer-Key: i=yongxing.mou@oss.qualcomm.com; a=ed25519; pk=rAy5J1eP+V7OXqH5FJ7ngMCtUrnHhut30ZTldOj52UM= X-Proofpoint-ORIG-GUID: POPaxOBaUuiUMqKafOOMk4QGaDHkBp3l X-Proofpoint-GUID: POPaxOBaUuiUMqKafOOMk4QGaDHkBp3l X-Authority-Analysis: v=2.4 cv=cKfQdFeN c=1 sm=1 tr=0 ts=69d8c49d cx=c_pps a=7E5Bxpl4vBhpaufnMqZlrw==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=qXKybx3EirU-fK6T7NYA:9 a=QEXdDO2ut3YA:10 a=pJ04lnu7RYOZP9TFuWaZ:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDEwMDA4OSBTYWx0ZWRfX8QpZrjDjdOg+ BZEaadclnMZSbLJbe3fucxWr6nAG4AiWyAv07Tku3EMdycpd9A5RYGgneFCoBTx/AtFme9ST0Jz uAcQ6q7LupPbERINTbIFVrWtHcsjz7Ek5mcjgSXBn00NAdnqYamXffj+JlhSOZSIH0Z+Q2EPdoV 8MA1yzuJTrcu5vSROBz7ygtAvp/volnKSUBBFzJSFMXCSHIElQwkFiz7WeBtc3x3FRVVKYHil3m iNFV0Po5p5rvN7fF/39TKXKzTnLjiMc0ufh6gb5zDZMnHs3rJRZV77Y9k+26HX4NNuyZGb0kKNz oO9RYRe9yKXdyEgIf9RBRKvVMJZVd1rNBi8ZNGGHO6IhF9GBy7dVU+2FmCGzjH9+k7Ulf9uxUIs 4cIb/E+zoKtxWkYOkQtlD8iejf0snzKyCqLq/B019XcXgWdjB4ITZXRjWnvQQAWdgvyP4WICZ2d m1ABUAIk5Xrh4+aHnpA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-10_03,2026-04-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 clxscore=1015 suspectscore=0 phishscore=0 lowpriorityscore=0 adultscore=0 malwarescore=0 bulkscore=0 priorityscore=1501 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604010000 definitions=main-2604100089 In MST mode, multiple streams share the same DP link. Track a prepared state so msm_dp_display_prepare() runs only once per link and repeated calls are skipped. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou --- drivers/gpu/drm/msm/dp/dp_display.c | 34 ++++++++++++++++++++++++++-------- drivers/gpu/drm/msm/dp/dp_display.h | 1 + 2 files changed, 27 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index 1f26283b2dee..9eaf6994a350 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -715,6 +715,11 @@ int msm_dp_display_prepare(struct msm_dp *msm_dp_displ= ay) if (msm_dp_display->is_edp) msm_dp_hpd_plug_handle(dp); =20 + if (msm_dp_display->prepared) { + drm_dbg_dp(dp->drm_dev, "Link already setup, return\n"); + return 0; + } + rc =3D pm_runtime_resume_and_get(&msm_dp_display->pdev->dev); if (rc) { DRM_ERROR("failed to pm_runtime_resume\n"); @@ -734,7 +739,11 @@ int msm_dp_display_prepare(struct msm_dp *msm_dp_displ= ay) // TODO: schedule drm_connector_set_link_status_property() } =20 - return msm_dp_ctrl_prepare_stream_on(dp->ctrl, force_link_train); + rc =3D msm_dp_ctrl_prepare_stream_on(dp->ctrl, force_link_train); + if (!rc) + msm_dp_display->prepared =3D true; + + return rc; } =20 static int msm_dp_display_enable(struct msm_dp_display_private *dp, @@ -1590,14 +1599,16 @@ void msm_dp_display_enable_helper(struct msm_dp *ms= m_dp_display, struct msm_dp_p =20 dp =3D container_of(msm_dp_display, struct msm_dp_display_private, msm_dp= _display); =20 - rc =3D msm_dp_display_enable(dp, msm_dp_panel); - if (rc) - DRM_ERROR("DP display enable failed, rc=3D%d\n", rc); + if (msm_dp_display->prepared) { + rc =3D msm_dp_display_enable(dp, msm_dp_panel); + if (rc) + DRM_ERROR("DP display enable failed, rc=3D%d\n", rc); =20 - rc =3D msm_dp_display_post_enable(msm_dp_display); - if (rc) { - DRM_ERROR("DP display post enable failed, rc=3D%d\n", rc); - msm_dp_display_disable(dp, msm_dp_panel); + rc =3D msm_dp_display_post_enable(msm_dp_display); + if (rc) { + DRM_ERROR("DP display post enable failed, rc=3D%d\n", rc); + msm_dp_display_disable(dp, msm_dp_panel); + } } =20 drm_dbg_dp(msm_dp_display->drm_dev, "type=3D%d Done\n", msm_dp_display->c= onnector_type); @@ -1646,6 +1657,11 @@ void msm_dp_display_unprepare(struct msm_dp *msm_dp_= display) =20 dp =3D container_of(msm_dp_display, struct msm_dp_display_private, msm_dp= _display); =20 + if (!msm_dp_display->prepared) { + drm_dbg_dp(dp->drm_dev, "Link already setup, return\n"); + return; + } + if (msm_dp_display->active_stream_cnt) { drm_dbg_dp(dp->drm_dev, "stream still active, return\n"); return; @@ -1664,6 +1680,8 @@ void msm_dp_display_unprepare(struct msm_dp *msm_dp_d= isplay) msm_dp_display_host_phy_exit(dp); =20 pm_runtime_put_sync(&msm_dp_display->pdev->dev); + + msm_dp_display->prepared =3D false; } =20 void msm_dp_display_atomic_post_disable_helper(struct msm_dp *dp, struct m= sm_dp_panel *msm_dp_panel) diff --git a/drivers/gpu/drm/msm/dp/dp_display.h b/drivers/gpu/drm/msm/dp/d= p_display.h index 5f3ef295d710..bda76319c459 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.h +++ b/drivers/gpu/drm/msm/dp/dp_display.h @@ -22,6 +22,7 @@ struct msm_dp { bool mst_active; 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Signed-off-by: Yongxing Mou Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 14 +++++++++++++- drivers/gpu/drm/msm/msm_drv.h | 7 ++++++- 2 files changed, 19 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/= disp/dpu1/dpu_kms.c index 61d7e65469b3..090e7d790593 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -653,7 +653,7 @@ static int _dpu_kms_initialize_displayport(struct drm_d= evice *dev, struct msm_display_info info; bool yuv_supported; int rc; - int i; + int i, stream_id, stream_cnt; =20 for (i =3D 0; i < ARRAY_SIZE(priv->kms->dp); i++) { if (!priv->kms->dp[i]) @@ -676,6 +676,18 @@ static int _dpu_kms_initialize_displayport(struct drm_= device *dev, DPU_ERROR("modeset_init failed for DP, rc =3D %d\n", rc); return rc; } + + stream_cnt =3D msm_dp_get_mst_max_stream(priv->kms->dp[i]); + + if (stream_cnt > 1) { + for (stream_id =3D 0; stream_id < stream_cnt; stream_id++) { + encoder =3D dpu_encoder_init(dev, DRM_MODE_ENCODER_DPMST, &info); + if (IS_ERR(encoder)) { + DPU_ERROR("encoder init failed for dp mst display\n"); + return PTR_ERR(encoder); + } + } + } } =20 return 0; diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h index 6d847d593f1a..3061eca49cb2 100644 --- a/drivers/gpu/drm/msm/msm_drv.h +++ b/drivers/gpu/drm/msm/msm_drv.h @@ -362,7 +362,7 @@ bool msm_dp_is_yuv_420_enabled(const struct msm_dp *dp_= display, bool msm_dp_needs_periph_flush(const struct msm_dp *dp_display, const struct drm_display_mode *mode); bool msm_dp_wide_bus_available(const struct msm_dp *dp_display); - +int msm_dp_get_mst_max_stream(struct msm_dp *dp_display); #else static inline int __init msm_dp_register(void) { @@ -379,6 +379,11 @@ static inline int msm_dp_modeset_init(struct msm_dp *d= p_display, return -EINVAL; } =20 +static inline int msm_dp_get_mst_max_stream(struct msm_dp *dp_display) +{ + return -EINVAL; +} + static inline void msm_dp_snapshot(struct msm_disp_state *disp_state, stru= ct msm_dp *dp_display) { } --=20 2.43.0 From nobody Sat Apr 18 10:45:33 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5D34C3C7E1E for ; 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The DP MST module for each controller is the central entity to manage its topology related operations as well as interfacing with the rest of the DP driver. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou --- drivers/gpu/drm/msm/Makefile | 3 +- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 6 +++ drivers/gpu/drm/msm/dp/dp_display.c | 18 ++++++++ drivers/gpu/drm/msm/dp/dp_display.h | 2 + drivers/gpu/drm/msm/dp/dp_mst_drm.c | 73 +++++++++++++++++++++++++++++= ++++ drivers/gpu/drm/msm/dp/dp_mst_drm.h | 13 ++++++ drivers/gpu/drm/msm/msm_drv.h | 6 +++ 7 files changed, 120 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile index 8b94c5f1cb68..1d8426876aa1 100644 --- a/drivers/gpu/drm/msm/Makefile +++ b/drivers/gpu/drm/msm/Makefile @@ -144,7 +144,8 @@ msm-display-$(CONFIG_DRM_MSM_DP)+=3D dp/dp_aux.o \ dp/dp_link.o \ dp/dp_panel.o \ dp/dp_audio.o \ - dp/dp_utils.o + dp/dp_utils.o \ + dp/dp_mst_drm.o =20 msm-display-$(CONFIG_DRM_MSM_HDMI_HDCP) +=3D hdmi/hdmi_hdcp.o =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/= disp/dpu1/dpu_kms.c index 090e7d790593..d7ce13a4586d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -680,6 +680,12 @@ static int _dpu_kms_initialize_displayport(struct drm_= device *dev, stream_cnt =3D msm_dp_get_mst_max_stream(priv->kms->dp[i]); =20 if (stream_cnt > 1) { + rc =3D msm_dp_mst_register(priv->kms->dp[i]); + if (rc) { + DPU_ERROR("dp_mst_init failed for DP, rc =3D %d\n", rc); + return rc; + } + for (stream_id =3D 0; stream_id < stream_cnt; stream_id++) { encoder =3D dpu_encoder_init(dev, DRM_MODE_ENCODER_DPMST, &info); if (IS_ERR(encoder)) { diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index 9eaf6994a350..919767945ba5 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -28,6 +28,7 @@ #include "dp_drm.h" #include "dp_audio.h" #include "dp_debug.h" +#include "dp_mst_drm.h" =20 static bool psr_enabled =3D false; module_param(psr_enabled, bool, 0); @@ -360,6 +361,9 @@ static int msm_dp_display_process_hpd_high(struct msm_d= p_display_private *dp) if (dp->max_stream > 1 && drm_dp_read_mst_cap(dp->aux, dp->panel->dpcd)) msm_dp_display_mst_init(dp); =20 + if (dp->msm_dp_display.mst_active) + msm_dp_mst_display_set_mgr_state(&dp->msm_dp_display, true); + msm_dp_link_reset_phy_params_vx_px(dp->link); =20 end: @@ -527,6 +531,11 @@ static int msm_dp_hpd_unplug_handle(struct msm_dp_disp= lay_private *dp) dp->panel->dpcd, dp->panel->downstream_ports); =20 + if (dp->msm_dp_display.mst_active) { + msm_dp_mst_display_set_mgr_state(&dp->msm_dp_display, false); + dp->msm_dp_display.mst_active =3D false; + } + /* signal the disconnect event early to ensure proper teardown */ msm_dp_display_handle_plugged_change(&dp->msm_dp_display, false); =20 @@ -1556,6 +1565,15 @@ int msm_dp_modeset_init(struct msm_dp *msm_dp_displa= y, struct drm_device *dev, return 0; } =20 +int msm_dp_mst_register(struct msm_dp *msm_dp_display) +{ + struct msm_dp_display_private *dp; + + dp =3D container_of(msm_dp_display, struct msm_dp_display_private, msm_dp= _display); + + return msm_dp_mst_init(msm_dp_display, dp->max_stream, dp->aux); +} + int msm_dp_display_set_mode_helper(struct msm_dp *msm_dp_display, struct drm_atomic_state *state, struct drm_encoder *drm_encoder, diff --git a/drivers/gpu/drm/msm/dp/dp_display.h b/drivers/gpu/drm/msm/dp/d= p_display.h index bda76319c459..55874daf41c4 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.h +++ b/drivers/gpu/drm/msm/dp/dp_display.h @@ -24,6 +24,8 @@ struct msm_dp { bool is_edp; bool prepared; =20 + void *msm_dp_mst; + struct msm_dp_audio *msm_dp_audio; bool psr_supported; }; diff --git a/drivers/gpu/drm/msm/dp/dp_mst_drm.c b/drivers/gpu/drm/msm/dp/d= p_mst_drm.c new file mode 100644 index 000000000000..b6c7b8211025 --- /dev/null +++ b/drivers/gpu/drm/msm/dp/dp_mst_drm.c @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include + +#include "dp_mst_drm.h" +#include "dp_panel.h" + +#define MAX_DPCD_TRANSACTION_BYTES 16 + +struct msm_dp_mst { + struct drm_dp_mst_topology_mgr mst_mgr; + struct msm_dp *msm_dp; + struct drm_dp_aux *dp_aux; + u32 max_streams; + /* Protects MST bridge enable/disable handling. */ + struct mutex mst_lock; +}; + +int msm_dp_mst_display_set_mgr_state(struct msm_dp *dp_display, bool state) +{ + struct msm_dp_mst *mst =3D dp_display->msm_dp_mst; + int rc; + + rc =3D drm_dp_mst_topology_mgr_set_mst(&mst->mst_mgr, state); + if (rc < 0) { + DRM_ERROR("failed to set topology mgr state to %d. rc %d\n", + state, rc); + } + + drm_dbg_dp(dp_display->drm_dev, "dp_mst_display_set_mgr_state state:%d\n"= , state); + return rc; +} + +int msm_dp_mst_init(struct msm_dp *dp_display, u32 max_streams, struct drm= _dp_aux *drm_aux) +{ + struct drm_device *dev =3D dp_display->drm_dev; + int conn_base_id =3D 0; + int ret; + struct msm_dp_mst *msm_dp_mst; + + msm_dp_mst =3D devm_kzalloc(dev->dev, sizeof(*msm_dp_mst), GFP_KERNEL); + if (!msm_dp_mst) + return -ENOMEM; + + memset(&msm_dp_mst->mst_mgr, 0, sizeof(msm_dp_mst->mst_mgr)); + + conn_base_id =3D dp_display->connector->base.id; + msm_dp_mst->msm_dp =3D dp_display; + msm_dp_mst->max_streams =3D max_streams; + + msm_dp_mst->dp_aux =3D drm_aux; + + ret =3D drm_dp_mst_topology_mgr_init(&msm_dp_mst->mst_mgr, dev, + drm_aux, + MAX_DPCD_TRANSACTION_BYTES, + max_streams, + conn_base_id); + if (ret) { + DRM_ERROR("DP DRM MST topology manager init failed\n"); + return ret; + } + + dp_display->msm_dp_mst =3D msm_dp_mst; + + mutex_init(&msm_dp_mst->mst_lock); + return ret; +} diff --git a/drivers/gpu/drm/msm/dp/dp_mst_drm.h b/drivers/gpu/drm/msm/dp/d= p_mst_drm.h new file mode 100644 index 000000000000..5d411529f681 --- /dev/null +++ b/drivers/gpu/drm/msm/dp/dp_mst_drm.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only + * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DP_MST_DRM_H_ +#define _DP_MST_DRM_H_ + +#include "dp_display.h" + +int msm_dp_mst_init(struct msm_dp *dp_display, u32 max_streams, struct drm= _dp_aux *drm_aux); +int msm_dp_mst_display_set_mgr_state(struct msm_dp *dp_display, bool state= ); + +#endif /* _DP_MST_DRM_H_ */ diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h index 3061eca49cb2..5f73e0aa1c2f 100644 --- a/drivers/gpu/drm/msm/msm_drv.h +++ b/drivers/gpu/drm/msm/msm_drv.h @@ -363,6 +363,7 @@ bool msm_dp_needs_periph_flush(const struct msm_dp *dp_= display, const struct drm_display_mode *mode); bool msm_dp_wide_bus_available(const struct msm_dp *dp_display); int msm_dp_get_mst_max_stream(struct msm_dp *dp_display); +int msm_dp_mst_register(struct msm_dp *dp_display); #else static inline int __init msm_dp_register(void) { @@ -384,6 +385,11 @@ static inline int msm_dp_get_mst_max_stream(struct msm= _dp *dp_display) return -EINVAL; } =20 +static inline int msm_dp_mst_register(struct msm_dp *dp_display) +{ + return -EINVAL; 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[129.46.232.65]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-8ac84cb135fsm19223386d6.38.2026.04.10.02.36.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Apr 2026 02:36:42 -0700 (PDT) From: Yongxing Mou Date: Fri, 10 Apr 2026 17:34:09 +0800 Subject: [PATCH v4 34/39] drm/msm/dp: add dp_mst_drm to manage DP MST bridge operations Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260410-msm-dp-mst-v4-34-b20518dea8de@oss.qualcomm.com> References: <20260410-msm-dp-mst-v4-0-b20518dea8de@oss.qualcomm.com> In-Reply-To: <20260410-msm-dp-mst-v4-0-b20518dea8de@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Jessica Zhang Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Yongxing Mou , Abhinav Kumar X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1775813628; l=18036; i=yongxing.mou@oss.qualcomm.com; s=20250910; h=from:subject:message-id; bh=ZA0ZDHazW5mLfSOyJreDBYX+tdkXRc4M9BjgDDcv31I=; b=bH1LF3A1hbnaw1FlsgJBsySUzWNryp4VsT5r3PNmo/tL8238u+Qr2+DOAb3mFtsNjfVXwtoo+ 77EAl981zXxCD5P66EMQyLJlnNgTw/Ye+rOab2pNa6n/FmJDdj8OSQE X-Developer-Key: i=yongxing.mou@oss.qualcomm.com; a=ed25519; pk=rAy5J1eP+V7OXqH5FJ7ngMCtUrnHhut30ZTldOj52UM= X-Authority-Analysis: v=2.4 cv=S/fpBosP c=1 sm=1 tr=0 ts=69d8c4ab cx=c_pps a=7E5Bxpl4vBhpaufnMqZlrw==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=tQpwhndg4eEXWrdZBYkA:9 a=QEXdDO2ut3YA:10 a=pJ04lnu7RYOZP9TFuWaZ:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDEwMDA4OSBTYWx0ZWRfX6j0hqzr6YlEh TcN9Q22EYPW95LGV9aDKXDLFODmAooO12lCNWqylDtVmk6hcnoT/aSvVQjzU2WAwRU4KtveXfzc xFx2yBFoXDRDekX1tIdDSqX8NXaz7/E+9V0Ot6j3UWpczwmGG1UFejCd12M4uuKqcUCiHZno92/ 0nYrjSK6MPZtlDSOQWBttdP0LH2UO7S9vSdQYg27aps4hGYw7VOO8dFYObRxcW70OcOP8jUtPbp bgjVA7Mir3cIcmlUF3dqYG7IxcBKjcE/unYyKDwgn2PHbqrjR+n1A3zGvZ/vB9YSQ9yYmnZfpIo 8qJkt8SKzd+Y0jzLw59kyMWgW2ZowrDvk7HOkwt9ZCKBGkXpcxNwz8cbapIN+jfe+ViN3BvYj2o 0BQPqOIUOS3lk1vizQT3+TbN9vcjmSSnTfLUefFqzUIlGZTjJY8+OFH2EMdRHXE0rdv777kLY/l k7zeDi6um5YZwrzfcdw== X-Proofpoint-ORIG-GUID: T3ba-keeyB3eDU9C5l-sIzra9h77KHjs X-Proofpoint-GUID: T3ba-keeyB3eDU9C5l-sIzra9h77KHjs X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-10_03,2026-04-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 malwarescore=0 adultscore=0 spamscore=0 priorityscore=1501 impostorscore=0 lowpriorityscore=0 bulkscore=0 phishscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604010000 definitions=main-2604100089 From: Abhinav Kumar Add dp_mst_drm to manage the DP MST bridge operations similar to the dp_drm file which manages the SST bridge operations. Each MST encoder creates one bridge and each bridge is bound to its own dp_panel abstraction to manage the operations of its pipeline. Keep the connector/panel association in bridge private state for atomic assignment and release, and mirror it in the bridge object for runtime bridge callbacks. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou --- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 6 + drivers/gpu/drm/msm/dp/dp_mst_drm.c | 459 ++++++++++++++++++++++++++++= +++- drivers/gpu/drm/msm/msm_drv.h | 7 + 3 files changed, 471 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/= disp/dpu1/dpu_kms.c index d7ce13a4586d..89868443c0fe 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -692,6 +692,12 @@ static int _dpu_kms_initialize_displayport(struct drm_= device *dev, DPU_ERROR("encoder init failed for dp mst display\n"); return PTR_ERR(encoder); } + + rc =3D msm_dp_mst_attach_encoder(priv->kms->dp[i], encoder); + if (rc) { + DPU_ERROR("DP MST init failed, %d\n", rc); + continue; + } } } } diff --git a/drivers/gpu/drm/msm/dp/dp_mst_drm.c b/drivers/gpu/drm/msm/dp/d= p_mst_drm.c index b6c7b8211025..4df3ea5e36d0 100644 --- a/drivers/gpu/drm/msm/dp/dp_mst_drm.c +++ b/drivers/gpu/drm/msm/dp/dp_mst_drm.c @@ -13,8 +13,47 @@ =20 #define MAX_DPCD_TRANSACTION_BYTES 16 =20 +#define to_dp_mst_bridge(x) container_of((x), struct msm_dp_mst_bridge= , base) +#define to_dp_mst_bridge_state_priv(x) \ + container_of((x), struct msm_dp_mst_bridge_state, base) +#define to_dp_mst_bridge_state(x) \ + to_dp_mst_bridge_state_priv((x)->obj.state) +#define to_dp_mst_connector(x) \ + container_of((x), struct msm_dp_mst_connector, connector) + +#define DP_MST_CONN_ID(x) ((x)->connector ? \ + (x)->connector->base.id : 0) + +struct msm_dp_mst_bridge { + struct drm_bridge base; + struct drm_private_obj obj; + u32 id; + + bool initialized; + + struct msm_dp *display; + struct drm_encoder *encoder; + + struct drm_connector *connector; + struct msm_dp_panel *msm_dp_panel; +}; + +struct msm_dp_mst_bridge_state { + struct drm_private_state base; + struct drm_connector *connector; + struct msm_dp_panel *msm_dp_panel; +}; + +struct msm_dp_mst_connector { + struct drm_connector connector; + struct drm_dp_mst_port *mst_port; + struct msm_dp_mst *dp_mst; + struct msm_dp_panel *dp_panel; +}; + struct msm_dp_mst { struct drm_dp_mst_topology_mgr mst_mgr; + struct msm_dp_mst_bridge *mst_bridge[DP_STREAM_MAX]; struct msm_dp *msm_dp; struct drm_dp_aux *dp_aux; u32 max_streams; @@ -22,6 +61,419 @@ struct msm_dp_mst { struct mutex mst_lock; }; =20 +static struct drm_private_state *msm_dp_mst_duplicate_bridge_state(struct = drm_private_obj *obj) +{ + struct msm_dp_mst_bridge_state *mst_bridge_state; + + mst_bridge_state =3D kmemdup(obj->state, sizeof(*mst_bridge_state), GFP_K= ERNEL); + if (!mst_bridge_state) + return NULL; + + __drm_atomic_helper_private_obj_duplicate_state(obj, &mst_bridge_state->b= ase); + + return &mst_bridge_state->base; +} + +static void msm_dp_mst_destroy_bridge_state(struct drm_private_obj *obj, + struct drm_private_state *state) +{ + struct msm_dp_mst_bridge_state *mst_bridge_state =3D + to_dp_mst_bridge_state_priv(state); + + kfree(mst_bridge_state); +} + +static const struct drm_private_state_funcs msm_dp_mst_bridge_state_funcs = =3D { + .atomic_duplicate_state =3D msm_dp_mst_duplicate_bridge_state, + .atomic_destroy_state =3D msm_dp_mst_destroy_bridge_state, +}; + +static struct msm_dp_mst_bridge_state *msm_dp_mst_br_priv_state(struct drm= _atomic_state *st, + struct msm_dp_mst_bridge *bridge) +{ + struct drm_device *dev =3D bridge->base.dev; + struct drm_private_state *obj_state =3D drm_atomic_get_private_obj_state(= st, &bridge->obj); + + WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); + + return to_dp_mst_bridge_state_priv(obj_state); +} + +static void msm_dp_mst_update_timeslots(struct msm_dp_mst *mst, + struct msm_dp_mst_bridge *mst_bridge, + struct drm_atomic_state *state, + struct drm_dp_mst_port *port) +{ + struct drm_dp_mst_topology_state *mst_state; + struct drm_dp_mst_atomic_payload *payload; + + mst_state =3D to_drm_dp_mst_topology_state(mst->mst_mgr.base.state); + payload =3D drm_atomic_get_mst_payload_state(mst_state, port); + + if (!payload) { + DRM_ERROR("MST bridge [%d] update_timeslots failed, null payload\n", + mst_bridge->id); + return; + } + + if (payload->vc_start_slot < 0) + msm_dp_display_set_stream_info(mst->msm_dp, mst_bridge->msm_dp_panel, + mst_bridge->id, 1, 0, 0); + else + msm_dp_display_set_stream_info(mst->msm_dp, mst_bridge->msm_dp_panel, + mst_bridge->id, payload->vc_start_slot, + payload->time_slots, payload->pbn); +} + +static int msm_dp_mst_bridge_pre_enable_part1(struct msm_dp_mst_bridge *dp= _bridge, + struct drm_atomic_state *state) +{ + struct msm_dp *dp_display =3D dp_bridge->display; + struct msm_dp_mst *mst =3D dp_display->msm_dp_mst; + struct msm_dp_mst_connector *mst_conn =3D to_dp_mst_connector(dp_bridge->= connector); + struct drm_dp_mst_port *port =3D mst_conn->mst_port; + struct drm_dp_mst_topology_state *mst_state; + struct drm_dp_mst_atomic_payload *payload; + struct msm_dp_panel *dp_panel =3D mst_conn->dp_panel; + int pbn; + int rc =3D 0; + + mst_state =3D drm_atomic_get_new_mst_topology_state(state, &mst->mst_mgr); + + pbn =3D drm_dp_calc_pbn_mode(dp_panel->msm_dp_mode.drm_mode.clock, + (mst_conn->connector.display_info.bpc * 3) << 4); + + payload =3D drm_atomic_get_mst_payload_state(mst_state, port); + if (!payload || payload->time_slots <=3D 0) { + DRM_ERROR("time slots not allocated for conn:%d\n", DP_MST_CONN_ID(dp_br= idge)); + rc =3D -EINVAL; + return rc; + } + + drm_dbg_dp(dp_display->drm_dev, "conn:%d pbn:%d, slots:%d\n", DP_MST_CONN= _ID(dp_bridge), + pbn, payload->time_slots); + + drm_dp_mst_update_slots(mst_state, DP_CAP_ANSI_8B10B); + + rc =3D drm_dp_add_payload_part1(&mst->mst_mgr, mst_state, payload); + if (rc) { + DRM_ERROR("payload allocation failure for conn:%d\n", DP_MST_CONN_ID(dp_= bridge)); + return rc; + } + + msm_dp_mst_update_timeslots(mst, dp_bridge, state, port); + + return rc; +} + +static void _msm_dp_mst_bridge_pre_enable_part2(struct msm_dp_mst_bridge *= dp_bridge, + struct drm_atomic_state *state) +{ + struct msm_dp *dp_display =3D dp_bridge->display; + struct msm_dp_mst *mst =3D dp_display->msm_dp_mst; + struct msm_dp_mst_connector *mst_conn =3D to_dp_mst_connector(dp_bridge->= connector); + struct drm_dp_mst_port *port =3D mst_conn->mst_port; + struct drm_dp_mst_topology_state *mst_state; + struct drm_dp_mst_atomic_payload *payload; + + drm_dp_check_act_status(&mst->mst_mgr); + + mst_state =3D to_drm_dp_mst_topology_state(mst->mst_mgr.base.state); + payload =3D drm_atomic_get_mst_payload_state(mst_state, port); + + drm_dp_add_payload_part2(&mst->mst_mgr, payload); + + drm_dbg_dp(dp_display->drm_dev, "MST bridge [%d] _pre enable part-2 compl= ete\n", + dp_bridge->id); +} + +static void msm_dp_mst_bridge_pre_disable_part1(struct msm_dp_mst_bridge *= dp_bridge, + struct drm_atomic_state *state) +{ + struct msm_dp *dp_display =3D dp_bridge->display; + struct msm_dp_mst *mst =3D dp_display->msm_dp_mst; + struct msm_dp_mst_connector *mst_conn =3D to_dp_mst_connector(dp_bridge->= connector); + struct drm_dp_mst_port *port =3D mst_conn->mst_port; + struct drm_dp_mst_topology_state *old_mst_state; + struct drm_dp_mst_topology_state *new_mst_state; + const struct drm_dp_mst_atomic_payload *old_payload; + struct drm_dp_mst_atomic_payload *new_payload; + + old_mst_state =3D drm_atomic_get_old_mst_topology_state(state, &mst->mst_= mgr); + new_mst_state =3D drm_atomic_get_new_mst_topology_state(state, &mst->mst_= mgr); + + old_payload =3D drm_atomic_get_mst_payload_state(old_mst_state, port); + new_payload =3D drm_atomic_get_mst_payload_state(new_mst_state, port); + + if (!old_payload || !new_payload) { + DRM_ERROR("MST bridge [%d] _pre disable part-1 failed, null payload\n", + dp_bridge->id); + return; + } + + drm_dp_remove_payload_part1(&mst->mst_mgr, new_mst_state, new_payload); + drm_dp_remove_payload_part2(&mst->mst_mgr, new_mst_state, old_payload, ne= w_payload); + + msm_dp_mst_update_timeslots(mst, dp_bridge, state, port); + + drm_dbg_dp(dp_display->drm_dev, "MST bridge [%d] _pre disable part-1 comp= lete\n", + dp_bridge->id); +} + +static void msm_dp_mst_bridge_atomic_pre_enable(struct drm_bridge *drm_bri= dge, + struct drm_atomic_state *state) +{ + int rc =3D 0; + struct msm_dp_mst_bridge *bridge; + struct msm_dp *dp_display; + struct msm_dp_mst_bridge_state *mst_bridge_state; + struct msm_dp_mst *dp_mst; + struct msm_dp_panel *msm_dp_panel; + + if (!drm_bridge) { + DRM_ERROR("Invalid params\n"); + return; + } + + bridge =3D to_dp_mst_bridge(drm_bridge); + mst_bridge_state =3D to_dp_mst_bridge_state(bridge); + dp_display =3D bridge->display; + dp_mst =3D dp_display->msm_dp_mst; + + /* to cover cases of bridge_disable/bridge_enable without modeset */ + bridge->connector =3D mst_bridge_state->connector; + bridge->msm_dp_panel =3D mst_bridge_state->msm_dp_panel; + + if (!bridge->connector) { + DRM_ERROR("Invalid connector\n"); + return; + } + + msm_dp_panel =3D bridge->msm_dp_panel; + mutex_lock(&dp_mst->mst_lock); + + rc =3D msm_dp_display_set_mode_helper(dp_display, state, drm_bridge->enco= der, msm_dp_panel); + if (rc) { + DRM_ERROR("Failed to perform a mode set, rc=3D%d\n", rc); + mutex_unlock(&dp_mst->mst_lock); + return; + } + msm_dp_panel->pbn =3D drm_dp_calc_pbn_mode(msm_dp_panel->msm_dp_mode.drm_= mode.clock, + msm_dp_panel->msm_dp_mode.bpp << 4); + rc =3D msm_dp_display_prepare(dp_display); + if (rc) { + DRM_ERROR("[%d] DP display pre-enable failed, rc=3D%d\n", bridge->id, rc= ); + msm_dp_display_unprepare(dp_display); + mutex_unlock(&dp_mst->mst_lock); + return; + } + + rc =3D msm_dp_mst_bridge_pre_enable_part1(bridge, state); + if (rc) { + DRM_ERROR("[%d] DP display pre-enable failed, rc=3D%d\n", bridge->id, rc= ); + mutex_unlock(&dp_mst->mst_lock); + return; + } + + msm_dp_display_enable_helper(dp_display, bridge->msm_dp_panel); + + _msm_dp_mst_bridge_pre_enable_part2(bridge, state); + + mutex_unlock(&dp_mst->mst_lock); + + drm_dbg_dp(dp_display->drm_dev, "conn:%d mode:%s pre enable done\n", + DP_MST_CONN_ID(bridge), bridge->msm_dp_panel->msm_dp_mode.drm_mode.na= me); +} + +static void msm_dp_mst_bridge_atomic_disable(struct drm_bridge *drm_bridge, + struct drm_atomic_state *state) +{ + struct msm_dp_mst_bridge *bridge; + struct msm_dp *dp_display; + struct msm_dp_mst *mst; + + if (!drm_bridge) { + DRM_ERROR("Invalid params\n"); + return; + } + + bridge =3D to_dp_mst_bridge(drm_bridge); + if (!bridge->connector) { + DRM_ERROR("Invalid connector\n"); + return; + } + + dp_display =3D bridge->display; + mst =3D dp_display->msm_dp_mst; + + mutex_lock(&mst->mst_lock); + + msm_dp_mst_bridge_pre_disable_part1(bridge, state); + + msm_dp_display_disable_helper(dp_display, bridge->msm_dp_panel); + + drm_dp_check_act_status(&mst->mst_mgr); + + mutex_unlock(&mst->mst_lock); + + drm_dbg_dp(dp_display->drm_dev, "MST bridge:%d disable complete\n", bridg= e->id); +} + +static void msm_dp_mst_bridge_atomic_post_disable(struct drm_bridge *drm_b= ridge, + struct drm_atomic_state *state) +{ + struct msm_dp_mst_bridge *bridge; + struct msm_dp *dp_display; + struct msm_dp_mst *mst; + + if (!drm_bridge) { + DRM_ERROR("Invalid params\n"); + return; + } + + bridge =3D to_dp_mst_bridge(drm_bridge); + if (!bridge->connector) { + DRM_ERROR("Invalid connector\n"); + return; + } + + dp_display =3D bridge->display; + mst =3D dp_display->msm_dp_mst; + + mutex_lock(&mst->mst_lock); + + msm_dp_display_atomic_post_disable_helper(dp_display, bridge->msm_dp_pane= l); + + if (!dp_display->mst_active) + msm_dp_display_unprepare(dp_display); + + bridge->connector =3D NULL; + bridge->msm_dp_panel =3D NULL; + + mutex_unlock(&mst->mst_lock); + + drm_dbg_dp(dp_display->drm_dev, "MST bridge:%d conn:%d post disable compl= ete\n", + bridge->id, DP_MST_CONN_ID(bridge)); +} + +static int msm_dp_mst_bridge_atomic_check(struct drm_bridge *drm_bridge, + struct drm_bridge_state *bridge_state, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state) +{ + struct drm_atomic_state *state =3D crtc_state->state; + struct drm_connector *connector =3D conn_state->connector; + struct drm_dp_mst_topology_state *mst_state; + struct msm_dp_mst_connector *mst_conn; + struct msm_dp_mst *mst; + int rc =3D 0, pbn, slots; + struct msm_dp_mst_bridge_state *mst_bridge_state; + u32 bpp; + + if (!drm_atomic_crtc_needs_modeset(crtc_state) || !crtc_state->enable) + return 0; + + mst_conn =3D to_dp_mst_connector(connector); + mst =3D mst_conn->dp_mst; + + bpp =3D connector->display_info.bpc * 3; + + if (!bpp) + bpp =3D 24; + + pbn =3D drm_dp_calc_pbn_mode(crtc_state->mode.clock, bpp << 4); + + mst_state =3D to_drm_dp_mst_topology_state(mst->mst_mgr.base.state); + if (IS_ERR(mst_state)) + return PTR_ERR(mst_state); + + if (!dfixed_trunc(mst_state->pbn_div)) { + mst_state->pbn_div =3D + drm_dp_get_vc_payload_bw(mst_conn->dp_panel->link_info.rate, + mst_conn->dp_panel->link_info.num_lanes); + } + + slots =3D drm_dp_atomic_find_time_slots(state, &mst->mst_mgr, mst_conn->m= st_port, pbn); + + drm_dbg_dp(drm_bridge->dev, "add slots, conn:%d pbn:%d slots:%d rc:%d\n", + connector->base.id, pbn, slots, rc); + + if (!conn_state->crtc) { + mst_bridge_state =3D msm_dp_mst_br_priv_state(state, to_dp_mst_bridge(dr= m_bridge)); + mst_bridge_state->connector =3D NULL; + mst_bridge_state->msm_dp_panel =3D NULL; + } + + return 0; +} + +/* DP MST Bridge APIs */ +static const struct drm_bridge_funcs msm_dp_mst_bridge_ops =3D { + .atomic_duplicate_state =3D drm_atomic_helper_bridge_duplicate_state, + .atomic_destroy_state =3D drm_atomic_helper_bridge_destroy_state, + .atomic_reset =3D drm_atomic_helper_bridge_reset, + .atomic_pre_enable =3D msm_dp_mst_bridge_atomic_pre_enable, + .atomic_disable =3D msm_dp_mst_bridge_atomic_disable, + .atomic_post_disable =3D msm_dp_mst_bridge_atomic_post_disable, + .atomic_check =3D msm_dp_mst_bridge_atomic_check, +}; + +int msm_dp_mst_attach_encoder(struct msm_dp *dp_display, struct drm_encode= r *encoder) +{ + int rc =3D 0; + struct msm_dp_mst_bridge *bridge =3D NULL; + struct msm_dp_mst_bridge_state *mst_bridge_state; + struct drm_device *dev; + struct msm_dp_mst *mst =3D dp_display->msm_dp_mst; + int i; + + for (i =3D 0; i < mst->max_streams; i++) { + if (!mst->mst_bridge[i]->initialized) { + bridge =3D mst->mst_bridge[i]; + bridge->encoder =3D encoder; + bridge->initialized =3D true; + bridge->id =3D i; + break; + } + } + + if (i =3D=3D mst->max_streams) { + DRM_ERROR("MST supports only %d bridges\n", mst->max_streams); + rc =3D -EACCES; + goto end; + } + + dev =3D dp_display->drm_dev; + bridge->display =3D dp_display; + bridge->base.encoder =3D encoder; + bridge->base.type =3D dp_display->connector_type; + bridge->base.ops =3D DRM_BRIDGE_OP_MODES; + drm_bridge_add(&bridge->base); + + rc =3D drm_bridge_attach(encoder, &bridge->base, NULL, 0); + if (rc) { + DRM_ERROR("failed to attach bridge, rc=3D%d\n", rc); + goto end; + } + + mst_bridge_state =3D kzalloc(sizeof(*mst_bridge_state), GFP_KERNEL); + if (!mst_bridge_state) { + rc =3D -ENOMEM; + goto end; + } + + drm_atomic_private_obj_init(dev, &bridge->obj, + &mst_bridge_state->base, + &msm_dp_mst_bridge_state_funcs); + + drm_dbg_dp(dp_display->drm_dev, "MST drm bridge init. bridge id:%d\n", i); + + return 0; + +end: + return rc; +} + int msm_dp_mst_display_set_mgr_state(struct msm_dp *dp_display, bool state) { struct msm_dp_mst *mst =3D dp_display->msm_dp_mst; @@ -49,11 +501,16 @@ int msm_dp_mst_init(struct msm_dp *dp_display, u32 max= _streams, struct drm_dp_au return -ENOMEM; =20 memset(&msm_dp_mst->mst_mgr, 0, sizeof(msm_dp_mst->mst_mgr)); - conn_base_id =3D dp_display->connector->base.id; msm_dp_mst->msm_dp =3D dp_display; msm_dp_mst->max_streams =3D max_streams; =20 + for (int i =3D 0; i < DP_STREAM_MAX; i++) { + msm_dp_mst->mst_bridge[i] =3D + devm_drm_bridge_alloc(dev->dev, struct msm_dp_mst_bridge, base, + &msm_dp_mst_bridge_ops); + } + msm_dp_mst->dp_aux =3D drm_aux; =20 ret =3D drm_dp_mst_topology_mgr_init(&msm_dp_mst->mst_mgr, dev, diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h index 5f73e0aa1c2f..03bedd15fe02 100644 --- a/drivers/gpu/drm/msm/msm_drv.h +++ b/drivers/gpu/drm/msm/msm_drv.h @@ -364,6 +364,8 @@ bool msm_dp_needs_periph_flush(const struct msm_dp *dp_= display, bool msm_dp_wide_bus_available(const struct msm_dp *dp_display); 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Hook the MST helpers into atomic_commit_setup() and atomic_commit_tail() to support non-blocking atomic commits for DisplayPort MST, and ensure MST commits properly wait for dependencies. For SST, non-blocking commits are already handled via commit_tail(), which waits for dependencies in the DRM core. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/msm_atomic.c | 9 ++++++++- drivers/gpu/drm/msm/msm_kms.c | 2 ++ 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/msm_atomic.c b/drivers/gpu/drm/msm/msm_ato= mic.c index 87a91148a731..ea064aa6d8fc 100644 --- a/drivers/gpu/drm/msm/msm_atomic.c +++ b/drivers/gpu/drm/msm/msm_atomic.c @@ -4,6 +4,7 @@ * Author: Rob Clark */ =20 +#include #include #include =20 @@ -207,7 +208,11 @@ int msm_atomic_check(struct drm_device *dev, struct dr= m_atomic_state *state) if (ret) return ret; =20 - return drm_atomic_helper_check(dev, state); + ret =3D drm_atomic_helper_check(dev, state); + if (ret) + return ret; + + return drm_dp_mst_atomic_check(state); } =20 void msm_atomic_commit_tail(struct drm_atomic_state *state) @@ -221,6 +226,8 @@ void msm_atomic_commit_tail(struct drm_atomic_state *st= ate) =20 trace_msm_atomic_commit_tail_start(async, crtc_mask); =20 + drm_dp_mst_atomic_wait_for_dependencies(state); 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The connector is only used for MST helper callbacks, such as detect, get_modes, and get_encoder. Display enable/disable, hotplug handling, and modeset sequencing continue to be handled by the bridge path. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou --- drivers/gpu/drm/msm/dp/dp_mst_drm.c | 231 ++++++++++++++++++++++++++++++++= ++++ 1 file changed, 231 insertions(+) diff --git a/drivers/gpu/drm/msm/dp/dp_mst_drm.c b/drivers/gpu/drm/msm/dp/d= p_mst_drm.c index 4df3ea5e36d0..bb3898b1f6b1 100644 --- a/drivers/gpu/drm/msm/dp/dp_mst_drm.c +++ b/drivers/gpu/drm/msm/dp/dp_mst_drm.c @@ -7,6 +7,7 @@ #include #include #include +#include =20 #include "dp_mst_drm.h" #include "dp_panel.h" @@ -489,6 +490,235 @@ int msm_dp_mst_display_set_mgr_state(struct msm_dp *d= p_display, bool state) return rc; } =20 +/* DP MST Connector OPs */ +static int +msm_dp_mst_connector_detect(struct drm_connector *connector, + struct drm_modeset_acquire_ctx *ctx, + bool force) +{ + struct msm_dp_mst_connector *mst_conn =3D to_dp_mst_connector(connector); + struct msm_dp_mst *mst =3D mst_conn->dp_mst; + struct msm_dp *dp_display =3D mst->msm_dp; + struct device *dev =3D dp_display->drm_dev->dev; + enum drm_connector_status status =3D connector_status_disconnected; + int ret; + + ret =3D pm_runtime_resume_and_get(dev); + if (ret < 0) + return status; + + if (dp_display->mst_active) + status =3D drm_dp_mst_detect_port(connector, + ctx, &mst->mst_mgr, mst_conn->mst_port); + + pm_runtime_put_autosuspend(dev); + + return status; +} + +static int msm_dp_mst_connector_get_modes(struct drm_connector *connector) +{ + struct msm_dp_mst_connector *mst_conn =3D to_dp_mst_connector(connector); + struct msm_dp_mst *mst =3D mst_conn->dp_mst; + const struct drm_edid *drm_edid; + + drm_edid =3D drm_dp_mst_edid_read(connector, &mst->mst_mgr, mst_conn->mst= _port); + drm_edid_connector_update(connector, drm_edid); + + return drm_edid_connector_add_modes(connector); +} + +static enum drm_mode_status msm_dp_mst_connector_mode_valid(struct drm_con= nector *connector, + const struct drm_display_mode *mode) +{ + struct msm_dp_mst_connector *mst_conn; + struct drm_dp_mst_port *mst_port; + struct msm_dp *dp_display; + int required_pbn; + + if (drm_connector_is_unregistered(connector)) + return 0; + + mst_conn =3D to_dp_mst_connector(connector); + mst_port =3D mst_conn->mst_port; + dp_display =3D mst_conn->dp_mst->msm_dp; + + if (!mst_port) + return MODE_ERROR; + + required_pbn =3D drm_dp_calc_pbn_mode(mode->clock, (6 * 3) << 4); + + if (required_pbn > mst_port->full_pbn) { + drm_dbg_dp(dp_display->drm_dev, "mode:%s not supported.\n", mode->name); + return MODE_CLOCK_HIGH; + } + + return msm_dp_display_mode_valid(dp_display, &connector->display_info, mo= de); +} + +static struct drm_encoder * +msm_dp_mst_atomic_best_encoder(struct drm_connector *connector, struct drm= _atomic_state *state) +{ + struct msm_dp_mst_connector *mst_conn =3D to_dp_mst_connector(connector); + struct msm_dp_mst *mst =3D mst_conn->dp_mst; + struct msm_dp *dp_display =3D mst->msm_dp; + struct drm_encoder *enc =3D NULL; + struct msm_dp_mst_bridge_state *mst_bridge_state; + u32 i; + struct drm_connector_state *conn_state =3D drm_atomic_get_new_connector_s= tate(state, + connector); + + if (conn_state && conn_state->best_encoder) + return conn_state->best_encoder; + + for (i =3D 0; i < mst->max_streams; i++) { + mst_bridge_state =3D msm_dp_mst_br_priv_state(state, mst->mst_bridge[i]); + if (IS_ERR(mst_bridge_state)) + goto end; + + if (mst_bridge_state->connector =3D=3D connector) { + enc =3D mst->mst_bridge[i]->encoder; + goto end; + } + } + + for (i =3D 0; i < mst->max_streams; i++) { + mst_bridge_state =3D msm_dp_mst_br_priv_state(state, mst->mst_bridge[i]); + + if (!mst_bridge_state->connector) { + mst_bridge_state->connector =3D connector; + mst_bridge_state->msm_dp_panel =3D mst_conn->dp_panel; + enc =3D mst->mst_bridge[i]->encoder; + break; + } + } + +end: + if (enc) + drm_dbg_dp(dp_display->drm_dev, "MST connector:%d atomic best encoder:%d= \n", + connector->base.id, i); + else + drm_dbg_dp(dp_display->drm_dev, "MST connector:%d atomic best encoder fa= iled\n", + connector->base.id); + + return enc; +} + +static int msm_dp_mst_connector_atomic_check(struct drm_connector *connect= or, + struct drm_atomic_state *state) +{ + struct msm_dp_mst_connector *mst_conn =3D to_dp_mst_connector(connector); + struct msm_dp_mst *mst =3D mst_conn->dp_mst; + + return drm_dp_atomic_release_time_slots(state, &mst->mst_mgr, mst_conn->m= st_port); +} + +static void dp_mst_connector_destroy(struct drm_connector *connector) +{ + struct msm_dp_mst_connector *mst_conn =3D to_dp_mst_connector(connector); + + drm_connector_cleanup(connector); + drm_dp_mst_put_port_malloc(mst_conn->mst_port); + kfree(mst_conn); +} + +/* DRM MST callbacks */ +static const struct drm_connector_helper_funcs msm_dp_drm_mst_connector_he= lper_funcs =3D { + .get_modes =3D msm_dp_mst_connector_get_modes, + .detect_ctx =3D msm_dp_mst_connector_detect, + .mode_valid =3D msm_dp_mst_connector_mode_valid, + .atomic_best_encoder =3D msm_dp_mst_atomic_best_encoder, + .atomic_check =3D msm_dp_mst_connector_atomic_check, +}; + +static const struct drm_connector_funcs msm_dp_drm_mst_connector_funcs =3D= { + .reset =3D drm_atomic_helper_connector_reset, + .destroy =3D dp_mst_connector_destroy, + .fill_modes =3D drm_helper_probe_single_connector_modes, + .atomic_duplicate_state =3D drm_atomic_helper_connector_duplicate_state, + .atomic_destroy_state =3D drm_atomic_helper_connector_destroy_state, +}; + +static struct drm_connector * +msm_dp_mst_add_connector(struct drm_dp_mst_topology_mgr *mgr, + struct drm_dp_mst_port *port, const char *pathprop) +{ + struct msm_dp_mst *dp_mst; + struct drm_device *dev; + struct msm_dp *dp_display; + struct msm_dp_mst_connector *mst_conn; + struct drm_connector *connector; + int rc, i; + + dp_mst =3D container_of(mgr, struct msm_dp_mst, mst_mgr); + + dp_display =3D dp_mst->msm_dp; + dev =3D dp_display->drm_dev; + + mst_conn =3D kzalloc_obj(*mst_conn); + + if (!mst_conn) + return NULL; + + drm_modeset_lock_all(dev); + + connector =3D &mst_conn->connector; + rc =3D drm_connector_dynamic_init(dev, connector, + &msm_dp_drm_mst_connector_funcs, + DRM_MODE_CONNECTOR_DisplayPort, NULL); + if (rc) { + kfree(mst_conn); + drm_modeset_unlock_all(dev); + return NULL; + } + + mst_conn->dp_panel =3D msm_dp_display_get_panel(dp_display); + if (!mst_conn->dp_panel) { + DRM_ERROR("failed to get dp_panel for connector\n"); + kfree(mst_conn); + drm_modeset_unlock_all(dev); + return NULL; + } + + mst_conn->dp_panel->connector =3D connector; + mst_conn->dp_mst =3D dp_mst; + + drm_connector_helper_add(connector, &msm_dp_drm_mst_connector_helper_func= s); + + if (connector->funcs->reset) + connector->funcs->reset(connector); + + /* add all encoders as possible encoders */ + for (i =3D 0; i < dp_mst->max_streams; i++) { + rc =3D drm_connector_attach_encoder(connector, dp_mst->mst_bridge[i]->en= coder); + + if (rc) { + DRM_ERROR("failed to attach encoder to connector, %d\n", rc); + kfree(mst_conn); + drm_modeset_unlock_all(dev); + return NULL; + } + } + + mst_conn->mst_port =3D port; + drm_dp_mst_get_port_malloc(mst_conn->mst_port); + + drm_object_attach_property(&connector->base, + dev->mode_config.path_property, 0); + drm_object_attach_property(&connector->base, + dev->mode_config.tile_property, 0); + drm_connector_set_path_property(connector, pathprop); + drm_modeset_unlock_all(dev); + + drm_dbg_dp(dp_display->drm_dev, "add MST connector id:%d\n", connector->b= ase.id); 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In MST case, route the HPD messages to MST module. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou --- drivers/gpu/drm/msm/dp/dp_display.c | 23 +++++++++++++++++++---- drivers/gpu/drm/msm/dp/dp_mst_drm.c | 34 ++++++++++++++++++++++++++++++++++ drivers/gpu/drm/msm/dp/dp_mst_drm.h | 1 + 3 files changed, 54 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index 919767945ba5..ca89e20b7563 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -454,6 +454,9 @@ static int msm_dp_hpd_plug_handle(struct msm_dp_display= _private *dp) dp->msm_dp_display.connector_type, dp->link->sink_count); =20 + if (dp->plugged) + return 0; + mutex_lock(&dp->plugged_lock); =20 ret =3D pm_runtime_resume_and_get(&pdev->dev); @@ -556,12 +559,19 @@ static int msm_dp_irq_hpd_handle(struct msm_dp_displa= y_private *dp) { u32 sink_request; int rc =3D 0; + struct msm_dp *msm_dp_display =3D &dp->msm_dp_display; =20 /* irq_hpd can happen at either connected or disconnected state */ drm_dbg_dp(dp->drm_dev, "Before, type=3D%d, sink_count=3D%d\n", dp->msm_dp_display.connector_type, dp->link->sink_count); =20 + if (msm_dp_display->mst_active) { + if (msm_dp_aux_is_link_connected(dp->aux) !=3D ISR_DISCONNECTED) + msm_dp_mst_display_hpd_irq(&dp->msm_dp_display); + return 0; + } + /* check for any test request issued by sink */ rc =3D msm_dp_link_process_request(dp->link); if (!rc) { @@ -1125,9 +1135,13 @@ static irqreturn_t msm_dp_display_irq_thread(int irq= , void *dev_id) connector_status_connected); =20 /* Send HPD as connected and distinguish it in the notifier */ - if (hpd_isr_status & DP_DP_IRQ_HPD_INT_MASK) - drm_bridge_hpd_notify(dp->msm_dp_display.bridge, - connector_status_connected); + if (hpd_isr_status & DP_DP_IRQ_HPD_INT_MASK) { + if (dp->msm_dp_display.mst_active) + msm_dp_irq_hpd_handle(dp); + else + drm_bridge_hpd_notify(dp->msm_dp_display.bridge, + connector_status_connected); + } =20 ret =3D IRQ_HANDLED; =20 @@ -1793,7 +1807,8 @@ void msm_dp_bridge_hpd_notify(struct drm_bridge *brid= ge, msm_dp_hpd_plug_handle(dp); } } else { - msm_dp_hpd_unplug_handle(dp); + if (hpd_link_status =3D=3D ISR_DISCONNECTED) + msm_dp_hpd_unplug_handle(dp); } =20 pm_runtime_put_sync(&msm_dp_display->pdev->dev); diff --git a/drivers/gpu/drm/msm/dp/dp_mst_drm.c b/drivers/gpu/drm/msm/dp/d= p_mst_drm.c index bb3898b1f6b1..71d3f63973e6 100644 --- a/drivers/gpu/drm/msm/dp/dp_mst_drm.c +++ b/drivers/gpu/drm/msm/dp/dp_mst_drm.c @@ -490,6 +490,40 @@ int msm_dp_mst_display_set_mgr_state(struct msm_dp *dp= _display, bool state) return rc; } =20 +/* DP MST HPD IRQ callback */ +void msm_dp_mst_display_hpd_irq(struct msm_dp *dp_display) +{ + int rc; + struct msm_dp_mst *mst =3D dp_display->msm_dp_mst; + u8 ack[8] =3D {}; + u8 esi[4]; + unsigned int esi_res =3D DP_SINK_COUNT_ESI + 1; + bool handled; + + rc =3D drm_dp_dpcd_read_data(mst->dp_aux, DP_SINK_COUNT_ESI, esi, 4); + if (rc < 0) { + DRM_ERROR("DPCD sink status read failed, rlen=3D%d\n", rc); + return; + } + + drm_dbg_dp(dp_display->drm_dev, "MST irq: esi1[0x%x] esi2[0x%x] esi3[%x]\= n", + esi[1], esi[2], esi[3]); + + rc =3D drm_dp_mst_hpd_irq_handle_event(&mst->mst_mgr, esi, ack, &handled); + + /* ack the request */ + if (handled) { + rc =3D drm_dp_dpcd_write_byte(mst->dp_aux, esi_res, ack[1]); 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For DSI/eDP/DP SST, the stream_id is always 0, so existing behavior remains unchanged. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 20 +++++++++++--------- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 2 ++ drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 4 ++++ 3 files changed, 17 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/= msm/disp/dpu1/dpu_encoder.c index eba1d52211f6..d6813107a27d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -1438,18 +1438,21 @@ static void dpu_encoder_virt_atomic_disable(struct = drm_encoder *drm_enc, =20 static struct dpu_hw_intf *dpu_encoder_get_intf(const struct dpu_mdss_cfg = *catalog, struct dpu_rm *dpu_rm, - enum dpu_intf_type type, u32 controller_id) + struct msm_display_info *disp_info, u32 controller_id) { - int i =3D 0; + int i =3D 0, cnt =3D 0; + int stream_id =3D disp_info->stream_id; =20 - if (type =3D=3D INTF_WB) + if (disp_info->intf_type =3D=3D INTF_WB) return NULL; =20 + DPU_DEBUG("intf_type 0x%x controller_id %d stream_id %d\n", + disp_info->intf_type, controller_id, stream_id); for (i =3D 0; i < catalog->intf_count; i++) { - if (catalog->intf[i].type =3D=3D type - && catalog->intf[i].controller_id =3D=3D controller_id) { - return dpu_rm_get_intf(dpu_rm, catalog->intf[i].id); - } + if (catalog->intf[i].type =3D=3D disp_info->intf_type && + controller_id =3D=3D catalog->intf[i].controller_id) + if (cnt++ =3D=3D stream_id) + return dpu_rm_get_intf(dpu_rm, catalog->intf[i].id); } =20 return NULL; @@ -2675,8 +2678,7 @@ static int dpu_encoder_setup_display(struct dpu_encod= er_virt *dpu_enc, i, controller_id, phys_params.split_role); =20 phys_params.hw_intf =3D dpu_encoder_get_intf(dpu_kms->catalog, &dpu_kms-= >rm, - disp_info->intf_type, - controller_id); + disp_info, controller_id); =20 if (disp_info->intf_type =3D=3D INTF_WB && controller_id < WB_MAX) phys_params.hw_wb =3D dpu_rm_get_wb(&dpu_kms->rm, controller_id); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h b/drivers/gpu/drm/= msm/disp/dpu1/dpu_encoder.h index ca1ca2e51d7e..2eb4c39b111c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h @@ -28,6 +28,7 @@ * @h_tile_instance: Controller instance used per tile. Number of eleme= nts is * based on num_of_h_tiles * @is_cmd_mode Boolean to indicate if the CMD mode is requested + * @stream_id stream id for which the interface needs to be acquired * @vsync_source: Source of the TE signal for DSI CMD devices */ struct msm_display_info { @@ -35,6 +36,7 @@ struct msm_display_info { uint32_t num_of_h_tiles; uint32_t h_tile_instance[MAX_H_TILES_PER_DISPLAY]; bool is_cmd_mode; + int stream_id; enum dpu_vsync_source vsync_source; }; =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/= disp/dpu1/dpu_kms.c index 89868443c0fe..305d4c76098d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -612,6 +612,7 @@ static int _dpu_kms_initialize_dsi(struct drm_device *d= ev, info.h_tile_instance[info.num_of_h_tiles++] =3D other; =20 info.is_cmd_mode =3D msm_dsi_is_cmd_mode(priv->kms->dsi[i]); + info.stream_id =3D 0; =20 rc =3D dpu_kms_dsi_set_te_source(&info, priv->kms->dsi[i]); if (rc) { @@ -687,6 +688,7 @@ static int _dpu_kms_initialize_displayport(struct drm_d= evice *dev, } =20 for (stream_id =3D 0; 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[129.46.232.65]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-8ac84cb135fsm19223386d6.38.2026.04.10.02.37.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Apr 2026 02:37:06 -0700 (PDT) From: Yongxing Mou Date: Fri, 10 Apr 2026 17:34:14 +0800 Subject: [PATCH v4 39/39] drm/msm/dp: Add MST stream support for supported DP controllers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260410-msm-dp-mst-v4-39-b20518dea8de@oss.qualcomm.com> References: <20260410-msm-dp-mst-v4-0-b20518dea8de@oss.qualcomm.com> In-Reply-To: <20260410-msm-dp-mst-v4-0-b20518dea8de@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Jessica Zhang Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Yongxing Mou X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1775813628; l=5055; i=yongxing.mou@oss.qualcomm.com; s=20250910; h=from:subject:message-id; bh=iMwTEQlSLqdMIjLd0OShc7tEQJwDmpIpI7plmhl2Ppk=; b=px7SlUcm5iFaAIhHhWYgr6H/gk/oToLLLHCVm9P87IRUEQz56O+VqMbU3shfdcsF1u9qPYrSP htEkTk0ua/rCYN1iG20pUn7fp1phB8aCIdFm0UxQ3k+ZRE5ZuYMKKey X-Developer-Key: i=yongxing.mou@oss.qualcomm.com; a=ed25519; pk=rAy5J1eP+V7OXqH5FJ7ngMCtUrnHhut30ZTldOj52UM= X-Authority-Analysis: v=2.4 cv=PMM/P/qC c=1 sm=1 tr=0 ts=69d8c4c4 cx=c_pps a=UgVkIMxJMSkC9lv97toC5g==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=EUspDBNiAAAA:8 a=PGsfSfowbhEG1GcfnYsA:9 a=QEXdDO2ut3YA:10 a=1HOtulTD9v-eNWfpl4qZ:22 X-Proofpoint-ORIG-GUID: utizB9wTUM3wZaWK_BfCQUy2brqqkbQW X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDEwMDA4OSBTYWx0ZWRfX3Qm17XbH2/x+ Kv+9JlNgkmAbB25uidnwgEQPviSRCuBFNddOLjfSkaV4yi5YReIAtxlwmZeh73IGQgXswMzmzme 8vWZdDhyrkiT2GZW6ARnb4Mhz4DnMl65NyikTdfrSaOQ1e9N4k9Ox5I6SCx0FH6VbjxFisI+vHl BQr7zZhZ7iDFF/rIMUAFnKfWf+EGRm3E7gdXLhNBvw7xc7jzg2Yiw/mCQOW4oANPUT4gi/qJCJl vuDPYInSdxlNn9DCG2sDO3CQ/YWMUBZrHLZ8ZJyk4uhhmXka4+x8aBzMB9XM6B/P470ehJWbX5P kgFEo5BdINO4hwTCP3gdMHoRb1533Wj5JsJDyN2CeGFZrc1PL1Bixfga/XNNlDhwmwjbxj3bpuO YIyDD/fvdwrtT69iB+5LQ2Seh5whfr4X3BukcUJANkXRWRjb2d2WddC3BSeMBMwEVV0eofdJpVy u7xyeUy+iR2bP6KK9Yg== X-Proofpoint-GUID: utizB9wTUM3wZaWK_BfCQUy2brqqkbQW X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-10_03,2026-04-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 suspectscore=0 priorityscore=1501 adultscore=0 lowpriorityscore=0 bulkscore=0 phishscore=0 clxscore=1015 malwarescore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604010000 definitions=main-2604100089 Enables MST support for MSM DP controllers that support it, allowing each controller to handle up to two or four DisplayPort streams. All necessary MST support code was already implemented in the previous series of patches. Signed-off-by: Yongxing Mou --- drivers/gpu/drm/msm/dp/dp_display.c | 42 ++++++++++++++++++++++++---------= ---- 1 file changed, 28 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index ca89e20b7563..f632b4f64ccc 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -107,16 +107,21 @@ struct msm_dp_desc { }; =20 static const struct msm_dp_desc msm_dp_desc_glymur[] =3D { - { .io_start =3D 0x0af54000, .id =3D MSM_DP_CONTROLLER_0, .wide_bus_suppor= ted =3D true }, - { .io_start =3D 0x0af5c000, .id =3D MSM_DP_CONTROLLER_1, .wide_bus_suppor= ted =3D true }, - { .io_start =3D 0x0af64000, .id =3D MSM_DP_CONTROLLER_2, .wide_bus_suppor= ted =3D true }, + { .io_start =3D 0x0af54000, .id =3D MSM_DP_CONTROLLER_0, .wide_bus_suppor= ted =3D true, + .mst_streams =3D 2 }, + { .io_start =3D 0x0af5c000, .id =3D MSM_DP_CONTROLLER_1, .wide_bus_suppor= ted =3D true, + .mst_streams =3D 2 }, + { .io_start =3D 0x0af64000, .id =3D MSM_DP_CONTROLLER_2, .wide_bus_suppor= ted =3D true, + .mst_streams =3D 2 }, { .io_start =3D 0x0af6c000, .id =3D MSM_DP_CONTROLLER_3, .wide_bus_suppor= ted =3D true }, {} }; =20 static const struct msm_dp_desc msm_dp_desc_sa8775p[] =3D { - { .io_start =3D 0x0af54000, .id =3D MSM_DP_CONTROLLER_0, .wide_bus_suppor= ted =3D true }, - { .io_start =3D 0x0af5c000, .id =3D MSM_DP_CONTROLLER_1, .wide_bus_suppor= ted =3D true }, + { .io_start =3D 0x0af54000, .id =3D MSM_DP_CONTROLLER_0, .wide_bus_suppor= ted =3D true, + .mst_streams =3D 4}, + { .io_start =3D 0x0af5c000, .id =3D MSM_DP_CONTROLLER_1, .wide_bus_suppor= ted =3D true, + .mst_streams =3D 2}, { .io_start =3D 0x22154000, .id =3D MSM_DP_CONTROLLER_0, .wide_bus_suppor= ted =3D true }, { .io_start =3D 0x2215c000, .id =3D MSM_DP_CONTROLLER_1, .wide_bus_suppor= ted =3D true }, {} @@ -133,38 +138,47 @@ static const struct msm_dp_desc msm_dp_desc_sc7180[] = =3D { }; =20 static const struct msm_dp_desc msm_dp_desc_sc7280[] =3D { - { .io_start =3D 0x0ae90000, .id =3D MSM_DP_CONTROLLER_0, .wide_bus_suppor= ted =3D true }, + { .io_start =3D 0x0ae90000, .id =3D MSM_DP_CONTROLLER_0, .wide_bus_suppor= ted =3D true, + .mst_streams =3D 2 }, { .io_start =3D 0x0aea0000, .id =3D MSM_DP_CONTROLLER_1, .wide_bus_suppor= ted =3D true }, {} }; =20 static const struct msm_dp_desc msm_dp_desc_sc8180x[] =3D { - { .io_start =3D 0x0ae90000, .id =3D MSM_DP_CONTROLLER_0, .wide_bus_suppor= ted =3D true }, + { .io_start =3D 0x0ae90000, .id =3D MSM_DP_CONTROLLER_0, .wide_bus_suppor= ted =3D true, + .mst_streams =3D 2 }, { .io_start =3D 0x0ae98000, .id =3D MSM_DP_CONTROLLER_1, .wide_bus_suppor= ted =3D true }, { .io_start =3D 0x0ae9a000, .id =3D MSM_DP_CONTROLLER_2, .wide_bus_suppor= ted =3D true }, {} }; =20 static const struct msm_dp_desc msm_dp_desc_sc8280xp[] =3D { - { .io_start =3D 0x0ae90000, .id =3D MSM_DP_CONTROLLER_0, .wide_bus_suppor= ted =3D true }, - { .io_start =3D 0x0ae98000, .id =3D MSM_DP_CONTROLLER_1, .wide_bus_suppor= ted =3D true }, + { .io_start =3D 0x0ae90000, .id =3D MSM_DP_CONTROLLER_0, .wide_bus_suppor= ted =3D true, + .mst_streams =3D 2}, + { .io_start =3D 0x0ae98000, .id =3D MSM_DP_CONTROLLER_1, .wide_bus_suppor= ted =3D true, + .mst_streams =3D 2}, { .io_start =3D 0x0ae9a000, .id =3D MSM_DP_CONTROLLER_2, .wide_bus_suppor= ted =3D true }, { .io_start =3D 0x0aea0000, .id =3D MSM_DP_CONTROLLER_3, .wide_bus_suppor= ted =3D true }, - { .io_start =3D 0x22090000, .id =3D MSM_DP_CONTROLLER_0, .wide_bus_suppor= ted =3D true }, - { .io_start =3D 0x22098000, .id =3D MSM_DP_CONTROLLER_1, .wide_bus_suppor= ted =3D true }, + { .io_start =3D 0x22090000, .id =3D MSM_DP_CONTROLLER_0, .wide_bus_suppor= ted =3D true, + .mst_streams =3D 2}, + { .io_start =3D 0x22098000, .id =3D MSM_DP_CONTROLLER_1, .wide_bus_suppor= ted =3D true, + .mst_streams =3D 2}, { .io_start =3D 0x2209a000, .id =3D MSM_DP_CONTROLLER_2, .wide_bus_suppor= ted =3D true }, { .io_start =3D 0x220a0000, .id =3D MSM_DP_CONTROLLER_3, .wide_bus_suppor= ted =3D true }, {} }; =20 static const struct msm_dp_desc msm_dp_desc_sm8650[] =3D { - { .io_start =3D 0x0af54000, .id =3D MSM_DP_CONTROLLER_0, .wide_bus_suppor= ted =3D true }, + { .io_start =3D 0x0af54000, .id =3D MSM_DP_CONTROLLER_0, .wide_bus_suppor= ted =3D true, + .mst_streams =3D 2 }, {} }; =20 static const struct msm_dp_desc msm_dp_desc_x1e80100[] =3D { - { .io_start =3D 0x0ae90000, .id =3D MSM_DP_CONTROLLER_0, .wide_bus_suppor= ted =3D true }, - { .io_start =3D 0x0ae98000, .id =3D MSM_DP_CONTROLLER_1, .wide_bus_suppor= ted =3D true }, + { .io_start =3D 0x0ae90000, .id =3D MSM_DP_CONTROLLER_0, .wide_bus_suppor= ted =3D true, + .mst_streams =3D 2}, + { .io_start =3D 0x0ae98000, .id =3D MSM_DP_CONTROLLER_1, .wide_bus_suppor= ted =3D true, + .mst_streams =3D 2}, { .io_start =3D 0x0ae9a000, .id =3D MSM_DP_CONTROLLER_2, .wide_bus_suppor= ted =3D true }, { .io_start =3D 0x0aea0000, .id =3D MSM_DP_CONTROLLER_3, .wide_bus_suppor= ted =3D true }, {} --=20 2.43.0