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Reviewed-by: Konrad Dybcio Signed-off-by: Taniya Das --- arch/arm64/boot/dts/qcom/glymur.dtsi | 47 ++++++++++++++++++++++++++++++++= ++++ 1 file changed, 47 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qco= m/glymur.dtsi index e269cec7942c85447892c0661f83171eded94f3b..882b8fe025e78ec7a9916226ea3= b9c9c9e5c03f3 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -5,7 +5,10 @@ =20 #include #include +#include #include +#include +#include #include #include #include @@ -3335,6 +3338,34 @@ hsc_noc: interconnect@2000000 { #interconnect-cells =3D <2>; }; =20 + gxclkctl: clock-controller@3d64000 { + compatible =3D "qcom,glymur-gxclkctl"; + reg =3D <0x0 0x03d64000 0x0 0x6000>; + + power-domains =3D <&rpmhpd RPMHPD_GFX>, + <&rpmhpd RPMHPD_GMXC>, + <&gpucc GPU_CC_CX_GDSC>; + + #power-domain-cells =3D <1>; + }; + + gpucc: clock-controller@3d90000 { + compatible =3D "qcom,glymur-gpucc"; + reg =3D <0x0 0x03d90000 0x0 0x9800>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + + power-domains =3D <&rpmhpd RPMHPD_MX>, + <&rpmhpd RPMHPD_CX>; + required-opps =3D <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + ipcc: mailbox@3e04000 { compatible =3D "qcom,glymur-ipcc", "qcom,ipcc"; reg =3D <0x0 0x03e04000 0x0 0x1000>; @@ -3367,6 +3398,22 @@ lpass_ag_noc: interconnect@7e40000 { #interconnect-cells =3D <2>; }; =20 + videocc: clock-controller@aaf0000 { + compatible =3D "qcom,glymur-videocc"; + reg =3D <0x0 0x0aaf0000 0x0 0x10000>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>; + + power-domains =3D <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MXC>; + required-opps =3D <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + dispcc: clock-controller@af00000 { compatible =3D "qcom,glymur-dispcc"; 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Thu, 09 Apr 2026 20:49:18 -0700 (PDT) Received: from hu-tdas-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2b2d4ddcda9sm11588185ad.28.2026.04.09.20.49.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Apr 2026 20:49:18 -0700 (PDT) From: Taniya Das Date: Fri, 10 Apr 2026 09:19:05 +0530 Subject: [PATCH v3 2/2] arm64: defconfig: Enable Qualcomm Glymur clock controllers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260410-glymur_mmcc_dt_config_v2-v3-2-acce9d106e72@oss.qualcomm.com> References: <20260410-glymur_mmcc_dt_config_v2-v3-0-acce9d106e72@oss.qualcomm.com> In-Reply-To: <20260410-glymur_mmcc_dt_config_v2-v3-0-acce9d106e72@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Taniya Das , Dmitry Baryshkov X-Mailer: b4 0.15-dev-aa3f6 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDEwMDAzMSBTYWx0ZWRfX2/ihClAq7iFD qbIHSTOFuPI4RlcrzI9Z7BVItQz+iYEVGrLvYYinDgYkhjEGgCEQWtYPcDRiIKSWy99WiAxPct0 +mH5QXuxdJBKLop5V4VrQiWmLFvaPkJQ5ZnvKe9TKHHRTVg6aSGtiy6CoHE9xSKZV3Q9XmY233V POlfqUlKaLH3yY/6cOGlaElQ0BoQlDR3T8kC61t+Qe4SSMwvn7nlm7JfNOiDTdc0J9qks9pn+Xg VntQwatFeoudNvIQwsPVyXumYUWjCw+GWOHz1aRHwOuovWyaXJ3kvfqJysMxUwidGHzTemA46WO QxLpQFt1TW9gjuw+V7BpnYtI/cNlLDyFRtGz8cTlsISmHtuuobGPJippLmrE078ruwZ6pcOAeU8 mP9wIWHgCrVuJ6EAhfUDIrk0zJgP3c46x52T6LboSZB33TuVWaHgCt1nko6ypu5adtQwi07/o8S aPpGgmBoC272cT2YUWw== X-Proofpoint-ORIG-GUID: 07lTmpSixY9ntD92xz8PgQi3oYBsiMqA X-Authority-Analysis: v=2.4 cv=fZmdDUQF c=1 sm=1 tr=0 ts=69d8733f cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=EUspDBNiAAAA:8 a=rO3wVDe-YCVyVCuK1RsA:9 a=QEXdDO2ut3YA:10 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-GUID: 07lTmpSixY9ntD92xz8PgQi3oYBsiMqA X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-10_01,2026-04-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 bulkscore=0 spamscore=0 adultscore=0 priorityscore=1501 suspectscore=0 clxscore=1015 phishscore=0 impostorscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604010000 definitions=main-2604100031 Enable the Glymur video and gpu clock controller for their respective functionalities on the Qualcomm Glymur CRD boards. Reviewed-by: Dmitry Baryshkov Signed-off-by: Taniya Das --- arch/arm64/configs/defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 4ed70ab7ee854038fa7a756d8b650a609258bdb3..a607bf49c1563d22550c4b81a23= 7d46fe4ea41ce 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1457,7 +1457,9 @@ CONFIG_COMMON_CLK_MT8192_VENCSYS=3Dy CONFIG_COMMON_CLK_QCOM=3Dy CONFIG_CLK_GLYMUR_DISPCC=3Dm CONFIG_CLK_GLYMUR_GCC=3Dy +CONFIG_CLK_GLYMUR_GPUCC=3Dm CONFIG_CLK_GLYMUR_TCSRCC=3Dm +CONFIG_CLK_GLYMUR_VIDEOCC=3Dm CONFIG_CLK_KAANAPALI_GCC=3Dy CONFIG_CLK_KAANAPALI_TCSRCC=3Dm CONFIG_CLK_X1E80100_CAMCC=3Dm --=20 2.34.1