From nobody Thu Jun 4 20:28:10 2026 Received: from mail-pj1-f74.google.com (mail-pj1-f74.google.com [209.85.216.74]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B941038F945 for ; Thu, 9 Apr 2026 22:24:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.74 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775773496; cv=none; b=btWJkkDJkp1GvHFetGUVrHUYS+WhuvFPbN1qKogSaJHtv46w7X+uLSmY80SOrMSleZ5DyiPVcv1c2cM/SaH+qNTpGrwIxykAMpRr8jT04qsk4tL3KRAM91TdH/z674cM+f5X4cyBmF0ZFGhxe22+xEet7TAXscsVStNLAmCTn2I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775773496; c=relaxed/simple; bh=aDwH+MMYXaOvmnW6sjqONolO2mDyDJseqaYwCrZzXCc=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=nTxE47wrgZkEiKsudFSppk2pgpwGV8YZSCXwB/03cBp954hJ8mwXPtmo9vyPW7SiZQAQGlbJhzo79ljJ2NouHiD4QszuB5dfXh1UuGrd/dNFAe+K3splRXZHoaS8M4kukzcw2jylu+c/vSC3e13bUQUeTYhToRzDn49sRw7QyJs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=M48zMlM9; arc=none smtp.client-ip=209.85.216.74 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="M48zMlM9" Received: by mail-pj1-f74.google.com with SMTP id 98e67ed59e1d1-35842aa350fso3043317a91.0 for ; Thu, 09 Apr 2026 15:24:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20251104; t=1775773494; x=1776378294; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:from:to:cc:subject:date:message-id:reply-to; bh=voCuk6N+Zbgqw6oi0f6cUzYlY+mVhATQs0grs8oy33k=; b=M48zMlM94N3uorFv8a6RoQHAR2vjrNO+4h34ssYOisJv+COAdeETCetGUew0o5Yp3X Jp2NgDGMQZbGtbxCQudfaw6NIHROTYVF38P4C6cnzb73vpj9ub1BI+/IhaBgpmv1TR7j dYOhViZeoohCvOqvxQE0ioNSsCuPJGVV9RFJDnO8MK4S+UKnNDPvpsHRn3VBzIerrsFE eGcKhnv9KF8amcEoZDlT/BSZJD70fmxuBBnL0OrjsrwbcWS4vE+nbvi16hLCitb5jMAw 9BP3KzCx5l4rqlaiODql61aggHa5CAyzrJsormipspIk41Swr6TE8HAIHP3osJeK3pOP SxlQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1775773494; x=1776378294; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=voCuk6N+Zbgqw6oi0f6cUzYlY+mVhATQs0grs8oy33k=; b=OmJgqhqMiGXJB5regiFtyNQW9bAMsiX381AEXjgXFBCEkvmJyYgVClRbSGroCg4xvv UvYc3jtRyu4KxaQnMBTngw3yxmo+lhMyCSVD1CXzF5ZyjadU7tCRt2yvQ1d0ASmHBsm0 W7tcSkoI34uWvaUT4o4ipezpMrO8f2Lx8dE+NZLYtRqzZfwx4nqs7ojZj6ejhSD9+hwZ ExX9iWGGapUqQERltgeYwJeUyoKTQ1pgyctAKrLa7EG0vUUUCnG97SW1QkGtMQFUwyP7 tHOrDhyRewNf5wPd4nu2tCsniLtfzjV2itAcVwtfewRNuy+WnE0DGbsQVI4O9m/3X2GR ORgg== X-Forwarded-Encrypted: i=1; AJvYcCUqN5M06YeWyrp8/FNF89d2HDMvsJhVRY4tuKQ4VmEedDJ3pVMLo4ExbulsA66rC8VJpRt04BcPjTuTvAQ=@vger.kernel.org X-Gm-Message-State: AOJu0YwDh8hM0qcb2Kltt9hPoZhttG+fLoriOYYl81rrlqeyesQp/P8A kq+hz8CLYErt41CGKjJn4Zx5RKtozeiLsvUEe4uHAe1DyCFFuyB1qt2xecvieXNbVVB1ZLrwITc K0tP3Fw== X-Received: from pjbcp1.prod.google.com ([2002:a17:90a:fb81:b0:35d:972a:7f6a]) (user=seanjc job=prod-delivery.src-stubby-dispatcher) by 2002:a17:90b:3b49:b0:35b:ea35:c3ce with SMTP id 98e67ed59e1d1-35e42867ce0mr710269a91.27.1775773493865; Thu, 09 Apr 2026 15:24:53 -0700 (PDT) Reply-To: Sean Christopherson Date: Thu, 9 Apr 2026 15:24:47 -0700 In-Reply-To: <20260409222449.2013847-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20260409222449.2013847-1-seanjc@google.com> X-Mailer: git-send-email 2.53.0.1213.gd9a14994de-goog Message-ID: <20260409222449.2013847-2-seanjc@google.com> Subject: [PATCH 1/3] KVM: SVM: Disable x2AVIC RDMSR interception for MSRs KVM actually supports From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Naveen N Rao Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Fix multiple (classes of) bugs with one stone by using KVM's mask of readable local APIC registers to determine which x2APIC MSRs to pass through (or not) when toggling x2AVIC on/off. The existing hand-coded list of MSRs is wrong on multiple fronts: - ARBPRI, DFR, and ICR2 aren't supported by x2APIC; disabling interception is nonsensical and suboptimal (the access generates a #VMEXIT that requires decoding the instruction). - RRR is completely unsupported. - AVIC currently fails to pass through the "range of vectors" registers, IRR, ISR, and TMR, as e.g. X2APIC_MSR(APIC_IRR) only affects IRR0, and thus only disables intercept for vectors 31:0 (which are the *least* interesting registers). Fixes: 4d1d7942e36a ("KVM: SVM: Introduce logic to (de)activate x2AVIC mode= ") Cc: stable@vger.kernel.org Cc: Naveen N Rao (AMD) Signed-off-by: Sean Christopherson --- arch/x86/kvm/svm/avic.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c index adf211860949..df974ee290d0 100644 --- a/arch/x86/kvm/svm/avic.c +++ b/arch/x86/kvm/svm/avic.c @@ -122,6 +122,9 @@ static u32 x2avic_max_physical_id; static void avic_set_x2apic_msr_interception(struct vcpu_svm *svm, bool intercept) { + struct kvm_vcpu *vcpu =3D &svm->vcpu; + u64 x2apic_readable_mask; + static const u32 x2avic_passthrough_msrs[] =3D { X2APIC_MSR(APIC_ID), X2APIC_MSR(APIC_LVR), @@ -162,9 +165,15 @@ static void avic_set_x2apic_msr_interception(struct vc= pu_svm *svm, if (!x2avic_enabled) return; =20 + x2apic_readable_mask =3D kvm_lapic_readable_reg_mask(vcpu->arch.apic); + + for (i =3D 0; i < BITS_PER_TYPE(typeof(x2apic_readable_mask)); i++) + svm_set_intercept_for_msr(vcpu, APIC_BASE_MSR + i, + MSR_TYPE_R, intercept); + for (i =3D 0; i < ARRAY_SIZE(x2avic_passthrough_msrs); i++) - svm_set_intercept_for_msr(&svm->vcpu, x2avic_passthrough_msrs[i], - MSR_TYPE_RW, intercept); + svm_set_intercept_for_msr(vcpu, x2avic_passthrough_msrs[i], + MSR_TYPE_W, intercept); =20 svm->x2avic_msrs_intercepted =3D intercept; } --=20 2.53.0.1213.gd9a14994de-goog From nobody Thu Jun 4 20:28:10 2026 Received: from mail-pg1-f201.google.com (mail-pg1-f201.google.com [209.85.215.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6EC35390235 for ; Thu, 9 Apr 2026 22:24:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.215.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775773498; cv=none; b=UxGV4A62m5o8mdIAnk/9xOM8V8UBMfLewXn4hMLOSkz0sJ34JcApdUNUiWFmhYtumcbChnOaHPhN0hlsCGbuA4bDESgsssxRAM9k/BNxtxzwkAf9TqyhIbD9ZqJbXJ7xOsBk8rqdaXlpSpH7lJTsUqhBcfpkdKdoTBn+u0D0+YU= ARC-Message-Signature: i=1; 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charset="utf-8" Explicitly intercept RDMSR for TMMCT, a.k.a. the current APIC timer count, when x2AVIC is enabled, as TMMCT reads aren't accelerated by hardware. Disabling interception is suboptimal as the RDMSR generates an AVIC_UNACCELERATED_ACCESS fault #VMEXIT, which forces KVM to decode the instruction to figure out what the guest was trying to access. Note, the only reason this isn't a fatal bug is that the AVIC architecture had the foresight to guard against buggy hypervisors. E.g. if hardware simply read from the virtual APIC page, the guest would get garbage. Fixes: 4d1d7942e36a ("KVM: SVM: Introduce logic to (de)activate x2AVIC mode= ") Cc: stable@vger.kernel.org Cc: Naveen N Rao (AMD) Signed-off-by: Sean Christopherson --- arch/x86/kvm/svm/avic.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c index df974ee290d0..c9e9872ad880 100644 --- a/arch/x86/kvm/svm/avic.c +++ b/arch/x86/kvm/svm/avic.c @@ -171,6 +171,9 @@ static void avic_set_x2apic_msr_interception(struct vcp= u_svm *svm, svm_set_intercept_for_msr(vcpu, APIC_BASE_MSR + i, MSR_TYPE_R, intercept); =20 + if (!intercept) + svm_enable_intercept_for_msr(vcpu, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_R); + for (i =3D 0; i < ARRAY_SIZE(x2avic_passthrough_msrs); i++) svm_set_intercept_for_msr(vcpu, x2avic_passthrough_msrs[i], MSR_TYPE_W, intercept); --=20 2.53.0.1213.gd9a14994de-goog From nobody Thu Jun 4 20:28:10 2026 Received: from mail-pl1-f201.google.com (mail-pl1-f201.google.com [209.85.214.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3CAE039099C for ; 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Thu, 09 Apr 2026 15:24:57 -0700 (PDT) Reply-To: Sean Christopherson Date: Thu, 9 Apr 2026 15:24:49 -0700 In-Reply-To: <20260409222449.2013847-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20260409222449.2013847-1-seanjc@google.com> X-Mailer: git-send-email 2.53.0.1213.gd9a14994de-goog Message-ID: <20260409222449.2013847-4-seanjc@google.com> Subject: [PATCH 3/3] KVM: SVM: Only disable x2AVIC WRMSR interception for MSRs that are accelerated From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Naveen N Rao Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When x2AVIC is enabled, disable WRMSR interception only for MSRs that are actually accelerated by hardware. Disabling interception for MSRs that aren't accelerated is functionally "fine", but very suboptimal as many accesses generate AVIC_UNACCELERATED_ACCESS fault #VMEXITs, which requires KVM to decode the instruction to figure out what the guest was trying to access. Note, the set of MSRs that are passed through for write is identical to VMX's set when IPI virtualization is enabled. This is not a coincidence, as x2AVIC is functionally equivalent to APICv+IPIv. Fixes: 4d1d7942e36a ("KVM: SVM: Introduce logic to (de)activate x2AVIC mode= ") Cc: stable@vger.kernel.org Cc: Naveen N Rao (AMD) Signed-off-by: Sean Christopherson --- arch/x86/kvm/svm/avic.c | 40 ++++------------------------------------ 1 file changed, 4 insertions(+), 36 deletions(-) diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c index c9e9872ad880..2b07cc347b90 100644 --- a/arch/x86/kvm/svm/avic.c +++ b/arch/x86/kvm/svm/avic.c @@ -124,39 +124,6 @@ static void avic_set_x2apic_msr_interception(struct vc= pu_svm *svm, { struct kvm_vcpu *vcpu =3D &svm->vcpu; u64 x2apic_readable_mask; - - static const u32 x2avic_passthrough_msrs[] =3D { - X2APIC_MSR(APIC_ID), - X2APIC_MSR(APIC_LVR), - X2APIC_MSR(APIC_TASKPRI), - X2APIC_MSR(APIC_ARBPRI), - X2APIC_MSR(APIC_PROCPRI), - X2APIC_MSR(APIC_EOI), - X2APIC_MSR(APIC_RRR), - X2APIC_MSR(APIC_LDR), - X2APIC_MSR(APIC_DFR), - X2APIC_MSR(APIC_SPIV), - X2APIC_MSR(APIC_ISR), - X2APIC_MSR(APIC_TMR), - X2APIC_MSR(APIC_IRR), - X2APIC_MSR(APIC_ESR), - X2APIC_MSR(APIC_ICR), - X2APIC_MSR(APIC_ICR2), - - /* - * Note! Always intercept LVTT, as TSC-deadline timer mode - * isn't virtualized by hardware, and the CPU will generate a - * #GP instead of a #VMEXIT. - */ - X2APIC_MSR(APIC_LVTTHMR), - X2APIC_MSR(APIC_LVTPC), - X2APIC_MSR(APIC_LVT0), - X2APIC_MSR(APIC_LVT1), - X2APIC_MSR(APIC_LVTERR), - X2APIC_MSR(APIC_TMICT), - X2APIC_MSR(APIC_TMCCT), - X2APIC_MSR(APIC_TDCR), - }; int i; =20 if (intercept =3D=3D svm->x2avic_msrs_intercepted) @@ -174,9 +141,10 @@ static void avic_set_x2apic_msr_interception(struct vc= pu_svm *svm, if (!intercept) svm_enable_intercept_for_msr(vcpu, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_R); =20 - for (i =3D 0; i < ARRAY_SIZE(x2avic_passthrough_msrs); i++) - svm_set_intercept_for_msr(vcpu, x2avic_passthrough_msrs[i], - MSR_TYPE_W, intercept); + svm_set_intercept_for_msr(vcpu, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_W, int= ercept); + svm_set_intercept_for_msr(vcpu, X2APIC_MSR(APIC_EOI), MSR_TYPE_W, interce= pt); + svm_set_intercept_for_msr(vcpu, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W, in= tercept); + svm_set_intercept_for_msr(vcpu, X2APIC_MSR(APIC_ICR), MSR_TYPE_W, interce= pt); =20 svm->x2avic_msrs_intercepted =3D intercept; } --=20 2.53.0.1213.gd9a14994de-goog