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Thu, 09 Apr 2026 09:37:46 -0700 (PDT) Received: from iku.example.org ([2a06:5906:61b:2d00:e6c9:3997:12f3:90d]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43d63de2e4csm76587f8f.2.2026.04.09.09.37.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Apr 2026 09:37:45 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Linus Walleij Cc: linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH] pinctrl: renesas: rzg2l: Add SR register cache for PM suspend/resume Date: Thu, 9 Apr 2026 17:37:36 +0100 Message-ID: <20260409163736.2419396-1-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.53.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Include the SR (Slew Rate) register in the PM suspend/resume register cache. Signed-off-by: Lad Prabhakar --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/rene= sas/pinctrl-rzg2l.c index 561e6018fd89..347926dad0c9 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -322,6 +322,7 @@ struct rzg2l_pinctrl_pin_settings { * @pupd: PUPD registers cache * @ien: IEN registers cache * @smt: SMT registers cache + * @sr: SR registers cache * @sd_ch: SD_CH registers cache * @eth_poc: ET_POC registers cache * @oen: Output Enable register cache @@ -336,6 +337,7 @@ struct rzg2l_pinctrl_reg_cache { u32 *ien[2]; u32 *pupd[2]; u32 *smt; + u32 *sr; u8 sd_ch[2]; u8 eth_poc[2]; u8 oen; @@ -2741,6 +2743,10 @@ static int rzg2l_pinctrl_reg_cache_alloc(struct rzg2= l_pinctrl *pctrl) if (!cache->smt) return -ENOMEM; =20 + cache->sr =3D devm_kcalloc(pctrl->dev, nports, sizeof(*cache->sr), GFP_KE= RNEL); + if (!cache->sr) + return -ENOMEM; + for (u8 i =3D 0; i < 2; i++) { u32 n_dedicated_pins =3D pctrl->data->n_dedicated_pins; =20 @@ -3002,7 +3008,7 @@ static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l_= pinctrl *pctrl, bool suspen struct rzg2l_pinctrl_reg_cache *cache =3D pctrl->cache; =20 for (u32 port =3D 0; port < nports; port++) { - bool has_iolh, has_ien, has_pupd, has_smt; + bool has_iolh, has_ien, has_pupd, has_smt, has_sr; u32 off, caps; u8 pincnt; u64 cfg; @@ -3023,6 +3029,7 @@ static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l_= pinctrl *pctrl, bool suspen has_ien =3D !!(caps & PIN_CFG_IEN); has_pupd =3D !!(caps & PIN_CFG_PUPD); has_smt =3D !!(caps & PIN_CFG_SMT); + has_sr =3D !!(caps & PIN_CFG_SR); =20 if (suspend) RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + PFC(off), cache->pfc[po= rt]); @@ -3068,6 +3075,9 @@ static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l_= pinctrl *pctrl, bool suspen =20 if (has_smt) RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + SMT(off), cache->smt[po= rt]); + + if (has_sr) + RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + SR(off), cache->sr[port= ]); } } =20 --=20 2.53.0