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Thu, 9 Apr 2026 04:56:28 -0700 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , Shay Drory , Or Har-Toov , Edward Srouji , Maher Sanalla , Simon Horman , Moshe Shemesh , Kees Cook , Patrisious Haddad , Gerd Bayer , Parav Pandit , Cosmin Ratiu , Carolina Jubran , , , , Gal Pressman , Dragos Tatulea Subject: [PATCH net-next 1/7] net/mlx5: Lag: refactor representor reload handling Date: Thu, 9 Apr 2026 14:55:44 +0300 Message-ID: <20260409115550.156419-2-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260409115550.156419-1-tariqt@nvidia.com> References: <20260409115550.156419-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF00000143:EE_|SA0PR12MB4495:EE_ X-MS-Office365-Filtering-Correlation-Id: 6880a264-082b-4a17-8e2a-08de962f1500 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|82310400026|36860700016|7416014|18002099003|22082099003|56012099003; X-Microsoft-Antispam-Message-Info: k0oUwvdA9AUzoQT+Rj4J64LT4jB2XIjs7MXcVrnMhBZNRwcjKnDw7XCrAcQVYDvIP2wuHs8CtDoa1b4pJvMvY8bBxSqQvqqoBpnY+6cOI7gb7bglTDxZrOOFywMbNpU63s6RGBhp4zdEnIOa6nFshDrEKNujC9Fl7n6c+FULAOYV3bC/jFWgtc1IR8tsO7xanpNt3zsnZP9GMSlzJ9m1h4oN/8+1jvYLgOHMYdl9e6oZH4+uw/lKntHU3sBvCgwQ0mbgVIW3WEBUcHL+d4DMPyKrmyxDShwpndt8G8IpccG3dRLjVXsU+s7mxh4GYTWyP0e4oyQ18rhzJMtfFpM0Ny0LSd321PikO27zAPNLjlweynzTxbqDXwZ/HEMyt4FqRFlVVlGBSCQUvyuIZKfxI8xmcFxyu/zbr2aQKIK+AA9/Dgqzz3x7mzcgFl6DpLyF6FCN9H0ODa66l2bHfA9UAlbJlpzDqZONfEcDPxT96GHavt0evp8kqsprkuRH4nsU/GVWh75t1vr54EYhp/piGJtflEsZa9GpTtxJHs646olDEYh2xw1N/F95rZ8GPXfDpL/KhXWCkVaSKtlAoBGJYeFKs/mlViSEd/fd1VxQR/pztGSZyLzbCk+KVfmw3wX6ZFXNWaqCgc7+FmcgRq4YRR+2k5Yt2Ja2/cjVPct5ISsO1X/4bqvy/3exZUtORTPx3zm885XA/4HjP8hGZuHgRpk7rJGShNGSnDUpxBqbK5u7acMZphcUezLwcyu33piw428Izj1Iuq8J5kE2VGHqOQ== X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(376014)(82310400026)(36860700016)(7416014)(18002099003)(22082099003)(56012099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: JJmaBHU0WlKX8YnocdfDAHWSzNTFlrU+vVKDZ5pkkLZqW70ippFTfmzr5ukTAOIecMGiYDRRZIVq23aQ4YLvRlEP99y9uOi8wSs2+xLn3NCT2q1tOrC7qYYAaFuShMr16dZxGZTDDUFLrA6CqutRAtYvSlLoawraNLAEF6HuOIZOq6hKGc7c49TAU99urG+cSI7RNDzkoumxSNHlBboRScXw69qM06uBwJ+WQnnzx/8G5GYmcqF1+miNAv+qflfqF7zh1t2UroaP7rNStZ+r43OHlSME9h8eTRw/XlBciTQAj3bTfCTm22d/ihEy6IW269/Ep0glNbQ/l4KdQdjssoFqU0PDJxVBnrA6SgUf9pjK9faVsr+i9wy29AZowR5D9tE6s+mrKeYf2gu7mUGUw7RXjP8jc2QTRduhnOj48a8rVIgAzs/s42CyPtmtxXoL X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Apr 2026 11:56:49.1767 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6880a264-082b-4a17-8e2a-08de962f1500 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF00000143.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB4495 From: Mark Bloch Representor reload during LAG/MPESW transitions has to be repeated in several flows, and each open=E2=80=91coded loop was easy to get out of sync when adding new flags or tweaking error handling. Move the sequencing into a single helper so that all call sites share the same ordering and checks Signed-off-by: Mark Bloch Reviewed-by: Shay Drori Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/lag/lag.c | 44 +++++++++++-------- .../net/ethernet/mellanox/mlx5/core/lag/lag.h | 1 + .../ethernet/mellanox/mlx5/core/lag/mpesw.c | 12 ++--- 3 files changed, 31 insertions(+), 26 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/lag/lag.c index 449e4bd86c06..c402a8463081 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c @@ -1093,6 +1093,27 @@ void mlx5_lag_remove_devices(struct mlx5_lag *ldev) } } =20 +int mlx5_lag_reload_ib_reps(struct mlx5_lag *ldev, u32 flags) +{ + struct lag_func *pf; + int ret; + int i; + + mlx5_ldev_for_each(i, 0, ldev) { + pf =3D mlx5_lag_pf(ldev, i); + if (!(pf->dev->priv.flags & flags)) { + struct mlx5_eswitch *esw; + + esw =3D pf->dev->priv.eswitch; + ret =3D mlx5_eswitch_reload_ib_reps(esw); + if (ret) + return ret; + } + } + + return 0; +} + void mlx5_disable_lag(struct mlx5_lag *ldev) { bool shared_fdb =3D test_bit(MLX5_LAG_MODE_FLAG_SHARED_FDB, &ldev->mode_f= lags); @@ -1130,9 +1151,7 @@ void mlx5_disable_lag(struct mlx5_lag *ldev) mlx5_lag_add_devices(ldev); =20 if (shared_fdb) - mlx5_ldev_for_each(i, 0, ldev) - if (!(mlx5_lag_pf(ldev, i)->dev->priv.flags & MLX5_PRIV_FLAGS_DISABLE_A= LL_ADEV)) - mlx5_eswitch_reload_ib_reps(mlx5_lag_pf(ldev, i)->dev->priv.eswitch); + mlx5_lag_reload_ib_reps(ldev, MLX5_PRIV_FLAGS_DISABLE_ALL_ADEV); } =20 bool mlx5_lag_shared_fdb_supported(struct mlx5_lag *ldev) @@ -1388,10 +1407,8 @@ static void mlx5_do_bond(struct mlx5_lag *ldev) if (err) { if (shared_fdb || roce_lag) mlx5_lag_add_devices(ldev); - if (shared_fdb) { - mlx5_ldev_for_each(i, 0, ldev) - mlx5_eswitch_reload_ib_reps(mlx5_lag_pf(ldev, i)->dev->priv.eswitch); - } + if (shared_fdb) + mlx5_lag_reload_ib_reps(ldev, 0); =20 return; } @@ -1409,24 +1426,15 @@ static void mlx5_do_bond(struct mlx5_lag *ldev) mlx5_nic_vport_enable_roce(dev); } } else if (shared_fdb) { - int i; - dev0->priv.flags &=3D ~MLX5_PRIV_FLAGS_DISABLE_IB_ADEV; mlx5_rescan_drivers_locked(dev0); - - mlx5_ldev_for_each(i, 0, ldev) { - err =3D mlx5_eswitch_reload_ib_reps(mlx5_lag_pf(ldev, i)->dev->priv.es= witch); - if (err) - break; - } - + err =3D mlx5_lag_reload_ib_reps(ldev, 0); if (err) { dev0->priv.flags |=3D MLX5_PRIV_FLAGS_DISABLE_IB_ADEV; mlx5_rescan_drivers_locked(dev0); mlx5_deactivate_lag(ldev); mlx5_lag_add_devices(ldev); - mlx5_ldev_for_each(i, 0, ldev) - mlx5_eswitch_reload_ib_reps(mlx5_lag_pf(ldev, i)->dev->priv.eswitch); + mlx5_lag_reload_ib_reps(ldev, 0); mlx5_core_err(dev0, "Failed to enable lag\n"); return; } diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.h b/drivers/ne= t/ethernet/mellanox/mlx5/core/lag/lag.h index 6c911374f409..db561e306fc7 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.h @@ -199,4 +199,5 @@ int mlx5_get_next_ldev_func(struct mlx5_lag *ldev, int = start_idx); int mlx5_lag_get_dev_index_by_seq(struct mlx5_lag *ldev, int seq); int mlx5_lag_num_devs(struct mlx5_lag *ldev); int mlx5_lag_num_netdevs(struct mlx5_lag *ldev); +int mlx5_lag_reload_ib_reps(struct mlx5_lag *ldev, u32 flags); #endif /* __MLX5_LAG_H__ */ diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lag/mpesw.c b/drivers/= net/ethernet/mellanox/mlx5/core/lag/mpesw.c index 5eea12a6887a..4d68e3092a56 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lag/mpesw.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lag/mpesw.c @@ -70,7 +70,6 @@ static int mlx5_lag_enable_mpesw(struct mlx5_lag *ldev) int idx =3D mlx5_lag_get_dev_index_by_seq(ldev, MLX5_LAG_P1); struct mlx5_core_dev *dev0; int err; - int i; =20 if (ldev->mode =3D=3D MLX5_LAG_MODE_MPESW) return 0; @@ -103,11 +102,9 @@ static int mlx5_lag_enable_mpesw(struct mlx5_lag *ldev) =20 dev0->priv.flags &=3D ~MLX5_PRIV_FLAGS_DISABLE_IB_ADEV; mlx5_rescan_drivers_locked(dev0); - mlx5_ldev_for_each(i, 0, ldev) { - err =3D mlx5_eswitch_reload_ib_reps(mlx5_lag_pf(ldev, i)->dev->priv.eswi= tch); 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Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , Shay Drory , Or Har-Toov , Edward Srouji , Maher Sanalla , Simon Horman , Moshe Shemesh , Kees Cook , Patrisious Haddad , Gerd Bayer , Parav Pandit , Cosmin Ratiu , Carolina Jubran , , , , Gal Pressman , Dragos Tatulea Subject: [PATCH net-next 2/7] net/mlx5: E-Switch, move work queue generation counter Date: Thu, 9 Apr 2026 14:55:45 +0300 Message-ID: <20260409115550.156419-3-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260409115550.156419-1-tariqt@nvidia.com> References: <20260409115550.156419-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF00000144:EE_|DS0PR12MB6439:EE_ X-MS-Office365-Filtering-Correlation-Id: d897aa55-fde3-4254-d274-08de962f1ad7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|36860700016|7416014|376014|18002099003|56012099003|22082099003; X-Microsoft-Antispam-Message-Info: AJSyCSpAuAxUPgWU5HED8P1zyq61JlmQUReQsT0HpYEwOXVlE1uRLuVN9PGEq6N/Noy33ZDSn8jjZQbsxRgtzuxlJZ5NSwffzPJXBFRlrxn+kJ4tkunvLdtfFXS71jTmQ4bY12ICQFe0e4r0BZNHgSDcZJ6AGurTOQTpVHf8z4hJ0LECCbY4Sw+zAKObwOCWtHBEynTrbmm5GZasscbNoH7B8WaYOr6k/DIBwuPlAT/0f51B9PNxc0AF18dobWN35672ZuBgMcXj3cLHo3xlNeRpwX3D/pYCPYrT7J7LB82LMh/0IBb8LgyLb/FgKbTL6iaTOINlpjQB/Osx5swUrRzaIuG/KB0TsWCITqMSA5+0Sx4LmxptwZrima8/cq2wn+uGbipebElkEJux0aXoQpRP0o7YdGDHM2sku2M2hKSv7RK5kY5JGgG8PfHLnq42b9uoWrzCIPa3eg6nwlRdO3Z8VD0O59r8UtPzOHsTY/fo2pH9lM3RXlqrh6M96kBxA7rsmMLWz4zzhF1e6XEdfAEnU9zGle+/kmwIqbMgq1+yVxG5exG4RxyfS1awYgf/qIAbStlXOax/4uAsFt2iNTBBKGvTluVl+kZJ5MexzzNApWXepahdkrM/QMiqFZPzDdZw+TJIx++aYncZO+pi+9v6OvFNgoPIeYbm4A28Pp9oYnSd6alvs+9RloWoput1gy4y0XFNE1I6AtU+894BOaQUFix1Dbw3CQEJeXAF1nl5Jz+aW7kFknyqE20tvCELlDxnLSE4z3regCYWGlBmKw== X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(36860700016)(7416014)(376014)(18002099003)(56012099003)(22082099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: qBDVQxxANm7hmWfbIu6EcAmpYbe+LaFFWTPTRKTAy8jZzPnYmMA7aKQjZ8CjqbIHGJbw9ysMFAevs7ZCNhf2Llhp0tL70bI6IormzVHTexvNiwRheExnHeDdoCi7wUx3oeAw11/qNk5ZEQp/WfhuNlgot2rLwWLdodTwRjFBgenzwcgcjUGNszRIfoJTYqRrdl1iIR9f87btavVRHCRg4YYVpWNB+11k13HweeKeiNFMlZdssWLWuVRUQuZx+LHFOcrEA4NRXm1lT5t+dHufCJDTSHzSsnKc+rmyWwT8mpP+UMrIJF3vS5k6Mtwl8rDI+wau6QV3rFlG3PSo2e309rOg48rMZ/R/JcNrwwFMc3Bz0BArSYrpgrxumnafNuTgA9Gl92EYnSwgULUy/tbgRK+P5CagtN+piIe/TvMOmxhu9JlbnheMV7O31Vz84fXm X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Apr 2026 11:56:58.9579 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d897aa55-fde3-4254-d274-08de962f1ad7 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF00000144.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB6439 Content-Type: text/plain; charset="utf-8" From: Mark Bloch The generation counter in mlx5_esw_functions is used to detect stale work items on the E-Switch work queue. Move it from mlx5_esw_functions to the top-level mlx5_eswitch struct so it can guard all work types, not just function-change events. This is a mechanical refactor: no behavioral change. Signed-off-by: Mark Bloch Reviewed-by: Cosmin Ratiu Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/eswitch.c | 3 ++- drivers/net/ethernet/mellanox/mlx5/core/eswitch.h | 2 +- drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c | 4 ++-- 3 files changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/eswitch.c index 123c96716a54..1986d4d0e886 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c @@ -1075,7 +1075,7 @@ static void mlx5_eswitch_event_handler_unregister(str= uct mlx5_eswitch *esw) if (esw->mode =3D=3D MLX5_ESWITCH_OFFLOADS && mlx5_eswitch_is_funcs_handler(esw->dev)) { mlx5_eq_notifier_unregister(esw->dev, &esw->esw_funcs.nb); - atomic_inc(&esw->esw_funcs.generation); + atomic_inc(&esw->generation); } } =20 @@ -2072,6 +2072,7 @@ int mlx5_eswitch_init(struct mlx5_core_dev *dev) mutex_init(&esw->state_lock); init_rwsem(&esw->mode_lock); refcount_set(&esw->qos.refcnt, 0); + atomic_set(&esw->generation, 0); =20 esw->enabled_vports =3D 0; esw->offloads.inline_mode =3D MLX5_INLINE_MODE_NONE; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h b/drivers/ne= t/ethernet/mellanox/mlx5/core/eswitch.h index 5128f5020dae..0c3d2bdebf8c 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h @@ -340,7 +340,6 @@ struct mlx5_host_work { =20 struct mlx5_esw_functions { struct mlx5_nb nb; - atomic_t generation; bool host_funcs_disabled; u16 num_vfs; u16 num_ec_vfs; @@ -410,6 +409,7 @@ struct mlx5_eswitch { struct mlx5_devcom_comp_dev *devcom; u16 enabled_ipsec_vf_count; bool eswitch_operation_in_progress; + atomic_t generation; }; =20 void esw_offloads_disable(struct mlx5_eswitch *esw); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c b/d= rivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c index a078d06f4567..b2e7294d3a5c 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c @@ -3667,7 +3667,7 @@ esw_vfs_changed_event_handler(struct mlx5_eswitch *es= w, int work_gen, devl_lock(devlink); =20 /* Stale work from one or more mode changes ago. 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Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , Shay Drory , Or Har-Toov , Edward Srouji , Maher Sanalla , Simon Horman , Moshe Shemesh , Kees Cook , Patrisious Haddad , Gerd Bayer , Parav Pandit , Cosmin Ratiu , Carolina Jubran , , , , Gal Pressman , Dragos Tatulea Subject: [PATCH net-next 3/7] net/mlx5: E-Switch, introduce generic work queue dispatch helper Date: Thu, 9 Apr 2026 14:55:46 +0300 Message-ID: <20260409115550.156419-4-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260409115550.156419-1-tariqt@nvidia.com> References: <20260409115550.156419-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF00000149:EE_|DS7PR12MB6008:EE_ X-MS-Office365-Filtering-Correlation-Id: 49680846-1847-4ef2-c4b1-08de962f1d91 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|7416014|376014|36860700016|56012099003|22082099003|18002099003; X-Microsoft-Antispam-Message-Info: UEw0WwxxAbf8H56PkdLepsURhZMsKD5q1Z78gSYOudmI9PhKJuAKAzU/MUBGwmlA32bKkfUMgN+tL/DtCc78O8Oe77xSsGArcbVu0wxjZKjI/yC5ad40mzii/2pXx1PTbSnimkxbKJSg9NLz7ZBr+o8Qx99Nqe7VF5kIq6YCPYYkVFxNf+wOGo0QhotiJzmSmWtDGih+hgDmkpYHVr/mc/CY7+aUW/AKT3vcskr3433GIrmcmf4NoryIeP2OM93DglRvXZw0KeQn/XxhI8Wb06STIRwwyR7eXmvWObNbZ1XgzdFBOCFgED3wbtQGAy5pjHJhx+FRzqoFQcPt356tzPeaMefnLS5AszPLb/hnpJFnG1Sq4OLHRVPFO70qOS9Ki3gpGzXPl4udjDBtkWNmXWyXFRCwSiSY+NcI8O7GV6YMP3VhZzD+QeTJsRORf0Zgstvq/WVLdaDSHCNxBlg+G2LileNkP4+T51J8eaB/5cIZpGGzM6bMYTBSFK5M1hgXj0WGDMqiTtS1I7ZG8qVwCyUHAi0BrmaWeRQU0XW6ZsYTX1udT+TBeUXZoex4Hozx8rN4mYRkrhRB2XPBBSqfJQUYqeO54yIjLfDs12JamF6mtmm1Tb/NDWSMr1YNVMa05J43ra/3FtF6Sj8c//gE0jDjyguvZzW+McO64GSGHPkadLPMPTOheWfBrLIT0LYesfGS7/H80RBBmuT3+bRPDnDKkEhAY9rwnmjpPN5pLRm3u5OwdRRi4NpoWiYCjhf6SgkKej8d5JR/xr4K8tCr+g== X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(7416014)(376014)(36860700016)(56012099003)(22082099003)(18002099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: g2HvKVZ3ulPqv1qFmNjALkvz5N9/0ioRgszClK1LzJpYKRYPdUQT9Ms4LY1gAu5NHkl2ajW+xDvZKrww4IKYAyuMno3g/FhQX2soKLA7h8W2DxVMP2yBQmZP/7ruiLI6i3D2pEIqgt6WYW3pmaBmmTHe8wezXJUPissYXuFW18Q/5aWym2jZUt7XPLAgPhn3wiVBUCw3MyfyZtayzy+QdkXtbJ+Ze2KiBWgRPPqHC63lEEUrT1u0iYRCTEfSLmBaS4RS5sDwobaPX5ps9r6HVUG0hQToX/73abvFiA6LdbpHiG4yhSSFpul/XRmtKKxORxBLUrLrK5C/ZzO7hgH2wQTk0fFHeEABZj/KUP7jE7HvuPRHIKKCxCki1WV102o/qX36CI4gzYXu+NMEC6fySfLrwTJX/gMG0t7KeEljjomgPrE5Zsbqf28IdfV1tZPL X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Apr 2026 11:57:03.5615 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 49680846-1847-4ef2-c4b1-08de962f1d91 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF00000149.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB6008 Content-Type: text/plain; charset="utf-8" From: Mark Bloch Each E-Switch work item requires the same boilerplate: acquire the devlink lock, check whether the work is stale, dispatch to the appropriate handler, and release the lock. Factor this out. Add a func callback to mlx5_host_work so the generic handler esw_wq_handler() can dispatch to the right function without duplicating locking logic. Introduce mlx5_esw_add_work() as the single enqueue point: it stamps the work item with the current generation counter and queues it onto the E-Switch work queue. Refactor esw_vfs_changed_event_handler() to match the new contract: it no longer receives work_gen or out as parameters. It queries mlx5_esw_query_functions() itself and owns the kvfree() of the result. The devlink lock is acquired and released by esw_wq_handler() before dispatching, so the handler runs with the lock already held. Update mlx5_esw_funcs_changed_handler() to use mlx5_esw_add_work(). Signed-off-by: Mark Bloch Reviewed-by: Cosmin Ratiu Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/eswitch.h | 1 + .../mellanox/mlx5/core/eswitch_offloads.c | 77 +++++++++++-------- 2 files changed, 45 insertions(+), 33 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h b/drivers/ne= t/ethernet/mellanox/mlx5/core/eswitch.h index 0c3d2bdebf8c..e3ab8a30c174 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h @@ -336,6 +336,7 @@ struct mlx5_host_work { struct work_struct work; struct mlx5_eswitch *esw; int work_gen; + void (*func)(struct mlx5_eswitch *esw); }; =20 struct mlx5_esw_functions { diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c b/d= rivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c index b2e7294d3a5c..23af5a12dc07 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c @@ -3655,20 +3655,15 @@ static void esw_offloads_steering_cleanup(struct ml= x5_eswitch *esw) mutex_destroy(&esw->fdb_table.offloads.vports.lock); } =20 -static void -esw_vfs_changed_event_handler(struct mlx5_eswitch *esw, int work_gen, - const u32 *out) +static void esw_vfs_changed_event_handler(struct mlx5_eswitch *esw) { - struct devlink *devlink; bool host_pf_disabled; u16 new_num_vfs; + const u32 *out; =20 - devlink =3D priv_to_devlink(esw->dev); - devl_lock(devlink); - - /* Stale work from one or more mode changes ago. Bail out. */ - if (work_gen !=3D atomic_read(&esw->generation)) - goto unlock; + out =3D mlx5_esw_query_functions(esw->dev); + if (IS_ERR(out)) + return; =20 new_num_vfs =3D MLX5_GET(query_esw_functions_out, out, host_params_context.host_num_of_vfs); @@ -3676,7 +3671,7 @@ esw_vfs_changed_event_handler(struct mlx5_eswitch *es= w, int work_gen, host_params_context.host_pf_disabled); =20 if (new_num_vfs =3D=3D esw->esw_funcs.num_vfs || host_pf_disabled) - goto unlock; + goto free; =20 /* Number of VFs can only change from "0 to x" or "x to 0". */ if (esw->esw_funcs.num_vfs > 0) { @@ -3686,54 +3681,70 @@ esw_vfs_changed_event_handler(struct mlx5_eswitch *= esw, int work_gen, =20 err =3D mlx5_eswitch_load_vf_vports(esw, new_num_vfs, MLX5_VPORT_UC_ADDR_CHANGE); - if (err) { - devl_unlock(devlink); - return; - } + if (err) + goto free; } esw->esw_funcs.num_vfs =3D new_num_vfs; -unlock: - devl_unlock(devlink); +free: + kvfree(out); } =20 -static void esw_functions_changed_event_handler(struct work_struct *work) +static void esw_wq_handler(struct work_struct *work) { struct mlx5_host_work *host_work; struct mlx5_eswitch *esw; - const u32 *out; + struct devlink *devlink; =20 host_work =3D container_of(work, struct mlx5_host_work, work); esw =3D host_work->esw; + devlink =3D priv_to_devlink(esw->dev); =20 - out =3D mlx5_esw_query_functions(esw->dev); - if (IS_ERR(out)) - goto out; + devl_lock(devlink); =20 - esw_vfs_changed_event_handler(esw, host_work->work_gen, out); - kvfree(out); -out: + /* Stale work from one or more mode changes ago. Bail out. */ + if (host_work->work_gen !=3D atomic_read(&esw->generation)) + goto unlock; + + host_work->func(esw); + +unlock: + devl_unlock(devlink); kfree(host_work); } =20 -int mlx5_esw_funcs_changed_handler(struct notifier_block *nb, unsigned lon= g type, void *data) +static int mlx5_esw_add_work(struct mlx5_eswitch *esw, + void (*func)(struct mlx5_eswitch *esw)) { - struct mlx5_esw_functions *esw_funcs; struct mlx5_host_work *host_work; - struct mlx5_eswitch *esw; =20 host_work =3D kzalloc_obj(*host_work, GFP_ATOMIC); if (!host_work) - return NOTIFY_DONE; - - esw_funcs =3D mlx5_nb_cof(nb, struct mlx5_esw_functions, nb); - esw =3D container_of(esw_funcs, struct mlx5_eswitch, esw_funcs); + return -ENOMEM; =20 host_work->esw =3D esw; host_work->work_gen =3D atomic_read(&esw->generation); =20 - INIT_WORK(&host_work->work, esw_functions_changed_event_handler); + host_work->func =3D func; + INIT_WORK(&host_work->work, esw_wq_handler); queue_work(esw->work_queue, &host_work->work); =20 + return 0; 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Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , Shay Drory , Or Har-Toov , Edward Srouji , Maher Sanalla , Simon Horman , Moshe Shemesh , Kees Cook , Patrisious Haddad , Gerd Bayer , Parav Pandit , Cosmin Ratiu , Carolina Jubran , , , , Gal Pressman , Dragos Tatulea Subject: [PATCH net-next 4/7] net/mlx5: E-Switch, fix deadlock between devlink lock and esw->wq Date: Thu, 9 Apr 2026 14:55:47 +0300 Message-ID: <20260409115550.156419-5-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260409115550.156419-1-tariqt@nvidia.com> References: <20260409115550.156419-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF00000143:EE_|IA1PR12MB8335:EE_ X-MS-Office365-Filtering-Correlation-Id: f529d793-ef52-44ad-0045-08de962f2016 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|7416014|82310400026|36860700016|18002099003|22082099003|56012099003; X-Microsoft-Antispam-Message-Info: r1X6TRiPHkGidTTVdUnqHEgH08tCFpsP94WE0yRoSxDUg32YvqLYn8iUUGptjrFh/9nP4vFtkoOtj1vgfJkjlZ/iwCPfqrlWvmeCanLgsAtkZGYJ5YLUvtPRjad0SU68Kk8c+uBh7mJKySZEc5dZ3c2f1xDNmzjJFqiP9Fl9Ip7JbbI4rTEit3P5rxNBvvmOhxcpFZ+LJoHlwI/WU9iuMnCnM1HBxiqtHK1kO06qJ/OkIoDOnsHlpxG0tNQzTM5rTXp47qGq4v7P4BkB8TndlklrncerTrAnr/C16q0zJfyYujelaE9HwOuGb7pXAXAP3vEGWKMAjUaVcj+ApttkkPUQZXxxTycVIAvu4T/UZYoDuZOnSDTfcTxS7LORLlW7TqSzdPJnu9twIkUozIF5m27lytcN14JbCZinRYBWvrzRAbvWm1Q1HwmKKo1hqVNKafoZvw6hfYUxIz0ZaE0zSpKVXU7KJ8ic9fk8XYjwzqtNSubWTPK4pIdBgdwLf0/BkcmByC4YEfKAS6YRQygG7BAJqQ/QGlcOfMgP0H2NWLOkpOtv/2ExSQ9o9SSvTdTA92Fv6oo+cvC0gaaFZVavPzq6jxBs+7/7JG8Yet7kg82u0L2AGqDPGCrPL8wRW1bxpigCzx03BjIzm4gOY0et6k6PBFyF7tZ0Ch43oKgcrCflf8FTBaNdItLxyqfJAu/LFfnxGS91cPdzF8Ocgi6pt70fLPozzQHXA0u2ccWGiJ6DtJVoU1ix22GXpVqSOpGzepFS9zQWk56itfhBFMo6Qg== X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(376014)(7416014)(82310400026)(36860700016)(18002099003)(22082099003)(56012099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: skcjyuVeU9HjynhhtYPnqycrXyHSVyNGJgCqk5AvuyLk3CLmHeleOQc1ac32msloiDDgaS7GwlLw9JLSGPJv1YMuxq/pWGLisRhn7af8BKQ2E3a5Rv5HpEfkBw6gca73rJUJDVE+dI+T1mag/rTx78vObT/Uw58AaoQ56DFmy3cN+Gnka7dOfGYv/K9nt99K6ATv15vTY3RWaw461q/rhu10iAdZGoP8ras++jVXI7K/5YD2oeLQ+fU8xXMOgDHkc5MGz/ALWQs0oGcR2QsizGbb05KLazwP5kRCBJ37uDva72qr9vWxigdYkFsiR01Y1V7mA2WieMvzcVjLeTrUNtQMmzKVO3z4ZkXPvNTWUykiYbPxaHbVmtqDEy2TxwLFiwakscXwSzu+pxLxNuJtlBsme0D/NjDVjCmiTkghZ+l2FHT/lTboeirXXW9Hw4HT X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Apr 2026 11:57:07.7507 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f529d793-ef52-44ad-0045-08de962f2016 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF00000143.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB8335 Content-Type: text/plain; charset="utf-8" From: Mark Bloch mlx5_eswitch_cleanup() calls destroy_workqueue() while holding the devlink lock (via mlx5_uninit_one()). Workers on the queue call devl_lock() before checking whether their work is stale, which deadlocks: mlx5_uninit_one (holds devlink lock) mlx5_eswitch_cleanup() destroy_workqueue() <- waits for workers to finish worker: devl_lock() <- blocked on devlink lock held above The same pattern affects mlx5_devlink_eswitch_mode_set(), which can drain the queue while holding devlink lock. Fix by making esw_wq_handler() check the generation counter BEFORE acquiring the devlink lock, using devl_trylock() in a loop with cond_resched(). If the work is stale the handler exits immediately without ever contending for the lock. To guarantee stale detection, increment the generation counter at every E-Switch operation boundary: - mlx5_eswitch_cleanup(): increment before destroy_workqueue() so any in-flight worker sees stale and drains without blocking. Also move mlx5_esw_qos_cleanup() to after destroy_workqueue() so it runs only once all workers have finished. - mlx5_devlink_eswitch_mode_set(): increment before starting the mode change so workers from the previous mode are discarded. - mlx5_eswitch_disable(): increment so workers queued before the disable see stale and exit. - mlx5_eswitch_enable() and mlx5_eswitch_disable_sriov(): increment so in-flight work against an old VF count or mode is discarded when these operations begin. Remove the conditional atomic_inc() in mlx5_eswitch_event_handler_unregister(); the mlx5_eswitch_disable() increment now covers it unconditionally and earlier in the call chain. Signed-off-by: Mark Bloch Reviewed-by: Cosmin Ratiu Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/eswitch.c | 11 +++++++---- .../mellanox/mlx5/core/eswitch_offloads.c | 18 +++++++++++++++++- 2 files changed, 24 insertions(+), 5 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/eswitch.c index 1986d4d0e886..d315484390c8 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c @@ -1073,10 +1073,8 @@ static void mlx5_eswitch_event_handler_register(stru= ct mlx5_eswitch *esw) static void mlx5_eswitch_event_handler_unregister(struct mlx5_eswitch *esw) { if (esw->mode =3D=3D MLX5_ESWITCH_OFFLOADS && - mlx5_eswitch_is_funcs_handler(esw->dev)) { + mlx5_eswitch_is_funcs_handler(esw->dev)) mlx5_eq_notifier_unregister(esw->dev, &esw->esw_funcs.nb); - atomic_inc(&esw->generation); - } } =20 static void mlx5_eswitch_clear_vf_vports_info(struct mlx5_eswitch *esw) @@ -1701,6 +1699,8 @@ int mlx5_eswitch_enable(struct mlx5_eswitch *esw, int= num_vfs) if (toggle_lag) mlx5_lag_disable_change(esw->dev); =20 + atomic_inc(&esw->generation); + if (!mlx5_esw_is_fdb_created(esw)) { ret =3D mlx5_eswitch_enable_locked(esw, num_vfs); } else { @@ -1745,6 +1745,7 @@ void mlx5_eswitch_disable_sriov(struct mlx5_eswitch *= esw, bool clear_vf) esw_info(esw->dev, "Unload vfs: mode(%s), nvfs(%d), necvfs(%d), active vp= orts(%d)\n", esw->mode =3D=3D MLX5_ESWITCH_LEGACY ? "LEGACY" : "OFFLOADS", esw->esw_funcs.num_vfs, esw->esw_funcs.num_ec_vfs, esw->enabled_vports); + atomic_inc(&esw->generation); =20 if (!mlx5_core_is_ecpf(esw->dev)) { mlx5_eswitch_unload_vf_vports(esw, esw->esw_funcs.num_vfs); @@ -1809,6 +1810,7 @@ void mlx5_eswitch_disable(struct mlx5_eswitch *esw) return; =20 devl_assert_locked(priv_to_devlink(esw->dev)); + atomic_inc(&esw->generation); mlx5_lag_disable_change(esw->dev); mlx5_eswitch_disable_locked(esw); esw->mode =3D MLX5_ESWITCH_LEGACY; @@ -2110,8 +2112,9 @@ void mlx5_eswitch_cleanup(struct mlx5_eswitch *esw) =20 esw_info(esw->dev, "cleanup\n"); =20 - mlx5_esw_qos_cleanup(esw); + atomic_inc(&esw->generation); destroy_workqueue(esw->work_queue); + mlx5_esw_qos_cleanup(esw); WARN_ON(refcount_read(&esw->qos.refcnt)); mutex_destroy(&esw->state_lock); WARN_ON(!xa_empty(&esw->offloads.vhca_map)); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c b/d= rivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c index 23af5a12dc07..988595e1b425 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c @@ -3699,7 +3699,20 @@ static void esw_wq_handler(struct work_struct *work) esw =3D host_work->esw; devlink =3D priv_to_devlink(esw->dev); =20 - devl_lock(devlink); + /* Check for stale work BEFORE acquiring devlink lock. + * mlx5_eswitch_cleanup() increments the generation counter + * before destroy_workqueue() while holding devlink lock, + * so acquiring devlink lock here would deadlock. + */ + for (;;) { + if (host_work->work_gen !=3D atomic_read(&esw->generation)) + goto free; + + if (devl_trylock(devlink)) + break; + + cond_resched(); + } =20 /* Stale work from one or more mode changes ago. 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Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , Shay Drory , Or Har-Toov , Edward Srouji , Maher Sanalla , Simon Horman , Moshe Shemesh , Kees Cook , Patrisious Haddad , Gerd Bayer , Parav Pandit , Cosmin Ratiu , Carolina Jubran , , , , Gal Pressman , Dragos Tatulea Subject: [PATCH net-next 5/7] net/mlx5: E-Switch, block representors during reconfiguration Date: Thu, 9 Apr 2026 14:55:48 +0300 Message-ID: <20260409115550.156419-6-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260409115550.156419-1-tariqt@nvidia.com> References: <20260409115550.156419-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF0000231D:EE_|SJ2PR12MB7824:EE_ X-MS-Office365-Filtering-Correlation-Id: 7416c3d3-5277-41b5-0b43-08de962f2191 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700016|1800799024|7416014|376014|22082099003|18002099003|56012099003; X-Microsoft-Antispam-Message-Info: 2/vxrjPhOxba1XM/Cllxzl6eFnJF9LTGurv44TP8ShtOPI+uKynXWquvK9SNit63s4JfI3BA9+loPkdN3Daxdm+vV53DerJ4+ApwwRYNQm7fG1BRkh3fWCSyyt4YAsPP9Rbt1nHFUSsv0yvA8LhMguf7cVfHpX1NNZfcFWBabW+iL6JDIpcdl18ueGdVONg9mJhPznT4Q3vl92GNzfE6LieU/GAXEiGQGcuPDkBopIdSOcbGtrTABEkDvkCr+8liCzVwPFT4h7TVZAS/2weVb7J2/uDAGR1PCbzdACIV4ORPVC1oNLDghTeZ/11ZUPkx3Wyh5vfkyrO9O3yFIUYf4xYNJr+hdFAYW1s3zuHKzzkKxshyfA52+vbxKm6drKewTr4cyraJ1aYIwXHNq3BjpesQHwhqC91Bjs+6mAuvLJl05e878jIDP6ZQQ/AYzo6YK3u986kCHOgn1xV7cIPynrU7IE6WVKGLfy9ebkW4hK9BxSYsS2kBac0lsmZ3NWgNX3kiu7VSzMnoOadPG7ZzqKcQR3UdBF7Bu6OSJCPcqc4xZGKKR523VMCZlH/9lJQBx81f/VabY2wLjLRui2xUy8Uzql5J9JsEf04YSGIEIXk/TT3ulaW3UcOmFweOnJ9YNuRBe6Q4zz1mhRJtECpyG4glDfO9LfhVAlNm28H7WHoblKckSvzRbx7AQMOcE7J15h3ElXDGmR5tyzuBQ993Z3gg6pBBRxW4lp52kipyTHso5Am4f4Q9WXbSaVKWO7frO4TtFe7Txd910x4hSXx/nA== X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(36860700016)(1800799024)(7416014)(376014)(22082099003)(18002099003)(56012099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: mv5M7c5DcI9zuFUkSmQoPu8GJt9FKsuYR1kKmYfCYUCB1RYOn2UnTNSP7KIZgwf2Z4BQIyUFsaUsGaKco1ElhPXQ/gsRKMN94Ei0Se6HoIzrfE3ePIc1b4BQgSaS7NSyi7pAZea6UHiJsZBguyO3srXpjBL3EErHFMhAIs/THGvaDV2UobM5aLqcebAVVsyW3ZyPNEkwVzJ1yjihQ32J1IJKi23k7yz1lwkCkDycfUBunVxveWZlphsfBUKyntY8xRBrsDiycZJkGV7HhOPBiywsRc3bhm+1/c0fr5hxv7jyUZ3ViUls4LRKg3CZwZ5ubORnDFoCl4cq+p/PNg+aBH1OxtKZADTds4yuitJkSw2mbTvym0NK1dKEjo0VzRFM4P1lJUEo3l4oHp0nzE36ukrEeukW6I5ZKYHx61uvUl8GkAlzK0SKifQMGfMsGA1V X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Apr 2026 11:57:10.3753 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7416c3d3-5277-41b5-0b43-08de962f2191 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF0000231D.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB7824 Content-Type: text/plain; charset="utf-8" From: Mark Bloch Introduce a simple atomic block state via mlx5_esw_reps_block() and mlx5_esw_reps_unblock(). Internally, mlx5_esw_mark_reps() spins a cmpxchg between the UNBLOCKED and BLOCKED states. All E-Switch reconfiguration paths (mode set, enable, disable, VF/SF add/del, LAG reload) now bracket their work with this guard so representor changes won't race with the ongoing E-Switch update, yet we remain non-blocking and avoid new locks. A spinlock is out because the protected work can sleep (RDMA ops, devcom, netdev callbacks). A mutex won't work either: esw_mode_change() has to drop the guard mid-flight so mlx5_rescan_drivers_locked() can reload mlx5_ib, which calls back into mlx5_eswitch_register_vport_reps() on the same thread. Beyond that, any real lock would create an ABBA cycle: the LAG side holds the LAG lock when it calls reps_block(), and the mlx5_ib side holds RDMA locks when it calls register_vport_reps(), and those two subsystems talk to each other. The atomic CAS loop avoids all of this - no lock ordering, no sleep restrictions, and the owner can drop the guard and let a nested caller win the next transition before reclaiming it. With this infrastructure in place, downstream patches can safely tie representor load/unload to the mlx5_ib module's lifecycle. Loading mlx5_ib while the device is in switchdev mode has failed to bring up the IB representors for years; those patches will finally fix that. Signed-off-by: Mark Bloch Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/eswitch.c | 13 ++++ .../net/ethernet/mellanox/mlx5/core/eswitch.h | 6 ++ .../mellanox/mlx5/core/eswitch_offloads.c | 77 +++++++++++++++++-- .../net/ethernet/mellanox/mlx5/core/lag/lag.c | 2 + .../ethernet/mellanox/mlx5/core/sf/devlink.c | 5 ++ include/linux/mlx5/eswitch.h | 5 ++ 6 files changed, 100 insertions(+), 8 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/eswitch.c index d315484390c8..a7701c9d776a 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c @@ -1700,6 +1700,7 @@ int mlx5_eswitch_enable(struct mlx5_eswitch *esw, int= num_vfs) mlx5_lag_disable_change(esw->dev); =20 atomic_inc(&esw->generation); + mlx5_esw_reps_block(esw); =20 if (!mlx5_esw_is_fdb_created(esw)) { ret =3D mlx5_eswitch_enable_locked(esw, num_vfs); @@ -1723,6 +1724,8 @@ int mlx5_eswitch_enable(struct mlx5_eswitch *esw, int= num_vfs) } } =20 + mlx5_esw_reps_unblock(esw); + if (toggle_lag) mlx5_lag_enable_change(esw->dev); =20 @@ -1747,6 +1750,8 @@ void mlx5_eswitch_disable_sriov(struct mlx5_eswitch *= esw, bool clear_vf) esw->esw_funcs.num_vfs, esw->esw_funcs.num_ec_vfs, esw->enabled_vports); atomic_inc(&esw->generation); =20 + mlx5_esw_reps_block(esw); + if (!mlx5_core_is_ecpf(esw->dev)) { mlx5_eswitch_unload_vf_vports(esw, esw->esw_funcs.num_vfs); if (clear_vf) @@ -1757,6 +1762,8 @@ void mlx5_eswitch_disable_sriov(struct mlx5_eswitch *= esw, bool clear_vf) mlx5_eswitch_clear_ec_vf_vports_info(esw); } =20 + mlx5_esw_reps_unblock(esw); + if (esw->mode =3D=3D MLX5_ESWITCH_OFFLOADS) { struct devlink *devlink =3D priv_to_devlink(esw->dev); =20 @@ -1812,7 +1819,11 @@ void mlx5_eswitch_disable(struct mlx5_eswitch *esw) devl_assert_locked(priv_to_devlink(esw->dev)); atomic_inc(&esw->generation); mlx5_lag_disable_change(esw->dev); + + mlx5_esw_reps_block(esw); mlx5_eswitch_disable_locked(esw); + mlx5_esw_reps_unblock(esw); + esw->mode =3D MLX5_ESWITCH_LEGACY; mlx5_lag_enable_change(esw->dev); } @@ -2075,6 +2086,8 @@ int mlx5_eswitch_init(struct mlx5_core_dev *dev) init_rwsem(&esw->mode_lock); refcount_set(&esw->qos.refcnt, 0); atomic_set(&esw->generation, 0); + atomic_set(&esw->offloads.reps_conf_state, + MLX5_ESW_OFFLOADS_REP_TYPE_UNBLOCKED); =20 esw->enabled_vports =3D 0; esw->offloads.inline_mode =3D MLX5_INLINE_MODE_NONE; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h b/drivers/ne= t/ethernet/mellanox/mlx5/core/eswitch.h index e3ab8a30c174..256ac3ad37bc 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h @@ -315,6 +315,7 @@ struct mlx5_esw_offload { DECLARE_HASHTABLE(termtbl_tbl, 8); struct mutex termtbl_mutex; /* protects termtbl hash */ struct xarray vhca_map; + atomic_t reps_conf_state; const struct mlx5_eswitch_rep_ops *rep_ops[NUM_REP_TYPES]; u8 inline_mode; atomic64_t num_flows; @@ -949,6 +950,8 @@ mlx5_esw_lag_demux_fg_create(struct mlx5_eswitch *esw, struct mlx5_flow_handle * mlx5_esw_lag_demux_rule_create(struct mlx5_eswitch *esw, u16 vport_num, struct mlx5_flow_table *lag_ft); +void mlx5_esw_reps_block(struct mlx5_eswitch *esw); +void mlx5_esw_reps_unblock(struct mlx5_eswitch *esw); #else /* CONFIG_MLX5_ESWITCH */ /* eswitch API stubs */ static inline int mlx5_eswitch_init(struct mlx5_core_dev *dev) { return 0= ; } @@ -1026,6 +1029,9 @@ mlx5_esw_host_functions_enabled(const struct mlx5_cor= e_dev *dev) return true; } =20 +static inline void mlx5_esw_reps_block(struct mlx5_eswitch *esw) {} +static inline void mlx5_esw_reps_unblock(struct mlx5_eswitch *esw) {} + static inline bool mlx5_esw_vport_vhca_id(struct mlx5_eswitch *esw, u16 vportn, u16 *vhca_id) { diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c b/d= rivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c index 988595e1b425..4b626ffcfa8e 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c @@ -2410,23 +2410,56 @@ static int esw_create_restore_table(struct mlx5_esw= itch *esw) return err; } =20 +static void mlx5_esw_assert_reps_blocked(struct mlx5_eswitch *esw) +{ + if (atomic_read(&esw->offloads.reps_conf_state) =3D=3D + MLX5_ESW_OFFLOADS_REP_TYPE_BLOCKED) + return; + + esw_warn(esw->dev, "reps state machine violated: expected BLOCKED\n"); +} + +static void mlx5_esw_mark_reps(struct mlx5_eswitch *esw, + enum mlx5_esw_offloads_rep_type_state old, + enum mlx5_esw_offloads_rep_type_state new) +{ + atomic_t *reps_conf_state =3D &esw->offloads.reps_conf_state; + + do { + atomic_cond_read_relaxed(reps_conf_state, VAL =3D=3D old); + } while (atomic_cmpxchg(reps_conf_state, old, new) !=3D old); +} + +void mlx5_esw_reps_block(struct mlx5_eswitch *esw) +{ + mlx5_esw_mark_reps(esw, MLX5_ESW_OFFLOADS_REP_TYPE_UNBLOCKED, + MLX5_ESW_OFFLOADS_REP_TYPE_BLOCKED); +} + +void mlx5_esw_reps_unblock(struct mlx5_eswitch *esw) +{ + mlx5_esw_mark_reps(esw, MLX5_ESW_OFFLOADS_REP_TYPE_BLOCKED, + MLX5_ESW_OFFLOADS_REP_TYPE_UNBLOCKED); +} + static void esw_mode_change(struct mlx5_eswitch *esw, u16 mode) { + mlx5_esw_reps_unblock(esw); mlx5_devcom_comp_lock(esw->dev->priv.hca_devcom_comp); if (esw->dev->priv.flags & MLX5_PRIV_FLAGS_DISABLE_IB_ADEV || mlx5_core_mp_enabled(esw->dev)) { esw->mode =3D mode; - mlx5_rescan_drivers_locked(esw->dev); - mlx5_devcom_comp_unlock(esw->dev->priv.hca_devcom_comp); - return; + goto out; } =20 esw->dev->priv.flags |=3D MLX5_PRIV_FLAGS_DISABLE_IB_ADEV; mlx5_rescan_drivers_locked(esw->dev); esw->mode =3D mode; esw->dev->priv.flags &=3D ~MLX5_PRIV_FLAGS_DISABLE_IB_ADEV; +out: mlx5_rescan_drivers_locked(esw->dev); mlx5_devcom_comp_unlock(esw->dev->priv.hca_devcom_comp); + mlx5_esw_reps_block(esw); } =20 static void mlx5_esw_fdb_drop_destroy(struct mlx5_eswitch *esw) @@ -2761,6 +2794,8 @@ void esw_offloads_cleanup(struct mlx5_eswitch *esw) static int __esw_offloads_load_rep(struct mlx5_eswitch *esw, struct mlx5_eswitch_rep *rep, u8 rep_type) { + mlx5_esw_assert_reps_blocked(esw); + if (atomic_cmpxchg(&rep->rep_data[rep_type].state, REP_REGISTERED, REP_LOADED) =3D=3D REP_REGISTERED) return esw->offloads.rep_ops[rep_type]->load(esw->dev, rep); @@ -2771,6 +2806,8 @@ static int __esw_offloads_load_rep(struct mlx5_eswitc= h *esw, static void __esw_offloads_unload_rep(struct mlx5_eswitch *esw, struct mlx5_eswitch_rep *rep, u8 rep_type) { + mlx5_esw_assert_reps_blocked(esw); + if (atomic_cmpxchg(&rep->rep_data[rep_type].state, REP_LOADED, REP_REGISTERED) =3D=3D REP_LOADED) { if (rep_type =3D=3D REP_ETH) @@ -3673,6 +3710,7 @@ static void esw_vfs_changed_event_handler(struct mlx5= _eswitch *esw) if (new_num_vfs =3D=3D esw->esw_funcs.num_vfs || host_pf_disabled) goto free; =20 + mlx5_esw_reps_block(esw); /* Number of VFs can only change from "0 to x" or "x to 0". */ if (esw->esw_funcs.num_vfs > 0) { mlx5_eswitch_unload_vf_vports(esw, esw->esw_funcs.num_vfs); @@ -3682,9 +3720,11 @@ static void esw_vfs_changed_event_handler(struct mlx= 5_eswitch *esw) err =3D mlx5_eswitch_load_vf_vports(esw, new_num_vfs, MLX5_VPORT_UC_ADDR_CHANGE); if (err) - goto free; + goto unblock; } esw->esw_funcs.num_vfs =3D new_num_vfs; +unblock: + mlx5_esw_reps_unblock(esw); free: kvfree(out); } @@ -4164,6 +4204,7 @@ int mlx5_devlink_eswitch_mode_set(struct devlink *dev= link, u16 mode, goto unlock; } =20 + mlx5_esw_reps_block(esw); esw->eswitch_operation_in_progress =3D true; up_write(&esw->mode_lock); =20 @@ -4203,6 +4244,7 @@ int mlx5_devlink_eswitch_mode_set(struct devlink *dev= link, u16 mode, mlx5_devlink_netdev_netns_immutable_set(devlink, false); down_write(&esw->mode_lock); esw->eswitch_operation_in_progress =3D false; + mlx5_esw_reps_unblock(esw); unlock: mlx5_esw_unlock(esw); enable_lag: @@ -4474,9 +4516,10 @@ mlx5_eswitch_vport_has_rep(const struct mlx5_eswitch= *esw, u16 vport_num) return true; } =20 -void mlx5_eswitch_register_vport_reps(struct mlx5_eswitch *esw, - const struct mlx5_eswitch_rep_ops *ops, - u8 rep_type) +static void +mlx5_eswitch_register_vport_reps_blocked(struct mlx5_eswitch *esw, + const struct mlx5_eswitch_rep_ops *ops, + u8 rep_type) { struct mlx5_eswitch_rep_data *rep_data; struct mlx5_eswitch_rep *rep; @@ -4491,9 +4534,20 @@ void mlx5_eswitch_register_vport_reps(struct mlx5_es= witch *esw, } } } + +void mlx5_eswitch_register_vport_reps(struct mlx5_eswitch *esw, + const struct mlx5_eswitch_rep_ops *ops, + u8 rep_type) +{ + mlx5_esw_reps_block(esw); + mlx5_eswitch_register_vport_reps_blocked(esw, ops, rep_type); + mlx5_esw_reps_unblock(esw); +} EXPORT_SYMBOL(mlx5_eswitch_register_vport_reps); =20 -void mlx5_eswitch_unregister_vport_reps(struct mlx5_eswitch *esw, u8 rep_t= ype) +static void +mlx5_eswitch_unregister_vport_reps_blocked(struct mlx5_eswitch *esw, + u8 rep_type) { struct mlx5_eswitch_rep *rep; unsigned long i; @@ -4504,6 +4558,13 @@ void mlx5_eswitch_unregister_vport_reps(struct mlx5_= eswitch *esw, u8 rep_type) mlx5_esw_for_each_rep(esw, i, rep) atomic_set(&rep->rep_data[rep_type].state, REP_UNREGISTERED); } + +void mlx5_eswitch_unregister_vport_reps(struct mlx5_eswitch *esw, u8 rep_t= ype) +{ + mlx5_esw_reps_block(esw); + mlx5_eswitch_unregister_vport_reps_blocked(esw, rep_type); + mlx5_esw_reps_unblock(esw); +} EXPORT_SYMBOL(mlx5_eswitch_unregister_vport_reps); =20 void *mlx5_eswitch_get_uplink_priv(struct mlx5_eswitch *esw, u8 rep_type) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/lag/lag.c index c402a8463081..ff2e6f6caa0c 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c @@ -1105,7 +1105,9 @@ int mlx5_lag_reload_ib_reps(struct mlx5_lag *ldev, u3= 2 flags) struct mlx5_eswitch *esw; =20 esw =3D pf->dev->priv.eswitch; + mlx5_esw_reps_block(esw); ret =3D mlx5_eswitch_reload_ib_reps(esw); + mlx5_esw_reps_unblock(esw); if (ret) return ret; } diff --git a/drivers/net/ethernet/mellanox/mlx5/core/sf/devlink.c b/drivers= /net/ethernet/mellanox/mlx5/core/sf/devlink.c index 8503e532f423..2fc69897e35b 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/sf/devlink.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/sf/devlink.c @@ -245,8 +245,10 @@ static int mlx5_sf_add(struct mlx5_core_dev *dev, stru= ct mlx5_sf_table *table, if (IS_ERR(sf)) return PTR_ERR(sf); =20 + mlx5_esw_reps_block(esw); err =3D mlx5_eswitch_load_sf_vport(esw, sf->hw_fn_id, MLX5_VPORT_UC_ADDR_= CHANGE, &sf->dl_port, new_attr->controller, new_attr->sfnum); + mlx5_esw_reps_unblock(esw); if (err) goto esw_err; *dl_port =3D &sf->dl_port.dl_port; @@ -367,7 +369,10 @@ int mlx5_devlink_sf_port_del(struct devlink *devlink, struct mlx5_sf_table *table =3D dev->priv.sf_table; struct mlx5_sf *sf =3D mlx5_sf_by_dl_port(dl_port); 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Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , Shay Drory , Or Har-Toov , Edward Srouji , Maher Sanalla , Simon Horman , Moshe Shemesh , Kees Cook , Patrisious Haddad , Gerd Bayer , Parav Pandit , Cosmin Ratiu , Carolina Jubran , , , , Gal Pressman , Dragos Tatulea Subject: [PATCH net-next 6/7] net/mlx5: E-switch, load reps via work queue after registration Date: Thu, 9 Apr 2026 14:55:49 +0300 Message-ID: <20260409115550.156419-7-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260409115550.156419-1-tariqt@nvidia.com> References: <20260409115550.156419-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF00000148:EE_|MN0PR12MB6125:EE_ X-MS-Office365-Filtering-Correlation-Id: 4290c490-ced7-46cb-f777-08de962f29d0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|376014|7416014|36860700016|22082099003|56012099003|18002099003; X-Microsoft-Antispam-Message-Info: MOAB0KhHweDzXf634Cfn96U3UmvpAG4bfRt6xHAr8CV6ubQeiZ2B+7TB6V9OgdqAOJXvojgfHjnGa08bygKjKwjpDJtIncfEddnD8NSsTgajzMLwiokNhFyOUahUVeV4c8ugGiVkOa+jFN/GunR7MZigMO7/escZPOm6seSIB01llZY3gJ9FOAntK+5bhXDdkV+ZuZx+fe51qDagHsFzHaoHMjMPbe+OVmrMjUA7UmnuWPZfyrZFL16Ve6OXoppcgrdtqhWmhlEfR/JIsA+LWknPp/Yl79oCJmf8INtR9B0Axj/mmQSCZZ8XTsFGqMeQ7zw4m6MwFYJQEXXc6TN85bwE6pz4DQJM4YxnBoAFJq5MGy7siJp47EF0y6Qn0sslFo0itnMZrebKTczIoy4Tgz+AR9ifHwesi7KxDf7OBUkjQrGyVUhlhmexwXM4m2dpi2heiRTZKpIBJFVrbM9dAR84yyST9LUKfzg28+Zhy0/lckytGSrxK5wZx+vyy7mq9VFyMZL9yK+5UTH4Pe9ogZQLaqON/kopzFbec/sZTvoBLm7QmUDwQDLWhBj8wKgy8iTSa6ACORbgJhFKqOsRKERl/Ustgw2xdC7jz4+EHEC8hdVUgu1RxJGWg0DpXj24yyjmwfzl0/Vu1wwOlab4iiExRAUjy3fITqphUadx6elVEoVb1JNDU3W2PeBExEB9IGXPP9X6x+V37zqruUc70k9UxLheophyVGbXF+JxzEK2yWuodHLgu7sPhPJs+ieT6Joe4xAHYmxB4vO4hoNP6Q== X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(376014)(7416014)(36860700016)(22082099003)(56012099003)(18002099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: TKws6GUr6NXodz7HWeaYiRkPdQfESnEn+AZsFpiUk+sA4JOGCYvxn8B59GpNm2fGA8rcQ4LQPMEldBkSSPH+1ydjCJZKvnYmzdX9P+GbMfW99mtJ/9WA4nUPVKRSrylJy5r89w9L8rSbx5Xghny3rd72qVg/wvaqbp0P3cV08reL/l7mWpK0Fuwm1x65elAYgQepef3zn7tLqMurfGpB9ckvXJlbDBKC1i27ohvG++iegYO90bLIalQJ8qTIpXNhEDxhHxviZEhQeIkGLl/v1dShG5cAt3vk3gGvrZWU199CrT2Bm3SBbMg/sgLkp7EOVirB3yPi5YkfPKBtyYajU7wwdcES0bMUI119xYQD9//D796r5XQdxoOcqhrutz0l8UTNuoYovT4aUtyYLNT17MDHmcfFCWpjGfTUqNAM/6VFLLU+xv1l3yuh/trUHphX X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Apr 2026 11:57:24.0847 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4290c490-ced7-46cb-f777-08de962f29d0 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF00000148.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB6125 From: Mark Bloch mlx5_eswitch_register_vport_reps() merely sets the callbacks. The actual representor load/unload requires devlink locking and shouldn=E2=80=99t run = from the registration context. Queue a work that acquires the devlink lock, loads all relevant reps. This lets load happen where the needed locks can be taken. Signed-off-by: Mark Bloch Signed-off-by: Tariq Toukan --- .../mellanox/mlx5/core/eswitch_offloads.c | 34 +++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c b/d= rivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c index 4b626ffcfa8e..279490c0074c 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c @@ -4535,6 +4535,38 @@ mlx5_eswitch_register_vport_reps_blocked(struct mlx5= _eswitch *esw, } } =20 +static void mlx5_eswitch_reload_reps_blocked(struct mlx5_eswitch *esw) +{ + struct mlx5_vport *vport; + unsigned long i; + + if (esw->mode !=3D MLX5_ESWITCH_OFFLOADS) + return; + + if (mlx5_esw_offloads_rep_load(esw, MLX5_VPORT_UPLINK)) + return; + + mlx5_esw_for_each_vport(esw, i, vport) { + if (!vport) + continue; + if (!vport->enabled) + continue; + if (vport->vport =3D=3D MLX5_VPORT_UPLINK) + continue; + if (!mlx5_eswitch_vport_has_rep(esw, vport->vport)) + continue; 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Thu, 9 Apr 2026 04:57:13 -0700 Received: from drhqmail203.nvidia.com (10.126.190.182) by drhqmail203.nvidia.com (10.126.190.182) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 9 Apr 2026 04:57:12 -0700 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.126.190.182) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Thu, 9 Apr 2026 04:57:06 -0700 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , Shay Drory , Or Har-Toov , Edward Srouji , Maher Sanalla , Simon Horman , Moshe Shemesh , Kees Cook , Patrisious Haddad , Gerd Bayer , Parav Pandit , Cosmin Ratiu , Carolina Jubran , , , , Gal Pressman , Dragos Tatulea Subject: [PATCH net-next 7/7] net/mlx5: Add profile to auto-enable switchdev mode at device init Date: Thu, 9 Apr 2026 14:55:50 +0300 Message-ID: <20260409115550.156419-8-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260409115550.156419-1-tariqt@nvidia.com> References: <20260409115550.156419-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00002319:EE_|SA1PR12MB8967:EE_ X-MS-Office365-Filtering-Correlation-Id: 9f0a6bdf-ae38-425f-b55a-08de962f2c47 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700016|376014|7416014|1800799024|56012099003|22082099003|18002099003; X-Microsoft-Antispam-Message-Info: 37/R/MgZmBakGszC1A7D59A7VWx9cFQrRTKq/oq5yl50ELHgSWvHOVwHZKj8McbDKLtwwP+OyIoOnEeUSb02LiCp37rJ223pQXO/lqdP28czVJY29JOjV/6tZ5yYkGVKbukgaJq58ydvv3otfYxMqCE5ZIKHs5iKpK/lVXwvZlnP/HMh4J64XFATZ/j0A3S8ZIHEKgrzvMJGa6ASUX3tuhlTp89rgZYiwrw+EKcrExLM6M5+eEkdaV4flF+JdehEY0zI2Q8iTinQtc7O9nwxewCjO4lhHhI5LubRg+1KE2v0vCgSGH0hfnz5RReg8pnQXeud7X1WHHebOD+LFm5xmE2/3+Fzl+WPSWWzkRBxojKO1ncDzlFef6d5QXEiTDaSZmvndjyHbCOcdFiLxCeKDqwAZv5W6dMPXloe7ce/PKcTNX50KoB/iM5oIHce55MfzcU9cEgvVUb5iU1Jl4dv3feX+WSUMNS4DIJZiqm73GPUVzkQbCToOq4bHjn9l/bXJ4r0hMfsdhKUp6OQdXMob315QmOFMhI05gRA0fbniQmV6t5wsfyZWUOoK6vIys7uXcuaUzU3noiwYXe/U6QeJBGC500lmIKRwTM8kmzP6lOK7hRwrF02GYk83XrGSY9Szph8yNShyG8sro6gplRwt/7+I158lUPxqT2MPJmC88PzD2t6P6Ij+hnGNSTk4AKYiVwcD6xTER+alOW+18ulpL4SdhOFzOVb8pNGY8rtK6nqrFKAxcUy5e1CRogXj5lDrGgIaZjFKtPRl8Ag08iLkA== X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(36860700016)(376014)(7416014)(1800799024)(56012099003)(22082099003)(18002099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 8i4eO/VxYEWwjj9RcjJl+2/mi4YOXYqOsi0rI+zgFSrkKfOUFLLTOTmXzM79nyPkCaab3U9ZtcY1Rj4TvTTg9DhQBT0cujCTof2GcUJVVu5G6eTNe3YMdbBVe8drsTxL9nHdx+/6QOh+ITuS9G0mpDe8vnSguTJELj6SB5Kdv0grNBWpQ2fBX7tyZp1pn08QzP4eVWsDVlxEm3umSS6d9qhrt7e1amNuQjfOVvjKpl6+EDVAUjqyZdy1guhEU1CPo0T1Yy1/mDfmAMnrI8fTAVC87y9eLqTXtU2429wXJ4dDssF4Ej4ciqTFSVuNgdo0whpLNkhiPBxZSroXtP4YWNC6RU9fN+G8VZ3UUOwnyt0YyWqLZPSUoJIetM7sh78FFEZBqmxXdkKENJbXCh6yxLvhOXFCIIjM3pvqUXvu92Wg8SmDiJTu2hOlZqxsoFln X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Apr 2026 11:57:28.3506 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9f0a6bdf-ae38-425f-b55a-08de962f2c47 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00002319.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB8967 Content-Type: text/plain; charset="utf-8" From: Mark Bloch Deployments that always operate in switchdev mode currently require manual devlink configuration after driver probe, which complicates automated provisioning. Introduce MLX5_PROF_MASK_DEF_SWITCHDEV, a new profile mask bit, and profile index 4. When a device is initialized or reloaded with this profile, the driver automatically switches the e-switch to switchdev mode by calling mlx5_devlink_eswitch_mode_set() immediately after bringing the device online. A no-op stub of mlx5_devlink_eswitch_mode_set() is added for builds without CONFIG_MLX5_ESWITCH. Signed-off-by: Mark Bloch Reviewed-by: Moshe Shemesh Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/eswitch.h | 6 +++++ .../net/ethernet/mellanox/mlx5/core/main.c | 26 ++++++++++++++++++- include/linux/mlx5/driver.h | 1 + 3 files changed, 32 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h b/drivers/ne= t/ethernet/mellanox/mlx5/core/eswitch.h index 256ac3ad37bc..5dcca59c3125 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h @@ -1047,6 +1047,12 @@ mlx5_esw_lag_demux_rule_create(struct mlx5_eswitch *= esw, u16 vport_num, return ERR_PTR(-EOPNOTSUPP); } =20 +static inline int +mlx5_devlink_eswitch_mode_set(struct devlink *devlink, u16 mode, + struct netlink_ext_ack *extack) +{ + return -EOPNOTSUPP; +} #endif /* CONFIG_MLX5_ESWITCH */ =20 #endif /* __MLX5_ESWITCH_H__ */ diff --git a/drivers/net/ethernet/mellanox/mlx5/core/main.c b/drivers/net/e= thernet/mellanox/mlx5/core/main.c index dc7f20a357d9..12f39b4b6c2a 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/main.c @@ -86,7 +86,7 @@ MODULE_PARM_DESC(debug_mask, "debug mask: 1 =3D dump cmd = data, 2 =3D dump cmd exec t =20 static unsigned int prof_sel =3D MLX5_DEFAULT_PROF; module_param_named(prof_sel, prof_sel, uint, 0444); -MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2"); +MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 4"); =20 static u32 sw_owner_id[4]; #define MAX_SW_VHCA_ID (BIT(__mlx5_bit_sz(cmd_hca_cap_2, sw_vhca_id)) - 1) @@ -185,6 +185,11 @@ static struct mlx5_profile profile[] =3D { .log_max_qp =3D LOG_MAX_SUPPORTED_QPS, .num_cmd_caches =3D 0, }, + [4] =3D { + .mask =3D MLX5_PROF_MASK_DEF_SWITCHDEV | MLX5_PROF_MASK_QP_SIZE, + .log_max_qp =3D LOG_MAX_SUPPORTED_QPS, + .num_cmd_caches =3D MLX5_NUM_COMMAND_CACHES, + }, }; =20 static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili, @@ -1451,6 +1456,17 @@ static void mlx5_unload(struct mlx5_core_dev *dev) mlx5_free_bfreg(dev, &dev->priv.bfreg); } =20 +static void mlx5_set_default_switchdev(struct mlx5_core_dev *dev) +{ + int err; + + err =3D mlx5_devlink_eswitch_mode_set(priv_to_devlink(dev), + DEVLINK_ESWITCH_MODE_SWITCHDEV, + NULL); + if (err && err !=3D -EOPNOTSUPP) + mlx5_core_warn(dev, "failed setting switchdev as default\n"); +} + int mlx5_init_one_devl_locked(struct mlx5_core_dev *dev) { bool light_probe =3D mlx5_dev_is_lightweight(dev); @@ -1497,6 +1513,10 @@ int mlx5_init_one_devl_locked(struct mlx5_core_dev *= dev) mlx5_core_err(dev, "mlx5_hwmon_dev_register failed with error code %d\n"= , err); =20 mutex_unlock(&dev->intf_state_mutex); + + if (dev->profile.mask & MLX5_PROF_MASK_DEF_SWITCHDEV) + mlx5_set_default_switchdev(dev); + return 0; =20 err_register: @@ -1598,6 +1618,10 @@ int mlx5_load_one_devl_locked(struct mlx5_core_dev *= dev, bool recovery) goto err_attach; =20 mutex_unlock(&dev->intf_state_mutex); + + if (dev->profile.mask & MLX5_PROF_MASK_DEF_SWITCHDEV) + mlx5_set_default_switchdev(dev); + return 0; =20 err_attach: diff --git a/include/linux/mlx5/driver.h b/include/linux/mlx5/driver.h index 1268fcf35ec7..cfbc0ff6292a 100644 --- a/include/linux/mlx5/driver.h +++ b/include/linux/mlx5/driver.h @@ -706,6 +706,7 @@ struct mlx5_st; enum { MLX5_PROF_MASK_QP_SIZE =3D (u64)1 << 0, MLX5_PROF_MASK_MR_CACHE =3D (u64)1 << 1, + MLX5_PROF_MASK_DEF_SWITCHDEV =3D (u64)1 << 2, }; =20 enum { --=20 2.44.0