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[199.106.103.52]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2ca78df8942sm31265060eec.2.2026.04.09.02.11.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Apr 2026 02:11:47 -0700 (PDT) From: Shawn Guo To: Bjorn Andersson Cc: Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bartosz Golaszewski , Deepti Jaggi , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Shawn Guo , Konrad Dybcio Subject: [PATCH 1/8] arm64: dts: qcom: lemans: Move PCIe devices into soc node Date: Thu, 9 Apr 2026 17:10:53 +0800 Message-ID: <20260409091100.474358-2-shengchao.guo@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260409091100.474358-1-shengchao.guo@oss.qualcomm.com> References: <20260409091100.474358-1-shengchao.guo@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: fzK12EMnSK_xZqE-tRZ-iftGkf8h4IyP X-Proofpoint-GUID: fzK12EMnSK_xZqE-tRZ-iftGkf8h4IyP X-Authority-Analysis: v=2.4 cv=R9sz39RX c=1 sm=1 tr=0 ts=69d76d55 cx=c_pps a=cFYjgdjTJScbgFmBucgdfQ==:117 a=b9+bayejhc3NMeqCNyeLQQ==:17 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=rs7BxoZ7CQHKALr8RUwA:9 a=scEy_gLbYbu1JhEsrz4S:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDA5MDA4MSBTYWx0ZWRfXxxznBxS4a+sJ UNIMEMOREUhq8mqnUGXWhbznOz4eweRL1Vj3DzkuG0TDDilGJSoFjST8MQQBIEkQf9IooPJguXu F9S39akXF29QL5LDrkJFbwijSMFQO/Qm1jWXNvu6C7ty36RqlJaa/2QHp1YyTICXVe3nMUEhMUq GIPIyG8czmuIparaEdCyP13JHedc13iAxmV3FqFkcWlRq/vPq2OlasavcKFXeJhboZRvAUJJcYC SejUu62Ty0eB/T2JHZUlVjxcNjFmA564oAqI8gEU5ad0fbYqJ8F9lw4kZ7WK1MFqnE2Na8Q2kAi QB/zspEJ9szbiIEX4oSdR1OC4DSNa7b+FP5h61hQDG5rhQYwbatqSLumqIIWoJDLEknHpvJTfpo y5HNdZgn8UI+/Eo3G9MUP1qC6eGwgWkbiv1e9PBppHAVQyXawt72p6HZKS0Ms+VC8An9PXWmMBz bQk/TwMb1O81ar6dxYw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-09_02,2026-04-09_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 clxscore=1015 impostorscore=0 lowpriorityscore=0 phishscore=0 spamscore=0 priorityscore=1501 suspectscore=0 adultscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604010000 definitions=main-2604090081 Content-Type: text/plain; charset="utf-8" These PCIe devices with MMIO address should be inside soc node rather than outside. Fixes: 489f14be0e0a ("arm64: dts: qcom: sa8775p: Add pcie0 and pcie1 nodes") Reported-by: Bjorn Andersson Reviewed-by: Konrad Dybcio Signed-off-by: Shawn Guo Tested-by: Deepti Jaggi # sa8255p-ride board --- arch/arm64/boot/dts/qcom/lemans.dtsi | 692 +++++++++++++-------------- 1 file changed, 346 insertions(+), 346 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qco= m/lemans.dtsi index f565067bda31..03a712d82d78 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -2694,6 +2694,352 @@ mmss_noc: interconnect@17a0000 { qcom,bcm-voters =3D <&apps_bcm_voter>; }; =20 + pcie0: pcie@1c00000 { + compatible =3D "qcom,pcie-sa8775p"; + reg =3D <0x0 0x01c00000 0x0 0x3000>, + <0x0 0x40000000 0x0 0xf20>, + <0x0 0x40000f20 0x0 0xa8>, + <0x0 0x40001000 0x0 0x4000>, + <0x0 0x40100000 0x0 0x100000>, + <0x0 0x01c03000 0x0 0x1000>; + reg-names =3D "parf", "dbi", "elbi", "atu", "config", "mhi"; + device_type =3D "pci"; + + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges =3D <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, + <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; + bus-range =3D <0x00 0xff>; + + dma-coherent; + + linux,pci-domain =3D <0>; + num-lanes =3D <2>; + + interrupts =3D , + , + , + , + , + , + , + , + ; + interrupt-names =3D "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7", + "global"; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>; + + clocks =3D <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; + + clock-names =3D "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a"; + + assigned-clocks =3D <&gcc GCC_PCIE_0_AUX_CLK>; + assigned-clock-rates =3D <19200000>; + + interconnects =3D <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>; + interconnect-names =3D "pcie-mem", "cpu-pcie"; + + iommu-map =3D <0x0 &pcie_smmu 0x0000 0x1>, + <0x100 &pcie_smmu 0x0001 0x1>; + + resets =3D <&gcc GCC_PCIE_0_BCR>, + <&gcc GCC_PCIE_0_LINK_DOWN_BCR>; + reset-names =3D "pci", + "link_down"; + + power-domains =3D <&gcc PCIE_0_GDSC>; + + phys =3D <&pcie0_phy>; + phy-names =3D "pciephy"; + + eq-presets-8gts =3D /bits/ 16 <0x5555 0x5555>; + eq-presets-16gts =3D /bits/ 8 <0x55 0x55>; + + status =3D "disabled"; + + pcieport0: pcie@0 { + device_type =3D "pci"; + reg =3D <0x0 0x0 0x0 0x0 0x0>; + bus-range =3D <0x01 0xff>; + + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges; + }; + }; + + pcie0_ep: pcie-ep@1c00000 { + compatible =3D "qcom,sa8775p-pcie-ep"; + reg =3D <0x0 0x01c00000 0x0 0x3000>, + <0x0 0x40000000 0x0 0xf20>, + <0x0 0x40000f20 0x0 0xa8>, + <0x0 0x40001000 0x0 0x4000>, + <0x0 0x40200000 0x0 0x1fe00000>, + <0x0 0x01c03000 0x0 0x1000>, + <0x0 0x40005000 0x0 0x2000>; + reg-names =3D "parf", "dbi", "elbi", "atu", "addr_space", + "mmio", "dma"; + + clocks =3D <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; + + clock-names =3D "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a"; + + interrupts =3D , + , + ; + + interrupt-names =3D "global", "doorbell", "dma"; + + interconnects =3D <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>; + interconnect-names =3D "pcie-mem", "cpu-pcie"; + + dma-coherent; + iommus =3D <&pcie_smmu 0x0000 0x7f>; + resets =3D <&gcc GCC_PCIE_0_BCR>; + reset-names =3D "core"; + power-domains =3D <&gcc PCIE_0_GDSC>; + phys =3D <&pcie0_phy>; + phy-names =3D "pciephy"; + num-lanes =3D <2>; + linux,pci-domain =3D <0>; + + status =3D "disabled"; + }; + + pcie0_phy: phy@1c04000 { + compatible =3D "qcom,sa8775p-qmp-gen4x2-pcie-phy"; + reg =3D <0x0 0x1c04000 0x0 0x2000>; + + clocks =3D <&gcc GCC_PCIE_0_PHY_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_CLKREF_EN>, + <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_0_PIPE_CLK>, + <&gcc GCC_PCIE_0_PIPEDIV2_CLK>; + clock-names =3D "aux", + "cfg_ahb", + "ref", + "rchng", + "pipe", + "pipediv2"; + + assigned-clocks =3D <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; + assigned-clock-rates =3D <100000000>; + + resets =3D <&gcc GCC_PCIE_0_PHY_BCR>; + reset-names =3D "phy"; + + #clock-cells =3D <0>; + clock-output-names =3D "pcie_0_pipe_clk"; + + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + + pcie1: pcie@1c10000 { + compatible =3D "qcom,pcie-sa8775p"; + reg =3D <0x0 0x01c10000 0x0 0x3000>, + <0x0 0x60000000 0x0 0xf20>, + <0x0 0x60000f20 0x0 0xa8>, + <0x0 0x60001000 0x0 0x4000>, + <0x0 0x60100000 0x0 0x100000>, + <0x0 0x01c13000 0x0 0x1000>; + reg-names =3D "parf", "dbi", "elbi", "atu", "config", "mhi"; + device_type =3D "pci"; + + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges =3D <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, + <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x1fd00000>; + bus-range =3D <0x00 0xff>; + + dma-coherent; + + linux,pci-domain =3D <1>; + num-lanes =3D <4>; + + interrupts =3D , + , + , + , + , + , + , + , + ; + interrupt-names =3D "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7", + "global"; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; + + clocks =3D <&gcc GCC_PCIE_1_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>; + + clock-names =3D "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a"; + + assigned-clocks =3D <&gcc GCC_PCIE_1_AUX_CLK>; + assigned-clock-rates =3D <19200000>; + + interconnects =3D <&pcie_anoc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>; + interconnect-names =3D "pcie-mem", "cpu-pcie"; + + iommu-map =3D <0x0 &pcie_smmu 0x0080 0x1>, + <0x100 &pcie_smmu 0x0081 0x1>; + + resets =3D <&gcc GCC_PCIE_1_BCR>, + <&gcc GCC_PCIE_1_LINK_DOWN_BCR>; + reset-names =3D "pci", + "link_down"; + + power-domains =3D <&gcc PCIE_1_GDSC>; + + phys =3D <&pcie1_phy>; + phy-names =3D "pciephy"; + + eq-presets-8gts =3D /bits/ 16 <0x5555 0x5555 0x5555 0x5555>; + eq-presets-16gts =3D /bits/ 8 <0x55 0x55 0x55 0x55>; + + status =3D "disabled"; + + pcie@0 { + device_type =3D "pci"; + reg =3D <0x0 0x0 0x0 0x0 0x0>; + bus-range =3D <0x01 0xff>; + + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges; + }; + }; + + pcie1_ep: pcie-ep@1c10000 { + compatible =3D "qcom,sa8775p-pcie-ep"; + reg =3D <0x0 0x01c10000 0x0 0x3000>, + <0x0 0x60000000 0x0 0xf20>, + <0x0 0x60000f20 0x0 0xa8>, + <0x0 0x60001000 0x0 0x4000>, + <0x0 0x60200000 0x0 0x1fe00000>, + <0x0 0x01c13000 0x0 0x1000>, + <0x0 0x60005000 0x0 0x2000>; + reg-names =3D "parf", "dbi", "elbi", "atu", "addr_space", + "mmio", "dma"; + + clocks =3D <&gcc GCC_PCIE_1_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>; + + clock-names =3D "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a"; + + interrupts =3D , + , + ; + + interrupt-names =3D "global", "doorbell", "dma"; + + interconnects =3D <&pcie_anoc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>; + interconnect-names =3D "pcie-mem", "cpu-pcie"; + + dma-coherent; + iommus =3D <&pcie_smmu 0x80 0x7f>; + resets =3D <&gcc GCC_PCIE_1_BCR>; + reset-names =3D "core"; + power-domains =3D <&gcc PCIE_1_GDSC>; + phys =3D <&pcie1_phy>; + phy-names =3D "pciephy"; + num-lanes =3D <4>; + linux,pci-domain =3D <1>; + + status =3D "disabled"; + }; + + pcie1_phy: phy@1c14000 { + compatible =3D "qcom,sa8775p-qmp-gen4x4-pcie-phy"; + reg =3D <0x0 0x1c14000 0x0 0x4000>; + + clocks =3D <&gcc GCC_PCIE_1_PHY_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_CLKREF_EN>, + <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_1_PIPE_CLK>, + <&gcc GCC_PCIE_1_PIPEDIV2_CLK>; + clock-names =3D "aux", + "cfg_ahb", + "ref", + "rchng", + "pipe", + "pipediv2"; + + assigned-clocks =3D <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; + assigned-clock-rates =3D <100000000>; + + resets =3D <&gcc GCC_PCIE_1_PHY_BCR>; + reset-names =3D "phy"; + + #clock-cells =3D <0>; + clock-output-names =3D "pcie_1_pipe_clk"; + + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + ufs_mem_hc: ufshc@1d84000 { compatible =3D "qcom,sa8775p-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; reg =3D <0x0 0x01d84000 0x0 0x3000>; @@ -8601,350 +8947,4 @@ turing_llm_tpdm_out: endpoint { }; }; }; - - pcie0: pcie@1c00000 { - compatible =3D "qcom,pcie-sa8775p"; - reg =3D <0x0 0x01c00000 0x0 0x3000>, - <0x0 0x40000000 0x0 0xf20>, - <0x0 0x40000f20 0x0 0xa8>, - <0x0 0x40001000 0x0 0x4000>, - <0x0 0x40100000 0x0 0x100000>, - <0x0 0x01c03000 0x0 0x1000>; - reg-names =3D "parf", "dbi", "elbi", "atu", "config", "mhi"; - device_type =3D "pci"; - - #address-cells =3D <3>; - #size-cells =3D <2>; - ranges =3D <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, - <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; - bus-range =3D <0x00 0xff>; - - dma-coherent; - - linux,pci-domain =3D <0>; - num-lanes =3D <2>; - - interrupts =3D , - , - , - , - , - , - , - , - ; - interrupt-names =3D "msi0", - "msi1", - "msi2", - "msi3", - "msi4", - "msi5", - "msi6", - "msi7", - "global"; - #interrupt-cells =3D <1>; - interrupt-map-mask =3D <0 0 0 0x7>; - interrupt-map =3D <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>; - - clocks =3D <&gcc GCC_PCIE_0_AUX_CLK>, - <&gcc GCC_PCIE_0_CFG_AHB_CLK>, - <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, - <&gcc GCC_PCIE_0_SLV_AXI_CLK>, - <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; - - clock-names =3D "aux", - "cfg", - "bus_master", - "bus_slave", - "slave_q2a"; - - assigned-clocks =3D <&gcc GCC_PCIE_0_AUX_CLK>; - assigned-clock-rates =3D <19200000>; - - interconnects =3D <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>; - interconnect-names =3D "pcie-mem", "cpu-pcie"; - - iommu-map =3D <0x0 &pcie_smmu 0x0000 0x1>, - <0x100 &pcie_smmu 0x0001 0x1>; - - resets =3D <&gcc GCC_PCIE_0_BCR>, - <&gcc GCC_PCIE_0_LINK_DOWN_BCR>; - reset-names =3D "pci", - "link_down"; - - power-domains =3D <&gcc PCIE_0_GDSC>; - - phys =3D <&pcie0_phy>; - phy-names =3D "pciephy"; - - eq-presets-8gts =3D /bits/ 16 <0x5555 0x5555>; - eq-presets-16gts =3D /bits/ 8 <0x55 0x55>; - - status =3D "disabled"; - - pcieport0: pcie@0 { - device_type =3D "pci"; - reg =3D <0x0 0x0 0x0 0x0 0x0>; - bus-range =3D <0x01 0xff>; - - #address-cells =3D <3>; - #size-cells =3D <2>; - ranges; - }; - }; - - pcie0_ep: pcie-ep@1c00000 { - compatible =3D "qcom,sa8775p-pcie-ep"; - reg =3D <0x0 0x01c00000 0x0 0x3000>, - <0x0 0x40000000 0x0 0xf20>, - <0x0 0x40000f20 0x0 0xa8>, - <0x0 0x40001000 0x0 0x4000>, - <0x0 0x40200000 0x0 0x1fe00000>, - <0x0 0x01c03000 0x0 0x1000>, - <0x0 0x40005000 0x0 0x2000>; - reg-names =3D "parf", "dbi", "elbi", "atu", "addr_space", - "mmio", "dma"; - - clocks =3D <&gcc GCC_PCIE_0_AUX_CLK>, - <&gcc GCC_PCIE_0_CFG_AHB_CLK>, - <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, - <&gcc GCC_PCIE_0_SLV_AXI_CLK>, - <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; - - clock-names =3D "aux", - "cfg", - "bus_master", - "bus_slave", - "slave_q2a"; - - interrupts =3D , - , - ; - - interrupt-names =3D "global", "doorbell", "dma"; - - interconnects =3D <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>; - interconnect-names =3D "pcie-mem", "cpu-pcie"; - - dma-coherent; - iommus =3D <&pcie_smmu 0x0000 0x7f>; - resets =3D <&gcc GCC_PCIE_0_BCR>; - reset-names =3D "core"; - power-domains =3D <&gcc PCIE_0_GDSC>; - phys =3D <&pcie0_phy>; - phy-names =3D "pciephy"; - num-lanes =3D <2>; - linux,pci-domain =3D <0>; - - status =3D "disabled"; - }; - - pcie0_phy: phy@1c04000 { - compatible =3D "qcom,sa8775p-qmp-gen4x2-pcie-phy"; - reg =3D <0x0 0x1c04000 0x0 0x2000>; - - clocks =3D <&gcc GCC_PCIE_0_PHY_AUX_CLK>, - <&gcc GCC_PCIE_0_CFG_AHB_CLK>, - <&gcc GCC_PCIE_CLKREF_EN>, - <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, - <&gcc GCC_PCIE_0_PIPE_CLK>, - <&gcc GCC_PCIE_0_PIPEDIV2_CLK>; - clock-names =3D "aux", - "cfg_ahb", - "ref", - "rchng", - "pipe", - "pipediv2"; - - assigned-clocks =3D <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; - assigned-clock-rates =3D <100000000>; - - resets =3D <&gcc GCC_PCIE_0_PHY_BCR>; - reset-names =3D "phy"; - - #clock-cells =3D <0>; - clock-output-names =3D "pcie_0_pipe_clk"; - - #phy-cells =3D <0>; - - status =3D "disabled"; - }; - - pcie1: pcie@1c10000 { - compatible =3D "qcom,pcie-sa8775p"; - reg =3D <0x0 0x01c10000 0x0 0x3000>, - <0x0 0x60000000 0x0 0xf20>, - <0x0 0x60000f20 0x0 0xa8>, - <0x0 0x60001000 0x0 0x4000>, - <0x0 0x60100000 0x0 0x100000>, - <0x0 0x01c13000 0x0 0x1000>; - reg-names =3D "parf", "dbi", "elbi", "atu", "config", "mhi"; - device_type =3D "pci"; - - #address-cells =3D <3>; - #size-cells =3D <2>; - ranges =3D <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, - <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x1fd00000>; - bus-range =3D <0x00 0xff>; - - dma-coherent; - - linux,pci-domain =3D <1>; - num-lanes =3D <4>; - - interrupts =3D , - , - , - , - , - , - , - , - ; - interrupt-names =3D "msi0", - "msi1", - "msi2", - "msi3", - "msi4", - "msi5", - "msi6", - "msi7", - "global"; - #interrupt-cells =3D <1>; - interrupt-map-mask =3D <0 0 0 0x7>; - interrupt-map =3D <0 0 0 1 &intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; - - clocks =3D <&gcc GCC_PCIE_1_AUX_CLK>, - <&gcc GCC_PCIE_1_CFG_AHB_CLK>, - <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, - <&gcc GCC_PCIE_1_SLV_AXI_CLK>, - <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>; - - clock-names =3D "aux", - "cfg", - "bus_master", - "bus_slave", - "slave_q2a"; - - assigned-clocks =3D <&gcc GCC_PCIE_1_AUX_CLK>; - assigned-clock-rates =3D <19200000>; - - interconnects =3D <&pcie_anoc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>; - interconnect-names =3D "pcie-mem", "cpu-pcie"; - - iommu-map =3D <0x0 &pcie_smmu 0x0080 0x1>, - <0x100 &pcie_smmu 0x0081 0x1>; - - resets =3D <&gcc GCC_PCIE_1_BCR>, - <&gcc GCC_PCIE_1_LINK_DOWN_BCR>; - reset-names =3D "pci", - "link_down"; - - power-domains =3D <&gcc PCIE_1_GDSC>; - - phys =3D <&pcie1_phy>; - phy-names =3D "pciephy"; - - eq-presets-8gts =3D /bits/ 16 <0x5555 0x5555 0x5555 0x5555>; - eq-presets-16gts =3D /bits/ 8 <0x55 0x55 0x55 0x55>; - - status =3D "disabled"; - - pcie@0 { - device_type =3D "pci"; - reg =3D <0x0 0x0 0x0 0x0 0x0>; - bus-range =3D <0x01 0xff>; - - #address-cells =3D <3>; - #size-cells =3D <2>; - ranges; - }; - }; - - pcie1_ep: pcie-ep@1c10000 { - compatible =3D "qcom,sa8775p-pcie-ep"; - reg =3D <0x0 0x01c10000 0x0 0x3000>, - <0x0 0x60000000 0x0 0xf20>, - <0x0 0x60000f20 0x0 0xa8>, - <0x0 0x60001000 0x0 0x4000>, - <0x0 0x60200000 0x0 0x1fe00000>, - <0x0 0x01c13000 0x0 0x1000>, - <0x0 0x60005000 0x0 0x2000>; - reg-names =3D "parf", "dbi", "elbi", "atu", "addr_space", - "mmio", "dma"; - - clocks =3D <&gcc GCC_PCIE_1_AUX_CLK>, - <&gcc GCC_PCIE_1_CFG_AHB_CLK>, - <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, - <&gcc GCC_PCIE_1_SLV_AXI_CLK>, - <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>; - - clock-names =3D "aux", - "cfg", - "bus_master", - "bus_slave", - "slave_q2a"; - - interrupts =3D , - , - ; - - interrupt-names =3D "global", "doorbell", "dma"; - - interconnects =3D <&pcie_anoc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>; - interconnect-names =3D "pcie-mem", "cpu-pcie"; - - dma-coherent; - iommus =3D <&pcie_smmu 0x80 0x7f>; - resets =3D <&gcc GCC_PCIE_1_BCR>; - reset-names =3D "core"; - power-domains =3D <&gcc PCIE_1_GDSC>; - phys =3D <&pcie1_phy>; - phy-names =3D "pciephy"; - num-lanes =3D <4>; - linux,pci-domain =3D <1>; - - status =3D "disabled"; - }; - - pcie1_phy: phy@1c14000 { - compatible =3D "qcom,sa8775p-qmp-gen4x4-pcie-phy"; - reg =3D <0x0 0x1c14000 0x0 0x4000>; - - clocks =3D <&gcc GCC_PCIE_1_PHY_AUX_CLK>, - <&gcc GCC_PCIE_1_CFG_AHB_CLK>, - <&gcc GCC_PCIE_CLKREF_EN>, - <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, - <&gcc GCC_PCIE_1_PIPE_CLK>, - <&gcc GCC_PCIE_1_PIPEDIV2_CLK>; - clock-names =3D "aux", - "cfg_ahb", - "ref", - "rchng", - "pipe", - "pipediv2"; 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[199.106.103.52]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2ca78df8942sm31265060eec.2.2026.04.09.02.11.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Apr 2026 02:11:50 -0700 (PDT) From: Shawn Guo To: Bjorn Andersson Cc: Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bartosz Golaszewski , Deepti Jaggi , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Shawn Guo Subject: [PATCH 2/8] arm64: dts: qcom: Rename lemans-auto.dtsi to lemans-sa8775p.dtsi Date: Thu, 9 Apr 2026 17:10:54 +0800 Message-ID: <20260409091100.474358-3-shengchao.guo@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260409091100.474358-1-shengchao.guo@oss.qualcomm.com> References: <20260409091100.474358-1-shengchao.guo@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=TL51jVla c=1 sm=1 tr=0 ts=69d76d58 cx=c_pps a=PfFC4Oe2JQzmKTvty2cRDw==:117 a=b9+bayejhc3NMeqCNyeLQQ==:17 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8 a=qgi84oEYZtV-hQa44IwA:9 a=6Ab_bkdmUrQuMsNx7PHu:22 X-Proofpoint-ORIG-GUID: oopKrPosFfAJZYdIP52qfRx-f5kDUVxi X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDA5MDA4MSBTYWx0ZWRfX3fxE0u2jpfjO 9ZH7/m2Q42nV6uApS5FaSAz6DVm8klQ1GVjW1q/HYxpFTeI7lDZ659juywupHIN+FCR4imoFSu0 ypVmL3LpE3RgIOBk3l0YoqgfPKwwqhAEbZccEwwkZK5eKyQ5nuVLWYIKG7IfJ5xPAVZKbn2jAS8 qLO/TFj1uuMTbm/KBChGRXF7ivAI68UUWNjIkxrgFJWuS7pbVDi8DkX1MZ/MSupkkSeoHB7dXn8 wGvXfLAON2BSuyQIcXIJ4eH2ths+JEZcGXq17USGl0uDXQaKZhZXm+tXtrUbzMtE5T1Xn9V1p+j +rww4ABqcrMf0v0MXOOR8SMBqynSPJD9+trVO+51nye3sX10Iwg5+tYMRSo7Bhn33+NfM/v94Ul xo5m6RUwSSQyTJ1qnb+AX4yrWfOtbyWpt5yX7sjUeDLjLD20c1tY9gyrhtT+2cIhVIuBoq9rF6t 5G8zihWvkg9iBfi+ZnA== X-Proofpoint-GUID: oopKrPosFfAJZYdIP52qfRx-f5kDUVxi X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-09_02,2026-04-09_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 priorityscore=1501 clxscore=1015 bulkscore=0 adultscore=0 spamscore=0 suspectscore=0 impostorscore=0 malwarescore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604010000 definitions=main-2604090081 Content-Type: text/plain; charset="utf-8" SA8775P is highly compatible with IQ9 with only some reserved memory differences that are currently accommodated by lemans-auto.dtsi. Rename lemans-auto.dtsi to lemans-sa8775p.dtsi to make it clear this is SA8775P specific rather than something common to all Lemans based AUTO SoCs. Signed-off-by: Shawn Guo Tested-by: Deepti Jaggi # sa8255p-ride board --- .../boot/dts/qcom/{lemans-auto.dtsi =3D> lemans-sa8775p.dtsi} | 0 arch/arm64/boot/dts/qcom/sa8775p-ride-r3.dts | 2 +- arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 2 +- 3 files changed, 2 insertions(+), 2 deletions(-) rename arch/arm64/boot/dts/qcom/{lemans-auto.dtsi =3D> lemans-sa8775p.dtsi= } (100%) diff --git a/arch/arm64/boot/dts/qcom/lemans-auto.dtsi b/arch/arm64/boot/dt= s/qcom/lemans-sa8775p.dtsi similarity index 100% rename from arch/arm64/boot/dts/qcom/lemans-auto.dtsi rename to arch/arm64/boot/dts/qcom/lemans-sa8775p.dtsi diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride-r3.dts b/arch/arm64/boot= /dts/qcom/sa8775p-ride-r3.dts index b25f0b2c9410..7a33fa72af98 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p-ride-r3.dts +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride-r3.dts @@ -5,7 +5,7 @@ =20 /dts-v1/; =20 -#include "lemans-auto.dtsi" +#include "lemans-sa8775p.dtsi" =20 #include "lemans-pmics.dtsi" #include "lemans-ride-common.dtsi" diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts b/arch/arm64/boot/dt= s/qcom/sa8775p-ride.dts index 2d9028cd60be..436b0b1f3a63 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts @@ -5,7 +5,7 @@ =20 /dts-v1/; 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[199.106.103.52]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2ca78df8942sm31265060eec.2.2026.04.09.02.11.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Apr 2026 02:11:54 -0700 (PDT) From: Shawn Guo To: Bjorn Andersson Cc: Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bartosz Golaszewski , Deepti Jaggi , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Shawn Guo Subject: [PATCH 3/8] arm64: dts: qcom: Introduce lemans-iq9.dtsi as a placeholder Date: Thu, 9 Apr 2026 17:10:55 +0800 Message-ID: <20260409091100.474358-4-shengchao.guo@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260409091100.474358-1-shengchao.guo@oss.qualcomm.com> References: <20260409091100.474358-1-shengchao.guo@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: v43OPOMrpiJSs9bNrf1XCMeAO3sJSwWm X-Proofpoint-GUID: v43OPOMrpiJSs9bNrf1XCMeAO3sJSwWm X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDA5MDA4MSBTYWx0ZWRfX4Tsk4diuw8h1 5LqEerilqZvcT2jtUuuBHcH8Kg+xhVKgFOsEGwsFvidOu5THleisVTYMQ9fbccgx9358X4ESF49 ZdIfRahUSu5g3CpLZHmu0fzdX2ivVtvmK80k241VUsTsYoWvfTdf4ICxV6yiG6kXCaPV7x5RCcH JkXuK9xYuqZIqDUnLr1y7RzBVwMkEC3iMJFGFq+vq9a37++G1sq2ptBV0I/xn7V29BkRue8uCDL oB4pNCwEOuRTg5+bkklTRMzwqQVqI7WWAuivz2nfSTNGB2rZ+0vX3Ar1o8c2ztloYikVQp+cipR PtDhKugGU4RyCkTgEbvdw0rwXCKomz8ysnpKm4h5vonsZ0fkU0VtcypdMh3mhjGw7Yzvd41D5Kj bTvqcLytGlb1B9gHO8jKUEZJlr+fW/uBdzPyNa4Fe67nuCvOCvuRUUyEPzde1PwPy0gwdFd6bL7 Dh5unP5btosRFKBViFQ== X-Authority-Analysis: v=2.4 cv=TZemcxQh c=1 sm=1 tr=0 ts=69d76d5b cx=c_pps a=wEP8DlPgTf/vqF+yE6f9lg==:117 a=b9+bayejhc3NMeqCNyeLQQ==:17 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=EUspDBNiAAAA:8 a=FvohN9vnyHKddW96yrgA:9 a=bBxd6f-gb0O0v-kibOvt:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-09_02,2026-04-09_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 lowpriorityscore=0 priorityscore=1501 suspectscore=0 malwarescore=0 phishscore=0 bulkscore=0 spamscore=0 impostorscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604010000 definitions=main-2604090081 Content-Type: text/plain; charset="utf-8" Lemans is a Qualcomm SoC family that includes not only SoCs IQ9 and SA8775P where platform resources are managed by HLOS, but also SoCs like SA8255P where resources are managed by firmware via SCMI. The current lemans.dtsi covers the former variant only. Introduce lemans-iq9.dtsi as a placeholder for now, while later changes will move IQ9/SA8775P variant settings in there and introduce SA8255P variant support. Signed-off-by: Shawn Guo Tested-by: Deepti Jaggi # sa8255p-ride board --- arch/arm64/boot/dts/qcom/lemans-evk.dts | 2 +- arch/arm64/boot/dts/qcom/lemans-iq9.dtsi | 6 ++++++ arch/arm64/boot/dts/qcom/lemans-sa8775p.dtsi | 2 +- arch/arm64/boot/dts/qcom/qcs9100-ride-r3.dts | 2 +- arch/arm64/boot/dts/qcom/qcs9100-ride.dts | 2 +- 5 files changed, 10 insertions(+), 4 deletions(-) create mode 100644 arch/arm64/boot/dts/qcom/lemans-iq9.dtsi diff --git a/arch/arm64/boot/dts/qcom/lemans-evk.dts b/arch/arm64/boot/dts/= qcom/lemans-evk.dts index a1ef4eba2a20..cd6fa8c4f22b 100644 --- a/arch/arm64/boot/dts/qcom/lemans-evk.dts +++ b/arch/arm64/boot/dts/qcom/lemans-evk.dts @@ -10,7 +10,7 @@ #include #include =20 -#include "lemans.dtsi" +#include "lemans-iq9.dtsi" #include "lemans-pmics.dtsi" =20 / { diff --git a/arch/arm64/boot/dts/qcom/lemans-iq9.dtsi b/arch/arm64/boot/dts= /qcom/lemans-iq9.dtsi new file mode 100644 index 000000000000..80d8c75e4895 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/lemans-iq9.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include "lemans.dtsi" diff --git a/arch/arm64/boot/dts/qcom/lemans-sa8775p.dtsi b/arch/arm64/boot= /dts/qcom/lemans-sa8775p.dtsi index 8db958d60fd1..2b74e58c47c6 100644 --- a/arch/arm64/boot/dts/qcom/lemans-sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans-sa8775p.dtsi @@ -5,7 +5,7 @@ =20 /dts-v1/; =20 -#include "lemans.dtsi" +#include "lemans-iq9.dtsi" =20 /delete-node/ &pil_camera_mem; /delete-node/ &pil_adsp_mem; diff --git a/arch/arm64/boot/dts/qcom/qcs9100-ride-r3.dts b/arch/arm64/boot= /dts/qcom/qcs9100-ride-r3.dts index 7fc2de0d3d5e..e50da0da9c71 100644 --- a/arch/arm64/boot/dts/qcom/qcs9100-ride-r3.dts +++ b/arch/arm64/boot/dts/qcom/qcs9100-ride-r3.dts @@ -4,7 +4,7 @@ */ /dts-v1/; =20 -#include "lemans.dtsi" +#include "lemans-iq9.dtsi" #include "lemans-pmics.dtsi" =20 #include "lemans-ride-common.dtsi" diff --git a/arch/arm64/boot/dts/qcom/qcs9100-ride.dts b/arch/arm64/boot/dt= s/qcom/qcs9100-ride.dts index b0c5fdde56ae..eec68ab572a2 100644 --- a/arch/arm64/boot/dts/qcom/qcs9100-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs9100-ride.dts @@ -4,7 +4,7 @@ */ /dts-v1/; =20 -#include "lemans.dtsi" +#include "lemans-iq9.dtsi" #include "lemans-pmics.dtsi" =20 #include "lemans-ride-common.dtsi" --=20 2.43.0 From nobody Mon Jun 15 09:40:21 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A08C53AB260 for ; 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[199.106.103.52]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2ca78df8942sm31265060eec.2.2026.04.09.02.11.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Apr 2026 02:11:58 -0700 (PDT) From: Shawn Guo To: Bjorn Andersson Cc: Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bartosz Golaszewski , Deepti Jaggi , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Shawn Guo Subject: [PATCH 4/8] arm64: dts: qcom: lemans: Move pinctrl states into lemans-iq9.dtsi Date: Thu, 9 Apr 2026 17:10:56 +0800 Message-ID: <20260409091100.474358-5-shengchao.guo@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260409091100.474358-1-shengchao.guo@oss.qualcomm.com> References: <20260409091100.474358-1-shengchao.guo@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: 9SAqE903fdeHZWAA539K4qyzwn6tgXLV X-Authority-Analysis: v=2.4 cv=fIIJG5ae c=1 sm=1 tr=0 ts=69d76d60 cx=c_pps a=wEP8DlPgTf/vqF+yE6f9lg==:117 a=b9+bayejhc3NMeqCNyeLQQ==:17 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=EUspDBNiAAAA:8 a=lfu0pQ9szTVn3MWTFX8A:9 a=bBxd6f-gb0O0v-kibOvt:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDA5MDA4MSBTYWx0ZWRfXyeSJJni49Th/ +jpjhcnHQUT5A36ZVGKtdLdBCDKGKXfbU/ioM9pyDsTmQhWWk+OM3qa9YXURctpTqbdQcGJ2elO 3LLPYEi4FOJE4SKe9AYU1hsJLZ9eA4UFCj+RELPaA/GxhN6fiE0FGhHE3qa89C4mFVyNFk2TnpE leyugPUWGiBgkassImiEPUSZ9ZbjnQFjuJIMcHuNLVK0YluXPsjWoCkRNT3b+90gqPZ0AOBcfaa Uv12EZtNwv8QFGZAz91fGGGV8bxHKXH9AsNzBmgRtkNRocNu6waYr93xDkIzKYrpYxnqRgTOJiu Ux6gxrqD99A+3RKQR/mmlMcmu/6H3FpCvsu0xYVD1Mc0bGOBxduBIv9whFcCYIJZGoWymQjBt84 JutorCVs6dlsCK9NtsU2hqXTLtzGt6MWC6KyjqXTNiPBzZE3I6s5Q/2VE9fRI0iwur7GuxTay16 b4yN2ZsW7dX2VkO0aNA== X-Proofpoint-GUID: 9SAqE903fdeHZWAA539K4qyzwn6tgXLV X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-09_02,2026-04-09_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 lowpriorityscore=0 impostorscore=0 clxscore=1015 adultscore=0 bulkscore=0 malwarescore=0 phishscore=0 spamscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604010000 definitions=main-2604090081 Content-Type: text/plain; charset="utf-8" The lemans.dtsi will become a base devicetree common to all Lemans series SoCs. Move those pinctrl states into lemans-iq9.dtsi as they may not apply to other Lemans variant SoCs. Signed-off-by: Shawn Guo Tested-by: Deepti Jaggi # sa8255p-ride board --- arch/arm64/boot/dts/qcom/lemans-iq9.dtsi | 812 +++++++++++++++++++++++ arch/arm64/boot/dts/qcom/lemans.dtsi | 806 ---------------------- 2 files changed, 812 insertions(+), 806 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/lemans-iq9.dtsi b/arch/arm64/boot/dts= /qcom/lemans-iq9.dtsi index 80d8c75e4895..5c2aa83fe8b4 100644 --- a/arch/arm64/boot/dts/qcom/lemans-iq9.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans-iq9.dtsi @@ -4,3 +4,815 @@ */ =20 #include "lemans.dtsi" + +/ { + soc: soc@0 { + tlmm: pinctrl@f000000 { + dp0_hot_plug_det: dp0-hot-plug-det-state { + pins =3D "gpio101"; + function =3D "edp0_hot"; + bias-disable; + }; + + dp1_hot_plug_det: dp1-hot-plug-det-state { + pins =3D "gpio102"; + function =3D "edp1_hot"; + bias-disable; + }; + + hs0_mi2s_active: hs0-mi2s-active-state { + pins =3D "gpio114", "gpio115", "gpio116", "gpio117"; + function =3D "hs0_mi2s"; + drive-strength =3D <8>; + bias-disable; + }; + + hs2_mi2s_active: hs2-mi2s-active-state { + pins =3D "gpio122", "gpio123", "gpio124", "gpio125"; + function =3D "hs2_mi2s"; + drive-strength =3D <8>; + bias-disable; + }; + + cci0_0_default: cci0-0-default-state { + pins =3D "gpio60", "gpio61"; + function =3D "cci_i2c"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + + cci0_0_sleep: cci0-0-sleep-state { + pins =3D "gpio60", "gpio61"; + function =3D "cci_i2c"; + drive-strength =3D <2>; + bias-pull-down; + }; + + cci0_1_default: cci0-1-default-state { + pins =3D "gpio52", "gpio53"; + function =3D "cci_i2c"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + + cci0_1_sleep: cci0-1-sleep-state { + pins =3D "gpio52", "gpio53"; + function =3D "cci_i2c"; + drive-strength =3D <2>; + bias-pull-down; + }; + + cci1_0_default: cci1-0-default-state { + pins =3D "gpio62", "gpio63"; + function =3D "cci_i2c"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + + cci1_0_sleep: cci1-0-sleep-state { + pins =3D "gpio62", "gpio63"; + function =3D "cci_i2c"; + drive-strength =3D <2>; + bias-pull-down; + }; + + cci1_1_default: cci1-1-default-state { + pins =3D "gpio54", "gpio55"; + function =3D "cci_i2c"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + + cci1_1_sleep: cci1-1-sleep-state { + pins =3D "gpio54", "gpio55"; + function =3D "cci_i2c"; + drive-strength =3D <2>; + bias-pull-down; + }; + + cci2_0_default: cci2-0-default-state { + pins =3D "gpio64", "gpio65"; + function =3D "cci_i2c"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + + cci2_0_sleep: cci2-0-sleep-state { + pins =3D "gpio64", "gpio65"; + function =3D "cci_i2c"; + drive-strength =3D <2>; + bias-pull-down; + }; + + cci2_1_default: cci2-1-default-state { + pins =3D "gpio56", "gpio57"; + function =3D "cci_i2c"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + + cci2_1_sleep: cci2-1-sleep-state { + pins =3D "gpio56", "gpio57"; + function =3D "cci_i2c"; + drive-strength =3D <2>; + bias-pull-down; + }; + + cci3_0_default: cci3-0-default-state { + pins =3D "gpio66", "gpio67"; + function =3D "cci_i2c"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + + cci3_0_sleep: cci3-0-sleep-state { + pins =3D "gpio66", "gpio67"; + function =3D "cci_i2c"; + drive-strength =3D <2>; + bias-pull-down; + }; + + cci3_1_default: cci3-1-default-state { + pins =3D "gpio58", "gpio59"; + function =3D "cci_i2c"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + + cci3_1_sleep: cci3-1-sleep-state { + pins =3D "gpio58", "gpio59"; + function =3D "cci_i2c"; + drive-strength =3D <2>; + bias-pull-down; + }; + + qup_i2c0_default: qup-i2c0-state { + pins =3D "gpio20", "gpio21"; + function =3D "qup0_se0"; + }; + + qup_i2c1_default: qup-i2c1-state { + pins =3D "gpio24", "gpio25"; + function =3D "qup0_se1"; + }; + + qup_i2c2_default: qup-i2c2-state { + pins =3D "gpio36", "gpio37"; + function =3D "qup0_se2"; + }; + + qup_i2c3_default: qup-i2c3-state { + pins =3D "gpio28", "gpio29"; + function =3D "qup0_se3"; + }; + + qup_i2c4_default: qup-i2c4-state { + pins =3D "gpio32", "gpio33"; + function =3D "qup0_se4"; + }; + + qup_i2c5_default: qup-i2c5-state { + pins =3D "gpio36", "gpio37"; + function =3D "qup0_se5"; + }; + + qup_i2c7_default: qup-i2c7-state { + pins =3D "gpio40", "gpio41"; + function =3D "qup1_se0"; + }; + + qup_i2c8_default: qup-i2c8-state { + pins =3D "gpio42", "gpio43"; + function =3D "qup1_se1"; + }; + + qup_i2c9_default: qup-i2c9-state { + pins =3D "gpio46", "gpio47"; + function =3D "qup1_se2"; + }; + + qup_i2c10_default: qup-i2c10-state { + pins =3D "gpio44", "gpio45"; + function =3D "qup1_se3"; + }; + + qup_i2c11_default: qup-i2c11-state { + pins =3D "gpio48", "gpio49"; + function =3D "qup1_se4"; + }; + + qup_i2c12_default: qup-i2c12-state { + pins =3D "gpio52", "gpio53"; + function =3D "qup1_se5"; + }; + + qup_i2c13_default: qup-i2c13-state { + pins =3D "gpio56", "gpio57"; + function =3D "qup1_se6"; + }; + + qup_i2c14_default: qup-i2c14-state { + pins =3D "gpio80", "gpio81"; + function =3D "qup2_se0"; + }; + + qup_i2c15_default: qup-i2c15-state { + pins =3D "gpio84", "gpio85"; + function =3D "qup2_se1"; + }; + + qup_i2c16_default: qup-i2c16-state { + pins =3D "gpio86", "gpio87"; + function =3D "qup2_se2"; + }; + + qup_i2c17_default: qup-i2c17-state { + pins =3D "gpio91", "gpio92"; + function =3D "qup2_se3"; + }; + + qup_i2c18_default: qup-i2c18-state { + pins =3D "gpio95", "gpio96"; + function =3D "qup2_se4"; + }; + + qup_i2c19_default: qup-i2c19-state { + pins =3D "gpio99", "gpio100"; + function =3D "qup2_se5"; + }; + + qup_i2c20_default: qup-i2c20-state { + pins =3D "gpio97", "gpio98"; + function =3D "qup2_se6"; + }; + + qup_i2c21_default: qup-i2c21-state { + pins =3D "gpio13", "gpio14"; + function =3D "qup3_se0"; + }; + + qup_spi0_default: qup-spi0-state { + pins =3D "gpio20", "gpio21", "gpio22", "gpio23"; + function =3D "qup0_se0"; + }; + + qup_spi1_default: qup-spi1-state { + pins =3D "gpio24", "gpio25", "gpio26", "gpio27"; + function =3D "qup0_se1"; + }; + + qup_spi2_default: qup-spi2-state { + pins =3D "gpio36", "gpio37", "gpio38", "gpio39"; + function =3D "qup0_se2"; + }; + + qup_spi3_default: qup-spi3-state { + pins =3D "gpio28", "gpio29", "gpio30", "gpio31"; + function =3D "qup0_se3"; + }; + + qup_spi4_default: qup-spi4-state { + pins =3D "gpio32", "gpio33", "gpio34", "gpio35"; + function =3D "qup0_se4"; + }; + + qup_spi5_default: qup-spi5-state { + pins =3D "gpio36", "gpio37", "gpio38", "gpio39"; + function =3D "qup0_se5"; + }; + + qup_spi7_default: qup-spi7-state { + pins =3D "gpio40", "gpio41", "gpio42", "gpio43"; + function =3D "qup1_se0"; + }; + + qup_spi8_default: qup-spi8-state { + pins =3D "gpio42", "gpio43", "gpio40", "gpio41"; + function =3D "qup1_se1"; + }; + + qup_spi9_default: qup-spi9-state { + pins =3D "gpio46", "gpio47", "gpio44", "gpio45"; + function =3D "qup1_se2"; + }; + + qup_spi10_default: qup-spi10-state { + pins =3D "gpio44", "gpio45", "gpio46", "gpio47"; + function =3D "qup1_se3"; + }; + + qup_spi11_default: qup-spi11-state { + pins =3D "gpio48", "gpio49", "gpio50", "gpio51"; + function =3D "qup1_se4"; + }; + + qup_spi12_default: qup-spi12-state { + pins =3D "gpio52", "gpio53", "gpio54", "gpio55"; + function =3D "qup1_se5"; + }; + + qup_spi14_default: qup-spi14-state { + pins =3D "gpio80", "gpio81", "gpio82", "gpio83"; + function =3D "qup2_se0"; + }; + + qup_spi15_default: qup-spi15-state { + pins =3D "gpio84", "gpio85", "gpio99", "gpio100"; + function =3D "qup2_se1"; + }; + + qup_spi16_default: qup-spi16-state { + pins =3D "gpio86", "gpio87", "gpio88", "gpio89"; + function =3D "qup2_se2"; + }; + + qup_spi17_default: qup-spi17-state { + pins =3D "gpio91", "gpio92", "gpio93", "gpio94"; + function =3D "qup2_se3"; + }; + + qup_spi18_default: qup-spi18-state { + pins =3D "gpio95", "gpio96", "gpio97", "gpio98"; + function =3D "qup2_se4"; + }; + + qup_spi19_default: qup-spi19-state { + pins =3D "gpio99", "gpio100", "gpio84", "gpio85"; + function =3D "qup2_se5"; + }; + + qup_spi20_default: qup-spi20-state { + pins =3D "gpio97", "gpio98", "gpio95", "gpio96"; + function =3D "qup2_se6"; + }; + + qup_spi21_default: qup-spi21-state { + pins =3D "gpio13", "gpio14", "gpio15", "gpio16"; + function =3D "qup3_se0"; + }; + + qup_uart0_default: qup-uart0-state { + qup_uart0_cts: qup-uart0-cts-pins { + pins =3D "gpio20"; + function =3D "qup0_se0"; + }; + + qup_uart0_rts: qup-uart0-rts-pins { + pins =3D "gpio21"; + function =3D "qup0_se0"; + }; + + qup_uart0_tx: qup-uart0-tx-pins { + pins =3D "gpio22"; + function =3D "qup0_se0"; + }; + + qup_uart0_rx: qup-uart0-rx-pins { + pins =3D "gpio23"; + function =3D "qup0_se0"; + }; + }; + + qup_uart1_default: qup-uart1-state { + qup_uart1_cts: qup-uart1-cts-pins { + pins =3D "gpio24"; + function =3D "qup0_se1"; + }; + + qup_uart1_rts: qup-uart1-rts-pins { + pins =3D "gpio25"; + function =3D "qup0_se1"; + }; + + qup_uart1_tx: qup-uart1-tx-pins { + pins =3D "gpio26"; + function =3D "qup0_se1"; + }; + + qup_uart1_rx: qup-uart1-rx-pins { + pins =3D "gpio27"; + function =3D "qup0_se1"; + }; + }; + + qup_uart2_default: qup-uart2-state { + qup_uart2_cts: qup-uart2-cts-pins { + pins =3D "gpio36"; + function =3D "qup0_se2"; + }; + + qup_uart2_rts: qup-uart2-rts-pins { + pins =3D "gpio37"; + function =3D "qup0_se2"; + }; + + qup_uart2_tx: qup-uart2-tx-pins { + pins =3D "gpio38"; + function =3D "qup0_se2"; + }; + + qup_uart2_rx: qup-uart2-rx-pins { + pins =3D "gpio39"; + function =3D "qup0_se2"; + }; + }; + + qup_uart3_default: qup-uart3-state { + qup_uart3_cts: qup-uart3-cts-pins { + pins =3D "gpio28"; + function =3D "qup0_se3"; + }; + + qup_uart3_rts: qup-uart3-rts-pins { + pins =3D "gpio29"; + function =3D "qup0_se3"; + }; + + qup_uart3_tx: qup-uart3-tx-pins { + pins =3D "gpio30"; + function =3D "qup0_se3"; + }; + + qup_uart3_rx: qup-uart3-rx-pins { + pins =3D "gpio31"; + function =3D "qup0_se3"; + }; + }; + + qup_uart4_default: qup-uart4-state { + qup_uart4_cts: qup-uart4-cts-pins { + pins =3D "gpio32"; + function =3D "qup0_se4"; + }; + + qup_uart4_rts: qup-uart4-rts-pins { + pins =3D "gpio33"; + function =3D "qup0_se4"; + }; + + qup_uart4_tx: qup-uart4-tx-pins { + pins =3D "gpio34"; + function =3D "qup0_se4"; + }; + + qup_uart4_rx: qup-uart4-rx-pins { + pins =3D "gpio35"; + function =3D "qup0_se4"; + }; + }; + + qup_uart5_default: qup-uart5-state { + qup_uart5_cts: qup-uart5-cts-pins { + pins =3D "gpio36"; + function =3D "qup0_se5"; + }; + + qup_uart5_rts: qup-uart5-rts-pins { + pins =3D "gpio37"; + function =3D "qup0_se5"; + }; + + qup_uart5_tx: qup-uart5-tx-pins { + pins =3D "gpio38"; + function =3D "qup0_se5"; + }; + + qup_uart5_rx: qup-uart5-rx-pins { + pins =3D "gpio39"; + function =3D "qup0_se5"; + }; + }; + + qup_uart7_default: qup-uart7-state { + qup_uart7_cts: qup-uart7-cts-pins { + pins =3D "gpio40"; + function =3D "qup1_se0"; + }; + + qup_uart7_rts: qup-uart7-rts-pins { + pins =3D "gpio41"; + function =3D "qup1_se0"; + }; + + qup_uart7_tx: qup-uart7-tx-pins { + pins =3D "gpio42"; + function =3D "qup1_se0"; + }; + + qup_uart7_rx: qup-uart7-rx-pins { + pins =3D "gpio43"; + function =3D "qup1_se0"; + }; + }; + + qup_uart8_default: qup-uart8-state { + qup_uart8_cts: qup-uart8-cts-pins { + pins =3D "gpio42"; + function =3D "qup1_se1"; + }; + + qup_uart8_rts: qup-uart8-rts-pins { + pins =3D "gpio43"; + function =3D "qup1_se1"; + }; + + qup_uart8_tx: qup-uart8-tx-pins { + pins =3D "gpio40"; + function =3D "qup1_se1"; + }; + + qup_uart8_rx: qup-uart8-rx-pins { + pins =3D "gpio41"; + function =3D "qup1_se1"; + }; + }; + + qup_uart9_default: qup-uart9-state { + qup_uart9_cts: qup-uart9-cts-pins { + pins =3D "gpio46"; + function =3D "qup1_se2"; + }; + + qup_uart9_rts: qup-uart9-rts-pins { + pins =3D "gpio47"; + function =3D "qup1_se2"; + }; + + qup_uart9_tx: qup-uart9-tx-pins { + pins =3D "gpio44"; + function =3D "qup1_se2"; + }; + + qup_uart9_rx: qup-uart9-rx-pins { + pins =3D "gpio45"; + function =3D "qup1_se2"; + }; + }; + + qup_uart10_default: qup-uart10-state { + pins =3D "gpio46", "gpio47"; + function =3D "qup1_se3"; + }; + + qup_uart11_default: qup-uart11-state { + qup_uart11_cts: qup-uart11-cts-pins { + pins =3D "gpio48"; + function =3D "qup1_se4"; + }; + + qup_uart11_rts: qup-uart11-rts-pins { + pins =3D "gpio49"; + function =3D "qup1_se4"; + }; + + qup_uart11_tx: qup-uart11-tx-pins { + pins =3D "gpio50"; + function =3D "qup1_se4"; + }; + + qup_uart11_rx: qup-uart11-rx-pins { + pins =3D "gpio51"; + function =3D "qup1_se4"; + }; + }; + + qup_uart12_default: qup-uart12-state { + qup_uart12_cts: qup-uart12-cts-pins { + pins =3D "gpio52"; + function =3D "qup1_se5"; + }; + + qup_uart12_rts: qup-uart12-rts-pins { + pins =3D "gpio53"; + function =3D "qup1_se5"; + }; + + qup_uart12_tx: qup-uart12-tx-pins { + pins =3D "gpio54"; + function =3D "qup1_se5"; + }; + + qup_uart12_rx: qup-uart12-rx-pins { + pins =3D "gpio55"; + function =3D "qup1_se5"; + }; + }; + + qup_uart14_default: qup-uart14-state { + qup_uart14_cts: qup-uart14-cts-pins { + pins =3D "gpio80"; + function =3D "qup2_se0"; + }; + + qup_uart14_rts: qup-uart14-rts-pins { + pins =3D "gpio81"; + function =3D "qup2_se0"; + }; + + qup_uart14_tx: qup-uart14-tx-pins { + pins =3D "gpio82"; + function =3D "qup2_se0"; + }; + + qup_uart14_rx: qup-uart14-rx-pins { + pins =3D "gpio83"; + function =3D "qup2_se0"; + }; + }; + + qup_uart15_default: qup-uart15-state { + qup_uart15_cts: qup-uart15-cts-pins { + pins =3D "gpio84"; + function =3D "qup2_se1"; + }; + + qup_uart15_rts: qup-uart15-rts-pins { + pins =3D "gpio85"; + function =3D "qup2_se1"; + }; + + qup_uart15_tx: qup-uart15-tx-pins { + pins =3D "gpio99"; + function =3D "qup2_se1"; + }; + + qup_uart15_rx: qup-uart15-rx-pins { + pins =3D "gpio100"; + function =3D "qup2_se1"; + }; + }; + + qup_uart16_default: qup-uart16-state { + qup_uart16_cts: qup-uart16-cts-pins { + pins =3D "gpio86"; + function =3D "qup2_se2"; + }; + + qup_uart16_rts: qup-uart16-rts-pins { + pins =3D "gpio87"; + function =3D "qup2_se2"; + }; + + qup_uart16_tx: qup-uart16-tx-pins { + pins =3D "gpio88"; + function =3D "qup2_se2"; + }; + + qup_uart16_rx: qup-uart16-rx-pins { + pins =3D "gpio89"; + function =3D "qup2_se2"; + }; + }; + + qup_uart17_default: qup-uart17-state { + qup_uart17_cts: qup-uart17-cts-pins { + pins =3D "gpio91"; + function =3D "qup2_se3"; + }; + + qup_uart17_rts: qup0-uart17-rts-pins { + pins =3D "gpio92"; + function =3D "qup2_se3"; + }; + + qup_uart17_tx: qup0-uart17-tx-pins { + pins =3D "gpio93"; + function =3D "qup2_se3"; + }; + + qup_uart17_rx: qup0-uart17-rx-pins { + pins =3D "gpio94"; + function =3D "qup2_se3"; + }; + }; + + qup_uart18_default: qup-uart18-state { + qup_uart18_cts: qup-uart18-cts-pins { + pins =3D "gpio95"; + function =3D "qup2_se4"; + }; + + qup_uart18_rts: qup-uart18-rts-pins { + pins =3D "gpio96"; + function =3D "qup2_se4"; + }; + + qup_uart18_tx: qup-uart18-tx-pins { + pins =3D "gpio97"; + function =3D "qup2_se4"; + }; + + qup_uart18_rx: qup-uart18-rx-pins { + pins =3D "gpio98"; + function =3D "qup2_se4"; + }; + }; + + qup_uart19_default: qup-uart19-state { + qup_uart19_cts: qup-uart19-cts-pins { + pins =3D "gpio99"; + function =3D "qup2_se5"; + }; + + qup_uart19_rts: qup-uart19-rts-pins { + pins =3D "gpio100"; + function =3D "qup2_se5"; + }; + + qup_uart19_tx: qup-uart19-tx-pins { + pins =3D "gpio84"; + function =3D "qup2_se5"; + }; + + qup_uart19_rx: qup-uart19-rx-pins { + pins =3D "gpio85"; + function =3D "qup2_se5"; + }; + }; + + qup_uart20_default: qup-uart20-state { + qup_uart20_cts: qup-uart20-cts-pins { + pins =3D "gpio97"; + function =3D "qup2_se6"; + }; + + qup_uart20_rts: qup-uart20-rts-pins { + pins =3D "gpio98"; + function =3D "qup2_se6"; + }; + + qup_uart20_tx: qup-uart20-tx-pins { + pins =3D "gpio95"; + function =3D "qup2_se6"; + }; + + qup_uart20_rx: qup-uart20-rx-pins { + pins =3D "gpio96"; + function =3D "qup2_se6"; + }; + }; + + qup_uart21_default: qup-uart21-state { + qup_uart21_cts: qup-uart21-cts-pins { + pins =3D "gpio13"; + function =3D "qup3_se0"; + }; + + qup_uart21_rts: qup-uart21-rts-pins { + pins =3D "gpio14"; + function =3D "qup3_se0"; + }; + + qup_uart21_tx: qup-uart21-tx-pins { + pins =3D "gpio15"; + function =3D "qup3_se0"; + }; + + qup_uart21_rx: qup-uart21-rx-pins { + pins =3D "gpio16"; + function =3D "qup3_se0"; + }; + }; + + sdc_default: sdc-default-state { + clk-pins { + pins =3D "sdc1_clk"; + drive-strength =3D <16>; + bias-disable; + }; + + cmd-pins { + pins =3D "sdc1_cmd"; + drive-strength =3D <10>; + bias-pull-up; + }; + + data-pins { + pins =3D "sdc1_data"; + drive-strength =3D <10>; + bias-pull-up; + }; + }; + + sdc_sleep: sdc-sleep-state { + clk-pins { + pins =3D "sdc1_clk"; + drive-strength =3D <2>; + bias-bus-hold; + }; + + cmd-pins { + pins =3D "sdc1_cmd"; + drive-strength =3D <2>; + bias-bus-hold; + }; + + data-pins { + pins =3D "sdc1_data"; + drive-strength =3D <2>; + bias-bus-hold; + }; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qco= m/lemans.dtsi index 03a712d82d78..fa2f20a7b11f 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -6025,812 +6025,6 @@ tlmm: pinctrl@f000000 { #interrupt-cells =3D <2>; gpio-ranges =3D <&tlmm 0 0 149>; wakeup-parent =3D <&pdc>; - - dp0_hot_plug_det: dp0-hot-plug-det-state { - pins =3D "gpio101"; - function =3D "edp0_hot"; - bias-disable; - }; - - dp1_hot_plug_det: dp1-hot-plug-det-state { - pins =3D "gpio102"; - function =3D "edp1_hot"; - bias-disable; - }; - - hs0_mi2s_active: hs0-mi2s-active-state { - pins =3D "gpio114", "gpio115", "gpio116", "gpio117"; - function =3D "hs0_mi2s"; - drive-strength =3D <8>; - bias-disable; - }; - - hs2_mi2s_active: hs2-mi2s-active-state { - pins =3D "gpio122", "gpio123", "gpio124", "gpio125"; - function =3D "hs2_mi2s"; - drive-strength =3D <8>; - bias-disable; - }; - - cci0_0_default: cci0-0-default-state { - pins =3D "gpio60", "gpio61"; - function =3D "cci_i2c"; - drive-strength =3D <2>; - bias-pull-up =3D <2200>; - }; - - cci0_0_sleep: cci0-0-sleep-state { - pins =3D "gpio60", "gpio61"; - function =3D "cci_i2c"; - drive-strength =3D <2>; - bias-pull-down; - }; - - cci0_1_default: cci0-1-default-state { - pins =3D "gpio52", "gpio53"; - function =3D "cci_i2c"; - drive-strength =3D <2>; - bias-pull-up =3D <2200>; - }; - - cci0_1_sleep: cci0-1-sleep-state { - pins =3D "gpio52", "gpio53"; - function =3D "cci_i2c"; - drive-strength =3D <2>; - bias-pull-down; - }; - - cci1_0_default: cci1-0-default-state { - pins =3D "gpio62", "gpio63"; - function =3D "cci_i2c"; - drive-strength =3D <2>; - bias-pull-up =3D <2200>; - }; - - cci1_0_sleep: cci1-0-sleep-state { - pins =3D "gpio62", "gpio63"; - function =3D "cci_i2c"; - drive-strength =3D <2>; - bias-pull-down; - }; - - cci1_1_default: cci1-1-default-state { - pins =3D "gpio54", "gpio55"; - function =3D "cci_i2c"; - drive-strength =3D <2>; - bias-pull-up =3D <2200>; - }; - - cci1_1_sleep: cci1-1-sleep-state { - pins =3D "gpio54", "gpio55"; - function =3D "cci_i2c"; - drive-strength =3D <2>; - bias-pull-down; - }; - - cci2_0_default: cci2-0-default-state { - pins =3D "gpio64", "gpio65"; - function =3D "cci_i2c"; - drive-strength =3D <2>; - bias-pull-up =3D <2200>; - }; - - cci2_0_sleep: cci2-0-sleep-state { - pins =3D "gpio64", "gpio65"; - function =3D "cci_i2c"; - drive-strength =3D <2>; - bias-pull-down; - }; - - cci2_1_default: cci2-1-default-state { - pins =3D "gpio56", "gpio57"; - function =3D "cci_i2c"; - drive-strength =3D <2>; - bias-pull-up =3D <2200>; - }; - - cci2_1_sleep: cci2-1-sleep-state { - pins =3D "gpio56", "gpio57"; - function =3D "cci_i2c"; - drive-strength =3D <2>; - bias-pull-down; - }; - - cci3_0_default: cci3-0-default-state { - pins =3D "gpio66", "gpio67"; - function =3D "cci_i2c"; - drive-strength =3D <2>; - bias-pull-up =3D <2200>; - }; - - cci3_0_sleep: cci3-0-sleep-state { - pins =3D "gpio66", "gpio67"; - function =3D "cci_i2c"; - drive-strength =3D <2>; - bias-pull-down; - }; - - cci3_1_default: cci3-1-default-state { - pins =3D "gpio58", "gpio59"; - function =3D "cci_i2c"; - drive-strength =3D <2>; - bias-pull-up =3D <2200>; - }; - - cci3_1_sleep: cci3-1-sleep-state { - pins =3D "gpio58", "gpio59"; - function =3D "cci_i2c"; - drive-strength =3D <2>; - bias-pull-down; - }; - - qup_i2c0_default: qup-i2c0-state { - pins =3D "gpio20", "gpio21"; - function =3D "qup0_se0"; - }; - - qup_i2c1_default: qup-i2c1-state { - pins =3D "gpio24", "gpio25"; - function =3D "qup0_se1"; - }; - - qup_i2c2_default: qup-i2c2-state { - pins =3D "gpio36", "gpio37"; - function =3D "qup0_se2"; - }; - - qup_i2c3_default: qup-i2c3-state { - pins =3D "gpio28", "gpio29"; - function =3D "qup0_se3"; - }; - - qup_i2c4_default: qup-i2c4-state { - pins =3D "gpio32", "gpio33"; - function =3D "qup0_se4"; - }; - - qup_i2c5_default: qup-i2c5-state { - pins =3D "gpio36", "gpio37"; - function =3D "qup0_se5"; - }; - - qup_i2c7_default: qup-i2c7-state { - pins =3D "gpio40", "gpio41"; - function =3D "qup1_se0"; - }; - - qup_i2c8_default: qup-i2c8-state { - pins =3D "gpio42", "gpio43"; - function =3D "qup1_se1"; - }; - - qup_i2c9_default: qup-i2c9-state { - pins =3D "gpio46", "gpio47"; - function =3D "qup1_se2"; - }; - - qup_i2c10_default: qup-i2c10-state { - pins =3D "gpio44", "gpio45"; - function =3D "qup1_se3"; - }; - - qup_i2c11_default: qup-i2c11-state { - pins =3D "gpio48", "gpio49"; - function =3D "qup1_se4"; - }; - - qup_i2c12_default: qup-i2c12-state { - pins =3D "gpio52", "gpio53"; - function =3D "qup1_se5"; - }; - - qup_i2c13_default: qup-i2c13-state { - pins =3D "gpio56", "gpio57"; - function =3D "qup1_se6"; - }; - - qup_i2c14_default: qup-i2c14-state { - pins =3D "gpio80", "gpio81"; - function =3D "qup2_se0"; - }; - - qup_i2c15_default: qup-i2c15-state { - pins =3D "gpio84", "gpio85"; - function =3D "qup2_se1"; - }; - - qup_i2c16_default: qup-i2c16-state { - pins =3D "gpio86", "gpio87"; - function =3D "qup2_se2"; - }; - - qup_i2c17_default: qup-i2c17-state { - pins =3D "gpio91", "gpio92"; - function =3D "qup2_se3"; - }; - - qup_i2c18_default: qup-i2c18-state { - pins =3D "gpio95", "gpio96"; - function =3D "qup2_se4"; - }; - - qup_i2c19_default: qup-i2c19-state { - pins =3D "gpio99", "gpio100"; - function =3D "qup2_se5"; - }; - - qup_i2c20_default: qup-i2c20-state { - pins =3D "gpio97", "gpio98"; - function =3D "qup2_se6"; - }; - - qup_i2c21_default: qup-i2c21-state { - pins =3D "gpio13", "gpio14"; - function =3D "qup3_se0"; - }; - - qup_spi0_default: qup-spi0-state { - pins =3D "gpio20", "gpio21", "gpio22", "gpio23"; - function =3D "qup0_se0"; - }; - - qup_spi1_default: qup-spi1-state { - pins =3D "gpio24", "gpio25", "gpio26", "gpio27"; - function =3D "qup0_se1"; - }; - - qup_spi2_default: qup-spi2-state { - pins =3D "gpio36", "gpio37", "gpio38", "gpio39"; - function =3D "qup0_se2"; - }; - - qup_spi3_default: qup-spi3-state { - pins =3D "gpio28", "gpio29", "gpio30", "gpio31"; - function =3D "qup0_se3"; - }; - - qup_spi4_default: qup-spi4-state { - pins =3D "gpio32", "gpio33", "gpio34", "gpio35"; - function =3D "qup0_se4"; - }; - - qup_spi5_default: qup-spi5-state { - pins =3D "gpio36", "gpio37", "gpio38", "gpio39"; - function =3D "qup0_se5"; - }; - - qup_spi7_default: qup-spi7-state { - pins =3D "gpio40", "gpio41", "gpio42", "gpio43"; - function =3D "qup1_se0"; - }; - - qup_spi8_default: qup-spi8-state { - pins =3D "gpio42", "gpio43", "gpio40", "gpio41"; - function =3D "qup1_se1"; - }; - - qup_spi9_default: qup-spi9-state { - pins =3D "gpio46", "gpio47", "gpio44", "gpio45"; - function =3D "qup1_se2"; - }; - - qup_spi10_default: qup-spi10-state { - pins =3D "gpio44", "gpio45", "gpio46", "gpio47"; - function =3D "qup1_se3"; - }; - - qup_spi11_default: qup-spi11-state { - pins =3D "gpio48", "gpio49", "gpio50", "gpio51"; - function =3D "qup1_se4"; - }; - - qup_spi12_default: qup-spi12-state { - pins =3D "gpio52", "gpio53", "gpio54", "gpio55"; - function =3D "qup1_se5"; - }; - - qup_spi14_default: qup-spi14-state { - pins =3D "gpio80", "gpio81", "gpio82", "gpio83"; - function =3D "qup2_se0"; - }; - - qup_spi15_default: qup-spi15-state { - pins =3D "gpio84", "gpio85", "gpio99", "gpio100"; - function =3D "qup2_se1"; - }; - - qup_spi16_default: qup-spi16-state { - pins =3D "gpio86", "gpio87", "gpio88", "gpio89"; - function =3D "qup2_se2"; - }; - - qup_spi17_default: qup-spi17-state { - pins =3D "gpio91", "gpio92", "gpio93", "gpio94"; - function =3D "qup2_se3"; - }; - - qup_spi18_default: qup-spi18-state { - pins =3D "gpio95", "gpio96", "gpio97", "gpio98"; - function =3D "qup2_se4"; - }; - - qup_spi19_default: qup-spi19-state { - pins =3D "gpio99", "gpio100", "gpio84", "gpio85"; - function =3D "qup2_se5"; - }; - - qup_spi20_default: qup-spi20-state { - pins =3D "gpio97", "gpio98", "gpio95", "gpio96"; - function =3D "qup2_se6"; - }; - - qup_spi21_default: qup-spi21-state { - pins =3D "gpio13", "gpio14", "gpio15", "gpio16"; - function =3D "qup3_se0"; - }; - - qup_uart0_default: qup-uart0-state { - qup_uart0_cts: qup-uart0-cts-pins { - pins =3D "gpio20"; - function =3D "qup0_se0"; - }; - - qup_uart0_rts: qup-uart0-rts-pins { - pins =3D "gpio21"; - function =3D "qup0_se0"; - }; - - qup_uart0_tx: qup-uart0-tx-pins { - pins =3D "gpio22"; - function =3D "qup0_se0"; - }; - - qup_uart0_rx: qup-uart0-rx-pins { - pins =3D "gpio23"; - function =3D "qup0_se0"; - }; - }; - - qup_uart1_default: qup-uart1-state { - qup_uart1_cts: qup-uart1-cts-pins { - pins =3D "gpio24"; - function =3D "qup0_se1"; - }; - - qup_uart1_rts: qup-uart1-rts-pins { - pins =3D "gpio25"; - function =3D "qup0_se1"; - }; - - qup_uart1_tx: qup-uart1-tx-pins { - pins =3D "gpio26"; - function =3D "qup0_se1"; - }; - - qup_uart1_rx: qup-uart1-rx-pins { - pins =3D "gpio27"; - function =3D "qup0_se1"; - }; - }; - - qup_uart2_default: qup-uart2-state { - qup_uart2_cts: qup-uart2-cts-pins { - pins =3D "gpio36"; - function =3D "qup0_se2"; - }; - - qup_uart2_rts: qup-uart2-rts-pins { - pins =3D "gpio37"; - function =3D "qup0_se2"; - }; - - qup_uart2_tx: qup-uart2-tx-pins { - pins =3D "gpio38"; - function =3D "qup0_se2"; - }; - - qup_uart2_rx: qup-uart2-rx-pins { - pins =3D "gpio39"; - function =3D "qup0_se2"; - }; - }; - - qup_uart3_default: qup-uart3-state { - qup_uart3_cts: qup-uart3-cts-pins { - pins =3D "gpio28"; - function =3D "qup0_se3"; - }; - - qup_uart3_rts: qup-uart3-rts-pins { - pins =3D "gpio29"; - function =3D "qup0_se3"; - }; - - qup_uart3_tx: qup-uart3-tx-pins { - pins =3D "gpio30"; - function =3D "qup0_se3"; - }; - - qup_uart3_rx: qup-uart3-rx-pins { - pins =3D "gpio31"; - function =3D "qup0_se3"; - }; - }; - - qup_uart4_default: qup-uart4-state { - qup_uart4_cts: qup-uart4-cts-pins { - pins =3D "gpio32"; - function =3D "qup0_se4"; - }; - - qup_uart4_rts: qup-uart4-rts-pins { - pins =3D "gpio33"; - function =3D "qup0_se4"; - }; - - qup_uart4_tx: qup-uart4-tx-pins { - pins =3D "gpio34"; - function =3D "qup0_se4"; - }; - - qup_uart4_rx: qup-uart4-rx-pins { - pins =3D "gpio35"; - function =3D "qup0_se4"; - }; - }; - - qup_uart5_default: qup-uart5-state { - qup_uart5_cts: qup-uart5-cts-pins { - pins =3D "gpio36"; - function =3D "qup0_se5"; - }; - - qup_uart5_rts: qup-uart5-rts-pins { - pins =3D "gpio37"; - function =3D "qup0_se5"; - }; - - qup_uart5_tx: qup-uart5-tx-pins { - pins =3D "gpio38"; - function =3D "qup0_se5"; - }; - - qup_uart5_rx: qup-uart5-rx-pins { - pins =3D "gpio39"; - function =3D "qup0_se5"; - }; - }; - - qup_uart7_default: qup-uart7-state { - qup_uart7_cts: qup-uart7-cts-pins { - pins =3D "gpio40"; - function =3D "qup1_se0"; - }; - - qup_uart7_rts: qup-uart7-rts-pins { - pins =3D "gpio41"; - function =3D "qup1_se0"; - }; - - qup_uart7_tx: qup-uart7-tx-pins { - pins =3D "gpio42"; - function =3D "qup1_se0"; - }; - - qup_uart7_rx: qup-uart7-rx-pins { - pins =3D "gpio43"; - function =3D "qup1_se0"; - }; - }; - - qup_uart8_default: qup-uart8-state { - qup_uart8_cts: qup-uart8-cts-pins { - pins =3D "gpio42"; - function =3D "qup1_se1"; - }; - - qup_uart8_rts: qup-uart8-rts-pins { - pins =3D "gpio43"; - function =3D "qup1_se1"; - }; - - qup_uart8_tx: qup-uart8-tx-pins { - pins =3D "gpio40"; - function =3D "qup1_se1"; - }; - - qup_uart8_rx: qup-uart8-rx-pins { - pins =3D "gpio41"; - function =3D "qup1_se1"; - }; - }; - - qup_uart9_default: qup-uart9-state { - qup_uart9_cts: qup-uart9-cts-pins { - pins =3D "gpio46"; - function =3D "qup1_se2"; - }; - - qup_uart9_rts: qup-uart9-rts-pins { - pins =3D "gpio47"; - function =3D "qup1_se2"; - }; - - qup_uart9_tx: qup-uart9-tx-pins { - pins =3D "gpio44"; - function =3D "qup1_se2"; - }; - - qup_uart9_rx: qup-uart9-rx-pins { - pins =3D "gpio45"; - function =3D "qup1_se2"; - }; - }; - - qup_uart10_default: qup-uart10-state { - pins =3D "gpio46", "gpio47"; - function =3D "qup1_se3"; - }; - - qup_uart11_default: qup-uart11-state { - qup_uart11_cts: qup-uart11-cts-pins { - pins =3D "gpio48"; - function =3D "qup1_se4"; - }; - - qup_uart11_rts: qup-uart11-rts-pins { - pins =3D "gpio49"; - function =3D "qup1_se4"; - }; - - qup_uart11_tx: qup-uart11-tx-pins { - pins =3D "gpio50"; - function =3D "qup1_se4"; - }; - - qup_uart11_rx: qup-uart11-rx-pins { - pins =3D "gpio51"; - function =3D "qup1_se4"; - }; - }; - - qup_uart12_default: qup-uart12-state { - qup_uart12_cts: qup-uart12-cts-pins { - pins =3D "gpio52"; - function =3D "qup1_se5"; - }; - - qup_uart12_rts: qup-uart12-rts-pins { - pins =3D "gpio53"; - function =3D "qup1_se5"; - }; - - qup_uart12_tx: qup-uart12-tx-pins { - pins =3D "gpio54"; - function =3D "qup1_se5"; - }; - - qup_uart12_rx: qup-uart12-rx-pins { - pins =3D "gpio55"; - function =3D "qup1_se5"; - }; - }; - - qup_uart14_default: qup-uart14-state { - qup_uart14_cts: qup-uart14-cts-pins { - pins =3D "gpio80"; - function =3D "qup2_se0"; - }; - - qup_uart14_rts: qup-uart14-rts-pins { - pins =3D "gpio81"; - function =3D "qup2_se0"; - }; - - qup_uart14_tx: qup-uart14-tx-pins { - pins =3D "gpio82"; - function =3D "qup2_se0"; - }; - - qup_uart14_rx: qup-uart14-rx-pins { - pins =3D "gpio83"; - function =3D "qup2_se0"; - }; - }; - - qup_uart15_default: qup-uart15-state { - qup_uart15_cts: qup-uart15-cts-pins { - pins =3D "gpio84"; - function =3D "qup2_se1"; - }; - - qup_uart15_rts: qup-uart15-rts-pins { - pins =3D "gpio85"; - function =3D "qup2_se1"; - }; - - qup_uart15_tx: qup-uart15-tx-pins { - pins =3D "gpio99"; - function =3D "qup2_se1"; - }; - - qup_uart15_rx: qup-uart15-rx-pins { - pins =3D "gpio100"; - function =3D "qup2_se1"; - }; - }; - - qup_uart16_default: qup-uart16-state { - qup_uart16_cts: qup-uart16-cts-pins { - pins =3D "gpio86"; - function =3D "qup2_se2"; - }; - - qup_uart16_rts: qup-uart16-rts-pins { - pins =3D "gpio87"; - function =3D "qup2_se2"; - }; - - qup_uart16_tx: qup-uart16-tx-pins { - pins =3D "gpio88"; - function =3D "qup2_se2"; - }; - - qup_uart16_rx: qup-uart16-rx-pins { - pins =3D "gpio89"; - function =3D "qup2_se2"; - }; - }; - - qup_uart17_default: qup-uart17-state { - qup_uart17_cts: qup-uart17-cts-pins { - pins =3D "gpio91"; - function =3D "qup2_se3"; - }; - - qup_uart17_rts: qup0-uart17-rts-pins { - pins =3D "gpio92"; - function =3D "qup2_se3"; - }; - - qup_uart17_tx: qup0-uart17-tx-pins { - pins =3D "gpio93"; - function =3D "qup2_se3"; - }; - - qup_uart17_rx: qup0-uart17-rx-pins { - pins =3D "gpio94"; - function =3D "qup2_se3"; - }; - }; - - qup_uart18_default: qup-uart18-state { - qup_uart18_cts: qup-uart18-cts-pins { - pins =3D "gpio95"; - function =3D "qup2_se4"; - }; - - qup_uart18_rts: qup-uart18-rts-pins { - pins =3D "gpio96"; - function =3D "qup2_se4"; - }; - - qup_uart18_tx: qup-uart18-tx-pins { - pins =3D "gpio97"; - function =3D "qup2_se4"; - }; - - qup_uart18_rx: qup-uart18-rx-pins { - pins =3D "gpio98"; - function =3D "qup2_se4"; - }; - }; - - qup_uart19_default: qup-uart19-state { - qup_uart19_cts: qup-uart19-cts-pins { - pins =3D "gpio99"; - function =3D "qup2_se5"; - }; - - qup_uart19_rts: qup-uart19-rts-pins { - pins =3D "gpio100"; - function =3D "qup2_se5"; - }; - - qup_uart19_tx: qup-uart19-tx-pins { - pins =3D "gpio84"; - function =3D "qup2_se5"; - }; - - qup_uart19_rx: qup-uart19-rx-pins { - pins =3D "gpio85"; - function =3D "qup2_se5"; - }; - }; - - qup_uart20_default: qup-uart20-state { - qup_uart20_cts: qup-uart20-cts-pins { - pins =3D "gpio97"; - function =3D "qup2_se6"; - }; - - qup_uart20_rts: qup-uart20-rts-pins { - pins =3D "gpio98"; - function =3D "qup2_se6"; - }; - - qup_uart20_tx: qup-uart20-tx-pins { - pins =3D "gpio95"; - function =3D "qup2_se6"; - }; - - qup_uart20_rx: qup-uart20-rx-pins { - pins =3D "gpio96"; - function =3D "qup2_se6"; - }; - }; - - qup_uart21_default: qup-uart21-state { - qup_uart21_cts: qup-uart21-cts-pins { - pins =3D "gpio13"; - function =3D "qup3_se0"; - }; - - qup_uart21_rts: qup-uart21-rts-pins { - pins =3D "gpio14"; - function =3D "qup3_se0"; - }; - - qup_uart21_tx: qup-uart21-tx-pins { - pins =3D "gpio15"; - function =3D "qup3_se0"; - }; - - qup_uart21_rx: qup-uart21-rx-pins { - pins =3D "gpio16"; - function =3D "qup3_se0"; - }; - }; - - sdc_default: sdc-default-state { - clk-pins { - pins =3D "sdc1_clk"; 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[199.106.103.52]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2ca78df8942sm31265060eec.2.2026.04.09.02.11.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Apr 2026 02:12:02 -0700 (PDT) From: Shawn Guo To: Bjorn Andersson Cc: Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bartosz Golaszewski , Deepti Jaggi , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Shawn Guo Subject: [PATCH 5/8] arm64: dts: qcom: lemans: Move platform resources into lemans-iq9.dtsi Date: Thu, 9 Apr 2026 17:10:57 +0800 Message-ID: <20260409091100.474358-6-shengchao.guo@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260409091100.474358-1-shengchao.guo@oss.qualcomm.com> References: <20260409091100.474358-1-shengchao.guo@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: zjotQoZSJHEKMnNHi3MABztk6q7BWHjT X-Authority-Analysis: v=2.4 cv=b7OCJNGx c=1 sm=1 tr=0 ts=69d76d66 cx=c_pps a=PfFC4Oe2JQzmKTvty2cRDw==:117 a=b9+bayejhc3NMeqCNyeLQQ==:17 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=EUspDBNiAAAA:8 a=afSGG1qtvitiuWp1rUoA:9 a=6Ab_bkdmUrQuMsNx7PHu:22 X-Proofpoint-GUID: zjotQoZSJHEKMnNHi3MABztk6q7BWHjT X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDA5MDA4MSBTYWx0ZWRfX2VRXYFiSIoMK epXEIttPXiQWQe/GdQly2ASKl9ZMODra9al4mo+sE4tCU1+mkTFfOsqhp5Yk80aWZslLcXz3jlo SylIurnrGv3VVw58S7wdPa0zXBlyxIzdMg1AnZEx52D8TXZqsQBgutpUnpkXwSgb9QueMt7BqoV 7TF6m4zOzPrmZR1IliFMmz/ObgaTHjwkudMG6thQFn9f+OWoN/wnAuvZOUaDfHMqBSx+YpXu9vk 4hIAxnJbxIJLrorTZhj2ciTV8bO+vSQ8ZrPpKgqbiVJLDzo7Sp42Iha14RSazDf/1hABWKPSjOv P13S34KzyPlpQwdSmghJgG2io9wR2mCzNUTKFKLDVHEUS871y8X1VcI7+XN4rwKeW44cH4H6UyT hZyRMiGGKzFIyYyvoJzcCBjjS28iX/CEZzhF8ysm0K4Re6jhT0Cv6HxrlVodJhVT45rv6RWhUKa y0jnXRs/ppwlVG5eucQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-09_02,2026-04-09_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 lowpriorityscore=0 malwarescore=0 priorityscore=1501 impostorscore=0 bulkscore=0 phishscore=0 spamscore=0 suspectscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604010000 definitions=main-2604090081 Content-Type: text/plain; charset="utf-8" Devicetree lemans-iq9.dtsi was created for Lemans variant where platform resource like clocks, regulator, interconnects, pinctrls and PHYs are managed by Linux. Move them from lemans.dtsi to lemans-iq9.dtsi, so that lemans.dtsi could be used by SCMI variant SoCs. ICE, GMU and PMU are completely moved to lemans-iq9.dtsi, as they do not seem to be used by SCMI variant. Signed-off-by: Shawn Guo Tested-by: Deepti Jaggi # sa8255p-ride board --- arch/arm64/boot/dts/qcom/lemans-iq9.dtsi | 2893 ++++++++++++++++++++++ arch/arm64/boot/dts/qcom/lemans.dtsi | 2603 ------------------- 2 files changed, 2893 insertions(+), 2603 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/lemans-iq9.dtsi b/arch/arm64/boot/dts= /qcom/lemans-iq9.dtsi index 5c2aa83fe8b4..68e211555909 100644 --- a/arch/arm64/boot/dts/qcom/lemans-iq9.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans-iq9.dtsi @@ -3,10 +3,2661 @@ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ =20 +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + #include "lemans.dtsi" =20 / { + clocks { + xo_board_clk: xo-board-clk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + }; + + sleep_clk: sleep-clk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + }; + }; + + cpus { + cpu0: cpu@0 { + operating-points-v2 =3D <&cpu0_opp_table>; + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3_cl0 MASTER_EPSS_L3_APPS + &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; + }; + + cpu1: cpu@100 { + operating-points-v2 =3D <&cpu0_opp_table>; + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3_cl0 MASTER_EPSS_L3_APPS + &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; + }; + + cpu2: cpu@200 { + operating-points-v2 =3D <&cpu0_opp_table>; + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3_cl0 MASTER_EPSS_L3_APPS + &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; + }; + + cpu3: cpu@300 { + operating-points-v2 =3D <&cpu0_opp_table>; + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3_cl0 MASTER_EPSS_L3_APPS + &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; + }; + + cpu4: cpu@10000 { + operating-points-v2 =3D <&cpu4_opp_table>; + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3_cl1 MASTER_EPSS_L3_APPS + &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; + }; + + cpu5: cpu@10100 { + operating-points-v2 =3D <&cpu4_opp_table>; + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3_cl1 MASTER_EPSS_L3_APPS + &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; + }; + + cpu6: cpu@10200 { + operating-points-v2 =3D <&cpu4_opp_table>; + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3_cl1 MASTER_EPSS_L3_APPS + &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; + }; + + cpu7: cpu@10300 { + operating-points-v2 =3D <&cpu4_opp_table>; + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3_cl1 MASTER_EPSS_L3_APPS + &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; + }; + }; + + cpu0_opp_table: opp-table-cpu0 { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-1267200000 { + opp-hz =3D /bits/ 64 <1267200000>; + opp-peak-kBps =3D <(1555200 * 4) (921600 * 32)>; + }; + + opp-1363200000 { + opp-hz =3D /bits/ 64 <1363200000>; + opp-peak-kBps =3D <(1555200 * 4) (921600 * 32)>; + }; + + opp-1459200000 { + opp-hz =3D /bits/ 64 <1459200000>; + opp-peak-kBps =3D <(1555200 * 4) (921600 * 32)>; + }; + + opp-1536000000 { + opp-hz =3D /bits/ 64 <1536000000>; + opp-peak-kBps =3D <(1555200 * 4) (921600 * 32)>; + }; + + opp-1632000000 { + opp-hz =3D /bits/ 64 <1632000000>; + opp-peak-kBps =3D <(1708800 * 4) (1228800 * 32)>; + }; + + opp-1708800000 { + opp-hz =3D /bits/ 64 <1708800000>; + opp-peak-kBps =3D <(1708800 * 4) (1228800 * 32)>; + }; + + opp-1785600000 { + opp-hz =3D /bits/ 64 <1785600000>; + opp-peak-kBps =3D <(1708800 * 4) (1228800 * 32)>; + }; + + opp-1862400000 { + opp-hz =3D /bits/ 64 <1862400000>; + opp-peak-kBps =3D <(1708800 * 4) (1228800 * 32)>; + }; + + opp-1939200000 { + opp-hz =3D /bits/ 64 <1939200000>; + opp-peak-kBps =3D <(1708800 * 4) (1228800 * 32)>; + }; + + opp-2016000000 { + opp-hz =3D /bits/ 64 <2016000000>; + opp-peak-kBps =3D <(1708800 * 4) (1228800 * 32)>; + }; + + opp-2112000000 { + opp-hz =3D /bits/ 64 <2112000000>; + opp-peak-kBps =3D <(2092800 * 4) (1555200 * 32)>; + }; + + opp-2188800000 { + opp-hz =3D /bits/ 64 <2188800000>; + opp-peak-kBps =3D <(2092800 * 4) (1555200 * 32)>; + }; + + opp-2265600000 { + opp-hz =3D /bits/ 64 <2265600000>; + opp-peak-kBps =3D <(2092800 * 4) (1555200 * 32)>; + }; + + opp-2361600000 { + opp-hz =3D /bits/ 64 <2361600000>; + opp-peak-kBps =3D <(3196800 * 4) (1612800 * 32)>; + }; + + opp-2457600000 { + opp-hz =3D /bits/ 64 <2457600000>; + opp-peak-kBps =3D <(3196800 * 4) (1612800 * 32)>; + }; + + opp-2553600000 { + opp-hz =3D /bits/ 64 <2553600000>; + opp-peak-kBps =3D <(3196800 * 4) (1708800 * 32)>; + }; + }; + + cpu4_opp_table: opp-table-cpu4 { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-1267200000 { + opp-hz =3D /bits/ 64 <1267200000>; + opp-peak-kBps =3D <(1555200 * 4) (921600 * 32)>; + }; + + opp-1363200000 { + opp-hz =3D /bits/ 64 <1363200000>; + opp-peak-kBps =3D <(1555200 * 4) (921600 * 32)>; + }; + + opp-1459200000 { + opp-hz =3D /bits/ 64 <1459200000>; + opp-peak-kBps =3D <(1555200 * 4) (921600 * 32)>; + }; + + opp-1536000000 { + opp-hz =3D /bits/ 64 <1536000000>; + opp-peak-kBps =3D <(1555200 * 4) (921600 * 32)>; + }; + + opp-1632000000 { + opp-hz =3D /bits/ 64 <1632000000>; + opp-peak-kBps =3D <(1708800 * 4) (1228800 * 32)>; + }; + + opp-1708800000 { + opp-hz =3D /bits/ 64 <1708800000>; + opp-peak-kBps =3D <(1708800 * 4) (1228800 * 32)>; + }; + + opp-1785600000 { + opp-hz =3D /bits/ 64 <1785600000>; + opp-peak-kBps =3D <(1708800 * 4) (1228800 * 32)>; + }; + + opp-1862400000 { + opp-hz =3D /bits/ 64 <1862400000>; + opp-peak-kBps =3D <(1708800 * 4) (1228800 * 32)>; + }; + + opp-1939200000 { + opp-hz =3D /bits/ 64 <1939200000>; + opp-peak-kBps =3D <(1708800 * 4) (1228800 * 32)>; + }; + + opp-2016000000 { + opp-hz =3D /bits/ 64 <2016000000>; + opp-peak-kBps =3D <(1708800 * 4) (1228800 * 32)>; + }; + + opp-2112000000 { + opp-hz =3D /bits/ 64 <2112000000>; + opp-peak-kBps =3D <(2092800 * 4) (1555200 * 32)>; + }; + + opp-2188800000 { + opp-hz =3D /bits/ 64 <2188800000>; + opp-peak-kBps =3D <(2092800 * 4) (1555200 * 32)>; + }; + + opp-2265600000 { + opp-hz =3D /bits/ 64 <2265600000>; + opp-peak-kBps =3D <(2092800 * 4) (1555200 * 32)>; + }; + + opp-2361600000 { + opp-hz =3D /bits/ 64 <2361600000>; + opp-peak-kBps =3D <(3196800 * 4) (1612800 * 32)>; + }; + + opp-2457600000 { + opp-hz =3D /bits/ 64 <2457600000>; + opp-peak-kBps =3D <(3196800 * 4) (1612800 * 32)>; + }; + + opp-2553600000 { + opp-hz =3D /bits/ 64 <2553600000>; + opp-peak-kBps =3D <(3196800 * 4) (1708800 * 32)>; + }; + }; + + clk_virt: interconnect-clk-virt { + compatible =3D "qcom,sa8775p-clk-virt"; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + mc_virt: interconnect-mc-virt { + compatible =3D "qcom,sa8775p-mc-virt"; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + qup_opp_table_100mhz: opp-table-qup100mhz { + compatible =3D "operating-points-v2"; + + opp-100000000 { + opp-hz =3D /bits/ 64 <100000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + }; + soc: soc@0 { + gcc: clock-controller@100000 { + compatible =3D "qcom,sa8775p-gcc"; + reg =3D <0x0 0x00100000 0x0 0xc7018>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>, + <0>, + <0>, + <0>, + <&usb_0_qmpphy>, + <&usb_1_qmpphy>, + <0>, + <0>, + <0>, + <&pcie0_phy>, + <&pcie1_phy>, + <0>, + <0>, + <0>; + power-domains =3D <&rpmhpd SA8775P_CX>; + }; + + qupv3_id_2: geniqup@8c0000 { + clocks =3D <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + clock-names =3D "m-ahb", "s-ahb"; + + i2c14: i2c@880000 { + clocks =3D <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_i2c14_default>; + pinctrl-names =3D "default"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + power-domains =3D <&rpmhpd SA8775P_CX>; + }; + + spi14: spi@880000 { + clocks =3D <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_spi14_default>; + pinctrl-names =3D "default"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + power-domains =3D <&rpmhpd SA8775P_CX>; + }; + + uart14: serial@880000 { + clocks =3D <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_uart14_default>; + pinctrl-names =3D "default"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", "qup-config"; + power-domains =3D <&rpmhpd SA8775P_CX>; + }; + + i2c15: i2c@884000 { + clocks =3D <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_i2c15_default>; + pinctrl-names =3D "default"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + power-domains =3D <&rpmhpd SA8775P_CX>; + }; + + spi15: spi@884000 { + clocks =3D <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_spi15_default>; + pinctrl-names =3D "default"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + power-domains =3D <&rpmhpd SA8775P_CX>; + }; + + uart15: serial@884000 { + clocks =3D <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_uart15_default>; + pinctrl-names =3D "default"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", "qup-config"; + power-domains =3D <&rpmhpd SA8775P_CX>; + }; + + i2c16: i2c@888000 { + clocks =3D <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_i2c16_default>; + pinctrl-names =3D "default"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + power-domains =3D <&rpmhpd SA8775P_CX>; + }; + + spi16: spi@888000 { + clocks =3D <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_spi16_default>; + pinctrl-names =3D "default"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + power-domains =3D <&rpmhpd SA8775P_CX>; + }; + + uart16: serial@888000 { + clocks =3D <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_uart16_default>; + pinctrl-names =3D "default"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", "qup-config"; + power-domains =3D <&rpmhpd SA8775P_CX>; + }; + + i2c17: i2c@88c000 { + clocks =3D <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_i2c17_default>; + pinctrl-names =3D "default"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + power-domains =3D <&rpmhpd SA8775P_CX>; + }; + + spi17: spi@88c000 { + clocks =3D <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_spi17_default>; + pinctrl-names =3D "default"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + power-domains =3D <&rpmhpd SA8775P_CX>; + }; + + uart17: serial@88c000 { + clocks =3D <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_uart17_default>; + pinctrl-names =3D "default"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", "qup-config"; + power-domains =3D <&rpmhpd SA8775P_CX>; + }; + + i2c18: i2c@890000 { + clocks =3D <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_i2c18_default>; + pinctrl-names =3D "default"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + power-domains =3D <&rpmhpd SA8775P_CX>; + }; + + spi18: spi@890000 { + clocks =3D <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_spi18_default>; + pinctrl-names =3D "default"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + power-domains =3D <&rpmhpd SA8775P_CX>; + }; + + uart18: serial@890000 { + clocks =3D <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_uart18_default>; + pinctrl-names =3D "default"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", "qup-config"; + power-domains =3D <&rpmhpd SA8775P_CX>; + }; + + i2c19: i2c@894000 { + clocks =3D <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_i2c19_default>; + pinctrl-names =3D "default"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + power-domains =3D <&rpmhpd SA8775P_CX>; + }; + + spi19: spi@894000 { + clocks =3D <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_spi19_default>; + pinctrl-names =3D "default"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + power-domains =3D <&rpmhpd SA8775P_CX>; + }; + + uart19: serial@894000 { + clocks =3D <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_uart19_default>; + pinctrl-names =3D "default"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", "qup-config"; + power-domains =3D <&rpmhpd SA8775P_CX>; + }; + + i2c20: i2c@898000 { + clocks =3D <&gcc GCC_QUPV3_WRAP2_S6_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_i2c20_default>; + pinctrl-names =3D "default"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + power-domains =3D <&rpmhpd SA8775P_CX>; + }; + + spi20: spi@898000 { + clocks =3D <&gcc GCC_QUPV3_WRAP2_S6_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_spi20_default>; + pinctrl-names =3D "default"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + power-domains =3D <&rpmhpd SA8775P_CX>; + }; + + uart20: serial@898000 { + clocks =3D <&gcc GCC_QUPV3_WRAP2_S6_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_uart20_default>; + pinctrl-names =3D "default"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", "qup-config"; + power-domains =3D <&rpmhpd SA8775P_CX>; + }; + }; + + qupv3_id_0: geniqup@9c0000 { + clock-names =3D "m-ahb", "s-ahb"; + clocks =3D <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + + i2c0: i2c@980000 { + clocks =3D <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_i2c0_default>; + pinctrl-names =3D "default"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + power-domains =3D <&rpmhpd SA8775P_CX>; + }; + + spi0: spi@980000 { + clocks =3D <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_spi0_default>; + pinctrl-names =3D "default"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + power-domains =3D <&rpmhpd SA8775P_CX>; + }; + + uart0: serial@980000 { + clocks =3D <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_uart0_default>; + pinctrl-names =3D "default"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", "qup-config"; + power-domains =3D <&rpmhpd SA8775P_CX>; + }; + + i2c1: i2c@984000 { + clocks =3D <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_i2c1_default>; + pinctrl-names =3D "default"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + power-domains =3D <&rpmhpd SA8775P_CX>; + }; + + spi1: spi@984000 { + clocks =3D <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_spi1_default>; + pinctrl-names =3D "default"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + power-domains =3D <&rpmhpd SA8775P_CX>; + }; + + uart1: serial@984000 { + clocks =3D <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_uart1_default>; + pinctrl-names =3D "default"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", "qup-config"; + power-domains =3D <&rpmhpd SA8775P_CX>; + }; + + i2c2: i2c@988000 { + clocks =3D <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_i2c2_default>; + pinctrl-names =3D "default"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + power-domains =3D <&rpmhpd SA8775P_CX>; + }; + + spi2: spi@988000 { + clocks =3D <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_spi2_default>; + pinctrl-names =3D "default"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + power-domains =3D <&rpmhpd SA8775P_CX>; + }; + + uart2: serial@988000 { + clocks =3D <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_uart2_default>; + pinctrl-names =3D "default"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", "qup-config"; + power-domains =3D <&rpmhpd SA8775P_CX>; + }; + + i2c3: i2c@98c000 { + clocks =3D <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_i2c3_default>; + pinctrl-names =3D "default"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + power-domains =3D <&rpmhpd SA8775P_CX>; + }; + + spi3: spi@98c000 { + clocks =3D <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_spi3_default>; + pinctrl-names =3D "default"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + power-domains =3D <&rpmhpd SA8775P_CX>; + }; + + uart3: serial@98c000 { + clocks =3D <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_uart3_default>; + pinctrl-names =3D "default"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", "qup-config"; + power-domains =3D <&rpmhpd SA8775P_CX>; + }; + + i2c4: i2c@990000 { + clocks =3D <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_i2c4_default>; + pinctrl-names =3D "default"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + power-domains =3D <&rpmhpd SA8775P_CX>; + }; + + spi4: spi@990000 { + clocks =3D <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_spi4_default>; + pinctrl-names =3D "default"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + power-domains =3D <&rpmhpd SA8775P_CX>; + }; + + uart4: serial@990000 { + clocks =3D <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_uart4_default>; + pinctrl-names =3D "default"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", "qup-config"; + power-domains =3D <&rpmhpd SA8775P_CX>; + }; + + i2c5: i2c@994000 { + clocks =3D <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_i2c5_default>; + pinctrl-names =3D "default"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + power-domains =3D <&rpmhpd SA8775P_CX>; + }; + + spi5: spi@994000 { + clocks =3D <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_spi5_default>; + pinctrl-names =3D "default"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + power-domains =3D <&rpmhpd SA8775P_CX>; + }; + + uart5: serial@994000 { + clocks =3D <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_uart5_default>; + pinctrl-names =3D "default"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", "qup-config"; + power-domains =3D <&rpmhpd SA8775P_CX>; + }; + }; + + qupv3_id_1: geniqup@ac0000 { + clock-names =3D "m-ahb", "s-ahb"; + clocks =3D <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + + i2c7: i2c@a80000 { + clocks =3D <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_i2c7_default>; + pinctrl-names =3D "default"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + power-domains =3D <&rpmhpd SA8775P_CX>; + }; + + spi7: spi@a80000 { + clocks =3D <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_spi7_default>; + pinctrl-names =3D "default"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + power-domains =3D <&rpmhpd SA8775P_CX>; + }; + + uart7: serial@a80000 { + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + pinctrl-0 =3D <&qup_uart7_default>; + pinctrl-names =3D "default"; + interconnect-names =3D "qup-core", "qup-config"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; + power-domains =3D <&rpmhpd SA8775P_CX>; + operating-points-v2 =3D <&qup_opp_table_100mhz>; + }; + + i2c8: i2c@a84000 { + clocks =3D <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_i2c8_default>; + pinctrl-names =3D "default"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + power-domains =3D <&rpmhpd SA8775P_CX>; + }; + + spi8: spi@a84000 { + clocks =3D <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_spi8_default>; + pinctrl-names =3D "default"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + power-domains =3D <&rpmhpd SA8775P_CX>; + }; + + uart8: serial@a84000 { + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + pinctrl-0 =3D <&qup_uart8_default>; + pinctrl-names =3D "default"; + interconnect-names =3D "qup-core", "qup-config"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; + power-domains =3D <&rpmhpd SA8775P_CX>; + operating-points-v2 =3D <&qup_opp_table_100mhz>; + }; + + i2c9: i2c@a88000 { + clocks =3D <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_i2c9_default>; + pinctrl-names =3D "default"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + power-domains =3D <&rpmhpd SA8775P_CX>; + }; + + spi9: spi@a88000 { + clocks =3D <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_spi9_default>; + pinctrl-names =3D "default"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + power-domains =3D <&rpmhpd SA8775P_CX>; + }; + + uart9: serial@a88000 { + clocks =3D <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_uart9_default>; + pinctrl-names =3D "default"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", "qup-config"; + power-domains =3D <&rpmhpd SA8775P_CX>; + }; + + i2c10: i2c@a8c000 { + clocks =3D <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_i2c10_default>; + pinctrl-names =3D "default"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + power-domains =3D <&rpmhpd SA8775P_CX>; + }; + + spi10: spi@a8c000 { + clocks =3D <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_spi10_default>; + pinctrl-names =3D "default"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + power-domains =3D <&rpmhpd SA8775P_CX>; + }; + + uart10: serial@a8c000 { + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + pinctrl-0 =3D <&qup_uart10_default>; + pinctrl-names =3D "default"; + interconnect-names =3D "qup-core", "qup-config"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 + &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 + &config_noc SLAVE_QUP_1 0>; + power-domains =3D <&rpmhpd SA8775P_CX>; + operating-points-v2 =3D <&qup_opp_table_100mhz>; + }; + + i2c11: i2c@a90000 { + clocks =3D <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_i2c11_default>; + pinctrl-names =3D "default"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + power-domains =3D <&rpmhpd SA8775P_CX>; + }; + + spi11: spi@a90000 { + clocks =3D <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_spi11_default>; + pinctrl-names =3D "default"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + power-domains =3D <&rpmhpd SA8775P_CX>; + }; + + uart11: serial@a90000 { + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + pinctrl-0 =3D <&qup_uart11_default>; + pinctrl-names =3D "default"; + interconnect-names =3D "qup-core", "qup-config"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; + power-domains =3D <&rpmhpd SA8775P_CX>; + operating-points-v2 =3D <&qup_opp_table_100mhz>; + }; + + i2c12: i2c@a94000 { + clocks =3D <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_i2c12_default>; + pinctrl-names =3D "default"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + power-domains =3D <&rpmhpd SA8775P_CX>; + }; + + spi12: spi@a94000 { + clocks =3D <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_spi12_default>; + pinctrl-names =3D "default"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + power-domains =3D <&rpmhpd SA8775P_CX>; + }; + + uart12: serial@a94000 { + clocks =3D <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_uart12_default>; + pinctrl-names =3D "default"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", "qup-config"; + power-domains =3D <&rpmhpd SA8775P_CX>; + }; + + i2c13: i2c@a98000 { + clocks =3D <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_i2c13_default>; + pinctrl-names =3D "default"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + power-domains =3D <&rpmhpd SA8775P_CX>; + }; + }; + + qupv3_id_3: geniqup@bc0000 { + clock-names =3D "m-ahb", "s-ahb"; + clocks =3D <&gcc GCC_QUPV3_WRAP_3_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_3_S_AHB_CLK>; + + i2c21: i2c@b80000 { + clocks =3D <&gcc GCC_QUPV3_WRAP3_S0_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_i2c21_default>; + pinctrl-names =3D "default"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + power-domains =3D <&rpmhpd SA8775P_CX>; + }; + + spi21: spi@b80000 { + clocks =3D <&gcc GCC_QUPV3_WRAP3_S0_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_spi21_default>; + pinctrl-names =3D "default"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + power-domains =3D <&rpmhpd SA8775P_CX>; + }; + + uart21: serial@b80000 { + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP3_S0_CLK>; + interconnect-names =3D "qup-core", "qup-config"; + pinctrl-0 =3D <&qup_uart21_default>; + pinctrl-names =3D "default"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>; + power-domains =3D <&rpmhpd SA8775P_CX>; + operating-points-v2 =3D <&qup_opp_table_100mhz>; + }; + }; + + config_noc: interconnect@14c0000 { + compatible =3D "qcom,sa8775p-config-noc"; + reg =3D <0x0 0x014c0000 0x0 0x13080>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + system_noc: interconnect@1680000 { + compatible =3D "qcom,sa8775p-system-noc"; + reg =3D <0x0 0x01680000 0x0 0x15080>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + aggre1_noc: interconnect@16c0000 { + compatible =3D "qcom,sa8775p-aggre1-noc"; + reg =3D <0x0 0x016c0000 0x0 0x18080>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + clocks =3D <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_QUPV3_AXI_CLK>, + <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>; + }; + + aggre2_noc: interconnect@1700000 { + compatible =3D "qcom,sa8775p-aggre2-noc"; + reg =3D <0x0 0x01700000 0x0 0x1b080>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + clocks =3D <&gcc GCC_AGGRE_UFS_CARD_AXI_CLK>, + <&rpmhcc RPMH_IPA_CLK>; + }; + + pcie_anoc: interconnect@1760000 { + compatible =3D "qcom,sa8775p-pcie-anoc"; + reg =3D <0x0 0x01760000 0x0 0xc080>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + gpdsp_anoc: interconnect@1780000 { + compatible =3D "qcom,sa8775p-gpdsp-anoc"; + reg =3D <0x0 0x01780000 0x0 0xe080>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + mmss_noc: interconnect@17a0000 { + compatible =3D "qcom,sa8775p-mmss-noc"; + reg =3D <0x0 0x017a0000 0x0 0x40000>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + pcie0: pcie@1c00000 { + clocks =3D <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; + clock-names =3D "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a"; + + assigned-clocks =3D <&gcc GCC_PCIE_0_AUX_CLK>; + assigned-clock-rates =3D <19200000>; + + interconnects =3D <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>; + interconnect-names =3D "pcie-mem", "cpu-pcie"; + + resets =3D <&gcc GCC_PCIE_0_BCR>, + <&gcc GCC_PCIE_0_LINK_DOWN_BCR>; + reset-names =3D "pci", + "link_down"; + + power-domains =3D <&gcc PCIE_0_GDSC>; + + phys =3D <&pcie0_phy>; + phy-names =3D "pciephy"; + }; + + pcie0_ep: pcie-ep@1c00000 { + clocks =3D <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; + clock-names =3D "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a"; + + interconnects =3D <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>; + interconnect-names =3D "pcie-mem", "cpu-pcie"; + + resets =3D <&gcc GCC_PCIE_0_BCR>; + reset-names =3D "core"; + + power-domains =3D <&gcc PCIE_0_GDSC>; + + phys =3D <&pcie0_phy>; + phy-names =3D "pciephy"; + }; + + pcie0_phy: phy@1c04000 { + compatible =3D "qcom,sa8775p-qmp-gen4x2-pcie-phy"; + reg =3D <0x0 0x1c04000 0x0 0x2000>; + + clocks =3D <&gcc GCC_PCIE_0_PHY_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_CLKREF_EN>, + <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_0_PIPE_CLK>, + <&gcc GCC_PCIE_0_PIPEDIV2_CLK>; + clock-names =3D "aux", + "cfg_ahb", + "ref", + "rchng", + "pipe", + "pipediv2"; + + assigned-clocks =3D <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; + assigned-clock-rates =3D <100000000>; + + resets =3D <&gcc GCC_PCIE_0_PHY_BCR>; + reset-names =3D "phy"; + + #clock-cells =3D <0>; + clock-output-names =3D "pcie_0_pipe_clk"; + + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + + pcie1: pcie@1c10000 { + clocks =3D <&gcc GCC_PCIE_1_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>; + clock-names =3D "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a"; + + assigned-clocks =3D <&gcc GCC_PCIE_1_AUX_CLK>; + assigned-clock-rates =3D <19200000>; + + interconnects =3D <&pcie_anoc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>; + interconnect-names =3D "pcie-mem", "cpu-pcie"; + + resets =3D <&gcc GCC_PCIE_1_BCR>, + <&gcc GCC_PCIE_1_LINK_DOWN_BCR>; + reset-names =3D "pci", + "link_down"; + + power-domains =3D <&gcc PCIE_1_GDSC>; + + phys =3D <&pcie1_phy>; + phy-names =3D "pciephy"; + }; + + pcie1_ep: pcie-ep@1c10000 { + clocks =3D <&gcc GCC_PCIE_1_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>; + clock-names =3D "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a"; + + interconnects =3D <&pcie_anoc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>; + interconnect-names =3D "pcie-mem", "cpu-pcie"; + + resets =3D <&gcc GCC_PCIE_1_BCR>; + reset-names =3D "core"; + + power-domains =3D <&gcc PCIE_1_GDSC>; + + phys =3D <&pcie1_phy>; + phy-names =3D "pciephy"; + }; + + pcie1_phy: phy@1c14000 { + compatible =3D "qcom,sa8775p-qmp-gen4x4-pcie-phy"; + reg =3D <0x0 0x1c14000 0x0 0x4000>; + + clocks =3D <&gcc GCC_PCIE_1_PHY_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_CLKREF_EN>, + <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_1_PIPE_CLK>, + <&gcc GCC_PCIE_1_PIPEDIV2_CLK>; + clock-names =3D "aux", + "cfg_ahb", + "ref", + "rchng", + "pipe", + "pipediv2"; + + assigned-clocks =3D <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; + assigned-clock-rates =3D <100000000>; + + resets =3D <&gcc GCC_PCIE_1_PHY_BCR>; + reset-names =3D "phy"; + + #clock-cells =3D <0>; + clock-output-names =3D "pcie_1_pipe_clk"; + + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + + ufs_mem_hc: ufshc@1d84000 { + phys =3D <&ufs_mem_phy>; + phy-names =3D "ufsphy"; + #reset-cells =3D <1>; + resets =3D <&gcc GCC_UFS_PHY_BCR>; + reset-names =3D "rst"; + power-domains =3D <&gcc UFS_PHY_GDSC>; + required-opps =3D <&rpmhpd_opp_nom>; + clocks =3D <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + clock-names =3D "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + freq-table-hz =3D <75000000 300000000>, + <0 0>, + <0 0>, + <75000000 300000000>, + <0 0>, + <0 0>, + <0 0>, + <0 0>; + qcom,ice =3D <&ice>; + }; + + ufs_mem_phy: phy@1d87000 { + compatible =3D "qcom,sa8775p-qmp-ufs-phy"; + reg =3D <0x0 0x01d87000 0x0 0xe10>; + /* + * Yes, GCC_EDP_REF_CLKREF_EN is correct in qref. It + * enables the CXO clock to eDP *and* UFS PHY. + */ + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, + <&gcc GCC_EDP_REF_CLKREF_EN>; + clock-names =3D "ref", "ref_aux", "qref"; + power-domains =3D <&gcc UFS_PHY_GDSC>; + resets =3D <&ufs_mem_hc 0>; + reset-names =3D "ufsphy"; + #phy-cells =3D <0>; + status =3D "disabled"; + }; + + ice: crypto@1d88000 { + compatible =3D "qcom,sa8775p-inline-crypto-engine", + "qcom,inline-crypto-engine"; + reg =3D <0x0 0x01d88000 0x0 0x18000>; + clocks =3D <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + }; + + crypto: crypto@1dfa000 { + interconnects =3D <&aggre2_noc MASTER_CRYPTO_CORE0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "memory"; + }; + + lpass_ag_noc: interconnect@3c40000 { + compatible =3D "qcom,sa8775p-lpass-ag-noc"; + reg =3D <0x0 0x03c40000 0x0 0x17200>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + sdhc: mmc@87c4000 { + clocks =3D <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>; + clock-names =3D "iface", + "core"; + + interconnects =3D <&aggre1_noc MASTER_SDC QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_SDC1 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "sdhc-ddr", + "cpu-sdhc"; + + operating-points-v2 =3D <&sdhc_opp_table>; + power-domains =3D <&rpmhpd SA8775P_CX>; + resets =3D <&gcc GCC_SDCC1_BCR>; + + sdhc_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-100000000 { + opp-hz =3D /bits/ 64 <100000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <1800000 400000>; + opp-avg-kBps =3D <100000 0>; + }; + + opp-384000000 { + opp-hz =3D /bits/ 64 <384000000>; + required-opps =3D <&rpmhpd_opp_nom>; + opp-peak-kBps =3D <5400000 1600000>; + opp-avg-kBps =3D <390000 0>; + }; + }; + }; + + usb_0_hsphy: phy@88e4000 { + compatible =3D "qcom,sa8775p-usb-hs-phy", + "qcom,usb-snps-hs-5nm-phy"; + reg =3D <0 0x088e4000 0 0x120>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "ref"; + resets =3D <&gcc GCC_USB2_PHY_PRIM_BCR>; + + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + + usb_1_hsphy: phy@88e6000 { + compatible =3D "qcom,sa8775p-usb-hs-phy", + "qcom,usb-snps-hs-5nm-phy"; + reg =3D <0 0x088e6000 0 0x120>; + clocks =3D <&gcc GCC_USB_CLKREF_EN>; + clock-names =3D "ref"; + resets =3D <&gcc GCC_USB2_PHY_SEC_BCR>; + + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + + usb_2_hsphy: phy@88e7000 { + compatible =3D "qcom,sa8775p-usb-hs-phy", + "qcom,usb-snps-hs-5nm-phy"; + reg =3D <0 0x088e7000 0 0x120>; + clocks =3D <&gcc GCC_USB_CLKREF_EN>; + clock-names =3D "ref"; + resets =3D <&gcc GCC_USB3_PHY_TERT_BCR>; + + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + + usb_0_qmpphy: phy@88e8000 { + compatible =3D "qcom,sa8775p-qmp-usb3-uni-phy"; + reg =3D <0 0x088e8000 0 0x2000>; + + clocks =3D <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, + <&gcc GCC_USB_CLKREF_EN>, + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; + clock-names =3D "aux", "ref", "com_aux", "pipe"; + + resets =3D <&gcc GCC_USB3_PHY_PRIM_BCR>, + <&gcc GCC_USB3PHY_PHY_PRIM_BCR>; + reset-names =3D "phy", "phy_phy"; + + power-domains =3D <&gcc USB30_PRIM_GDSC>; + + #clock-cells =3D <0>; + clock-output-names =3D "usb3_prim_phy_pipe_clk_src"; + + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + + usb_1_qmpphy: phy@88ea000 { + compatible =3D "qcom,sa8775p-qmp-usb3-uni-phy"; + reg =3D <0 0x088ea000 0 0x2000>; + + clocks =3D <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, + <&gcc GCC_USB_CLKREF_EN>, + <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; + clock-names =3D "aux", "ref", "com_aux", "pipe"; + + resets =3D <&gcc GCC_USB3_PHY_SEC_BCR>, + <&gcc GCC_USB3PHY_PHY_SEC_BCR>; + reset-names =3D "phy", "phy_phy"; + + power-domains =3D <&gcc USB30_SEC_GDSC>; + + #clock-cells =3D <0>; + clock-output-names =3D "usb3_sec_phy_pipe_clk_src"; + + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + + refgen: regulator@891c000 { + compatible =3D "qcom,sa8775p-refgen-regulator", + "qcom,sm8250-refgen-regulator"; + reg =3D <0x0 0x0891c000 0x0 0x84>; + }; + + dc_noc: interconnect@90e0000 { + compatible =3D "qcom,sa8775p-dc-noc"; + reg =3D <0x0 0x090e0000 0x0 0x5080>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + gem_noc: interconnect@9100000 { + compatible =3D "qcom,sa8775p-gem-noc"; + reg =3D <0x0 0x09100000 0x0 0xf6080>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + usb_0: usb@a600000 { + clocks =3D <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; + clock-names =3D "cfg_noc", "core", "iface", "sleep", "mock_utmi"; + assigned-clocks =3D <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>; + assigned-clock-rates =3D <19200000>, <200000000>; + + power-domains =3D <&gcc USB30_PRIM_GDSC>; + required-opps =3D <&rpmhpd_opp_nom>; + + resets =3D <&gcc GCC_USB30_PRIM_BCR>; + + interconnects =3D <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; + interconnect-names =3D "usb-ddr", "apps-usb"; + + phys =3D <&usb_0_hsphy>, <&usb_0_qmpphy>; + phy-names =3D "usb2-phy", "usb3-phy"; + }; + + usb_1: usb@a800000 { + clocks =3D <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, + <&gcc GCC_USB30_SEC_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, + <&gcc GCC_USB30_SEC_SLEEP_CLK>, + <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>; + clock-names =3D "cfg_noc", "core", "iface", "sleep", "mock_utmi"; + + assigned-clocks =3D <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_SEC_MASTER_CLK>; + assigned-clock-rates =3D <19200000>, <200000000>; + + power-domains =3D <&gcc USB30_SEC_GDSC>; + required-opps =3D <&rpmhpd_opp_nom>; + + resets =3D <&gcc GCC_USB30_SEC_BCR>; + + interconnects =3D <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>; + interconnect-names =3D "usb-ddr", "apps-usb"; + + phys =3D <&usb_1_hsphy>, <&usb_1_qmpphy>; + phy-names =3D "usb2-phy", "usb3-phy"; + }; + + usb_2: usb@a400000 { + clocks =3D <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>, + <&gcc GCC_USB20_MASTER_CLK>, + <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>, + <&gcc GCC_USB20_SLEEP_CLK>, + <&gcc GCC_USB20_MOCK_UTMI_CLK>; + clock-names =3D "cfg_noc", "core", "iface", "sleep", "mock_utmi"; + + assigned-clocks =3D <&gcc GCC_USB20_MOCK_UTMI_CLK>, + <&gcc GCC_USB20_MASTER_CLK>; + assigned-clock-rates =3D <19200000>, <200000000>; + + power-domains =3D <&gcc USB20_PRIM_GDSC>; + required-opps =3D <&rpmhpd_opp_nom>; + + resets =3D <&gcc GCC_USB20_PRIM_BCR>; + + interconnects =3D <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB2 0>; + interconnect-names =3D "usb-ddr", "apps-usb"; + + phys =3D <&usb_2_hsphy>; + phy-names =3D "usb2-phy"; + }; + + gpu: gpu@3d00000 { + operating-points-v2 =3D <&gpu_opp_table>; + qcom,gmu =3D <&gmu>; + interconnects =3D <&gem_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "gfx-mem"; + + gpu_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-405000000 { + opp-hz =3D /bits/ 64 <405000000>; + opp-level =3D ; + opp-peak-kBps =3D <5285156>; + opp-supported-hw =3D <0x3>; + }; + + opp-530000000 { + opp-hz =3D /bits/ 64 <530000000>; + opp-level =3D ; + opp-peak-kBps =3D <12484375>; + opp-supported-hw =3D <0x2>; + }; + + opp-676000000 { + opp-hz =3D /bits/ 64 <676000000>; + opp-level =3D ; + opp-peak-kBps =3D <8171875>; + opp-supported-hw =3D <0x1>; + }; + + opp-778000000 { + opp-hz =3D /bits/ 64 <778000000>; + opp-level =3D ; + opp-peak-kBps =3D <10687500>; + opp-supported-hw =3D <0x1>; + }; + + opp-800000000 { + opp-hz =3D /bits/ 64 <800000000>; + opp-level =3D ; + opp-peak-kBps =3D <12484375>; + opp-supported-hw =3D <0x1>; + }; + }; + }; + + gmu: gmu@3d6a000 { + compatible =3D "qcom,adreno-gmu-663.0", "qcom,adreno-gmu"; + reg =3D <0x0 0x03d6a000 0x0 0x34000>, + <0x0 0x03de0000 0x0 0x10000>, + <0x0 0x0b290000 0x0 0x10000>; + reg-names =3D "gmu", "rscc", "gmu_pdc"; + interrupts =3D , + ; + interrupt-names =3D "hfi", "gmu"; + clocks =3D <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>, + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; + clock-names =3D "gmu", + "cxo", + "axi", + "memnoc", + "ahb", + "hub", + "smmu_vote"; + power-domains =3D <&gpucc GPU_CC_CX_GDSC>, + <&gpucc GPU_CC_GX_GDSC>; + power-domain-names =3D "cx", + "gx"; + iommus =3D <&adreno_smmu 5 0xc00>; + operating-points-v2 =3D <&gmu_opp_table>; + + gmu_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-500000000 { + opp-hz =3D /bits/ 64 <500000000>; + opp-level =3D ; + }; + }; + }; + + gpucc: clock-controller@3d90000 { + compatible =3D "qcom,sa8775p-gpucc"; + reg =3D <0x0 0x03d90000 0x0 0xa000>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + clock-names =3D "bi_tcxo", + "gcc_gpu_gpll0_clk_src", + "gcc_gpu_gpll0_div_clk_src"; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + + adreno_smmu: iommu@3da0000 { + power-domains =3D <&gpucc GPU_CC_CX_GDSC>; + clocks =3D <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, + <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>, + <&gpucc GPU_CC_HUB_AON_CLK>; + clock-names =3D "gcc_gpu_memnoc_gfx_clk", + "gcc_gpu_snoc_dvm_gfx_clk", + "gpu_cc_ahb_clk", + "gpu_cc_hlos1_vote_gpu_smmu_clk", + "gpu_cc_cx_gmu_clk", + "gpu_cc_hub_cx_int_clk", + "gpu_cc_hub_aon_clk"; + }; + + serdes0: phy@8901000 { + compatible =3D "qcom,sa8775p-dwmac-sgmii-phy"; + reg =3D <0x0 0x08901000 0x0 0xe10>; + clocks =3D <&gcc GCC_SGMI_CLKREF_EN>; + clock-names =3D "sgmi_ref"; + #phy-cells =3D <0>; + status =3D "disabled"; + }; + + serdes1: phy@8902000 { + compatible =3D "qcom,sa8775p-dwmac-sgmii-phy"; + reg =3D <0x0 0x08902000 0x0 0xe10>; + clocks =3D <&gcc GCC_SGMI_CLKREF_EN>; + clock-names =3D "sgmi_ref"; + #phy-cells =3D <0>; + status =3D "disabled"; + }; + + pmu@9091000 { + compatible =3D "qcom,sa8775p-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; + reg =3D <0x0 0x9091000 0x0 0x1000>; + interrupts =3D ; + interconnects =3D <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; + + operating-points-v2 =3D <&llcc_bwmon_opp_table>; + + llcc_bwmon_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-0 { + opp-peak-kBps =3D <762000>; + }; + + opp-1 { + opp-peak-kBps =3D <1720000>; + }; + + opp-2 { + opp-peak-kBps =3D <2086000>; + }; + + opp-3 { + opp-peak-kBps =3D <2601000>; + }; + + opp-4 { + opp-peak-kBps =3D <2929000>; + }; + + opp-5 { + opp-peak-kBps =3D <5931000>; + }; + + opp-6 { + opp-peak-kBps =3D <6515000>; + }; + + opp-7 { + opp-peak-kBps =3D <7984000>; + }; + + opp-8 { + opp-peak-kBps =3D <10437000>; + }; + + opp-9 { + opp-peak-kBps =3D <12195000>; + }; + }; + }; + + pmu@90b5400 { + compatible =3D "qcom,sa8775p-cpu-bwmon", "qcom,sdm845-bwmon"; + reg =3D <0x0 0x90b5400 0x0 0x600>; + interrupts =3D ; + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; + + operating-points-v2 =3D <&cpu_bwmon_opp_table>; + + cpu_bwmon_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-0 { + opp-peak-kBps =3D <9155000>; + }; + + opp-1 { + opp-peak-kBps =3D <12298000>; + }; + + opp-2 { + opp-peak-kBps =3D <14236000>; + }; + + opp-3 { + opp-peak-kBps =3D <16265000>; + }; + }; + + }; + + pmu@90b6400 { + compatible =3D "qcom,sa8775p-cpu-bwmon", "qcom,sdm845-bwmon"; + reg =3D <0x0 0x90b6400 0x0 0x600>; + interrupts =3D ; + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; + + operating-points-v2 =3D <&cpu_bwmon_opp_table>; + }; + + iris: video-codec@aa00000 { + power-domains =3D <&videocc VIDEO_CC_MVS0C_GDSC>, + <&videocc VIDEO_CC_MVS0_GDSC>, + <&rpmhpd SA8775P_MX>, + <&rpmhpd SA8775P_MMCX>; + power-domain-names =3D "venus", + "vcodec0", + "mxc", + "mmcx"; + operating-points-v2 =3D <&iris_opp_table>; + + clocks =3D <&gcc GCC_VIDEO_AXI0_CLK>, + <&videocc VIDEO_CC_MVS0C_CLK>, + <&videocc VIDEO_CC_MVS0_CLK>; + clock-names =3D "iface", + "core", + "vcodec0_core"; + + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mmss_noc MASTER_VIDEO_P0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "cpu-cfg", + "video-mem"; + + iris_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-366000000 { + opp-hz =3D /bits/ 64 <366000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>, + <&rpmhpd_opp_svs_l1>; + }; + + opp-444000000 { + opp-hz =3D /bits/ 64 <444000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>, + <&rpmhpd_opp_nom>; + }; + + opp-533000000 { + opp-hz =3D /bits/ 64 <533000000>; + required-opps =3D <&rpmhpd_opp_nom>, + <&rpmhpd_opp_turbo>; + }; + + opp-560000000 { + opp-hz =3D /bits/ 64 <560000000>; + required-opps =3D <&rpmhpd_opp_nom>, + <&rpmhpd_opp_turbo_l1>; + }; + }; + }; + + iris: video-codec@aa00000 { + resets =3D <&gcc GCC_VIDEO_AXI0_CLK_ARES>; + reset-names =3D "bus"; + }; + + videocc: clock-controller@abf0000 { + compatible =3D "qcom,sa8775p-videocc"; + reg =3D <0x0 0x0abf0000 0x0 0x10000>; + clocks =3D <&gcc GCC_VIDEO_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>; + power-domains =3D <&rpmhpd SA8775P_MMCX>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + + cci0: cci@ac13000 { + power-domains =3D <&camcc CAM_CC_TITAN_TOP_GDSC>; + + clocks =3D <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CCI_0_CLK>; + clock-names =3D "camnoc_axi", + "cpas_ahb", + "cci"; + + pinctrl-0 =3D <&cci0_0_default &cci0_1_default>; + pinctrl-1 =3D <&cci0_0_sleep &cci0_1_sleep>; + pinctrl-names =3D "default", "sleep"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + cci0_i2c0: i2c-bus@0 { + reg =3D <0>; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + cci0_i2c1: i2c-bus@1 { + reg =3D <1>; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; + + + cci1: cci@ac14000 { + power-domains =3D <&camcc CAM_CC_TITAN_TOP_GDSC>; + + clocks =3D <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CCI_1_CLK>; + clock-names =3D "camnoc_axi", + "cpas_ahb", + "cci"; + + pinctrl-0 =3D <&cci1_0_default &cci1_1_default>; + pinctrl-1 =3D <&cci1_0_sleep &cci1_1_sleep>; + pinctrl-names =3D "default", "sleep"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + cci1_i2c0: i2c-bus@0 { + reg =3D <0>; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + cci1_i2c1: i2c-bus@1 { + reg =3D <1>; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; + + cci2: cci@ac15000 { + power-domains =3D <&camcc CAM_CC_TITAN_TOP_GDSC>; + + clocks =3D <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CCI_2_CLK>; + clock-names =3D "camnoc_axi", + "cpas_ahb", + "cci"; + + pinctrl-0 =3D <&cci2_0_default &cci2_1_default>; + pinctrl-1 =3D <&cci2_0_sleep &cci2_1_sleep>; + pinctrl-names =3D "default", "sleep"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + cci2_i2c0: i2c-bus@0 { + reg =3D <0>; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + cci2_i2c1: i2c-bus@1 { + reg =3D <1>; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; + + cci3: cci@ac16000 { + power-domains =3D <&camcc CAM_CC_TITAN_TOP_GDSC>; + + clocks =3D <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CCI_3_CLK>; + clock-names =3D "camnoc_axi", + "cpas_ahb", + "cci"; + + pinctrl-0 =3D <&cci3_0_default &cci3_1_default>; + pinctrl-1 =3D <&cci3_0_sleep &cci3_1_sleep>; + pinctrl-names =3D "default", "sleep"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + cci3_i2c0: i2c-bus@0 { + reg =3D <0>; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + cci3_i2c1: i2c-bus@1 { + reg =3D <1>; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; + + camss: isp@ac78000 { + clocks =3D <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_CORE_AHB_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CPAS_FAST_AHB_CLK>, + <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, + <&camcc CAM_CC_CPAS_IFE_0_CLK>, + <&camcc CAM_CC_CPAS_IFE_1_CLK>, + <&camcc CAM_CC_CSID_CLK>, + <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY1_CLK>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY2_CLK>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY3_CLK>, + <&camcc CAM_CC_CSI3PHYTIMER_CLK>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&gcc GCC_CAMERA_SF_AXI_CLK>, + <&camcc CAM_CC_ICP_AHB_CLK>, + <&camcc CAM_CC_IFE_0_CLK>, + <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_1_CLK>, + <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>; + clock-names =3D "camnoc_axi", + "core_ahb", + "cpas_ahb", + "cpas_fast_ahb_clk", + "cpas_vfe_lite", + "cpas_vfe0", + "cpas_vfe1", + "csid", + "csiphy0", + "csiphy0_timer", + "csiphy1", + "csiphy1_timer", + "csiphy2", + "csiphy2_timer", + "csiphy3", + "csiphy3_timer", + "csiphy_rx", + "gcc_axi_hf", + "gcc_axi_sf", + "icp_ahb", + "vfe0", + "vfe0_fast_ahb", + "vfe1", + "vfe1_fast_ahb", + "vfe_lite", + "vfe_lite_ahb", + "vfe_lite_cphy_rx", + "vfe_lite_csid"; + + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "ahb", + "hf_0"; + + power-domains =3D <&camcc CAM_CC_TITAN_TOP_GDSC>; + power-domain-names =3D "top"; + }; + + camcc: clock-controller@ade0000 { + compatible =3D "qcom,sa8775p-camcc"; + reg =3D <0x0 0x0ade0000 0x0 0x20000>; + clocks =3D <&gcc GCC_CAMERA_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>; + power-domains =3D <&rpmhpd SA8775P_MMCX>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + + mdss0: display-subsystem@ae00000 { + /* same path used twice */ + interconnects =3D <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&mmss_noc MASTER_MDP1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "mdp0-mem", + "mdp1-mem", + "cpu-cfg"; + + resets =3D <&dispcc0 MDSS_DISP_CC_MDSS_CORE_BCR>; + + power-domains =3D <&dispcc0 MDSS_DISP_CC_MDSS_CORE_GDSC>; + + clocks =3D <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_MDP_CLK>; + + mdss0_mdp: display-controller@ae01000 { + clocks =3D <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_MDP_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_VSYNC_CLK>; + clock-names =3D "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks =3D <&dispcc0 MDSS_DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates =3D <19200000>; + + operating-points-v2 =3D <&mdss0_mdp_opp_table>; + power-domains =3D <&rpmhpd SA8775P_MMCX>; + + mdss0_mdp_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-375000000 { + opp-hz =3D /bits/ 64 <375000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + + opp-500000000 { + opp-hz =3D /bits/ 64 <500000000>; + required-opps =3D <&rpmhpd_opp_nom>; + }; + + opp-575000000 { + opp-hz =3D /bits/ 64 <575000000>; + required-opps =3D <&rpmhpd_opp_turbo>; + }; + + opp-650000000 { + opp-hz =3D /bits/ 64 <650000000>; + required-opps =3D <&rpmhpd_opp_turbo_l1>; + }; + }; + }; + + mdss0_dsi0: dsi@ae94000 { + clocks =3D <&dispcc0 MDSS_DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_ESC0_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names =3D "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + assigned-clocks =3D <&dispcc0 MDSS_DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc0 MDSS_DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents =3D <&mdss0_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss0_dsi0_phy DSI_PIXEL_PLL_CLK>; + phys =3D <&mdss0_dsi0_phy>; + + operating-points-v2 =3D <&mdss_dsi_opp_table>; + power-domains =3D <&rpmhpd SA8775P_MMCX>; + + refgen-supply =3D <&refgen>; + + mdss_dsi_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-358000000 { + opp-hz =3D /bits/ 64 <358000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + mdss0_dsi0_phy: phy@ae94400 { + compatible =3D "qcom,sa8775p-dsi-phy-5nm"; + reg =3D <0x0 0x0ae94400 0x0 0x200>, + <0x0 0x0ae94600 0x0 0x280>, + <0x0 0x0ae94900 0x0 0x27c>; + reg-names =3D "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells =3D <1>; + #phy-cells =3D <0>; + + clocks =3D <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "iface", "ref"; + + status =3D "disabled"; + }; + + mdss0_dsi1: dsi@ae96000 { + clocks =3D <&dispcc0 MDSS_DISP_CC_MDSS_BYTE1_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_PCLK1_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_ESC1_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names =3D "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + assigned-clocks =3D <&dispcc0 MDSS_DISP_CC_MDSS_BYTE1_CLK_SRC>, + <&dispcc0 MDSS_DISP_CC_MDSS_PCLK1_CLK_SRC>; + assigned-clock-parents =3D <&mdss0_dsi1_phy DSI_BYTE_PLL_CLK>, + <&mdss0_dsi1_phy DSI_PIXEL_PLL_CLK>; + phys =3D <&mdss0_dsi1_phy>; + + operating-points-v2 =3D <&mdss_dsi_opp_table>; + power-domains =3D <&rpmhpd SA8775P_MMCX>; + + refgen-supply =3D <&refgen>; + }; + + mdss0_dsi1_phy: phy@ae96400 { + compatible =3D "qcom,sa8775p-dsi-phy-5nm"; + reg =3D <0x0 0x0ae96400 0x0 0x200>, + <0x0 0x0ae96600 0x0 0x280>, + <0x0 0x0ae96900 0x0 0x27c>; + reg-names =3D "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells =3D <1>; + #phy-cells =3D <0>; + + clocks =3D <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "iface", "ref"; + + status =3D "disabled"; + }; + + mdss0_dp0_phy: phy@aec2a00 { + compatible =3D "qcom,sa8775p-edp-phy"; + + reg =3D <0x0 0x0aec2a00 0x0 0x200>, + <0x0 0x0aec2200 0x0 0xd0>, + <0x0 0x0aec2600 0x0 0xd0>, + <0x0 0x0aec2000 0x0 0x1c8>; + + clocks =3D <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>; + clock-names =3D "aux", + "cfg_ahb"; + + #clock-cells =3D <1>; + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + + mdss0_dp1_phy: phy@aec5a00 { + compatible =3D "qcom,sa8775p-edp-phy"; + + reg =3D <0x0 0x0aec5a00 0x0 0x200>, + <0x0 0x0aec5200 0x0 0xd0>, + <0x0 0x0aec5600 0x0 0xd0>, + <0x0 0x0aec5000 0x0 0x1c8>; + + clocks =3D <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>; + clock-names =3D "aux", + "cfg_ahb"; + + #clock-cells =3D <1>; + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + + mdss0_dp0: displayport-controller@af54000 { + clocks =3D <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK>; + clock-names =3D "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel", + "stream_1_pixel", + "stream_2_pixel", + "stream_3_pixel"; + assigned-clocks =3D <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK_SRC>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK_SRC>; + assigned-clock-parents =3D <&mdss0_dp0_phy 0>, + <&mdss0_dp0_phy 1>, + <&mdss0_dp0_phy 1>, + <&mdss0_dp0_phy 1>, + <&mdss0_dp0_phy 1>; + phys =3D <&mdss0_dp0_phy>; + phy-names =3D "dp"; + + operating-points-v2 =3D <&dp_opp_table>; + power-domains =3D <&rpmhpd SA8775P_MMCX>; + + dp_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-162000000 { + opp-hz =3D /bits/ 64 <162000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz =3D /bits/ 64 <270000000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz =3D /bits/ 64 <540000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz =3D /bits/ 64 <810000000>; + required-opps =3D <&rpmhpd_opp_nom>; + }; + }; + }; + + mdss0_dp1: displayport-controller@af5c000 { + clocks =3D <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK>; + clock-names =3D "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel", + "stream_1_pixel"; + assigned-clocks =3D <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>; + assigned-clock-parents =3D <&mdss0_dp1_phy 0>, + <&mdss0_dp1_phy 1>, + <&mdss0_dp1_phy 1>; + phys =3D <&mdss0_dp1_phy>; + phy-names =3D "dp"; + + operating-points-v2 =3D <&dp1_opp_table>; + power-domains =3D <&rpmhpd SA8775P_MMCX>; + + dp1_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-162000000 { + opp-hz =3D /bits/ 64 <162000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz =3D /bits/ 64 <270000000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz =3D /bits/ 64 <540000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz =3D /bits/ 64 <810000000>; + required-opps =3D <&rpmhpd_opp_nom>; + }; + }; + }; + }; + + dispcc0: clock-controller@af00000 { + compatible =3D "qcom,sa8775p-dispcc0"; + reg =3D <0x0 0x0af00000 0x0 0x20000>; + clocks =3D <&gcc GCC_DISP_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>, + <&mdss0_dp0_phy 0>, <&mdss0_dp0_phy 1>, + <&mdss0_dp1_phy 0>, <&mdss0_dp1_phy 1>, + <&mdss0_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss0_dsi0_phy DSI_PIXEL_PLL_CLK>, + <&mdss0_dsi1_phy DSI_BYTE_PLL_CLK>, + <&mdss0_dsi1_phy DSI_PIXEL_PLL_CLK>; + power-domains =3D <&rpmhpd SA8775P_MMCX>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + tlmm: pinctrl@f000000 { dp0_hot_plug_det: dp0-hot-plug-det-state { pins =3D "gpio101"; @@ -814,5 +3465,247 @@ data-pins { }; }; }; + + apps_rsc: rsc@18200000 { + compatible =3D "qcom,rpmh-rsc"; + reg =3D <0x0 0x18200000 0x0 0x10000>, + <0x0 0x18210000 0x0 0x10000>, + <0x0 0x18220000 0x0 0x10000>; + reg-names =3D "drv-0", "drv-1", "drv-2"; + interrupts =3D , + , + ; + qcom,tcs-offset =3D <0xd00>; + qcom,drv-id =3D <2>; + qcom,tcs-config =3D , + , + , + ; + label =3D "apps_rsc"; + power-domains =3D <&system_pd>; + + apps_bcm_voter: bcm-voter { + compatible =3D "qcom,bcm-voter"; + }; + + rpmhcc: clock-controller { + compatible =3D "qcom,sa8775p-rpmh-clk"; + #clock-cells =3D <1>; + clock-names =3D "xo"; + clocks =3D <&xo_board_clk>; + }; + + rpmhpd: power-controller { + compatible =3D "qcom,sa8775p-rpmhpd"; + #power-domain-cells =3D <1>; + operating-points-v2 =3D <&rpmhpd_opp_table>; + + rpmhpd_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + rpmhpd_opp_ret: opp-0 { + opp-level =3D ; + }; + + rpmhpd_opp_min_svs: opp-1 { + opp-level =3D ; + }; + + rpmhpd_opp_low_svs: opp2 { + opp-level =3D ; + }; + + rpmhpd_opp_svs: opp3 { + opp-level =3D ; + }; + + rpmhpd_opp_svs_l1: opp-4 { + opp-level =3D ; + }; + + rpmhpd_opp_nom: opp-5 { + opp-level =3D ; + }; + + rpmhpd_opp_nom_l1: opp-6 { + opp-level =3D ; + }; + + rpmhpd_opp_nom_l2: opp-7 { + opp-level =3D ; + }; + + rpmhpd_opp_turbo: opp-8 { + opp-level =3D ; + }; + + rpmhpd_opp_turbo_l1: opp-9 { + opp-level =3D ; + }; + }; + }; + }; + + epss_l3_cl0: interconnect@18590000 { + compatible =3D "qcom,sa8775p-epss-l3", + "qcom,epss-l3"; + reg =3D <0x0 0x18590000 0x0 0x1000>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; + clock-names =3D "xo", "alternate"; + #interconnect-cells =3D <1>; + }; + + cpufreq_hw: cpufreq@18591000 { + clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; + clock-names =3D "xo", "alternate"; + }; + + epss_l3_cl1: interconnect@18592000 { + compatible =3D "qcom,sa8775p-epss-l3", + "qcom,epss-l3"; + reg =3D <0x0 0x18592000 0x0 0x1000>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; + clock-names =3D "xo", "alternate"; + #interconnect-cells =3D <1>; + }; + + remoteproc_gpdsp0: remoteproc@20c00000 { + clocks =3D <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "xo"; + + power-domains =3D <&rpmhpd SA8775P_CX>, + <&rpmhpd SA8775P_MXC>; + power-domain-names =3D "cx", "mxc"; + + interconnects =3D <&gpdsp_anoc MASTER_DSP0 0 + &config_noc SLAVE_CLK_CTL 0>; + }; + + remoteproc_gpdsp1: remoteproc@21c00000 { + clocks =3D <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "xo"; + + power-domains =3D <&rpmhpd SA8775P_CX>, + <&rpmhpd SA8775P_MXC>; + power-domain-names =3D "cx", "mxc"; + + interconnects =3D <&gpdsp_anoc MASTER_DSP1 0 + &config_noc SLAVE_CLK_CTL 0>; + }; + + dispcc1: clock-controller@22100000 { + compatible =3D "qcom,sa8775p-dispcc1"; + reg =3D <0x0 0x22100000 0x0 0x20000>; + clocks =3D <&gcc GCC_DISP_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>, + <0>, <0>, <0>, <0>, + <0>, <0>, <0>, <0>; + power-domains =3D <&rpmhpd SA8775P_MMCX>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + status =3D "disabled"; + }; + + ethernet1: ethernet@23000000 { + clocks =3D <&gcc GCC_EMAC1_AXI_CLK>, + <&gcc GCC_EMAC1_SLV_AHB_CLK>, + <&gcc GCC_EMAC1_PTP_CLK>, + <&gcc GCC_EMAC1_PHY_AUX_CLK>; + clock-names =3D "stmmaceth", + "pclk", + "ptp_ref", + "phyaux"; + + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_EMAC1_CFG QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_EMAC_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "cpu-mac", + "mac-mem"; + + power-domains =3D <&gcc EMAC1_GDSC>; + + phys =3D <&serdes1>; + phy-names =3D "serdes"; + }; + + ethernet0: ethernet@23040000 { + clocks =3D <&gcc GCC_EMAC0_AXI_CLK>, + <&gcc GCC_EMAC0_SLV_AHB_CLK>, + <&gcc GCC_EMAC0_PTP_CLK>, + <&gcc GCC_EMAC0_PHY_AUX_CLK>; + clock-names =3D "stmmaceth", + "pclk", + "ptp_ref", + "phyaux"; + + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_EMAC_CFG QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_EMAC QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "cpu-mac", + "mac-mem"; + + power-domains =3D <&gcc EMAC0_GDSC>; + + phys =3D <&serdes0>; + phy-names =3D "serdes"; + }; + + nspa_noc: interconnect@260c0000 { + compatible =3D "qcom,sa8775p-nspa-noc"; + reg =3D <0x0 0x260c0000 0x0 0x16080>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + remoteproc_cdsp0: remoteproc@26300000 { + clocks =3D <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "xo"; + + power-domains =3D <&rpmhpd SA8775P_CX>, + <&rpmhpd SA8775P_MXC>, + <&rpmhpd SA8775P_NSP0>; + power-domain-names =3D "cx", "mxc", "nsp"; + + interconnects =3D <&nspa_noc MASTER_CDSP_PROC 0 + &mc_virt SLAVE_EBI1 0>; + }; + + nspb_noc: interconnect@2a0c0000 { + compatible =3D "qcom,sa8775p-nspb-noc"; + reg =3D <0x0 0x2a0c0000 0x0 0x16080>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + remoteproc_cdsp1: remoteproc@2a300000 { + clocks =3D <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "xo"; + + power-domains =3D <&rpmhpd SA8775P_CX>, + <&rpmhpd SA8775P_MXC>, + <&rpmhpd SA8775P_NSP1>; + power-domain-names =3D "cx", "mxc", "nsp"; + + interconnects =3D <&nspb_noc MASTER_CDSP_PROC_B 0 + &mc_virt SLAVE_EBI1 0>; + }; + + remoteproc_adsp: remoteproc@30000000 { + clocks =3D <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "xo"; + + power-domains =3D <&rpmhpd SA8775P_LCX>, + <&rpmhpd SA8775P_LMX>; + power-domain-names =3D "lcx", "lmx"; + + interconnects =3D <&lpass_ag_noc MASTER_LPASS_PROC 0 + &mc_virt SLAVE_EBI1 0>; + + }; }; }; diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qco= m/lemans.dtsi index fa2f20a7b11f..099754e3bdfa 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -4,23 +4,11 @@ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. */ =20 -#include #include -#include -#include -#include -#include -#include -#include -#include #include -#include -#include #include #include -#include #include -#include #include =20 / { @@ -29,18 +17,6 @@ / { #address-cells =3D <2>; #size-cells =3D <2>; =20 - clocks { - xo_board_clk: xo-board-clk { - compatible =3D "fixed-clock"; - #clock-cells =3D <0>; - }; - - sleep_clk: sleep-clk { - compatible =3D "fixed-clock"; - #clock-cells =3D <0>; - }; - }; - cpus { #address-cells =3D <2>; #size-cells =3D <0>; @@ -57,11 +33,6 @@ cpu0: cpu@0 { capacity-dmips-mhz =3D <1024>; #cooling-cells =3D <2>; dynamic-power-coefficient =3D <100>; - operating-points-v2 =3D <&cpu0_opp_table>; - interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, - <&epss_l3_cl0 MASTER_EPSS_L3_APPS - &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; l2_0: l2-cache { compatible =3D "cache"; cache-level =3D <2>; @@ -87,11 +58,6 @@ cpu1: cpu@100 { capacity-dmips-mhz =3D <1024>; #cooling-cells =3D <2>; dynamic-power-coefficient =3D <100>; - operating-points-v2 =3D <&cpu0_opp_table>; - interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, - <&epss_l3_cl0 MASTER_EPSS_L3_APPS - &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; l2_1: l2-cache { compatible =3D "cache"; cache-level =3D <2>; @@ -112,11 +78,6 @@ cpu2: cpu@200 { capacity-dmips-mhz =3D <1024>; #cooling-cells =3D <2>; dynamic-power-coefficient =3D <100>; - operating-points-v2 =3D <&cpu0_opp_table>; - interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, - <&epss_l3_cl0 MASTER_EPSS_L3_APPS - &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; l2_2: l2-cache { compatible =3D "cache"; cache-level =3D <2>; @@ -137,11 +98,6 @@ cpu3: cpu@300 { capacity-dmips-mhz =3D <1024>; #cooling-cells =3D <2>; dynamic-power-coefficient =3D <100>; - operating-points-v2 =3D <&cpu0_opp_table>; - interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, - <&epss_l3_cl0 MASTER_EPSS_L3_APPS - &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; l2_3: l2-cache { compatible =3D "cache"; cache-level =3D <2>; @@ -162,11 +118,6 @@ cpu4: cpu@10000 { capacity-dmips-mhz =3D <1024>; #cooling-cells =3D <2>; dynamic-power-coefficient =3D <100>; - operating-points-v2 =3D <&cpu4_opp_table>; - interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, - <&epss_l3_cl1 MASTER_EPSS_L3_APPS - &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; l2_4: l2-cache { compatible =3D "cache"; cache-level =3D <2>; @@ -193,11 +144,6 @@ cpu5: cpu@10100 { capacity-dmips-mhz =3D <1024>; #cooling-cells =3D <2>; dynamic-power-coefficient =3D <100>; - operating-points-v2 =3D <&cpu4_opp_table>; - interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, - <&epss_l3_cl1 MASTER_EPSS_L3_APPS - &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; l2_5: l2-cache { compatible =3D "cache"; cache-level =3D <2>; @@ -218,11 +164,6 @@ cpu6: cpu@10200 { capacity-dmips-mhz =3D <1024>; #cooling-cells =3D <2>; dynamic-power-coefficient =3D <100>; - operating-points-v2 =3D <&cpu4_opp_table>; - interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, - <&epss_l3_cl1 MASTER_EPSS_L3_APPS - &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; l2_6: l2-cache { compatible =3D "cache"; cache-level =3D <2>; @@ -243,11 +184,6 @@ cpu7: cpu@10300 { capacity-dmips-mhz =3D <1024>; #cooling-cells =3D <2>; dynamic-power-coefficient =3D <100>; - operating-points-v2 =3D <&cpu4_opp_table>; - interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, - <&epss_l3_cl1 MASTER_EPSS_L3_APPS - &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; l2_7: l2-cache { compatible =3D "cache"; cache-level =3D <2>; @@ -337,176 +273,6 @@ cluster_sleep_apss_rsc_pc: cluster-sleep-1 { }; }; =20 - cpu0_opp_table: opp-table-cpu0 { - compatible =3D "operating-points-v2"; - opp-shared; - - opp-1267200000 { - opp-hz =3D /bits/ 64 <1267200000>; - opp-peak-kBps =3D <(1555200 * 4) (921600 * 32)>; - }; - - opp-1363200000 { - opp-hz =3D /bits/ 64 <1363200000>; - opp-peak-kBps =3D <(1555200 * 4) (921600 * 32)>; - }; - - opp-1459200000 { - opp-hz =3D /bits/ 64 <1459200000>; - opp-peak-kBps =3D <(1555200 * 4) (921600 * 32)>; - }; - - opp-1536000000 { - opp-hz =3D /bits/ 64 <1536000000>; - opp-peak-kBps =3D <(1555200 * 4) (921600 * 32)>; - }; - - opp-1632000000 { - opp-hz =3D /bits/ 64 <1632000000>; - opp-peak-kBps =3D <(1708800 * 4) (1228800 * 32)>; - }; - - opp-1708800000 { - opp-hz =3D /bits/ 64 <1708800000>; - opp-peak-kBps =3D <(1708800 * 4) (1228800 * 32)>; - }; - - opp-1785600000 { - opp-hz =3D /bits/ 64 <1785600000>; - opp-peak-kBps =3D <(1708800 * 4) (1228800 * 32)>; - }; - - opp-1862400000 { - opp-hz =3D /bits/ 64 <1862400000>; - opp-peak-kBps =3D <(1708800 * 4) (1228800 * 32)>; - }; - - opp-1939200000 { - opp-hz =3D /bits/ 64 <1939200000>; - opp-peak-kBps =3D <(1708800 * 4) (1228800 * 32)>; - }; - - opp-2016000000 { - opp-hz =3D /bits/ 64 <2016000000>; - opp-peak-kBps =3D <(1708800 * 4) (1228800 * 32)>; - }; - - opp-2112000000 { - opp-hz =3D /bits/ 64 <2112000000>; - opp-peak-kBps =3D <(2092800 * 4) (1555200 * 32)>; - }; - - opp-2188800000 { - opp-hz =3D /bits/ 64 <2188800000>; - opp-peak-kBps =3D <(2092800 * 4) (1555200 * 32)>; - }; - - opp-2265600000 { - opp-hz =3D /bits/ 64 <2265600000>; - opp-peak-kBps =3D <(2092800 * 4) (1555200 * 32)>; - }; - - opp-2361600000 { - opp-hz =3D /bits/ 64 <2361600000>; - opp-peak-kBps =3D <(3196800 * 4) (1612800 * 32)>; - }; - - opp-2457600000 { - opp-hz =3D /bits/ 64 <2457600000>; - opp-peak-kBps =3D <(3196800 * 4) (1612800 * 32)>; - }; - - opp-2553600000 { - opp-hz =3D /bits/ 64 <2553600000>; - opp-peak-kBps =3D <(3196800 * 4) (1708800 * 32)>; - }; - }; - - cpu4_opp_table: opp-table-cpu4 { - compatible =3D "operating-points-v2"; - opp-shared; - - opp-1267200000 { - opp-hz =3D /bits/ 64 <1267200000>; - opp-peak-kBps =3D <(1555200 * 4) (921600 * 32)>; - }; - - opp-1363200000 { - opp-hz =3D /bits/ 64 <1363200000>; - opp-peak-kBps =3D <(1555200 * 4) (921600 * 32)>; - }; - - opp-1459200000 { - opp-hz =3D /bits/ 64 <1459200000>; - opp-peak-kBps =3D <(1555200 * 4) (921600 * 32)>; - }; - - opp-1536000000 { - opp-hz =3D /bits/ 64 <1536000000>; - opp-peak-kBps =3D <(1555200 * 4) (921600 * 32)>; - }; - - opp-1632000000 { - opp-hz =3D /bits/ 64 <1632000000>; - opp-peak-kBps =3D <(1708800 * 4) (1228800 * 32)>; - }; - - opp-1708800000 { - opp-hz =3D /bits/ 64 <1708800000>; - opp-peak-kBps =3D <(1708800 * 4) (1228800 * 32)>; - }; - - opp-1785600000 { - opp-hz =3D /bits/ 64 <1785600000>; - opp-peak-kBps =3D <(1708800 * 4) (1228800 * 32)>; - }; - - opp-1862400000 { - opp-hz =3D /bits/ 64 <1862400000>; - opp-peak-kBps =3D <(1708800 * 4) (1228800 * 32)>; - }; - - opp-1939200000 { - opp-hz =3D /bits/ 64 <1939200000>; - opp-peak-kBps =3D <(1708800 * 4) (1228800 * 32)>; - }; - - opp-2016000000 { - opp-hz =3D /bits/ 64 <2016000000>; - opp-peak-kBps =3D <(1708800 * 4) (1228800 * 32)>; - }; - - opp-2112000000 { - opp-hz =3D /bits/ 64 <2112000000>; - opp-peak-kBps =3D <(2092800 * 4) (1555200 * 32)>; - }; - - opp-2188800000 { - opp-hz =3D /bits/ 64 <2188800000>; - opp-peak-kBps =3D <(2092800 * 4) (1555200 * 32)>; - }; - - opp-2265600000 { - opp-hz =3D /bits/ 64 <2265600000>; - opp-peak-kBps =3D <(2092800 * 4) (1555200 * 32)>; - }; - - opp-2361600000 { - opp-hz =3D /bits/ 64 <2361600000>; - opp-peak-kBps =3D <(3196800 * 4) (1612800 * 32)>; - }; - - opp-2457600000 { - opp-hz =3D /bits/ 64 <2457600000>; - opp-peak-kBps =3D <(3196800 * 4) (1612800 * 32)>; - }; - - opp-2553600000 { - opp-hz =3D /bits/ 64 <2553600000>; - opp-peak-kBps =3D <(3196800 * 4) (1708800 * 32)>; - }; - }; - dummy-sink { compatible =3D "arm,coresight-dummy-sink"; =20 @@ -527,33 +293,12 @@ scm { }; }; =20 - clk_virt: interconnect-clk-virt { - compatible =3D "qcom,sa8775p-clk-virt"; - #interconnect-cells =3D <2>; - qcom,bcm-voters =3D <&apps_bcm_voter>; - }; - - mc_virt: interconnect-mc-virt { - compatible =3D "qcom,sa8775p-mc-virt"; - #interconnect-cells =3D <2>; - qcom,bcm-voters =3D <&apps_bcm_voter>; - }; - /* Will be updated by the bootloader. */ memory@80000000 { device_type =3D "memory"; reg =3D <0x0 0x80000000 0x0 0x0>; }; =20 - qup_opp_table_100mhz: opp-table-qup100mhz { - compatible =3D "operating-points-v2"; - - opp-100000000 { - opp-hz =3D /bits/ 64 <100000000>; - required-opps =3D <&rpmhpd_opp_svs_l1>; - }; - }; - pmu { compatible =3D "arm,armv8-pmuv3"; interrupts =3D ; @@ -1002,30 +747,6 @@ soc: soc@0 { #size-cells =3D <2>; ranges =3D <0 0 0 0 0x10 0>; =20 - gcc: clock-controller@100000 { - compatible =3D "qcom,sa8775p-gcc"; - reg =3D <0x0 0x00100000 0x0 0xc7018>; - #clock-cells =3D <1>; - #reset-cells =3D <1>; - #power-domain-cells =3D <1>; - clocks =3D <&rpmhcc RPMH_CXO_CLK>, - <&sleep_clk>, - <0>, - <0>, - <0>, - <&usb_0_qmpphy>, - <&usb_1_qmpphy>, - <0>, - <0>, - <0>, - <&pcie0_phy>, - <&pcie1_phy>, - <0>, - <0>, - <0>; - power-domains =3D <&rpmhpd SA8775P_CX>; - }; - ipcc: mailbox@408000 { compatible =3D "qcom,sa8775p-ipcc", "qcom,ipcc"; reg =3D <0x0 0x00408000 0x0 0x1000>; @@ -1073,9 +794,6 @@ qupv3_id_2: geniqup@8c0000 { compatible =3D "qcom,geni-se-qup"; reg =3D <0x0 0x008c0000 0x0 0x6000>; ranges; - clocks =3D <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, - <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; - clock-names =3D "m-ahb", "s-ahb"; iommus =3D <&apps_smmu 0x5a3 0x0>; #address-cells =3D <2>; #size-cells =3D <2>; @@ -1087,20 +805,6 @@ i2c14: i2c@880000 { #address-cells =3D <1>; #size-cells =3D <0>; interrupts =3D ; - clocks =3D <&gcc GCC_QUPV3_WRAP2_S0_CLK>; - clock-names =3D "se"; - pinctrl-0 =3D <&qup_i2c14_default>; - pinctrl-names =3D "default"; - interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, - <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names =3D "qup-core", - "qup-config", - "qup-memory"; - power-domains =3D <&rpmhpd SA8775P_CX>; dmas =3D <&gpi_dma2 0 0 QCOM_GPI_I2C>, <&gpi_dma2 1 0 QCOM_GPI_I2C>; dma-names =3D "tx", @@ -1114,20 +818,6 @@ spi14: spi@880000 { #address-cells =3D <1>; #size-cells =3D <0>; interrupts =3D ; - clocks =3D <&gcc GCC_QUPV3_WRAP2_S0_CLK>; - clock-names =3D "se"; - pinctrl-0 =3D <&qup_spi14_default>; - pinctrl-names =3D "default"; - interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, - <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names =3D "qup-core", - "qup-config", - "qup-memory"; - power-domains =3D <&rpmhpd SA8775P_CX>; dmas =3D <&gpi_dma2 0 0 QCOM_GPI_SPI>, <&gpi_dma2 1 0 QCOM_GPI_SPI>; dma-names =3D "tx", @@ -1139,16 +829,6 @@ uart14: serial@880000 { compatible =3D "qcom,geni-uart"; reg =3D <0x0 0x00880000 0x0 0x4000>; interrupts =3D ; - clocks =3D <&gcc GCC_QUPV3_WRAP2_S0_CLK>; - clock-names =3D "se"; - pinctrl-0 =3D <&qup_uart14_default>; - pinctrl-names =3D "default"; - interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; - interconnect-names =3D "qup-core", "qup-config"; - power-domains =3D <&rpmhpd SA8775P_CX>; status =3D "disabled"; }; =20 @@ -1158,20 +838,6 @@ i2c15: i2c@884000 { #address-cells =3D <1>; #size-cells =3D <0>; interrupts =3D ; - clocks =3D <&gcc GCC_QUPV3_WRAP2_S1_CLK>; - clock-names =3D "se"; - pinctrl-0 =3D <&qup_i2c15_default>; - pinctrl-names =3D "default"; - interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, - <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names =3D "qup-core", - "qup-config", - "qup-memory"; - power-domains =3D <&rpmhpd SA8775P_CX>; dmas =3D <&gpi_dma2 0 1 QCOM_GPI_I2C>, <&gpi_dma2 1 1 QCOM_GPI_I2C>; dma-names =3D "tx", @@ -1185,20 +851,6 @@ spi15: spi@884000 { #address-cells =3D <1>; #size-cells =3D <0>; interrupts =3D ; - clocks =3D <&gcc GCC_QUPV3_WRAP2_S1_CLK>; - clock-names =3D "se"; - pinctrl-0 =3D <&qup_spi15_default>; - pinctrl-names =3D "default"; - interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, - <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names =3D "qup-core", - "qup-config", - "qup-memory"; - power-domains =3D <&rpmhpd SA8775P_CX>; dmas =3D <&gpi_dma2 0 1 QCOM_GPI_SPI>, <&gpi_dma2 1 1 QCOM_GPI_SPI>; dma-names =3D "tx", @@ -1210,16 +862,6 @@ uart15: serial@884000 { compatible =3D "qcom,geni-uart"; reg =3D <0x0 0x00884000 0x0 0x4000>; interrupts =3D ; - clocks =3D <&gcc GCC_QUPV3_WRAP2_S1_CLK>; - clock-names =3D "se"; - pinctrl-0 =3D <&qup_uart15_default>; - pinctrl-names =3D "default"; - interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; - interconnect-names =3D "qup-core", "qup-config"; - power-domains =3D <&rpmhpd SA8775P_CX>; status =3D "disabled"; }; =20 @@ -1229,20 +871,6 @@ i2c16: i2c@888000 { #address-cells =3D <1>; #size-cells =3D <0>; interrupts =3D ; - clocks =3D <&gcc GCC_QUPV3_WRAP2_S2_CLK>; - clock-names =3D "se"; - pinctrl-0 =3D <&qup_i2c16_default>; - pinctrl-names =3D "default"; - interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, - <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names =3D "qup-core", - "qup-config", - "qup-memory"; - power-domains =3D <&rpmhpd SA8775P_CX>; dmas =3D <&gpi_dma2 0 2 QCOM_GPI_I2C>, <&gpi_dma2 1 2 QCOM_GPI_I2C>; dma-names =3D "tx", @@ -1254,20 +882,6 @@ spi16: spi@888000 { compatible =3D "qcom,geni-spi"; reg =3D <0x0 0x00888000 0x0 0x4000>; interrupts =3D ; - clocks =3D <&gcc GCC_QUPV3_WRAP2_S2_CLK>; - clock-names =3D "se"; - pinctrl-0 =3D <&qup_spi16_default>; - pinctrl-names =3D "default"; - interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, - <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names =3D "qup-core", - "qup-config", - "qup-memory"; - power-domains =3D <&rpmhpd SA8775P_CX>; dmas =3D <&gpi_dma2 0 2 QCOM_GPI_SPI>, <&gpi_dma2 1 2 QCOM_GPI_SPI>; dma-names =3D "tx", @@ -1281,16 +895,6 @@ uart16: serial@888000 { compatible =3D "qcom,geni-uart"; reg =3D <0x0 0x00888000 0x0 0x4000>; interrupts =3D ; - clocks =3D <&gcc GCC_QUPV3_WRAP2_S2_CLK>; - clock-names =3D "se"; - pinctrl-0 =3D <&qup_uart16_default>; - pinctrl-names =3D "default"; - interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; - interconnect-names =3D "qup-core", "qup-config"; - power-domains =3D <&rpmhpd SA8775P_CX>; status =3D "disabled"; }; =20 @@ -1300,20 +904,6 @@ i2c17: i2c@88c000 { #address-cells =3D <1>; #size-cells =3D <0>; interrupts =3D ; - clocks =3D <&gcc GCC_QUPV3_WRAP2_S3_CLK>; - clock-names =3D "se"; - pinctrl-0 =3D <&qup_i2c17_default>; - pinctrl-names =3D "default"; - interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, - <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names =3D "qup-core", - "qup-config", - "qup-memory"; - power-domains =3D <&rpmhpd SA8775P_CX>; dmas =3D <&gpi_dma2 0 3 QCOM_GPI_I2C>, <&gpi_dma2 1 3 QCOM_GPI_I2C>; dma-names =3D "tx", @@ -1327,20 +917,6 @@ spi17: spi@88c000 { #address-cells =3D <1>; #size-cells =3D <0>; interrupts =3D ; - clocks =3D <&gcc GCC_QUPV3_WRAP2_S3_CLK>; - clock-names =3D "se"; - pinctrl-0 =3D <&qup_spi17_default>; - pinctrl-names =3D "default"; - interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, - <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names =3D "qup-core", - "qup-config", - "qup-memory"; - power-domains =3D <&rpmhpd SA8775P_CX>; dmas =3D <&gpi_dma2 0 3 QCOM_GPI_SPI>, <&gpi_dma2 1 3 QCOM_GPI_SPI>; dma-names =3D "tx", @@ -1352,16 +928,6 @@ uart17: serial@88c000 { compatible =3D "qcom,geni-uart"; reg =3D <0x0 0x0088c000 0x0 0x4000>; interrupts =3D ; - clocks =3D <&gcc GCC_QUPV3_WRAP2_S3_CLK>; - clock-names =3D "se"; - pinctrl-0 =3D <&qup_uart17_default>; - pinctrl-names =3D "default"; - interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; - interconnect-names =3D "qup-core", "qup-config"; - power-domains =3D <&rpmhpd SA8775P_CX>; status =3D "disabled"; }; =20 @@ -1369,20 +935,6 @@ i2c18: i2c@890000 { compatible =3D "qcom,geni-i2c"; reg =3D <0x0 0x00890000 0x0 0x4000>; interrupts =3D ; - clocks =3D <&gcc GCC_QUPV3_WRAP2_S4_CLK>; - clock-names =3D "se"; - pinctrl-0 =3D <&qup_i2c18_default>; - pinctrl-names =3D "default"; - interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, - <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names =3D "qup-core", - "qup-config", - "qup-memory"; - power-domains =3D <&rpmhpd SA8775P_CX>; dmas =3D <&gpi_dma2 0 4 QCOM_GPI_I2C>, <&gpi_dma2 1 4 QCOM_GPI_I2C>; dma-names =3D "tx", @@ -1398,20 +950,6 @@ spi18: spi@890000 { #address-cells =3D <1>; #size-cells =3D <0>; interrupts =3D ; - clocks =3D <&gcc GCC_QUPV3_WRAP2_S4_CLK>; - clock-names =3D "se"; - pinctrl-0 =3D <&qup_spi18_default>; - pinctrl-names =3D "default"; - interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, - <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names =3D "qup-core", - "qup-config", - "qup-memory"; - power-domains =3D <&rpmhpd SA8775P_CX>; dmas =3D <&gpi_dma2 0 4 QCOM_GPI_SPI>, <&gpi_dma2 1 4 QCOM_GPI_SPI>; dma-names =3D "tx", @@ -1423,16 +961,6 @@ uart18: serial@890000 { compatible =3D "qcom,geni-uart"; reg =3D <0x0 0x00890000 0x0 0x4000>; interrupts =3D ; - clocks =3D <&gcc GCC_QUPV3_WRAP2_S4_CLK>; - clock-names =3D "se"; - pinctrl-0 =3D <&qup_uart18_default>; - pinctrl-names =3D "default"; - interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; - interconnect-names =3D "qup-core", "qup-config"; - power-domains =3D <&rpmhpd SA8775P_CX>; status =3D "disabled"; }; =20 @@ -1442,20 +970,6 @@ i2c19: i2c@894000 { #address-cells =3D <1>; #size-cells =3D <0>; interrupts =3D ; - clocks =3D <&gcc GCC_QUPV3_WRAP2_S5_CLK>; - clock-names =3D "se"; - pinctrl-0 =3D <&qup_i2c19_default>; - pinctrl-names =3D "default"; - interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, - <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names =3D "qup-core", - "qup-config", - "qup-memory"; - power-domains =3D <&rpmhpd SA8775P_CX>; dmas =3D <&gpi_dma2 0 5 QCOM_GPI_I2C>, <&gpi_dma2 1 5 QCOM_GPI_I2C>; dma-names =3D "tx", @@ -1469,20 +983,6 @@ spi19: spi@894000 { #address-cells =3D <1>; #size-cells =3D <0>; interrupts =3D ; - clocks =3D <&gcc GCC_QUPV3_WRAP2_S5_CLK>; - clock-names =3D "se"; - pinctrl-0 =3D <&qup_spi19_default>; - pinctrl-names =3D "default"; - interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, - <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names =3D "qup-core", - "qup-config", - "qup-memory"; - power-domains =3D <&rpmhpd SA8775P_CX>; dmas =3D <&gpi_dma2 0 5 QCOM_GPI_SPI>, <&gpi_dma2 1 5 QCOM_GPI_SPI>; dma-names =3D "tx", @@ -1494,16 +994,6 @@ uart19: serial@894000 { compatible =3D "qcom,geni-uart"; reg =3D <0x0 0x00894000 0x0 0x4000>; interrupts =3D ; - clocks =3D <&gcc GCC_QUPV3_WRAP2_S5_CLK>; - clock-names =3D "se"; - pinctrl-0 =3D <&qup_uart19_default>; - pinctrl-names =3D "default"; - interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; - interconnect-names =3D "qup-core", "qup-config"; - power-domains =3D <&rpmhpd SA8775P_CX>; status =3D "disabled"; }; =20 @@ -1513,20 +1003,6 @@ i2c20: i2c@898000 { #address-cells =3D <1>; #size-cells =3D <0>; interrupts =3D ; - clocks =3D <&gcc GCC_QUPV3_WRAP2_S6_CLK>; - clock-names =3D "se"; - pinctrl-0 =3D <&qup_i2c20_default>; - pinctrl-names =3D "default"; - interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, - <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names =3D "qup-core", - "qup-config", - "qup-memory"; - power-domains =3D <&rpmhpd SA8775P_CX>; dmas =3D <&gpi_dma2 0 6 QCOM_GPI_I2C>, <&gpi_dma2 1 6 QCOM_GPI_I2C>; dma-names =3D "tx", @@ -1540,20 +1016,6 @@ spi20: spi@898000 { #address-cells =3D <1>; #size-cells =3D <0>; interrupts =3D ; - clocks =3D <&gcc GCC_QUPV3_WRAP2_S6_CLK>; - clock-names =3D "se"; - pinctrl-0 =3D <&qup_spi20_default>; - pinctrl-names =3D "default"; - interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, - <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names =3D "qup-core", - "qup-config", - "qup-memory"; - power-domains =3D <&rpmhpd SA8775P_CX>; dmas =3D <&gpi_dma2 0 6 QCOM_GPI_SPI>, <&gpi_dma2 1 6 QCOM_GPI_SPI>; dma-names =3D "tx", @@ -1565,16 +1027,6 @@ uart20: serial@898000 { compatible =3D "qcom,geni-uart"; reg =3D <0x0 0x00898000 0x0 0x4000>; interrupts =3D ; - clocks =3D <&gcc GCC_QUPV3_WRAP2_S6_CLK>; - clock-names =3D "se"; - pinctrl-0 =3D <&qup_uart20_default>; - pinctrl-names =3D "default"; - interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; - interconnect-names =3D "qup-core", "qup-config"; - power-domains =3D <&rpmhpd SA8775P_CX>; status =3D "disabled"; }; =20 @@ -1608,9 +1060,6 @@ qupv3_id_0: geniqup@9c0000 { #address-cells =3D <2>; #size-cells =3D <2>; ranges; - clock-names =3D "m-ahb", "s-ahb"; - clocks =3D <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, - <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; iommus =3D <&apps_smmu 0x403 0x0>; status =3D "disabled"; =20 @@ -1620,20 +1069,6 @@ i2c0: i2c@980000 { #address-cells =3D <1>; #size-cells =3D <0>; interrupts =3D ; - clocks =3D <&gcc GCC_QUPV3_WRAP0_S0_CLK>; - clock-names =3D "se"; - pinctrl-0 =3D <&qup_i2c0_default>; - pinctrl-names =3D "default"; - interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, - <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names =3D "qup-core", - "qup-config", - "qup-memory"; - power-domains =3D <&rpmhpd SA8775P_CX>; dmas =3D <&gpi_dma0 0 0 QCOM_GPI_I2C>, <&gpi_dma0 1 0 QCOM_GPI_I2C>; dma-names =3D "tx", @@ -1647,20 +1082,6 @@ spi0: spi@980000 { #address-cells =3D <1>; #size-cells =3D <0>; interrupts =3D ; - clocks =3D <&gcc GCC_QUPV3_WRAP0_S0_CLK>; - clock-names =3D "se"; - pinctrl-0 =3D <&qup_spi0_default>; - pinctrl-names =3D "default"; - interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, - <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names =3D "qup-core", - "qup-config", - "qup-memory"; - power-domains =3D <&rpmhpd SA8775P_CX>; dmas =3D <&gpi_dma0 0 0 QCOM_GPI_SPI>, <&gpi_dma0 1 0 QCOM_GPI_SPI>; dma-names =3D "tx", @@ -1672,16 +1093,6 @@ uart0: serial@980000 { compatible =3D "qcom,geni-uart"; reg =3D <0x0 0x980000 0x0 0x4000>; interrupts =3D ; - clocks =3D <&gcc GCC_QUPV3_WRAP0_S0_CLK>; - clock-names =3D "se"; - pinctrl-0 =3D <&qup_uart0_default>; - pinctrl-names =3D "default"; - interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; - interconnect-names =3D "qup-core", "qup-config"; - power-domains =3D <&rpmhpd SA8775P_CX>; status =3D "disabled"; }; =20 @@ -1691,20 +1102,6 @@ i2c1: i2c@984000 { #address-cells =3D <1>; #size-cells =3D <0>; interrupts =3D ; - clocks =3D <&gcc GCC_QUPV3_WRAP0_S1_CLK>; - clock-names =3D "se"; - pinctrl-0 =3D <&qup_i2c1_default>; - pinctrl-names =3D "default"; - interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, - <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names =3D "qup-core", - "qup-config", - "qup-memory"; - power-domains =3D <&rpmhpd SA8775P_CX>; dmas =3D <&gpi_dma0 0 1 QCOM_GPI_I2C>, <&gpi_dma0 1 1 QCOM_GPI_I2C>; dma-names =3D "tx", @@ -1718,20 +1115,6 @@ spi1: spi@984000 { #address-cells =3D <1>; #size-cells =3D <0>; interrupts =3D ; - clocks =3D <&gcc GCC_QUPV3_WRAP0_S1_CLK>; - clock-names =3D "se"; - pinctrl-0 =3D <&qup_spi1_default>; - pinctrl-names =3D "default"; - interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, - <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names =3D "qup-core", - "qup-config", - "qup-memory"; - power-domains =3D <&rpmhpd SA8775P_CX>; dmas =3D <&gpi_dma0 0 1 QCOM_GPI_SPI>, <&gpi_dma0 1 1 QCOM_GPI_SPI>; dma-names =3D "tx", @@ -1743,16 +1126,6 @@ uart1: serial@984000 { compatible =3D "qcom,geni-uart"; reg =3D <0x0 0x984000 0x0 0x4000>; interrupts =3D ; - clocks =3D <&gcc GCC_QUPV3_WRAP0_S1_CLK>; - clock-names =3D "se"; - pinctrl-0 =3D <&qup_uart1_default>; - pinctrl-names =3D "default"; - interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; - interconnect-names =3D "qup-core", "qup-config"; - power-domains =3D <&rpmhpd SA8775P_CX>; status =3D "disabled"; }; =20 @@ -1762,20 +1135,6 @@ i2c2: i2c@988000 { #address-cells =3D <1>; #size-cells =3D <0>; interrupts =3D ; - clocks =3D <&gcc GCC_QUPV3_WRAP0_S2_CLK>; - clock-names =3D "se"; - pinctrl-0 =3D <&qup_i2c2_default>; - pinctrl-names =3D "default"; - interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, - <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names =3D "qup-core", - "qup-config", - "qup-memory"; - power-domains =3D <&rpmhpd SA8775P_CX>; dmas =3D <&gpi_dma0 0 2 QCOM_GPI_I2C>, <&gpi_dma0 1 2 QCOM_GPI_I2C>; dma-names =3D "tx", @@ -1789,20 +1148,6 @@ spi2: spi@988000 { #address-cells =3D <1>; #size-cells =3D <0>; interrupts =3D ; - clocks =3D <&gcc GCC_QUPV3_WRAP0_S2_CLK>; - clock-names =3D "se"; - pinctrl-0 =3D <&qup_spi2_default>; - pinctrl-names =3D "default"; - interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, - <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names =3D "qup-core", - "qup-config", - "qup-memory"; - power-domains =3D <&rpmhpd SA8775P_CX>; dmas =3D <&gpi_dma0 0 2 QCOM_GPI_SPI>, <&gpi_dma0 1 2 QCOM_GPI_SPI>; dma-names =3D "tx", @@ -1814,16 +1159,6 @@ uart2: serial@988000 { compatible =3D "qcom,geni-uart"; reg =3D <0x0 0x988000 0x0 0x4000>; interrupts =3D ; - clocks =3D <&gcc GCC_QUPV3_WRAP0_S2_CLK>; - clock-names =3D "se"; - pinctrl-0 =3D <&qup_uart2_default>; - pinctrl-names =3D "default"; - interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; - interconnect-names =3D "qup-core", "qup-config"; - power-domains =3D <&rpmhpd SA8775P_CX>; status =3D "disabled"; }; =20 @@ -1833,20 +1168,6 @@ i2c3: i2c@98c000 { #address-cells =3D <1>; #size-cells =3D <0>; interrupts =3D ; - clocks =3D <&gcc GCC_QUPV3_WRAP0_S3_CLK>; - clock-names =3D "se"; - pinctrl-0 =3D <&qup_i2c3_default>; - pinctrl-names =3D "default"; - interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, - <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names =3D "qup-core", - "qup-config", - "qup-memory"; - power-domains =3D <&rpmhpd SA8775P_CX>; dmas =3D <&gpi_dma0 0 3 QCOM_GPI_I2C>, <&gpi_dma0 1 3 QCOM_GPI_I2C>; dma-names =3D "tx", @@ -1860,20 +1181,6 @@ spi3: spi@98c000 { #address-cells =3D <1>; #size-cells =3D <0>; interrupts =3D ; - clocks =3D <&gcc GCC_QUPV3_WRAP0_S3_CLK>; - clock-names =3D "se"; - pinctrl-0 =3D <&qup_spi3_default>; - pinctrl-names =3D "default"; - interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, - <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names =3D "qup-core", - "qup-config", - "qup-memory"; - power-domains =3D <&rpmhpd SA8775P_CX>; dmas =3D <&gpi_dma0 0 3 QCOM_GPI_SPI>, <&gpi_dma0 1 3 QCOM_GPI_SPI>; dma-names =3D "tx", @@ -1885,16 +1192,6 @@ uart3: serial@98c000 { compatible =3D "qcom,geni-uart"; reg =3D <0x0 0x98c000 0x0 0x4000>; interrupts =3D ; - clocks =3D <&gcc GCC_QUPV3_WRAP0_S3_CLK>; - clock-names =3D "se"; - pinctrl-0 =3D <&qup_uart3_default>; - pinctrl-names =3D "default"; - interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; - interconnect-names =3D "qup-core", "qup-config"; - power-domains =3D <&rpmhpd SA8775P_CX>; status =3D "disabled"; }; =20 @@ -1904,20 +1201,6 @@ i2c4: i2c@990000 { #address-cells =3D <1>; #size-cells =3D <0>; interrupts =3D ; - clocks =3D <&gcc GCC_QUPV3_WRAP0_S4_CLK>; - clock-names =3D "se"; - pinctrl-0 =3D <&qup_i2c4_default>; - pinctrl-names =3D "default"; - interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, - <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names =3D "qup-core", - "qup-config", - "qup-memory"; - power-domains =3D <&rpmhpd SA8775P_CX>; dmas =3D <&gpi_dma0 0 4 QCOM_GPI_I2C>, <&gpi_dma0 1 4 QCOM_GPI_I2C>; dma-names =3D "tx", @@ -1931,20 +1214,6 @@ spi4: spi@990000 { #address-cells =3D <1>; #size-cells =3D <0>; interrupts =3D ; - clocks =3D <&gcc GCC_QUPV3_WRAP0_S4_CLK>; - clock-names =3D "se"; - pinctrl-0 =3D <&qup_spi4_default>; - pinctrl-names =3D "default"; - interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, - <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names =3D "qup-core", - "qup-config", - "qup-memory"; - power-domains =3D <&rpmhpd SA8775P_CX>; dmas =3D <&gpi_dma0 0 4 QCOM_GPI_SPI>, <&gpi_dma0 1 4 QCOM_GPI_SPI>; dma-names =3D "tx", @@ -1956,16 +1225,6 @@ uart4: serial@990000 { compatible =3D "qcom,geni-uart"; reg =3D <0x0 0x990000 0x0 0x4000>; interrupts =3D ; - clocks =3D <&gcc GCC_QUPV3_WRAP0_S4_CLK>; - clock-names =3D "se"; - pinctrl-0 =3D <&qup_uart4_default>; - pinctrl-names =3D "default"; - interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; - interconnect-names =3D "qup-core", "qup-config"; - power-domains =3D <&rpmhpd SA8775P_CX>; status =3D "disabled"; }; =20 @@ -1975,20 +1234,6 @@ i2c5: i2c@994000 { #address-cells =3D <1>; #size-cells =3D <0>; interrupts =3D ; - clocks =3D <&gcc GCC_QUPV3_WRAP0_S5_CLK>; - clock-names =3D "se"; - pinctrl-0 =3D <&qup_i2c5_default>; - pinctrl-names =3D "default"; - interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, - <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names =3D "qup-core", - "qup-config", - "qup-memory"; - power-domains =3D <&rpmhpd SA8775P_CX>; dmas =3D <&gpi_dma0 0 5 QCOM_GPI_I2C>, <&gpi_dma0 1 5 QCOM_GPI_I2C>; dma-names =3D "tx", @@ -2002,20 +1247,6 @@ spi5: spi@994000 { #address-cells =3D <1>; #size-cells =3D <0>; interrupts =3D ; - clocks =3D <&gcc GCC_QUPV3_WRAP0_S5_CLK>; - clock-names =3D "se"; - pinctrl-0 =3D <&qup_spi5_default>; - pinctrl-names =3D "default"; - interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, - <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names =3D "qup-core", - "qup-config", - "qup-memory"; - power-domains =3D <&rpmhpd SA8775P_CX>; dmas =3D <&gpi_dma0 0 5 QCOM_GPI_SPI>, <&gpi_dma0 1 5 QCOM_GPI_SPI>; dma-names =3D "tx", @@ -2027,16 +1258,6 @@ uart5: serial@994000 { compatible =3D "qcom,geni-uart"; reg =3D <0x0 0x994000 0x0 0x4000>; interrupts =3D ; - clocks =3D <&gcc GCC_QUPV3_WRAP0_S5_CLK>; - clock-names =3D "se"; - pinctrl-0 =3D <&qup_uart5_default>; - pinctrl-names =3D "default"; - interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; - interconnect-names =3D "qup-core", "qup-config"; - power-domains =3D <&rpmhpd SA8775P_CX>; status =3D "disabled"; }; }; @@ -2069,9 +1290,6 @@ qupv3_id_1: geniqup@ac0000 { #address-cells =3D <2>; #size-cells =3D <2>; ranges; - clock-names =3D "m-ahb", "s-ahb"; - clocks =3D <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, - <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; iommus =3D <&apps_smmu 0x443 0x0>; status =3D "disabled"; =20 @@ -2081,20 +1299,6 @@ i2c7: i2c@a80000 { #address-cells =3D <1>; #size-cells =3D <0>; interrupts =3D ; - clocks =3D <&gcc GCC_QUPV3_WRAP1_S0_CLK>; - clock-names =3D "se"; - pinctrl-0 =3D <&qup_i2c7_default>; - pinctrl-names =3D "default"; - interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, - <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names =3D "qup-core", - "qup-config", - "qup-memory"; - power-domains =3D <&rpmhpd SA8775P_CX>; dmas =3D <&gpi_dma1 0 0 QCOM_GPI_I2C>, <&gpi_dma1 1 0 QCOM_GPI_I2C>; dma-names =3D "tx", @@ -2108,20 +1312,6 @@ spi7: spi@a80000 { #address-cells =3D <1>; #size-cells =3D <0>; interrupts =3D ; - clocks =3D <&gcc GCC_QUPV3_WRAP1_S0_CLK>; - clock-names =3D "se"; - pinctrl-0 =3D <&qup_spi7_default>; - pinctrl-names =3D "default"; - interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, - <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names =3D "qup-core", - "qup-config", - "qup-memory"; - power-domains =3D <&rpmhpd SA8775P_CX>; dmas =3D <&gpi_dma1 0 0 QCOM_GPI_SPI>, <&gpi_dma1 1 0 QCOM_GPI_SPI>; dma-names =3D "tx", @@ -2133,17 +1323,6 @@ uart7: serial@a80000 { compatible =3D "qcom,geni-uart"; reg =3D <0x0 0x00a80000 0x0 0x4000>; interrupts =3D ; - clock-names =3D "se"; - clocks =3D <&gcc GCC_QUPV3_WRAP1_S0_CLK>; - pinctrl-0 =3D <&qup_uart7_default>; - pinctrl-names =3D "default"; - interconnect-names =3D "qup-core", "qup-config"; - interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; - power-domains =3D <&rpmhpd SA8775P_CX>; - operating-points-v2 =3D <&qup_opp_table_100mhz>; status =3D "disabled"; }; =20 @@ -2153,20 +1332,6 @@ i2c8: i2c@a84000 { #address-cells =3D <1>; #size-cells =3D <0>; interrupts =3D ; - clocks =3D <&gcc GCC_QUPV3_WRAP1_S1_CLK>; - clock-names =3D "se"; - pinctrl-0 =3D <&qup_i2c8_default>; - pinctrl-names =3D "default"; - interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, - <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names =3D "qup-core", - "qup-config", - "qup-memory"; - power-domains =3D <&rpmhpd SA8775P_CX>; dmas =3D <&gpi_dma1 0 1 QCOM_GPI_I2C>, <&gpi_dma1 1 1 QCOM_GPI_I2C>; dma-names =3D "tx", @@ -2180,20 +1345,6 @@ spi8: spi@a84000 { #address-cells =3D <1>; #size-cells =3D <0>; interrupts =3D ; - clocks =3D <&gcc GCC_QUPV3_WRAP1_S1_CLK>; - clock-names =3D "se"; - pinctrl-0 =3D <&qup_spi8_default>; - pinctrl-names =3D "default"; - interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, - <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names =3D "qup-core", - "qup-config", - "qup-memory"; - power-domains =3D <&rpmhpd SA8775P_CX>; dmas =3D <&gpi_dma1 0 1 QCOM_GPI_SPI>, <&gpi_dma1 1 1 QCOM_GPI_SPI>; dma-names =3D "tx", @@ -2205,17 +1356,6 @@ uart8: serial@a84000 { compatible =3D "qcom,geni-uart"; reg =3D <0x0 0x00a84000 0x0 0x4000>; interrupts =3D ; - clock-names =3D "se"; - clocks =3D <&gcc GCC_QUPV3_WRAP1_S1_CLK>; - pinctrl-0 =3D <&qup_uart8_default>; - pinctrl-names =3D "default"; - interconnect-names =3D "qup-core", "qup-config"; - interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; - power-domains =3D <&rpmhpd SA8775P_CX>; - operating-points-v2 =3D <&qup_opp_table_100mhz>; status =3D "disabled"; }; =20 @@ -2225,20 +1365,6 @@ i2c9: i2c@a88000 { #address-cells =3D <1>; #size-cells =3D <0>; interrupts =3D ; - clocks =3D <&gcc GCC_QUPV3_WRAP1_S2_CLK>; - clock-names =3D "se"; - pinctrl-0 =3D <&qup_i2c9_default>; - pinctrl-names =3D "default"; - interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, - <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names =3D "qup-core", - "qup-config", - "qup-memory"; - power-domains =3D <&rpmhpd SA8775P_CX>; dmas =3D <&gpi_dma1 0 2 QCOM_GPI_I2C>, <&gpi_dma1 1 2 QCOM_GPI_I2C>; dma-names =3D "tx", @@ -2252,20 +1378,6 @@ spi9: spi@a88000 { #address-cells =3D <1>; #size-cells =3D <0>; interrupts =3D ; - clocks =3D <&gcc GCC_QUPV3_WRAP1_S2_CLK>; - clock-names =3D "se"; - pinctrl-0 =3D <&qup_spi9_default>; - pinctrl-names =3D "default"; - interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, - <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names =3D "qup-core", - "qup-config", - "qup-memory"; - power-domains =3D <&rpmhpd SA8775P_CX>; dmas =3D <&gpi_dma1 0 2 QCOM_GPI_SPI>, <&gpi_dma1 1 2 QCOM_GPI_SPI>; dma-names =3D "tx", @@ -2277,16 +1389,6 @@ uart9: serial@a88000 { compatible =3D "qcom,geni-uart"; reg =3D <0x0 0xa88000 0x0 0x4000>; interrupts =3D ; - clocks =3D <&gcc GCC_QUPV3_WRAP1_S2_CLK>; - clock-names =3D "se"; - pinctrl-0 =3D <&qup_uart9_default>; - pinctrl-names =3D "default"; - interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names =3D "qup-core", "qup-config"; - power-domains =3D <&rpmhpd SA8775P_CX>; status =3D "disabled"; }; =20 @@ -2296,20 +1398,6 @@ i2c10: i2c@a8c000 { #address-cells =3D <1>; #size-cells =3D <0>; interrupts =3D ; - clocks =3D <&gcc GCC_QUPV3_WRAP1_S3_CLK>; - clock-names =3D "se"; - pinctrl-0 =3D <&qup_i2c10_default>; - pinctrl-names =3D "default"; - interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, - <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names =3D "qup-core", - "qup-config", - "qup-memory"; - power-domains =3D <&rpmhpd SA8775P_CX>; dmas =3D <&gpi_dma1 0 3 QCOM_GPI_I2C>, <&gpi_dma1 1 3 QCOM_GPI_I2C>; dma-names =3D "tx", @@ -2323,20 +1411,6 @@ spi10: spi@a8c000 { #address-cells =3D <1>; #size-cells =3D <0>; interrupts =3D ; - clocks =3D <&gcc GCC_QUPV3_WRAP1_S3_CLK>; - clock-names =3D "se"; - pinctrl-0 =3D <&qup_spi10_default>; - pinctrl-names =3D "default"; - interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, - <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names =3D "qup-core", - "qup-config", - "qup-memory"; - power-domains =3D <&rpmhpd SA8775P_CX>; dmas =3D <&gpi_dma1 0 3 QCOM_GPI_SPI>, <&gpi_dma1 1 3 QCOM_GPI_SPI>; dma-names =3D "tx", @@ -2348,17 +1422,6 @@ uart10: serial@a8c000 { compatible =3D "qcom,geni-uart"; reg =3D <0x0 0x00a8c000 0x0 0x4000>; interrupts =3D ; - clock-names =3D "se"; - clocks =3D <&gcc GCC_QUPV3_WRAP1_S3_CLK>; - pinctrl-0 =3D <&qup_uart10_default>; - pinctrl-names =3D "default"; - interconnect-names =3D "qup-core", "qup-config"; - interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 - &clk_virt SLAVE_QUP_CORE_1 0>, - <&gem_noc MASTER_APPSS_PROC 0 - &config_noc SLAVE_QUP_1 0>; - power-domains =3D <&rpmhpd SA8775P_CX>; - operating-points-v2 =3D <&qup_opp_table_100mhz>; status =3D "disabled"; }; =20 @@ -2368,20 +1431,6 @@ i2c11: i2c@a90000 { #address-cells =3D <1>; #size-cells =3D <0>; interrupts =3D ; - clocks =3D <&gcc GCC_QUPV3_WRAP1_S4_CLK>; - clock-names =3D "se"; - pinctrl-0 =3D <&qup_i2c11_default>; - pinctrl-names =3D "default"; - interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, - <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names =3D "qup-core", - "qup-config", - "qup-memory"; - power-domains =3D <&rpmhpd SA8775P_CX>; dmas =3D <&gpi_dma1 0 4 QCOM_GPI_I2C>, <&gpi_dma1 1 4 QCOM_GPI_I2C>; dma-names =3D "tx", @@ -2395,20 +1444,6 @@ spi11: spi@a90000 { #address-cells =3D <1>; #size-cells =3D <0>; interrupts =3D ; - clocks =3D <&gcc GCC_QUPV3_WRAP1_S4_CLK>; - clock-names =3D "se"; - pinctrl-0 =3D <&qup_spi11_default>; - pinctrl-names =3D "default"; - interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, - <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names =3D "qup-core", - "qup-config", - "qup-memory"; - power-domains =3D <&rpmhpd SA8775P_CX>; dmas =3D <&gpi_dma1 0 4 QCOM_GPI_SPI>, <&gpi_dma1 1 4 QCOM_GPI_SPI>; dma-names =3D "tx", @@ -2420,17 +1455,6 @@ uart11: serial@a90000 { compatible =3D "qcom,geni-uart"; reg =3D <0x0 0x00a90000 0x0 0x4000>; interrupts =3D ; - clock-names =3D "se"; - clocks =3D <&gcc GCC_QUPV3_WRAP1_S4_CLK>; - pinctrl-0 =3D <&qup_uart11_default>; - pinctrl-names =3D "default"; - interconnect-names =3D "qup-core", "qup-config"; - interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; - power-domains =3D <&rpmhpd SA8775P_CX>; - operating-points-v2 =3D <&qup_opp_table_100mhz>; status =3D "disabled"; }; =20 @@ -2440,20 +1464,6 @@ i2c12: i2c@a94000 { #address-cells =3D <1>; #size-cells =3D <0>; interrupts =3D ; - clocks =3D <&gcc GCC_QUPV3_WRAP1_S5_CLK>; - clock-names =3D "se"; - pinctrl-0 =3D <&qup_i2c12_default>; - pinctrl-names =3D "default"; - interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, - <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names =3D "qup-core", - "qup-config", - "qup-memory"; - power-domains =3D <&rpmhpd SA8775P_CX>; dmas =3D <&gpi_dma1 0 5 QCOM_GPI_I2C>, <&gpi_dma1 1 5 QCOM_GPI_I2C>; dma-names =3D "tx", @@ -2467,20 +1477,6 @@ spi12: spi@a94000 { #address-cells =3D <1>; #size-cells =3D <0>; interrupts =3D ; - clocks =3D <&gcc GCC_QUPV3_WRAP1_S5_CLK>; - clock-names =3D "se"; - pinctrl-0 =3D <&qup_spi12_default>; - pinctrl-names =3D "default"; - interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, - <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names =3D "qup-core", - "qup-config", - "qup-memory"; - power-domains =3D <&rpmhpd SA8775P_CX>; dmas =3D <&gpi_dma1 0 5 QCOM_GPI_SPI>, <&gpi_dma1 1 5 QCOM_GPI_SPI>; dma-names =3D "tx", @@ -2492,16 +1488,6 @@ uart12: serial@a94000 { compatible =3D "qcom,geni-uart"; reg =3D <0x0 0x00a94000 0x0 0x4000>; interrupts =3D ; - clocks =3D <&gcc GCC_QUPV3_WRAP1_S5_CLK>; - clock-names =3D "se"; - pinctrl-0 =3D <&qup_uart12_default>; - pinctrl-names =3D "default"; - interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names =3D "qup-core", "qup-config"; - power-domains =3D <&rpmhpd SA8775P_CX>; status =3D "disabled"; }; =20 @@ -2511,20 +1497,6 @@ i2c13: i2c@a98000 { #address-cells =3D <1>; #size-cells =3D <0>; interrupts =3D ; - clocks =3D <&gcc GCC_QUPV3_WRAP1_S6_CLK>; - clock-names =3D "se"; - pinctrl-0 =3D <&qup_i2c13_default>; - pinctrl-names =3D "default"; - interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, - <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names =3D "qup-core", - "qup-config", - "qup-memory"; - power-domains =3D <&rpmhpd SA8775P_CX>; dmas =3D <&gpi_dma1 0 6 QCOM_GPI_I2C>, <&gpi_dma1 1 6 QCOM_GPI_I2C>; dma-names =3D "tx", @@ -2554,9 +1526,6 @@ qupv3_id_3: geniqup@bc0000 { #address-cells =3D <2>; #size-cells =3D <2>; ranges; - clock-names =3D "m-ahb", "s-ahb"; - clocks =3D <&gcc GCC_QUPV3_WRAP_3_M_AHB_CLK>, - <&gcc GCC_QUPV3_WRAP_3_S_AHB_CLK>; iommus =3D <&apps_smmu 0x43 0x0>; status =3D "disabled"; =20 @@ -2566,20 +1535,6 @@ i2c21: i2c@b80000 { #address-cells =3D <1>; #size-cells =3D <0>; interrupts =3D ; - clocks =3D <&gcc GCC_QUPV3_WRAP3_S0_CLK>; - clock-names =3D "se"; - pinctrl-0 =3D <&qup_i2c21_default>; - pinctrl-names =3D "default"; - interconnects =3D <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>, - <&aggre1_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names =3D "qup-core", - "qup-config", - "qup-memory"; - power-domains =3D <&rpmhpd SA8775P_CX>; dmas =3D <&gpi_dma3 0 0 QCOM_GPI_I2C>, <&gpi_dma3 1 0 QCOM_GPI_I2C>; dma-names =3D "tx", @@ -2593,20 +1548,6 @@ spi21: spi@b80000 { #address-cells =3D <1>; #size-cells =3D <0>; interrupts =3D ; - clocks =3D <&gcc GCC_QUPV3_WRAP3_S0_CLK>; - clock-names =3D "se"; - pinctrl-0 =3D <&qup_spi21_default>; - pinctrl-names =3D "default"; - interconnects =3D <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>, - <&aggre1_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names =3D "qup-core", - "qup-config", - "qup-memory"; - power-domains =3D <&rpmhpd SA8775P_CX>; dmas =3D <&gpi_dma3 0 0 QCOM_GPI_SPI>, <&gpi_dma3 1 0 QCOM_GPI_SPI>; dma-names =3D "tx", @@ -2618,17 +1559,6 @@ uart21: serial@b80000 { compatible =3D "qcom,geni-uart"; reg =3D <0x0 0x00b80000 0x0 0x4000>; interrupts =3D ; - clock-names =3D "se"; - clocks =3D <&gcc GCC_QUPV3_WRAP3_S0_CLK>; - interconnect-names =3D "qup-core", "qup-config"; - pinctrl-0 =3D <&qup_uart21_default>; - pinctrl-names =3D "default"; - interconnects =3D <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>; - power-domains =3D <&rpmhpd SA8775P_CX>; - operating-points-v2 =3D <&qup_opp_table_100mhz>; status =3D "disabled"; }; }; @@ -2638,62 +1568,6 @@ rng: rng@10d2000 { reg =3D <0 0x010d2000 0 0x1000>; }; =20 - config_noc: interconnect@14c0000 { - compatible =3D "qcom,sa8775p-config-noc"; - reg =3D <0x0 0x014c0000 0x0 0x13080>; - #interconnect-cells =3D <2>; - qcom,bcm-voters =3D <&apps_bcm_voter>; - }; - - system_noc: interconnect@1680000 { - compatible =3D "qcom,sa8775p-system-noc"; - reg =3D <0x0 0x01680000 0x0 0x15080>; - #interconnect-cells =3D <2>; - qcom,bcm-voters =3D <&apps_bcm_voter>; - }; - - aggre1_noc: interconnect@16c0000 { - compatible =3D "qcom,sa8775p-aggre1-noc"; - reg =3D <0x0 0x016c0000 0x0 0x18080>; - #interconnect-cells =3D <2>; - qcom,bcm-voters =3D <&apps_bcm_voter>; - clocks =3D <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, - <&gcc GCC_AGGRE_NOC_QUPV3_AXI_CLK>, - <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>, - <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, - <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>; - }; - - aggre2_noc: interconnect@1700000 { - compatible =3D "qcom,sa8775p-aggre2-noc"; - reg =3D <0x0 0x01700000 0x0 0x1b080>; - #interconnect-cells =3D <2>; - qcom,bcm-voters =3D <&apps_bcm_voter>; - clocks =3D <&gcc GCC_AGGRE_UFS_CARD_AXI_CLK>, - <&rpmhcc RPMH_IPA_CLK>; - }; - - pcie_anoc: interconnect@1760000 { - compatible =3D "qcom,sa8775p-pcie-anoc"; - reg =3D <0x0 0x01760000 0x0 0xc080>; - #interconnect-cells =3D <2>; - qcom,bcm-voters =3D <&apps_bcm_voter>; - }; - - gpdsp_anoc: interconnect@1780000 { - compatible =3D "qcom,sa8775p-gpdsp-anoc"; - reg =3D <0x0 0x01780000 0x0 0xe080>; - #interconnect-cells =3D <2>; - qcom,bcm-voters =3D <&apps_bcm_voter>; - }; - - mmss_noc: interconnect@17a0000 { - compatible =3D "qcom,sa8775p-mmss-noc"; - reg =3D <0x0 0x017a0000 0x0 0x40000>; - #interconnect-cells =3D <2>; - qcom,bcm-voters =3D <&apps_bcm_voter>; - }; - pcie0: pcie@1c00000 { compatible =3D "qcom,pcie-sa8775p"; reg =3D <0x0 0x01c00000 0x0 0x3000>, @@ -2741,38 +1615,9 @@ pcie0: pcie@1c00000 { <0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>; =20 - clocks =3D <&gcc GCC_PCIE_0_AUX_CLK>, - <&gcc GCC_PCIE_0_CFG_AHB_CLK>, - <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, - <&gcc GCC_PCIE_0_SLV_AXI_CLK>, - <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; - - clock-names =3D "aux", - "cfg", - "bus_master", - "bus_slave", - "slave_q2a"; - - assigned-clocks =3D <&gcc GCC_PCIE_0_AUX_CLK>; - assigned-clock-rates =3D <19200000>; - - interconnects =3D <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>; - interconnect-names =3D "pcie-mem", "cpu-pcie"; - iommu-map =3D <0x0 &pcie_smmu 0x0000 0x1>, <0x100 &pcie_smmu 0x0001 0x1>; =20 - resets =3D <&gcc GCC_PCIE_0_BCR>, - <&gcc GCC_PCIE_0_LINK_DOWN_BCR>; - reset-names =3D "pci", - "link_down"; - - power-domains =3D <&gcc PCIE_0_GDSC>; - - phys =3D <&pcie0_phy>; - phy-names =3D "pciephy"; - eq-presets-8gts =3D /bits/ 16 <0x5555 0x5555>; eq-presets-16gts =3D /bits/ 8 <0x55 0x55>; =20 @@ -2800,73 +1645,20 @@ pcie0_ep: pcie-ep@1c00000 { <0x0 0x40005000 0x0 0x2000>; reg-names =3D "parf", "dbi", "elbi", "atu", "addr_space", "mmio", "dma"; - - clocks =3D <&gcc GCC_PCIE_0_AUX_CLK>, - <&gcc GCC_PCIE_0_CFG_AHB_CLK>, - <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, - <&gcc GCC_PCIE_0_SLV_AXI_CLK>, - <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; - - clock-names =3D "aux", - "cfg", - "bus_master", - "bus_slave", - "slave_q2a"; - interrupts =3D , , ; =20 interrupt-names =3D "global", "doorbell", "dma"; =20 - interconnects =3D <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>; - interconnect-names =3D "pcie-mem", "cpu-pcie"; - dma-coherent; iommus =3D <&pcie_smmu 0x0000 0x7f>; - resets =3D <&gcc GCC_PCIE_0_BCR>; - reset-names =3D "core"; - power-domains =3D <&gcc PCIE_0_GDSC>; - phys =3D <&pcie0_phy>; - phy-names =3D "pciephy"; num-lanes =3D <2>; linux,pci-domain =3D <0>; =20 status =3D "disabled"; }; =20 - pcie0_phy: phy@1c04000 { - compatible =3D "qcom,sa8775p-qmp-gen4x2-pcie-phy"; - reg =3D <0x0 0x1c04000 0x0 0x2000>; - - clocks =3D <&gcc GCC_PCIE_0_PHY_AUX_CLK>, - <&gcc GCC_PCIE_0_CFG_AHB_CLK>, - <&gcc GCC_PCIE_CLKREF_EN>, - <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, - <&gcc GCC_PCIE_0_PIPE_CLK>, - <&gcc GCC_PCIE_0_PIPEDIV2_CLK>; - clock-names =3D "aux", - "cfg_ahb", - "ref", - "rchng", - "pipe", - "pipediv2"; - - assigned-clocks =3D <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; - assigned-clock-rates =3D <100000000>; - - resets =3D <&gcc GCC_PCIE_0_PHY_BCR>; - reset-names =3D "phy"; - - #clock-cells =3D <0>; - clock-output-names =3D "pcie_0_pipe_clk"; - - #phy-cells =3D <0>; - - status =3D "disabled"; - }; - pcie1: pcie@1c10000 { compatible =3D "qcom,pcie-sa8775p"; reg =3D <0x0 0x01c10000 0x0 0x3000>, @@ -2914,38 +1706,9 @@ pcie1: pcie@1c10000 { <0 0 0 3 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 4 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; =20 - clocks =3D <&gcc GCC_PCIE_1_AUX_CLK>, - <&gcc GCC_PCIE_1_CFG_AHB_CLK>, - <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, - <&gcc GCC_PCIE_1_SLV_AXI_CLK>, - <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>; - - clock-names =3D "aux", - "cfg", - "bus_master", - "bus_slave", - "slave_q2a"; - - assigned-clocks =3D <&gcc GCC_PCIE_1_AUX_CLK>; - assigned-clock-rates =3D <19200000>; - - interconnects =3D <&pcie_anoc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>; - interconnect-names =3D "pcie-mem", "cpu-pcie"; - iommu-map =3D <0x0 &pcie_smmu 0x0080 0x1>, <0x100 &pcie_smmu 0x0081 0x1>; =20 - resets =3D <&gcc GCC_PCIE_1_BCR>, - <&gcc GCC_PCIE_1_LINK_DOWN_BCR>; - reset-names =3D "pci", - "link_down"; - - power-domains =3D <&gcc PCIE_1_GDSC>; - - phys =3D <&pcie1_phy>; - phy-names =3D "pciephy"; - eq-presets-8gts =3D /bits/ 16 <0x5555 0x5555 0x5555 0x5555>; eq-presets-16gts =3D /bits/ 8 <0x55 0x55 0x55 0x55>; =20 @@ -2974,139 +1737,30 @@ pcie1_ep: pcie-ep@1c10000 { reg-names =3D "parf", "dbi", "elbi", "atu", "addr_space", "mmio", "dma"; =20 - clocks =3D <&gcc GCC_PCIE_1_AUX_CLK>, - <&gcc GCC_PCIE_1_CFG_AHB_CLK>, - <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, - <&gcc GCC_PCIE_1_SLV_AXI_CLK>, - <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>; - - clock-names =3D "aux", - "cfg", - "bus_master", - "bus_slave", - "slave_q2a"; - interrupts =3D , , ; =20 interrupt-names =3D "global", "doorbell", "dma"; =20 - interconnects =3D <&pcie_anoc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>; - interconnect-names =3D "pcie-mem", "cpu-pcie"; - dma-coherent; iommus =3D <&pcie_smmu 0x80 0x7f>; - resets =3D <&gcc GCC_PCIE_1_BCR>; - reset-names =3D "core"; - power-domains =3D <&gcc PCIE_1_GDSC>; - phys =3D <&pcie1_phy>; - phy-names =3D "pciephy"; num-lanes =3D <4>; linux,pci-domain =3D <1>; =20 status =3D "disabled"; }; =20 - pcie1_phy: phy@1c14000 { - compatible =3D "qcom,sa8775p-qmp-gen4x4-pcie-phy"; - reg =3D <0x0 0x1c14000 0x0 0x4000>; - - clocks =3D <&gcc GCC_PCIE_1_PHY_AUX_CLK>, - <&gcc GCC_PCIE_1_CFG_AHB_CLK>, - <&gcc GCC_PCIE_CLKREF_EN>, - <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, - <&gcc GCC_PCIE_1_PIPE_CLK>, - <&gcc GCC_PCIE_1_PIPEDIV2_CLK>; - clock-names =3D "aux", - "cfg_ahb", - "ref", - "rchng", - "pipe", - "pipediv2"; - - assigned-clocks =3D <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; - assigned-clock-rates =3D <100000000>; - - resets =3D <&gcc GCC_PCIE_1_PHY_BCR>; - reset-names =3D "phy"; - - #clock-cells =3D <0>; - clock-output-names =3D "pcie_1_pipe_clk"; - - #phy-cells =3D <0>; - - status =3D "disabled"; - }; - ufs_mem_hc: ufshc@1d84000 { compatible =3D "qcom,sa8775p-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; reg =3D <0x0 0x01d84000 0x0 0x3000>; interrupts =3D ; - phys =3D <&ufs_mem_phy>; - phy-names =3D "ufsphy"; lanes-per-direction =3D <2>; - #reset-cells =3D <1>; - resets =3D <&gcc GCC_UFS_PHY_BCR>; - reset-names =3D "rst"; - power-domains =3D <&gcc UFS_PHY_GDSC>; - required-opps =3D <&rpmhpd_opp_nom>; iommus =3D <&apps_smmu 0x100 0x0>; dma-coherent; - clocks =3D <&gcc GCC_UFS_PHY_AXI_CLK>, - <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, - <&gcc GCC_UFS_PHY_AHB_CLK>, - <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, - <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, - <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, - <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; - clock-names =3D "core_clk", - "bus_aggr_clk", - "iface_clk", - "core_clk_unipro", - "ref_clk", - "tx_lane0_sync_clk", - "rx_lane0_sync_clk", - "rx_lane1_sync_clk"; - freq-table-hz =3D <75000000 300000000>, - <0 0>, - <0 0>, - <75000000 300000000>, - <0 0>, - <0 0>, - <0 0>, - <0 0>; - qcom,ice =3D <&ice>; - status =3D "disabled"; - }; - - ufs_mem_phy: phy@1d87000 { - compatible =3D "qcom,sa8775p-qmp-ufs-phy"; - reg =3D <0x0 0x01d87000 0x0 0xe10>; - /* - * Yes, GCC_EDP_REF_CLKREF_EN is correct in qref. It - * enables the CXO clock to eDP *and* UFS PHY. - */ - clocks =3D <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, - <&gcc GCC_EDP_REF_CLKREF_EN>; - clock-names =3D "ref", "ref_aux", "qref"; - power-domains =3D <&gcc UFS_PHY_GDSC>; - resets =3D <&ufs_mem_hc 0>; - reset-names =3D "ufsphy"; - #phy-cells =3D <0>; status =3D "disabled"; }; =20 - ice: crypto@1d88000 { - compatible =3D "qcom,sa8775p-inline-crypto-engine", - "qcom,inline-crypto-engine"; - reg =3D <0x0 0x01d88000 0x0 0x18000>; - clocks =3D <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; - }; - cryptobam: dma-controller@1dc4000 { compatible =3D "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; reg =3D <0x0 0x01dc4000 0x0 0x28000>; @@ -3127,16 +1781,6 @@ crypto: crypto@1dfa000 { dma-names =3D "rx", "tx"; iommus =3D <&apps_smmu 0x480 0x0>, <&apps_smmu 0x481 0x0>; - interconnects =3D <&aggre2_noc MASTER_CRYPTO_CORE0 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names =3D "memory"; - }; - - lpass_ag_noc: interconnect@3c40000 { - compatible =3D "qcom,sa8775p-lpass-ag-noc"; - reg =3D <0x0 0x03c40000 0x0 0x17200>; - #interconnect-cells =3D <2>; - qcom,bcm-voters =3D <&apps_bcm_voter>; }; =20 ctcu@4001000 { @@ -4306,171 +2950,19 @@ sdhc: mmc@87c4000 { interrupt-names =3D "hc_irq", "pwr_irq"; =20 - clocks =3D <&gcc GCC_SDCC1_AHB_CLK>, - <&gcc GCC_SDCC1_APPS_CLK>; - clock-names =3D "iface", - "core"; - - interconnects =3D <&aggre1_noc MASTER_SDC QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY - &config_noc SLAVE_SDC1 QCOM_ICC_TAG_ACTIVE_ONLY>; - interconnect-names =3D "sdhc-ddr", - "cpu-sdhc"; - iommus =3D <&apps_smmu 0x0 0x0>; dma-coherent; =20 - operating-points-v2 =3D <&sdhc_opp_table>; - power-domains =3D <&rpmhpd SA8775P_CX>; - resets =3D <&gcc GCC_SDCC1_BCR>; - qcom,dll-config =3D <0x0007642c>; qcom,ddr-config =3D <0x80040868>; =20 status =3D "disabled"; - - sdhc_opp_table: opp-table { - compatible =3D "operating-points-v2"; - - opp-100000000 { - opp-hz =3D /bits/ 64 <100000000>; - required-opps =3D <&rpmhpd_opp_low_svs>; - opp-peak-kBps =3D <1800000 400000>; - opp-avg-kBps =3D <100000 0>; - }; - - opp-384000000 { - opp-hz =3D /bits/ 64 <384000000>; - required-opps =3D <&rpmhpd_opp_nom>; - opp-peak-kBps =3D <5400000 1600000>; - opp-avg-kBps =3D <390000 0>; - }; - }; - }; - - usb_0_hsphy: phy@88e4000 { - compatible =3D "qcom,sa8775p-usb-hs-phy", - "qcom,usb-snps-hs-5nm-phy"; - reg =3D <0 0x088e4000 0 0x120>; - clocks =3D <&rpmhcc RPMH_CXO_CLK>; - clock-names =3D "ref"; - resets =3D <&gcc GCC_USB2_PHY_PRIM_BCR>; - - #phy-cells =3D <0>; - - status =3D "disabled"; - }; - - usb_1_hsphy: phy@88e6000 { - compatible =3D "qcom,sa8775p-usb-hs-phy", - "qcom,usb-snps-hs-5nm-phy"; - reg =3D <0 0x088e6000 0 0x120>; - clocks =3D <&gcc GCC_USB_CLKREF_EN>; - clock-names =3D "ref"; - resets =3D <&gcc GCC_USB2_PHY_SEC_BCR>; - - #phy-cells =3D <0>; - - status =3D "disabled"; - }; - - usb_2_hsphy: phy@88e7000 { - compatible =3D "qcom,sa8775p-usb-hs-phy", - "qcom,usb-snps-hs-5nm-phy"; - reg =3D <0 0x088e7000 0 0x120>; - clocks =3D <&gcc GCC_USB_CLKREF_EN>; - clock-names =3D "ref"; - resets =3D <&gcc GCC_USB3_PHY_TERT_BCR>; - - #phy-cells =3D <0>; - - status =3D "disabled"; - }; - - usb_0_qmpphy: phy@88e8000 { - compatible =3D "qcom,sa8775p-qmp-usb3-uni-phy"; - reg =3D <0 0x088e8000 0 0x2000>; - - clocks =3D <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, - <&gcc GCC_USB_CLKREF_EN>, - <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, - <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; - clock-names =3D "aux", "ref", "com_aux", "pipe"; - - resets =3D <&gcc GCC_USB3_PHY_PRIM_BCR>, - <&gcc GCC_USB3PHY_PHY_PRIM_BCR>; - reset-names =3D "phy", "phy_phy"; - - power-domains =3D <&gcc USB30_PRIM_GDSC>; - - #clock-cells =3D <0>; - clock-output-names =3D "usb3_prim_phy_pipe_clk_src"; - - #phy-cells =3D <0>; - - status =3D "disabled"; - }; - - usb_1_qmpphy: phy@88ea000 { - compatible =3D "qcom,sa8775p-qmp-usb3-uni-phy"; - reg =3D <0 0x088ea000 0 0x2000>; - - clocks =3D <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, - <&gcc GCC_USB_CLKREF_EN>, - <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, - <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; - clock-names =3D "aux", "ref", "com_aux", "pipe"; - - resets =3D <&gcc GCC_USB3_PHY_SEC_BCR>, - <&gcc GCC_USB3PHY_PHY_SEC_BCR>; - reset-names =3D "phy", "phy_phy"; - - power-domains =3D <&gcc USB30_SEC_GDSC>; - - #clock-cells =3D <0>; - clock-output-names =3D "usb3_sec_phy_pipe_clk_src"; - - #phy-cells =3D <0>; - - status =3D "disabled"; - }; - - refgen: regulator@891c000 { - compatible =3D "qcom,sa8775p-refgen-regulator", - "qcom,sm8250-refgen-regulator"; - reg =3D <0x0 0x0891c000 0x0 0x84>; - }; - - dc_noc: interconnect@90e0000 { - compatible =3D "qcom,sa8775p-dc-noc"; - reg =3D <0x0 0x090e0000 0x0 0x5080>; - #interconnect-cells =3D <2>; - qcom,bcm-voters =3D <&apps_bcm_voter>; - }; - - gem_noc: interconnect@9100000 { - compatible =3D "qcom,sa8775p-gem-noc"; - reg =3D <0x0 0x09100000 0x0 0xf6080>; - #interconnect-cells =3D <2>; - qcom,bcm-voters =3D <&apps_bcm_voter>; }; =20 usb_0: usb@a600000 { compatible =3D "qcom,sa8775p-dwc3", "qcom,snps-dwc3"; reg =3D <0 0x0a600000 0 0xfc100>; =20 - clocks =3D <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, - <&gcc GCC_USB30_PRIM_MASTER_CLK>, - <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, - <&gcc GCC_USB30_PRIM_SLEEP_CLK>, - <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; - clock-names =3D "cfg_noc", "core", "iface", "sleep", "mock_utmi"; - - assigned-clocks =3D <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_PRIM_MASTER_CLK>; - assigned-clock-rates =3D <19200000>, <200000000>; - interrupts-extended =3D <&intc GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, @@ -4484,20 +2976,9 @@ usb_0: usb@a600000 { "dm_hs_phy_irq", "ss_phy_irq"; =20 - power-domains =3D <&gcc USB30_PRIM_GDSC>; - required-opps =3D <&rpmhpd_opp_nom>; - - resets =3D <&gcc GCC_USB30_PRIM_BCR>; - - interconnects =3D <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; - interconnect-names =3D "usb-ddr", "apps-usb"; - wakeup-source; =20 iommus =3D <&apps_smmu 0x080 0x0>; - phys =3D <&usb_0_hsphy>, <&usb_0_qmpphy>; - phy-names =3D "usb2-phy", "usb3-phy"; snps,dis-u1-entry-quirk; snps,dis-u2-entry-quirk; =20 @@ -4528,17 +3009,6 @@ usb_1: usb@a800000 { compatible =3D "qcom,sa8775p-dwc3", "qcom,snps-dwc3"; reg =3D <0 0x0a800000 0 0xfc100>; =20 - clocks =3D <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, - <&gcc GCC_USB30_SEC_MASTER_CLK>, - <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, - <&gcc GCC_USB30_SEC_SLEEP_CLK>, - <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>; - clock-names =3D "cfg_noc", "core", "iface", "sleep", "mock_utmi"; - - assigned-clocks =3D <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_SEC_MASTER_CLK>; - assigned-clock-rates =3D <19200000>, <200000000>; - interrupts-extended =3D <&intc GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, @@ -4552,20 +3022,9 @@ usb_1: usb@a800000 { "dm_hs_phy_irq", "ss_phy_irq"; =20 - power-domains =3D <&gcc USB30_SEC_GDSC>; - required-opps =3D <&rpmhpd_opp_nom>; - - resets =3D <&gcc GCC_USB30_SEC_BCR>; - - interconnects =3D <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>; - interconnect-names =3D "usb-ddr", "apps-usb"; - wakeup-source; =20 iommus =3D <&apps_smmu 0x0a0 0x0>; - phys =3D <&usb_1_hsphy>, <&usb_1_qmpphy>; - phy-names =3D "usb2-phy", "usb3-phy"; snps,dis-u1-entry-quirk; snps,dis-u2-entry-quirk; =20 @@ -4576,17 +3035,6 @@ usb_2: usb@a400000 { compatible =3D "qcom,sa8775p-dwc3", "qcom,snps-dwc3"; reg =3D <0 0x0a400000 0 0xfc100>; =20 - clocks =3D <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>, - <&gcc GCC_USB20_MASTER_CLK>, - <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>, - <&gcc GCC_USB20_SLEEP_CLK>, - <&gcc GCC_USB20_MOCK_UTMI_CLK>; - clock-names =3D "cfg_noc", "core", "iface", "sleep", "mock_utmi"; - - assigned-clocks =3D <&gcc GCC_USB20_MOCK_UTMI_CLK>, - <&gcc GCC_USB20_MASTER_CLK>; - assigned-clock-rates =3D <19200000>, <200000000>; - interrupts-extended =3D <&intc GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, @@ -4598,21 +3046,10 @@ usb_2: usb@a400000 { "dp_hs_phy_irq", "dm_hs_phy_irq"; =20 - power-domains =3D <&gcc USB20_PRIM_GDSC>; - required-opps =3D <&rpmhpd_opp_nom>; - - resets =3D <&gcc GCC_USB20_PRIM_BCR>; - - interconnects =3D <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB2 0>; - interconnect-names =3D "usb-ddr", "apps-usb"; - qcom,select-utmi-as-pipe-clk; wakeup-source; =20 iommus =3D <&apps_smmu 0x020 0x0>; - phys =3D <&usb_2_hsphy>; - phy-names =3D "usb2-phy"; snps,dis-u1-entry-quirk; snps,dis-u2-entry-quirk; =20 @@ -4648,11 +3085,6 @@ gpu: gpu@3d00000 { interrupts =3D ; iommus =3D <&adreno_smmu 0 0xc00>, <&adreno_smmu 1 0xc00>; - operating-points-v2 =3D <&gpu_opp_table>; - qcom,gmu =3D <&gmu>; - interconnects =3D <&gem_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names =3D "gfx-mem"; #cooling-cells =3D <2>; =20 nvmem-cells =3D <&gpu_speed_bin>; @@ -4663,99 +3095,6 @@ gpu: gpu@3d00000 { gpu_zap_shader: zap-shader { memory-region =3D <&pil_gpu_mem>; }; - - gpu_opp_table: opp-table { - compatible =3D "operating-points-v2"; - - opp-405000000 { - opp-hz =3D /bits/ 64 <405000000>; - opp-level =3D ; - opp-peak-kBps =3D <5285156>; - opp-supported-hw =3D <0x3>; - }; - - opp-530000000 { - opp-hz =3D /bits/ 64 <530000000>; - opp-level =3D ; - opp-peak-kBps =3D <12484375>; - opp-supported-hw =3D <0x2>; - }; - - opp-676000000 { - opp-hz =3D /bits/ 64 <676000000>; - opp-level =3D ; - opp-peak-kBps =3D <8171875>; - opp-supported-hw =3D <0x1>; - }; - - opp-778000000 { - opp-hz =3D /bits/ 64 <778000000>; - opp-level =3D ; - opp-peak-kBps =3D <10687500>; - opp-supported-hw =3D <0x1>; - }; - - opp-800000000 { - opp-hz =3D /bits/ 64 <800000000>; - opp-level =3D ; - opp-peak-kBps =3D <12484375>; - opp-supported-hw =3D <0x1>; - }; - }; - }; - - gmu: gmu@3d6a000 { - compatible =3D "qcom,adreno-gmu-663.0", "qcom,adreno-gmu"; - reg =3D <0x0 0x03d6a000 0x0 0x34000>, - <0x0 0x03de0000 0x0 0x10000>, - <0x0 0x0b290000 0x0 0x10000>; - reg-names =3D "gmu", "rscc", "gmu_pdc"; - interrupts =3D , - ; - interrupt-names =3D "hfi", "gmu"; - clocks =3D <&gpucc GPU_CC_CX_GMU_CLK>, - <&gpucc GPU_CC_CXO_CLK>, - <&gcc GCC_DDRSS_GPU_AXI_CLK>, - <&gcc GCC_GPU_MEMNOC_GFX_CLK>, - <&gpucc GPU_CC_AHB_CLK>, - <&gpucc GPU_CC_HUB_CX_INT_CLK>, - <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; - clock-names =3D "gmu", - "cxo", - "axi", - "memnoc", - "ahb", - "hub", - "smmu_vote"; - power-domains =3D <&gpucc GPU_CC_CX_GDSC>, - <&gpucc GPU_CC_GX_GDSC>; - power-domain-names =3D "cx", - "gx"; - iommus =3D <&adreno_smmu 5 0xc00>; - operating-points-v2 =3D <&gmu_opp_table>; - - gmu_opp_table: opp-table { - compatible =3D "operating-points-v2"; - - opp-500000000 { - opp-hz =3D /bits/ 64 <500000000>; - opp-level =3D ; - }; - }; - }; - - gpucc: clock-controller@3d90000 { - compatible =3D "qcom,sa8775p-gpucc"; - reg =3D <0x0 0x03d90000 0x0 0xa000>; - clocks =3D <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_GPU_GPLL0_CLK_SRC>, - <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; - clock-names =3D "bi_tcxo", - "gcc_gpu_gpll0_clk_src", - "gcc_gpu_gpll0_div_clk_src"; - #clock-cells =3D <1>; - #reset-cells =3D <1>; - #power-domain-cells =3D <1>; }; =20 adreno_smmu: iommu@3da0000 { @@ -4765,21 +3104,6 @@ adreno_smmu: iommu@3da0000 { #iommu-cells =3D <2>; #global-interrupts =3D <2>; dma-coherent; - power-domains =3D <&gpucc GPU_CC_CX_GDSC>; - clocks =3D <&gcc GCC_GPU_MEMNOC_GFX_CLK>, - <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, - <&gpucc GPU_CC_AHB_CLK>, - <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, - <&gpucc GPU_CC_CX_GMU_CLK>, - <&gpucc GPU_CC_HUB_CX_INT_CLK>, - <&gpucc GPU_CC_HUB_AON_CLK>; - clock-names =3D "gcc_gpu_memnoc_gfx_clk", - "gcc_gpu_snoc_dvm_gfx_clk", - "gpu_cc_ahb_clk", - "gpu_cc_hlos1_vote_gpu_smmu_clk", - "gpu_cc_cx_gmu_clk", - "gpu_cc_hub_cx_int_clk", - "gpu_cc_hub_aon_clk"; interrupts =3D , , , @@ -4794,119 +3118,6 @@ adreno_smmu: iommu@3da0000 { ; }; =20 - serdes0: phy@8901000 { - compatible =3D "qcom,sa8775p-dwmac-sgmii-phy"; - reg =3D <0x0 0x08901000 0x0 0xe10>; - clocks =3D <&gcc GCC_SGMI_CLKREF_EN>; - clock-names =3D "sgmi_ref"; - #phy-cells =3D <0>; - status =3D "disabled"; - }; - - serdes1: phy@8902000 { - compatible =3D "qcom,sa8775p-dwmac-sgmii-phy"; - reg =3D <0x0 0x08902000 0x0 0xe10>; - clocks =3D <&gcc GCC_SGMI_CLKREF_EN>; - clock-names =3D "sgmi_ref"; - #phy-cells =3D <0>; - status =3D "disabled"; - }; - - pmu@9091000 { - compatible =3D "qcom,sa8775p-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; - reg =3D <0x0 0x9091000 0x0 0x1000>; - interrupts =3D ; - interconnects =3D <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; - - operating-points-v2 =3D <&llcc_bwmon_opp_table>; - - llcc_bwmon_opp_table: opp-table { - compatible =3D "operating-points-v2"; - - opp-0 { - opp-peak-kBps =3D <762000>; - }; - - opp-1 { - opp-peak-kBps =3D <1720000>; - }; - - opp-2 { - opp-peak-kBps =3D <2086000>; - }; - - opp-3 { - opp-peak-kBps =3D <2601000>; - }; - - opp-4 { - opp-peak-kBps =3D <2929000>; - }; - - opp-5 { - opp-peak-kBps =3D <5931000>; - }; - - opp-6 { - opp-peak-kBps =3D <6515000>; - }; - - opp-7 { - opp-peak-kBps =3D <7984000>; - }; - - opp-8 { - opp-peak-kBps =3D <10437000>; - }; - - opp-9 { - opp-peak-kBps =3D <12195000>; - }; - }; - }; - - pmu@90b5400 { - compatible =3D "qcom,sa8775p-cpu-bwmon", "qcom,sdm845-bwmon"; - reg =3D <0x0 0x90b5400 0x0 0x600>; - interrupts =3D ; - interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY - &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; - - operating-points-v2 =3D <&cpu_bwmon_opp_table>; - - cpu_bwmon_opp_table: opp-table { - compatible =3D "operating-points-v2"; - - opp-0 { - opp-peak-kBps =3D <9155000>; - }; - - opp-1 { - opp-peak-kBps =3D <12298000>; - }; - - opp-2 { - opp-peak-kBps =3D <14236000>; - }; - - opp-3 { - opp-peak-kBps =3D <16265000>; - }; - }; - - }; - - pmu@90b6400 { - compatible =3D "qcom,sa8775p-cpu-bwmon", "qcom,sdm845-bwmon"; - reg =3D <0x0 0x90b6400 0x0 0x600>; - interrupts =3D ; - interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY - &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; - - operating-points-v2 =3D <&cpu_bwmon_opp_table>; - }; - llcc: system-cache-controller@9200000 { compatible =3D "qcom,sa8775p-llcc"; reg =3D <0x0 0x09200000 0x0 0x80000>, @@ -4932,237 +3143,41 @@ iris: video-codec@aa00000 { reg =3D <0x0 0x0aa00000 0x0 0xf0000>; interrupts =3D ; =20 - power-domains =3D <&videocc VIDEO_CC_MVS0C_GDSC>, - <&videocc VIDEO_CC_MVS0_GDSC>, - <&rpmhpd SA8775P_MX>, - <&rpmhpd SA8775P_MMCX>; - power-domain-names =3D "venus", - "vcodec0", - "mxc", - "mmcx"; - operating-points-v2 =3D <&iris_opp_table>; - - clocks =3D <&gcc GCC_VIDEO_AXI0_CLK>, - <&videocc VIDEO_CC_MVS0C_CLK>, - <&videocc VIDEO_CC_MVS0_CLK>; - clock-names =3D "iface", - "core", - "vcodec0_core"; - - interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY - &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, - <&mmss_noc MASTER_VIDEO_P0 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names =3D "cpu-cfg", - "video-mem"; - memory-region =3D <&pil_video_mem>; =20 - resets =3D <&gcc GCC_VIDEO_AXI0_CLK_ARES>; - reset-names =3D "bus"; - iommus =3D <&apps_smmu 0x0880 0x0400>, <&apps_smmu 0x0887 0x0400>; dma-coherent; =20 status =3D "disabled"; - - iris_opp_table: opp-table { - compatible =3D "operating-points-v2"; - - opp-366000000 { - opp-hz =3D /bits/ 64 <366000000>; - required-opps =3D <&rpmhpd_opp_svs_l1>, - <&rpmhpd_opp_svs_l1>; - }; - - opp-444000000 { - opp-hz =3D /bits/ 64 <444000000>; - required-opps =3D <&rpmhpd_opp_svs_l1>, - <&rpmhpd_opp_nom>; - }; - - opp-533000000 { - opp-hz =3D /bits/ 64 <533000000>; - required-opps =3D <&rpmhpd_opp_nom>, - <&rpmhpd_opp_turbo>; - }; - - opp-560000000 { - opp-hz =3D /bits/ 64 <560000000>; - required-opps =3D <&rpmhpd_opp_nom>, - <&rpmhpd_opp_turbo_l1>; - }; - }; - }; - - videocc: clock-controller@abf0000 { - compatible =3D "qcom,sa8775p-videocc"; - reg =3D <0x0 0x0abf0000 0x0 0x10000>; - clocks =3D <&gcc GCC_VIDEO_AHB_CLK>, - <&rpmhcc RPMH_CXO_CLK>, - <&rpmhcc RPMH_CXO_CLK_A>, - <&sleep_clk>; - power-domains =3D <&rpmhpd SA8775P_MMCX>; - #clock-cells =3D <1>; - #reset-cells =3D <1>; - #power-domain-cells =3D <1>; }; =20 cci0: cci@ac13000 { compatible =3D "qcom,sa8775p-cci", "qcom,msm8996-cci"; reg =3D <0x0 0x0ac13000 0x0 0x1000>; - interrupts =3D ; - - power-domains =3D <&camcc CAM_CC_TITAN_TOP_GDSC>; - - clocks =3D <&camcc CAM_CC_CAMNOC_AXI_CLK>, - <&camcc CAM_CC_CPAS_AHB_CLK>, - <&camcc CAM_CC_CCI_0_CLK>; - clock-names =3D "camnoc_axi", - "cpas_ahb", - "cci"; - - pinctrl-0 =3D <&cci0_0_default &cci0_1_default>; - pinctrl-1 =3D <&cci0_0_sleep &cci0_1_sleep>; - pinctrl-names =3D "default", "sleep"; - - #address-cells =3D <1>; - #size-cells =3D <0>; - status =3D "disabled"; - - cci0_i2c0: i2c-bus@0 { - reg =3D <0>; - clock-frequency =3D <1000000>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - - cci0_i2c1: i2c-bus@1 { - reg =3D <1>; - clock-frequency =3D <1000000>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; }; =20 cci1: cci@ac14000 { compatible =3D "qcom,sa8775p-cci", "qcom,msm8996-cci"; reg =3D <0x0 0x0ac14000 0x0 0x1000>; - interrupts =3D ; - - power-domains =3D <&camcc CAM_CC_TITAN_TOP_GDSC>; - - clocks =3D <&camcc CAM_CC_CAMNOC_AXI_CLK>, - <&camcc CAM_CC_CPAS_AHB_CLK>, - <&camcc CAM_CC_CCI_1_CLK>; - clock-names =3D "camnoc_axi", - "cpas_ahb", - "cci"; - - pinctrl-0 =3D <&cci1_0_default &cci1_1_default>; - pinctrl-1 =3D <&cci1_0_sleep &cci1_1_sleep>; - pinctrl-names =3D "default", "sleep"; - - #address-cells =3D <1>; - #size-cells =3D <0>; - status =3D "disabled"; - - cci1_i2c0: i2c-bus@0 { - reg =3D <0>; - clock-frequency =3D <1000000>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - - cci1_i2c1: i2c-bus@1 { - reg =3D <1>; - clock-frequency =3D <1000000>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; }; =20 cci2: cci@ac15000 { compatible =3D "qcom,sa8775p-cci", "qcom,msm8996-cci"; reg =3D <0x0 0x0ac15000 0x0 0x1000>; - interrupts =3D ; - - power-domains =3D <&camcc CAM_CC_TITAN_TOP_GDSC>; - - clocks =3D <&camcc CAM_CC_CAMNOC_AXI_CLK>, - <&camcc CAM_CC_CPAS_AHB_CLK>, - <&camcc CAM_CC_CCI_2_CLK>; - clock-names =3D "camnoc_axi", - "cpas_ahb", - "cci"; - - pinctrl-0 =3D <&cci2_0_default &cci2_1_default>; - pinctrl-1 =3D <&cci2_0_sleep &cci2_1_sleep>; - pinctrl-names =3D "default", "sleep"; - - #address-cells =3D <1>; - #size-cells =3D <0>; - status =3D "disabled"; - - cci2_i2c0: i2c-bus@0 { - reg =3D <0>; - clock-frequency =3D <1000000>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - - cci2_i2c1: i2c-bus@1 { - reg =3D <1>; - clock-frequency =3D <1000000>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; }; =20 cci3: cci@ac16000 { compatible =3D "qcom,sa8775p-cci", "qcom,msm8996-cci"; reg =3D <0x0 0x0ac16000 0x0 0x1000>; - interrupts =3D ; - - power-domains =3D <&camcc CAM_CC_TITAN_TOP_GDSC>; - - clocks =3D <&camcc CAM_CC_CAMNOC_AXI_CLK>, - <&camcc CAM_CC_CPAS_AHB_CLK>, - <&camcc CAM_CC_CCI_3_CLK>; - clock-names =3D "camnoc_axi", - "cpas_ahb", - "cci"; - - pinctrl-0 =3D <&cci3_0_default &cci3_1_default>; - pinctrl-1 =3D <&cci3_0_sleep &cci3_1_sleep>; - pinctrl-names =3D "default", "sleep"; - - #address-cells =3D <1>; - #size-cells =3D <0>; - status =3D "disabled"; - - cci3_i2c0: i2c-bus@0 { - reg =3D <0>; - clock-frequency =3D <1000000>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - - cci3_i2c1: i2c-bus@1 { - reg =3D <1>; - clock-frequency =3D <1000000>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; }; =20 camss: isp@ac78000 { @@ -5213,63 +3228,6 @@ camss: isp@ac78000 { "vfe_lite3", "vfe_lite4"; =20 - clocks =3D <&camcc CAM_CC_CAMNOC_AXI_CLK>, - <&camcc CAM_CC_CORE_AHB_CLK>, - <&camcc CAM_CC_CPAS_AHB_CLK>, - <&camcc CAM_CC_CPAS_FAST_AHB_CLK>, - <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, - <&camcc CAM_CC_CPAS_IFE_0_CLK>, - <&camcc CAM_CC_CPAS_IFE_1_CLK>, - <&camcc CAM_CC_CSID_CLK>, - <&camcc CAM_CC_CSIPHY0_CLK>, - <&camcc CAM_CC_CSI0PHYTIMER_CLK>, - <&camcc CAM_CC_CSIPHY1_CLK>, - <&camcc CAM_CC_CSI1PHYTIMER_CLK>, - <&camcc CAM_CC_CSIPHY2_CLK>, - <&camcc CAM_CC_CSI2PHYTIMER_CLK>, - <&camcc CAM_CC_CSIPHY3_CLK>, - <&camcc CAM_CC_CSI3PHYTIMER_CLK>, - <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>, - <&gcc GCC_CAMERA_HF_AXI_CLK>, - <&gcc GCC_CAMERA_SF_AXI_CLK>, - <&camcc CAM_CC_ICP_AHB_CLK>, - <&camcc CAM_CC_IFE_0_CLK>, - <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>, - <&camcc CAM_CC_IFE_1_CLK>, - <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>, - <&camcc CAM_CC_IFE_LITE_CLK>, - <&camcc CAM_CC_IFE_LITE_AHB_CLK>, - <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, - <&camcc CAM_CC_IFE_LITE_CSID_CLK>; - clock-names =3D "camnoc_axi", - "core_ahb", - "cpas_ahb", - "cpas_fast_ahb_clk", - "cpas_vfe_lite", - "cpas_vfe0", - "cpas_vfe1", - "csid", - "csiphy0", - "csiphy0_timer", - "csiphy1", - "csiphy1_timer", - "csiphy2", - "csiphy2_timer", - "csiphy3", - "csiphy3_timer", - "csiphy_rx", - "gcc_axi_hf", - "gcc_axi_sf", - "icp_ahb", - "vfe0", - "vfe0_fast_ahb", - "vfe1", - "vfe1_fast_ahb", - "vfe_lite", - "vfe_lite_ahb", - "vfe_lite_cphy_rx", - "vfe_lite_csid"; - interrupts =3D , , , @@ -5313,18 +3271,8 @@ camss: isp@ac78000 { "vfe_lite3", "vfe_lite4"; =20 - interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY - &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, - <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names =3D "ahb", - "hf_0"; - iommus =3D <&apps_smmu 0x3400 0x20>; =20 - power-domains =3D <&camcc CAM_CC_TITAN_TOP_GDSC>; - power-domain-names =3D "top"; - status =3D "disabled"; =20 ports { @@ -5349,43 +3297,11 @@ port@3 { }; }; =20 - camcc: clock-controller@ade0000 { - compatible =3D "qcom,sa8775p-camcc"; - reg =3D <0x0 0x0ade0000 0x0 0x20000>; - clocks =3D <&gcc GCC_CAMERA_AHB_CLK>, - <&rpmhcc RPMH_CXO_CLK>, - <&rpmhcc RPMH_CXO_CLK_A>, - <&sleep_clk>; - power-domains =3D <&rpmhpd SA8775P_MMCX>; - #clock-cells =3D <1>; - #reset-cells =3D <1>; - #power-domain-cells =3D <1>; - }; - mdss0: display-subsystem@ae00000 { compatible =3D "qcom,sa8775p-mdss"; reg =3D <0x0 0x0ae00000 0x0 0x1000>; reg-names =3D "mdss"; =20 - /* same path used twice */ - interconnects =3D <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, - <&mmss_noc MASTER_MDP1 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY - &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; - interconnect-names =3D "mdp0-mem", - "mdp1-mem", - "cpu-cfg"; - - resets =3D <&dispcc0 MDSS_DISP_CC_MDSS_CORE_BCR>; - - power-domains =3D <&dispcc0 MDSS_DISP_CC_MDSS_CORE_GDSC>; - - clocks =3D <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, - <&gcc GCC_DISP_HF_AXI_CLK>, - <&dispcc0 MDSS_DISP_CC_MDSS_MDP_CLK>; - interrupts =3D ; interrupt-controller; #interrupt-cells =3D <1>; @@ -5404,23 +3320,6 @@ mdss0_mdp: display-controller@ae01000 { <0x0 0x0aeb0000 0x0 0x3000>; reg-names =3D "mdp", "vbif"; =20 - clocks =3D <&gcc GCC_DISP_HF_AXI_CLK>, - <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, - <&dispcc0 MDSS_DISP_CC_MDSS_MDP_LUT_CLK>, - <&dispcc0 MDSS_DISP_CC_MDSS_MDP_CLK>, - <&dispcc0 MDSS_DISP_CC_MDSS_VSYNC_CLK>; - clock-names =3D "nrt_bus", - "iface", - "lut", - "core", - "vsync"; - - assigned-clocks =3D <&dispcc0 MDSS_DISP_CC_MDSS_VSYNC_CLK>; - assigned-clock-rates =3D <19200000>; - - operating-points-v2 =3D <&mdss0_mdp_opp_table>; - power-domains =3D <&rpmhpd SA8775P_MMCX>; - interrupt-parent =3D <&mdss0>; interrupts =3D <0>; =20 @@ -5460,30 +3359,6 @@ dpu_intf2_out: endpoint { }; }; }; - - mdss0_mdp_opp_table: opp-table { - compatible =3D "operating-points-v2"; - - opp-375000000 { - opp-hz =3D /bits/ 64 <375000000>; - required-opps =3D <&rpmhpd_opp_svs_l1>; - }; - - opp-500000000 { - opp-hz =3D /bits/ 64 <500000000>; - required-opps =3D <&rpmhpd_opp_nom>; - }; - - opp-575000000 { - opp-hz =3D /bits/ 64 <575000000>; - required-opps =3D <&rpmhpd_opp_turbo>; - }; - - opp-650000000 { - opp-hz =3D /bits/ 64 <650000000>; - required-opps =3D <&rpmhpd_opp_turbo_l1>; - }; - }; }; =20 mdss0_dsi0: dsi@ae94000 { @@ -5494,29 +3369,6 @@ mdss0_dsi0: dsi@ae94000 { interrupt-parent =3D <&mdss0>; interrupts =3D <4>; =20 - clocks =3D <&dispcc0 MDSS_DISP_CC_MDSS_BYTE0_CLK>, - <&dispcc0 MDSS_DISP_CC_MDSS_BYTE0_INTF_CLK>, - <&dispcc0 MDSS_DISP_CC_MDSS_PCLK0_CLK>, - <&dispcc0 MDSS_DISP_CC_MDSS_ESC0_CLK>, - <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, - <&gcc GCC_DISP_HF_AXI_CLK>; - clock-names =3D "byte", - "byte_intf", - "pixel", - "core", - "iface", - "bus"; - assigned-clocks =3D <&dispcc0 MDSS_DISP_CC_MDSS_BYTE0_CLK_SRC>, - <&dispcc0 MDSS_DISP_CC_MDSS_PCLK0_CLK_SRC>; - assigned-clock-parents =3D <&mdss0_dsi0_phy DSI_BYTE_PLL_CLK>, - <&mdss0_dsi0_phy DSI_PIXEL_PLL_CLK>; - phys =3D <&mdss0_dsi0_phy>; - - operating-points-v2 =3D <&mdss_dsi_opp_table>; - power-domains =3D <&rpmhpd SA8775P_MMCX>; - - refgen-supply =3D <&refgen>; - #address-cells =3D <1>; #size-cells =3D <0>; =20 @@ -5540,34 +3392,6 @@ port@1 { mdss0_dsi0_out: endpoint { }; }; }; - - mdss_dsi_opp_table: opp-table { - compatible =3D "operating-points-v2"; - - opp-358000000 { - opp-hz =3D /bits/ 64 <358000000>; - required-opps =3D <&rpmhpd_opp_svs_l1>; - }; - }; - }; - - mdss0_dsi0_phy: phy@ae94400 { - compatible =3D "qcom,sa8775p-dsi-phy-5nm"; - reg =3D <0x0 0x0ae94400 0x0 0x200>, - <0x0 0x0ae94600 0x0 0x280>, - <0x0 0x0ae94900 0x0 0x27c>; - reg-names =3D "dsi_phy", - "dsi_phy_lane", - "dsi_pll"; - - #clock-cells =3D <1>; - #phy-cells =3D <0>; - - clocks =3D <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, - <&rpmhcc RPMH_CXO_CLK>; - clock-names =3D "iface", "ref"; - - status =3D "disabled"; }; =20 mdss0_dsi1: dsi@ae96000 { @@ -5578,29 +3402,6 @@ mdss0_dsi1: dsi@ae96000 { interrupt-parent =3D <&mdss0>; interrupts =3D <5>; =20 - clocks =3D <&dispcc0 MDSS_DISP_CC_MDSS_BYTE1_CLK>, - <&dispcc0 MDSS_DISP_CC_MDSS_BYTE1_INTF_CLK>, - <&dispcc0 MDSS_DISP_CC_MDSS_PCLK1_CLK>, - <&dispcc0 MDSS_DISP_CC_MDSS_ESC1_CLK>, - <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, - <&gcc GCC_DISP_HF_AXI_CLK>; - clock-names =3D "byte", - "byte_intf", - "pixel", - "core", - "iface", - "bus"; - assigned-clocks =3D <&dispcc0 MDSS_DISP_CC_MDSS_BYTE1_CLK_SRC>, - <&dispcc0 MDSS_DISP_CC_MDSS_PCLK1_CLK_SRC>; - assigned-clock-parents =3D <&mdss0_dsi1_phy DSI_BYTE_PLL_CLK>, - <&mdss0_dsi1_phy DSI_PIXEL_PLL_CLK>; - phys =3D <&mdss0_dsi1_phy>; - - operating-points-v2 =3D <&mdss_dsi_opp_table>; - power-domains =3D <&rpmhpd SA8775P_MMCX>; - - refgen-supply =3D <&refgen>; - #address-cells =3D <1>; #size-cells =3D <0>; =20 @@ -5626,63 +3427,6 @@ port@1 { }; }; =20 - mdss0_dsi1_phy: phy@ae96400 { - compatible =3D "qcom,sa8775p-dsi-phy-5nm"; - reg =3D <0x0 0x0ae96400 0x0 0x200>, - <0x0 0x0ae96600 0x0 0x280>, - <0x0 0x0ae96900 0x0 0x27c>; - reg-names =3D "dsi_phy", - "dsi_phy_lane", - "dsi_pll"; - - #clock-cells =3D <1>; - #phy-cells =3D <0>; - - clocks =3D <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, - <&rpmhcc RPMH_CXO_CLK>; - clock-names =3D "iface", "ref"; - - status =3D "disabled"; - }; - - mdss0_dp0_phy: phy@aec2a00 { - compatible =3D "qcom,sa8775p-edp-phy"; - - reg =3D <0x0 0x0aec2a00 0x0 0x200>, - <0x0 0x0aec2200 0x0 0xd0>, - <0x0 0x0aec2600 0x0 0xd0>, - <0x0 0x0aec2000 0x0 0x1c8>; - - clocks =3D <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, - <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>; - clock-names =3D "aux", - "cfg_ahb"; - - #clock-cells =3D <1>; - #phy-cells =3D <0>; - - status =3D "disabled"; - }; - - mdss0_dp1_phy: phy@aec5a00 { - compatible =3D "qcom,sa8775p-edp-phy"; - - reg =3D <0x0 0x0aec5a00 0x0 0x200>, - <0x0 0x0aec5200 0x0 0xd0>, - <0x0 0x0aec5600 0x0 0xd0>, - <0x0 0x0aec5000 0x0 0x1c8>; - - clocks =3D <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>, - <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>; - clock-names =3D "aux", - "cfg_ahb"; - - #clock-cells =3D <1>; - #phy-cells =3D <0>; - - status =3D "disabled"; - }; - mdss0_dp0: displayport-controller@af54000 { compatible =3D "qcom,sa8775p-dp"; =20 @@ -5699,38 +3443,6 @@ mdss0_dp0: displayport-controller@af54000 { interrupt-parent =3D <&mdss0>; interrupts =3D <12>; =20 - clocks =3D <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, - <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, - <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK>, - <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, - <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, - <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK>, - <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK>, - <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK>; - clock-names =3D "core_iface", - "core_aux", - "ctrl_link", - "ctrl_link_iface", - "stream_pixel", - "stream_1_pixel", - "stream_2_pixel", - "stream_3_pixel"; - assigned-clocks =3D <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, - <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, - <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>, - <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK_SRC>, - <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK_SRC>; - assigned-clock-parents =3D <&mdss0_dp0_phy 0>, - <&mdss0_dp0_phy 1>, - <&mdss0_dp0_phy 1>, - <&mdss0_dp0_phy 1>, - <&mdss0_dp0_phy 1>; - phys =3D <&mdss0_dp0_phy>; - phy-names =3D "dp"; - - operating-points-v2 =3D <&dp_opp_table>; - power-domains =3D <&rpmhpd SA8775P_MMCX>; - #sound-dai-cells =3D <0>; =20 status =3D "disabled"; @@ -5753,30 +3465,6 @@ port@1 { mdss0_dp0_out: endpoint { }; }; }; - - dp_opp_table: opp-table { - compatible =3D "operating-points-v2"; - - opp-162000000 { - opp-hz =3D /bits/ 64 <162000000>; - required-opps =3D <&rpmhpd_opp_low_svs>; - }; - - opp-270000000 { - opp-hz =3D /bits/ 64 <270000000>; - required-opps =3D <&rpmhpd_opp_svs>; - }; - - opp-540000000 { - opp-hz =3D /bits/ 64 <540000000>; - required-opps =3D <&rpmhpd_opp_svs_l1>; - }; - - opp-810000000 { - opp-hz =3D /bits/ 64 <810000000>; - required-opps =3D <&rpmhpd_opp_nom>; - }; - }; }; =20 mdss0_dp1: displayport-controller@af5c000 { @@ -5795,30 +3483,6 @@ mdss0_dp1: displayport-controller@af5c000 { interrupt-parent =3D <&mdss0>; interrupts =3D <13>; =20 - clocks =3D <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, - <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>, - <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK>, - <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, - <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK>, - <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK>; - clock-names =3D "core_iface", - "core_aux", - "ctrl_link", - "ctrl_link_iface", - "stream_pixel", - "stream_1_pixel"; - assigned-clocks =3D <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, - <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>, - <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>; - assigned-clock-parents =3D <&mdss0_dp1_phy 0>, - <&mdss0_dp1_phy 1>, - <&mdss0_dp1_phy 1>; - phys =3D <&mdss0_dp1_phy>; - phy-names =3D "dp"; - - operating-points-v2 =3D <&dp1_opp_table>; - power-domains =3D <&rpmhpd SA8775P_MMCX>; - #sound-dai-cells =3D <0>; =20 status =3D "disabled"; @@ -5841,52 +3505,9 @@ port@1 { mdss0_dp1_out: endpoint { }; }; }; - - dp1_opp_table: opp-table { - compatible =3D "operating-points-v2"; - - opp-162000000 { - opp-hz =3D /bits/ 64 <162000000>; - required-opps =3D <&rpmhpd_opp_low_svs>; - }; - - opp-270000000 { - opp-hz =3D /bits/ 64 <270000000>; - required-opps =3D <&rpmhpd_opp_svs>; - }; - - opp-540000000 { - opp-hz =3D /bits/ 64 <540000000>; - required-opps =3D <&rpmhpd_opp_svs_l1>; - }; - - opp-810000000 { - opp-hz =3D /bits/ 64 <810000000>; - required-opps =3D <&rpmhpd_opp_nom>; - }; - }; }; }; =20 - dispcc0: clock-controller@af00000 { - compatible =3D "qcom,sa8775p-dispcc0"; - reg =3D <0x0 0x0af00000 0x0 0x20000>; - clocks =3D <&gcc GCC_DISP_AHB_CLK>, - <&rpmhcc RPMH_CXO_CLK>, - <&rpmhcc RPMH_CXO_CLK_A>, - <&sleep_clk>, - <&mdss0_dp0_phy 0>, <&mdss0_dp0_phy 1>, - <&mdss0_dp1_phy 0>, <&mdss0_dp1_phy 1>, - <&mdss0_dsi0_phy DSI_BYTE_PLL_CLK>, - <&mdss0_dsi0_phy DSI_PIXEL_PLL_CLK>, - <&mdss0_dsi1_phy DSI_BYTE_PLL_CLK>, - <&mdss0_dsi1_phy DSI_PIXEL_PLL_CLK>; - power-domains =3D <&rpmhpd SA8775P_MMCX>; - #clock-cells =3D <1>; - #reset-cells =3D <1>; - #power-domain-cells =3D <1>; - }; - pdc: interrupt-controller@b220000 { compatible =3D "qcom,sa8775p-pdc", "qcom,pdc"; reg =3D <0x0 0x0b220000 0x0 0x30000>, @@ -6332,95 +3953,6 @@ frame@17c2d000 { }; }; =20 - apps_rsc: rsc@18200000 { - compatible =3D "qcom,rpmh-rsc"; - reg =3D <0x0 0x18200000 0x0 0x10000>, - <0x0 0x18210000 0x0 0x10000>, - <0x0 0x18220000 0x0 0x10000>; - reg-names =3D "drv-0", "drv-1", "drv-2"; - interrupts =3D , - , - ; - qcom,tcs-offset =3D <0xd00>; - qcom,drv-id =3D <2>; - qcom,tcs-config =3D , - , - , - ; - label =3D "apps_rsc"; - power-domains =3D <&system_pd>; - - apps_bcm_voter: bcm-voter { - compatible =3D "qcom,bcm-voter"; - }; - - rpmhcc: clock-controller { - compatible =3D "qcom,sa8775p-rpmh-clk"; - #clock-cells =3D <1>; - clock-names =3D "xo"; - clocks =3D <&xo_board_clk>; - }; - - rpmhpd: power-controller { - compatible =3D "qcom,sa8775p-rpmhpd"; - #power-domain-cells =3D <1>; - operating-points-v2 =3D <&rpmhpd_opp_table>; - - rpmhpd_opp_table: opp-table { - compatible =3D "operating-points-v2"; - - rpmhpd_opp_ret: opp-0 { - opp-level =3D ; - }; - - rpmhpd_opp_min_svs: opp-1 { - opp-level =3D ; - }; - - rpmhpd_opp_low_svs: opp2 { - opp-level =3D ; - }; - - rpmhpd_opp_svs: opp3 { - opp-level =3D ; - }; - - rpmhpd_opp_svs_l1: opp-4 { - opp-level =3D ; - }; - - rpmhpd_opp_nom: opp-5 { - opp-level =3D ; - }; - - rpmhpd_opp_nom_l1: opp-6 { - opp-level =3D ; - }; - - rpmhpd_opp_nom_l2: opp-7 { - opp-level =3D ; - }; - - rpmhpd_opp_turbo: opp-8 { - opp-level =3D ; - }; - - rpmhpd_opp_turbo_l1: opp-9 { - opp-level =3D ; - }; - }; - }; - }; - - epss_l3_cl0: interconnect@18590000 { - compatible =3D "qcom,sa8775p-epss-l3", - "qcom,epss-l3"; - reg =3D <0x0 0x18590000 0x0 0x1000>; - clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; - clock-names =3D "xo", "alternate"; - #interconnect-cells =3D <1>; - }; - cpufreq_hw: cpufreq@18591000 { compatible =3D "qcom,sa8775p-cpufreq-epss", "qcom,cpufreq-epss"; @@ -6432,21 +3964,9 @@ cpufreq_hw: cpufreq@18591000 { ; interrupt-names =3D "dcvsh-irq-0", "dcvsh-irq-1"; =20 - clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; - clock-names =3D "xo", "alternate"; - #freq-domain-cells =3D <1>; }; =20 - epss_l3_cl1: interconnect@18592000 { - compatible =3D "qcom,sa8775p-epss-l3", - "qcom,epss-l3"; - reg =3D <0x0 0x18592000 0x0 0x1000>; - clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; - clock-names =3D "xo", "alternate"; - #interconnect-cells =3D <1>; - }; - remoteproc_gpdsp0: remoteproc@20c00000 { compatible =3D "qcom,sa8775p-gpdsp0-pas"; reg =3D <0x0 0x20c00000 0x0 0x10000>; @@ -6459,16 +3979,6 @@ remoteproc_gpdsp0: remoteproc@20c00000 { interrupt-names =3D "wdog", "fatal", "ready", "handover", "stop-ack"; =20 - clocks =3D <&rpmhcc RPMH_CXO_CLK>; - clock-names =3D "xo"; - - power-domains =3D <&rpmhpd SA8775P_CX>, - <&rpmhpd SA8775P_MXC>; - power-domain-names =3D "cx", "mxc"; - - interconnects =3D <&gpdsp_anoc MASTER_DSP0 0 - &config_noc SLAVE_CLK_CTL 0>; - memory-region =3D <&pil_gdsp0_mem>; =20 qcom,qmp =3D <&aoss_qmp>; @@ -6531,16 +4041,6 @@ remoteproc_gpdsp1: remoteproc@21c00000 { interrupt-names =3D "wdog", "fatal", "ready", "handover", "stop-ack"; =20 - clocks =3D <&rpmhcc RPMH_CXO_CLK>; - clock-names =3D "xo"; - - power-domains =3D <&rpmhpd SA8775P_CX>, - <&rpmhpd SA8775P_MXC>; - power-domain-names =3D "cx", "mxc"; - - interconnects =3D <&gpdsp_anoc MASTER_DSP1 0 - &config_noc SLAVE_CLK_CTL 0>; - memory-region =3D <&pil_gdsp1_mem>; =20 qcom,qmp =3D <&aoss_qmp>; @@ -6591,22 +4091,6 @@ compute-cb@3 { }; }; =20 - dispcc1: clock-controller@22100000 { - compatible =3D "qcom,sa8775p-dispcc1"; - reg =3D <0x0 0x22100000 0x0 0x20000>; - clocks =3D <&gcc GCC_DISP_AHB_CLK>, - <&rpmhcc RPMH_CXO_CLK>, - <&rpmhcc RPMH_CXO_CLK_A>, - <&sleep_clk>, - <0>, <0>, <0>, <0>, - <0>, <0>, <0>, <0>; - power-domains =3D <&rpmhpd SA8775P_MMCX>; - #clock-cells =3D <1>; - #reset-cells =3D <1>; - #power-domain-cells =3D <1>; - status =3D "disabled"; - }; - ethernet1: ethernet@23000000 { compatible =3D "qcom,sa8775p-ethqos"; reg =3D <0x0 0x23000000 0x0 0x10000>, @@ -6617,27 +4101,6 @@ ethernet1: ethernet@23000000 { ; interrupt-names =3D "macirq", "sfty"; =20 - clocks =3D <&gcc GCC_EMAC1_AXI_CLK>, - <&gcc GCC_EMAC1_SLV_AHB_CLK>, - <&gcc GCC_EMAC1_PTP_CLK>, - <&gcc GCC_EMAC1_PHY_AUX_CLK>; - clock-names =3D "stmmaceth", - "pclk", - "ptp_ref", - "phyaux"; - - interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_EMAC1_CFG QCOM_ICC_TAG_ALWAYS>, - <&aggre1_noc MASTER_EMAC_1 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names =3D "cpu-mac", - "mac-mem"; - - power-domains =3D <&gcc EMAC1_GDSC>; - - phys =3D <&serdes1>; - phy-names =3D "serdes"; - iommus =3D <&apps_smmu 0x140 0xf>; dma-coherent; =20 @@ -6659,27 +4122,6 @@ ethernet0: ethernet@23040000 { ; interrupt-names =3D "macirq", "sfty"; =20 - clocks =3D <&gcc GCC_EMAC0_AXI_CLK>, - <&gcc GCC_EMAC0_SLV_AHB_CLK>, - <&gcc GCC_EMAC0_PTP_CLK>, - <&gcc GCC_EMAC0_PHY_AUX_CLK>; - clock-names =3D "stmmaceth", - "pclk", - "ptp_ref", - "phyaux"; - - interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_EMAC_CFG QCOM_ICC_TAG_ALWAYS>, - <&aggre1_noc MASTER_EMAC QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names =3D "cpu-mac", - "mac-mem"; - - power-domains =3D <&gcc EMAC0_GDSC>; - - phys =3D <&serdes0>; - phy-names =3D "serdes"; - iommus =3D <&apps_smmu 0x120 0xf>; dma-coherent; =20 @@ -6691,13 +4133,6 @@ &config_noc SLAVE_EMAC_CFG QCOM_ICC_TAG_ALWAYS>, status =3D "disabled"; }; =20 - nspa_noc: interconnect@260c0000 { - compatible =3D "qcom,sa8775p-nspa-noc"; - reg =3D <0x0 0x260c0000 0x0 0x16080>; - #interconnect-cells =3D <2>; - qcom,bcm-voters =3D <&apps_bcm_voter>; - }; - remoteproc_cdsp0: remoteproc@26300000 { compatible =3D "qcom,sa8775p-cdsp0-pas"; reg =3D <0x0 0x26300000 0x0 0x10000>; @@ -6710,17 +4145,6 @@ remoteproc_cdsp0: remoteproc@26300000 { interrupt-names =3D "wdog", "fatal", "ready", "handover", "stop-ack"; =20 - clocks =3D <&rpmhcc RPMH_CXO_CLK>; - clock-names =3D "xo"; - - power-domains =3D <&rpmhpd SA8775P_CX>, - <&rpmhpd SA8775P_MXC>, - <&rpmhpd SA8775P_NSP0>; - power-domain-names =3D "cx", "mxc", "nsp"; - - interconnects =3D <&nspa_noc MASTER_CDSP_PROC 0 - &mc_virt SLAVE_EBI1 0>; - memory-region =3D <&pil_cdsp0_mem>; =20 qcom,qmp =3D <&aoss_qmp>; @@ -6830,13 +4254,6 @@ compute-cb@11 { }; }; =20 - nspb_noc: interconnect@2a0c0000 { - compatible =3D "qcom,sa8775p-nspb-noc"; - reg =3D <0x0 0x2a0c0000 0x0 0x16080>; - #interconnect-cells =3D <2>; - qcom,bcm-voters =3D <&apps_bcm_voter>; - }; - remoteproc_cdsp1: remoteproc@2a300000 { compatible =3D "qcom,sa8775p-cdsp1-pas"; reg =3D <0x0 0x2a300000 0x0 0x10000>; @@ -6849,17 +4266,6 @@ remoteproc_cdsp1: remoteproc@2a300000 { interrupt-names =3D "wdog", "fatal", "ready", "handover", "stop-ack"; =20 - clocks =3D <&rpmhcc RPMH_CXO_CLK>; - clock-names =3D "xo"; - - power-domains =3D <&rpmhpd SA8775P_CX>, - <&rpmhpd SA8775P_MXC>, - <&rpmhpd SA8775P_NSP1>; - power-domain-names =3D "cx", "mxc", "nsp"; - - interconnects =3D <&nspb_noc MASTER_CDSP_PROC_B 0 - &mc_virt SLAVE_EBI1 0>; - memory-region =3D <&pil_cdsp1_mem>; =20 qcom,qmp =3D <&aoss_qmp>; @@ -7005,15 +4411,6 @@ remoteproc_adsp: remoteproc@30000000 { interrupt-names =3D "wdog", "fatal", "ready", "handover", "stop-ack"; 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[199.106.103.52]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2ca78df8942sm31265060eec.2.2026.04.09.02.12.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Apr 2026 02:12:06 -0700 (PDT) From: Shawn Guo To: Bjorn Andersson Cc: Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bartosz Golaszewski , Deepti Jaggi , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Shawn Guo , Shazad Hussain , Nikunj Kela Subject: [PATCH 6/8] arm64: dts: qcom: lemans: Introduce SA8255P SoC support Date: Thu, 9 Apr 2026 17:10:58 +0800 Message-ID: <20260409091100.474358-7-shengchao.guo@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260409091100.474358-1-shengchao.guo@oss.qualcomm.com> References: <20260409091100.474358-1-shengchao.guo@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDA5MDA4MSBTYWx0ZWRfX/biTkENwdWzu WroVyQiO6GuheOBdmvBRQT/cbXzlzPZb/Lap6+aCqmO5wfCjhFKqo7zHpXON37X3gQbaaWuYCGG HndPmfBQBj8goZGnBeN3QUC0vx9YoyK2qX16WTS02XBSMLUHrhlPK+uU89vBwVeDpEtMp0VCqUN 9yHGK2h7ipuWmygWImPUOcm9lrpA/4rILE3x3etX7bkBcjuQi1Ir8WeSuvfDQdrfy8UFSITVwAH AYSWvj5O8kd0rEGKo5Cq4CcQhsMyiPBM8c3FnIRq1ZicQYRAyfXlV/O+BIbBFoBMYJZErhJXXO3 sgYVKKVb03WW1DwKIXyCqN/CwjoskR2RrDAOu7S6ABTifmOYfDgJGqHQMN1MKsLELtU67eiJ4Xf R9UzLABQhOkkCe6AYtBQ9s05GRUsxoJj3PJRMw+n2GmQMSJzLzUV7VfmoDEjTcvi0Pe6M1IqMrQ m3gvWvnFbf5++fAYItQ== X-Authority-Analysis: v=2.4 cv=SsWgLvO0 c=1 sm=1 tr=0 ts=69d76d6a cx=c_pps a=SvEPeNj+VMjHSW//kvnxuw==:117 a=b9+bayejhc3NMeqCNyeLQQ==:17 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=KKAkSRfTAAAA:8 a=EUspDBNiAAAA:8 a=COk6AnOGAAAA:8 a=JrOUzMwsbUcBTIasdiwA:9 a=Kq8ClHjjuc5pcCNDwlU0:22 a=cvBusfyB2V15izCimMoJ:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: ZOr05RroXL_amkL8zwpkjREKAZFKM7GP X-Proofpoint-ORIG-GUID: ZOr05RroXL_amkL8zwpkjREKAZFKM7GP X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-09_02,2026-04-09_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 suspectscore=0 lowpriorityscore=0 priorityscore=1501 spamscore=0 impostorscore=0 adultscore=0 bulkscore=0 clxscore=1015 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604010000 definitions=main-2604090081 Content-Type: text/plain; charset="utf-8" Add support for SA8255P, a Lemans series SoC that utilizes firmware to configure platform resources such as clocks, interconnects and TLMM. Device drivers request these resources through the SCMI power, reset and performance protocols. Assign each device driver a dedicated SCMI channel and Tx/Rx doorbells to support parallel resource requests and aggregation in the SCMI platform server. Operate the SCMI server stack in an SMP-enabled VM using the Qualcomm SMC/HVC transport driver for communication. Group resource operations to improve abstraction and reduce the number of SCMI requests. Follow the SCMI-based resource management approach demonstrated by Qualcomm at Linaro Connect 2024 [1]. [1] https://resources.linaro.org/en/resource/wfnfEwBhRjLV1PEAJoDDte Co-developed-by: Shazad Hussain Signed-off-by: Shazad Hussain Signed-off-by: Nikunj Kela Co-developed-by: Deepti Jaggi Signed-off-by: Deepti Jaggi Signed-off-by: Shawn Guo Tested-by: Deepti Jaggi # sa8255p-ride board --- arch/arm64/boot/dts/qcom/lemans-sa8255p.dtsi | 3027 ++++++++++++++++++ 1 file changed, 3027 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/lemans-sa8255p.dtsi diff --git a/arch/arm64/boot/dts/qcom/lemans-sa8255p.dtsi b/arch/arm64/boot= /dts/qcom/lemans-sa8255p.dtsi new file mode 100644 index 000000000000..7f15d66c68f9 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/lemans-sa8255p.dtsi @@ -0,0 +1,3027 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include "lemans.dtsi" + +/delete-node/ &xbl_boot_mem; +/delete-node/ &pil_adsp_mem; +/delete-node/ &q6_adsp_dtb_mem; +/delete-node/ &q6_gdsp0_dtb_mem; +/delete-node/ &pil_gdsp0_mem; +/delete-node/ &pil_gdsp1_mem; +/delete-node/ &q6_gdsp1_dtb_mem; +/delete-node/ &q6_cdsp0_dtb_mem; +/delete-node/ &pil_cdsp0_mem; +/delete-node/ &pil_gpu_mem; +/delete-node/ &q6_cdsp1_dtb_mem; +/delete-node/ &pil_cdsp1_mem; +/delete-node/ &pil_cvp_mem; +/delete-node/ &pil_video_mem; +/delete-node/ &scmi_mem; +/delete-node/ &firmware_reserved_mem; + +/ { + clocks { + bi_tcxo_div2: bi-tcxo-div2-clk { + compatible =3D "fixed-factor-clock"; + clocks =3D <&xo_board_clk>; + clock-mult =3D <1>; + clock-div =3D <2>; + #clock-cells =3D <0>; + }; + + gpll0_board_clk: gpll0-board-clk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + }; + + sleep_clk: sleep-clk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + }; + + xo_board_clk: xo-board-clk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + }; + }; + + firmware: firmware { + scm { + memory-region =3D <&tz_ffi_mem>; + }; + + scmi0: scmi-0 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem0>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi0_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi0_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi0_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi1: scmi-1 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem1>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi1_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi1_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi1_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi2: scmi-2 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem2>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi2_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi2_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi2_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi3: scmi-3 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem3>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi3_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi3_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi3_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi4: scmi-4 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem4>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi4_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi4_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi4_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi5: scmi-5 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem5>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi5_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi5_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi5_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi6: scmi-6 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem6>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi6_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi6_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi6_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi7: scmi-7 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem7>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi7_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi7_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi7_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi8: scmi-8 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem8>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi8_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi8_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi8_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi9: scmi-9 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem9>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi9_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi9_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi9_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi10: scmi-10 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem10>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi10_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi10_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi10_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi11: scmi-11 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem11>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi11_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi11_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi11_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi12: scmi-12 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem12>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi12_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi12_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi12_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi13: scmi-13 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem13>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi13_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi13_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi13_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi14: scmi-14 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem14>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi14_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi14_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi14_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi15: scmi-15 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem15>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi15_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi15_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi15_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi16: scmi-16 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem16>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi16_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi16_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi16_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi17: scmi-17 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem17>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi17_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi17_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi17_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi18: scmi-18 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem18>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi18_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi18_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi18_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi19: scmi-19 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem19>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi19_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi19_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi19_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi20: scmi-20 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem20>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi20_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi20_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi20_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi21: scmi-21 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem21>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi21_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi21_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi21_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi22: scmi-22 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem22>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi22_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi22_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi22_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi23: scmi-23 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem23>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi23_sensor: protocol@15 { + reg =3D <0x15>; + #thermal-sensor-cells =3D <1>; + }; + }; + + scmi24: scmi-24 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem24>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi24_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi24_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi24_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi25: scmi-25 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem25>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi25_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi25_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi25_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi26: scmi-26 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem26>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi26_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi26_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi26_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi27: scmi-27 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem27>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi27_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi27_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi27_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi28: scmi-28 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem28>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi28_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi28_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi28_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi29: scmi-29 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem29>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi29_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi29_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi29_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi30: scmi-30 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem30>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi30_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi30_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi30_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi31: scmi-31 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem31>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi31_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi31_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi31_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi32: scmi-32 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem32>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi32_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi32_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi32_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi33: scmi-33 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem33>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi33_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi33_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi33_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi34: scmi-34 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem34>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi34_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi34_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi34_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi35: scmi-35 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem35>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi35_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi35_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi35_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi36: scmi-36 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem36>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi36_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi36_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi36_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi37: scmi-37 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem37>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi37_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi37_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi37_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi38: scmi-38 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem38>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi38_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi38_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi38_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi39: scmi-39 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem39>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi39_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi39_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi39_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi40: scmi-40 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem40>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi40_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi40_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi40_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi41: scmi-41 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem41>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi41_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi41_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi41_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi42: scmi-42 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem42>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi42_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi42_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi42_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi43: scmi-43 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem43>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi43_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi43_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi43_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi44: scmi-44 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem44>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi44_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi44_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi44_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi45: scmi-45 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem45>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi45_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi45_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi45_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi46: scmi-46 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem46>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi46_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi46_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi46_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi47: scmi-47 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem47>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi47_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi47_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi47_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi48: scmi-48 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem48>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi48_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi48_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi48_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi49: scmi-49 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem49>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi49_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi49_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi49_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi50: scmi-50 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem50>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi50_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi50_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi50_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi51: scmi-51 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem51>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi51_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi51_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi51_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi52: scmi-52 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem52>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi52_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi52_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi52_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi53: scmi-53 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem53>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi53_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi53_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi53_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi54: scmi-54 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem54>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi54_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi54_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi54_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi55: scmi-55 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem55>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi55_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi55_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi55_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi56: scmi-56 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem56>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi56_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi56_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi56_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi57: scmi-57 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem57>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi57_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi57_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi57_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi58: scmi-58 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem58>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi58_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi58_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi58_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi59: scmi-59 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem59>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi59_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi59_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi59_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi60: scmi-60 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem60>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi60_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi60_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi60_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi61: scmi-61 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem61>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi61_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi61_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi61_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi62: scmi-62 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem62>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi62_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi62_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi62_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi63: scmi-63 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem63>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi63_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi63_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi63_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + xbl_boot_mem: xbl-boot@90700000 { + reg =3D <0x0 0x90700000 0x0 0x100000>; + no-map; + }; + + tz_ffi_mem: tz-ffi@91c00000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x0 0x91c00000 0x0 0x1400000>; + no-map; + }; + + pil_adsp_mem: pil-adsp@95c00000 { + reg =3D <0x0 0x95c00000 0x0 0x1e00000>; + no-map; + }; + + pil_adsp_dtb_mem: q6-adsp-dtb@97a00000 { + reg =3D <0x0 0x97a00000 0x0 0x80000>; + no-map; + }; + + pil_gdsp0_dtb_mem: pil-gdsp0-dtb@97a80000 { + reg =3D <0x0 0x97a80000 0x0 0x80000>; + no-map; + }; + + pil_gdsp0_mem: pil-gdsp0@97b00000 { + reg =3D <0x0 0x97b00000 0x0 0x1e00000>; + no-map; + }; + + pil_gdsp1_mem: pil-gdsp1@99900000 { + reg =3D <0x0 0x99900000 0x0 0x1e00000>; + no-map; + }; + + pil_gdsp1_dtb_mem: pil-gdsp1-dtb@9b700000 { + reg =3D <0x0 0x9b700000 0x0 0x80000>; + no-map; + }; + + pil_cdsp0_dtb_mem: pil-cdsp0-dtb@9b780000 { + reg =3D <0x0 0x9b780000 0x0 0x80000>; + no-map; + }; + + pil_cdsp0_mem: pil-cdsp0@9b800000 { + reg =3D <0x0 0x9b800000 0x0 0x1e00000>; + no-map; + }; + + pil_gpu_mem: pil-gpu@9d600000 { + reg =3D <0x0 0x9d600000 0x0 0x2000>; + no-map; + }; + + pil_cdsp1_dtb_mem: pil-cdsp1-dtb@9d680000 { + reg =3D <0x0 0x9d680000 0x0 0x80000>; + no-map; + }; + + pil_cdsp1_mem: pil-cdsp1@9d700000 { + reg =3D <0x0 0x9d700000 0x0 0x1e00000>; + no-map; + }; + + pil_cvp_mem: pil-cvp@9f500000 { + reg =3D <0x0 0x9f500000 0x0 0x700000>; + no-map; + }; + + pil_video_mem: pil-video@9fc00000 { + reg =3D <0x0 0x9fc00000 0x0 0x700000>; + no-map; + }; + + audio_config_mem: audio-config-region@ac600000 { + reg =3D <0x0 0xac600000 0x0 0xa00000>; + no-map; + }; + + audio_mdf_mem: audio-mdf-region@ad000000 { + reg =3D <0x0 0xad000000 0x0 0x2000000>; + no-map; + }; + + firmware_mem: firmware-region@b0000000 { + reg =3D <0x0 0xb0000000 0x0 0x800000>; + no-map; + }; + + hyptz_reserved_mem: hyptz-reserved@beb00000 { + reg =3D <0x0 0xbeb00000 0x0 0x11500000>; + no-map; + }; + + shmem0: scmi-mem@d0000000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd0000000 0x0 0x1000>; + no-map; + }; + + shmem1: scmi-mem@d0001000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd0001000 0x0 0x1000>; + no-map; + }; + + shmem2: scmi-mem@d0002000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd0002000 0x0 0x1000>; + no-map; + }; + + shmem3: scmi-mem@d0003000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd0003000 0x0 0x1000>; + no-map; + }; + + shmem4: scmi-mem@d0004000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd0004000 0x0 0x1000>; + no-map; + }; + + shmem5: scmi-mem@d0005000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd0005000 0x0 0x1000>; + no-map; + }; + + shmem6: scmi-mem@d0006000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd0006000 0x0 0x1000>; + no-map; + }; + + shmem7: scmi-mem@d0007000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd0007000 0x0 0x1000>; + no-map; + }; + + shmem8: scmi-mem@d0008000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd0008000 0x0 0x1000>; + no-map; + }; + + shmem9: scmi-mem@d0009000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd0009000 0x0 0x1000>; + no-map; + }; + + shmem10: scmi-mem@d000a000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd000a000 0x0 0x1000>; + no-map; + }; + + shmem11: scmi-mem@d000b000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd000b000 0x0 0x1000>; + no-map; + }; + + shmem12: scmi-mem@d000c000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd000c000 0x0 0x1000>; + no-map; + }; + + shmem13: scmi-mem@d000d000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd000d000 0x0 0x1000>; + no-map; + }; + + shmem14: scmi-mem@d000e000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd000e000 0x0 0x1000>; + no-map; + }; + + shmem15: scmi-mem@d000f000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd000f000 0x0 0x1000>; + no-map; + }; + + shmem16: scmi-mem@d0010000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd0010000 0x0 0x1000>; + no-map; + }; + + shmem17: scmi-mem@d0011000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd0011000 0x0 0x1000>; + no-map; + }; + + shmem18: scmi-mem@d0012000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd0012000 0x0 0x1000>; + no-map; + }; + + shmem19: scmi-mem@d0013000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd0013000 0x0 0x1000>; + no-map; + }; + + shmem20: scmi-mem@d0014000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd0014000 0x0 0x1000>; + no-map; + }; + + shmem21: scmi-mem@d0015000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd0015000 0x0 0x1000>; + no-map; + }; + + shmem22: scmi-mem@d0016000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd0016000 0x0 0x1000>; + no-map; + }; + + shmem23: scmi-mem@d0017000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd0017000 0x0 0x1000>; + no-map; + }; + + shmem24: scmi-mem@d0018000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd0018000 0x0 0x1000>; + no-map; + }; + + shmem25: scmi-mem@d0019000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd0019000 0x0 0x1000>; + no-map; + }; + + shmem26: scmi-mem@d001a000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd001a000 0x0 0x1000>; + no-map; + }; + + shmem27: scmi-mem@d001b000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd001b000 0x0 0x1000>; + no-map; + }; + + shmem28: scmi-mem@d001c000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd001c000 0x0 0x1000>; + no-map; + }; + + shmem29: scmi-mem@d001d000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd001d000 0x0 0x1000>; + no-map; + }; + + shmem30: scmi-mem@d001e000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd001e000 0x0 0x1000>; + no-map; + }; + + shmem31: scmi-mem@d001f000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd001f000 0x0 0x1000>; + no-map; + }; + + shmem32: scmi-mem@d0020000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd0020000 0x0 0x1000>; + no-map; + }; + + shmem33: scmi-mem@d0021000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd0021000 0x0 0x1000>; + no-map; + }; + + shmem34: scmi-mem@d0022000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd0022000 0x0 0x1000>; + no-map; + }; + + shmem35: scmi-mem@d0023000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd0023000 0x0 0x1000>; + no-map; + }; + + shmem36: scmi-mem@d0024000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd0024000 0x0 0x1000>; + no-map; + }; + + shmem37: scmi-mem@d0025000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd0025000 0x0 0x1000>; + no-map; + }; + + shmem38: scmi-mem@d0026000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd0026000 0x0 0x1000>; + no-map; + }; + + shmem39: scmi-mem@d0027000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd0027000 0x0 0x1000>; + no-map; + }; + + shmem40: scmi-mem@d0028000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd0028000 0x0 0x1000>; + no-map; + }; + + shmem41: scmi-mem@d0029000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd0029000 0x0 0x1000>; + no-map; + }; + + shmem42: scmi-mem@d002a000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd002a000 0x0 0x1000>; + no-map; + }; + + shmem43: scmi-mem@d002b000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd002b000 0x0 0x1000>; + no-map; + }; + + shmem44: scmi-mem@d002c000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd002c000 0x0 0x1000>; + no-map; + }; + + shmem45: scmi-mem@d002d000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd002d000 0x0 0x1000>; + no-map; + }; + + shmem46: scmi-mem@d002e000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd002e000 0x0 0x1000>; + no-map; + }; + + shmem47: scmi-mem@d002f000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd002f000 0x0 0x1000>; + no-map; + }; + + shmem48: scmi-mem@d0030000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd0030000 0x0 0x1000>; + no-map; + }; + + shmem49: scmi-mem@d0031000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd0031000 0x0 0x1000>; + no-map; + }; + + shmem50: scmi-mem@d0032000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd0032000 0x0 0x1000>; + no-map; + }; + + shmem51: scmi-mem@d0033000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd0033000 0x0 0x1000>; + no-map; + }; + + shmem52: scmi-mem@d0034000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd0034000 0x0 0x1000>; + no-map; + }; + + shmem53: scmi-mem@d0035000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd0035000 0x0 0x1000>; + no-map; + }; + + shmem54: scmi-mem@d0036000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd0036000 0x0 0x1000>; + no-map; + }; + + shmem55: scmi-mem@d0037000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd0037000 0x0 0x1000>; + no-map; + }; + + shmem56: scmi-mem@d0038000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd0038000 0x0 0x1000>; + no-map; + }; + + shmem57: scmi-mem@d0039000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd0039000 0x0 0x1000>; + no-map; + }; + + shmem58: scmi-mem@d003a000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd003a000 0x0 0x1000>; + no-map; + }; + + shmem59: scmi-mem@d003b000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd003b000 0x0 0x1000>; + no-map; + }; + + shmem60: scmi-mem@d003c000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd003c000 0x0 0x1000>; + no-map; + }; + + shmem61: scmi-mem@d003d000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd003d000 0x0 0x1000>; + no-map; + }; + + shmem62: scmi-mem@d003e000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd003e000 0x0 0x1000>; + no-map; + }; + + shmem63: scmi-mem@d003f000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd003f000 0x0 0x1000>; + no-map; + }; + + firmware_logs_mem: firmware-logs@d0040000 { + reg =3D <0x0 0xd0040000 0x0 0x10000>; + no-map; + }; + + firmware_audio_mem: firmware-audio@d0050000 { + reg =3D <0x0 0xd0050000 0x0 0x4000>; + no-map; + }; + + firmware_camera_mem: firmware-camera@d0054000 { + no-map; + reg =3D <0x0 0xd0054000 0x0 0x2000>; + }; + + firmware_reserved_mem: firmware-reserved@d0056000 { + reg =3D <0x0 0xd0056000 0x0 0x9a000>; + no-map; + }; + + firmware_quantum_test_mem: firmware-quantum-test@d00f0000 { + reg =3D <0x0 0xd00f0000 0x0 0x10000>; + no-map; + }; + + tags_mem: tags@d0100000 { + reg =3D <0x0 0xd0100000 0x0 0x1200000>; + no-map; + }; + + qtee_mem: qtee@d1300000 { + reg =3D <0x0 0xd1300000 0x0 0x500000>; + no-map; + }; + + deepsleep_backup_mem: deepsleep-backup@d1800000 { + reg =3D <0x0 0xd1800000 0x0 0x100000>; + no-map; + }; + + trusted_apps_mem: trusted-apps@d1900000 { + reg =3D <0x0 0xd1900000 0x0 0x3800000>; + no-map; + }; + + tz_stat_mem: tz-stat@db100000 { + reg =3D <0x0 0xdb100000 0x0 0x100000>; + no-map; + }; + + cpucp_fw_mem: cpucp-fw@db200000 { + reg =3D <0x0 0xdb200000 0x0 0x100000>; + no-map; + }; + + cma: linux,cma { + compatible =3D "shared-dma-pool"; + alloc-ranges =3D <0x0 0x00000000 0x0 0xdfffffff>; + reusable; + alignment =3D <0x0 0x400000>; + size =3D <0x0 0x2000000>; + linux,cma-default; + }; + }; + + soc: soc@0 { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges =3D <0 0 0 0 0x10 0>; + + qupv3_id_2: geniqup@8c0000 { + compatible =3D "qcom,sa8255p-geni-se-qup"; + + i2c14: i2c@880000 { + compatible =3D "qcom,sa8255p-geni-i2c"; + }; + + spi14: spi@880000 { + compatible =3D "qcom,sa8255p-geni-spi"; + }; + + uart14: serial@880000 { + compatible =3D "qcom,sa8255p-geni-uart"; + }; + + i2c15: i2c@884000 { + compatible =3D "qcom,sa8255p-geni-i2c"; + }; + + spi15: spi@884000 { + compatible =3D "qcom,sa8255p-geni-spi"; + }; + + uart15: serial@884000 { + compatible =3D "qcom,sa8255p-geni-uart"; + }; + + i2c16: i2c@888000 { + compatible =3D "qcom,sa8255p-geni-i2c"; + }; + + spi16: spi@888000 { + compatible =3D "qcom,sa8255p-geni-spi"; + }; + + uart16: serial@888000 { + compatible =3D "qcom,sa8255p-geni-uart"; + }; + + i2c17: i2c@88c000 { + compatible =3D "qcom,sa8255p-geni-i2c"; + }; + + spi17: spi@88c000 { + compatible =3D "qcom,sa8255p-geni-spi"; + }; + + uart17: serial@88c000 { + compatible =3D "qcom,sa8255p-geni-uart"; + }; + + i2c18: i2c@890000 { + compatible =3D "qcom,sa8255p-geni-i2c"; + }; + + spi18: spi@890000 { + compatible =3D "qcom,sa8255p-geni-spi"; + }; + + uart18: serial@890000 { + compatible =3D "qcom,sa8255p-geni-uart"; + }; + + i2c19: i2c@894000 { + compatible =3D "qcom,sa8255p-geni-i2c"; + }; + + spi19: spi@894000 { + compatible =3D "qcom,sa8255p-geni-spi"; + }; + + uart19: serial@894000 { + compatible =3D "qcom,sa8255p-geni-uart"; + }; + + i2c20: i2c@898000 { + compatible =3D "qcom,sa8255p-geni-i2c"; + }; + + spi20: spi@898000 { + compatible =3D "qcom,sa8255p-geni-spi"; + }; + + uart20: serial@898000 { + compatible =3D "qcom,sa8255p-geni-uart"; + }; + }; + + qupv3_id_0: geniqup@9c0000 { + compatible =3D "qcom,sa8255p-geni-se-qup"; + + i2c0: i2c@980000 { + compatible =3D "qcom,sa8255p-geni-i2c"; + }; + + spi0: spi@980000 { + compatible =3D "qcom,sa8255p-geni-spi"; + }; + + uart0: serial@980000 { + compatible =3D "qcom,sa8255p-geni-uart"; + power-domains =3D <&scmi11_pd 0>, <&scmi11_dvfs 0>; + power-domain-names =3D "power", "perf"; + }; + + i2c1: i2c@984000 { + compatible =3D "qcom,sa8255p-geni-i2c"; + }; + + spi1: spi@984000 { + compatible =3D "qcom,sa8255p-geni-spi"; + }; + + uart1: serial@984000 { + compatible =3D "qcom,sa8255p-geni-uart"; + power-domains =3D <&scmi11_pd 1>, <&scmi11_dvfs 1>; + power-domain-names =3D "power", "perf"; + }; + + i2c2: i2c@988000 { + compatible =3D "qcom,sa8255p-geni-i2c"; + }; + + spi2: spi@988000 { + compatible =3D "qcom,sa8255p-geni-spi"; + }; + + uart2: serial@988000 { + compatible =3D "qcom,sa8255p-geni-uart"; + power-domains =3D <&scmi11_pd 2>, <&scmi11_dvfs 2>; + power-domain-names =3D "power", "perf"; + }; + + i2c3: i2c@98c000 { + compatible =3D "qcom,sa8255p-geni-i2c"; + }; + + spi3: spi@98c000 { + compatible =3D "qcom,sa8255p-geni-spi"; + }; + + uart3: serial@98c000 { + compatible =3D "qcom,sa8255p-geni-uart"; + power-domains =3D <&scmi11_pd 3>, <&scmi11_dvfs 3>; + power-domain-names =3D "power", "perf"; + }; + + i2c4: i2c@990000 { + compatible =3D "qcom,sa8255p-geni-i2c"; + }; + + spi4: spi@990000 { + compatible =3D "qcom,sa8255p-geni-spi"; + }; + + uart4: serial@990000 { + compatible =3D "qcom,sa8255p-geni-uart"; + power-domains =3D <&scmi11_pd 4>, <&scmi11_dvfs 4>; + power-domain-names =3D "power", "perf"; + }; + + i2c5: i2c@994000 { + compatible =3D "qcom,sa8255p-geni-i2c"; + }; + + spi5: spi@994000 { + compatible =3D "qcom,sa8255p-geni-spi"; + }; + + uart5: serial@994000 { + compatible =3D "qcom,sa8255p-geni-uart"; + power-domains =3D <&scmi11_pd 5>, <&scmi11_dvfs 5>; + power-domain-names =3D "power", "perf"; + }; + }; + + qupv3_id_1: geniqup@ac0000 { + compatible =3D "qcom,sa8255p-geni-se-qup"; + + i2c7: i2c@a80000 { + compatible =3D "qcom,sa8255p-geni-i2c"; + }; + + spi7: spi@a80000 { + compatible =3D "qcom,sa8255p-geni-spi"; + }; + + uart7: serial@a80000 { + compatible =3D "qcom,sa8255p-geni-uart"; + power-domains =3D <&scmi11_pd 7>, <&scmi11_dvfs 7>; + power-domain-names =3D "power", "perf"; + }; + + i2c8: i2c@a84000 { + compatible =3D "qcom,sa8255p-geni-i2c"; + }; + + spi8: spi@a84000 { + compatible =3D "qcom,sa8255p-geni-spi"; + }; + + uart8: serial@a84000 { + compatible =3D "qcom,sa8255p-geni-uart"; + power-domains =3D <&scmi11_pd 8>, <&scmi11_dvfs 8>; + power-domain-names =3D "power", "perf"; + }; + + i2c9: i2c@a88000 { + compatible =3D "qcom,sa8255p-geni-i2c"; + }; + + spi9: spi@a88000 { + compatible =3D "qcom,sa8255p-geni-spi"; + }; + + uart9: serial@a88000 { + compatible =3D "qcom,sa8255p-geni-uart"; + power-domains =3D <&scmi11_pd 9>, <&scmi11_dvfs 9>; + power-domain-names =3D "power", "perf"; + }; + + i2c10: i2c@a8c000 { + compatible =3D "qcom,sa8255p-geni-i2c"; + }; + + spi10: spi@a8c000 { + compatible =3D "qcom,sa8255p-geni-spi"; + }; + + uart10: serial@a8c000 { + compatible =3D "qcom,sa8255p-geni-debug-uart"; + power-domains =3D <&scmi11_pd 10>, <&scmi11_dvfs 10>; + power-domain-names =3D "power", "perf"; + }; + + i2c11: i2c@a90000 { + compatible =3D "qcom,sa8255p-geni-i2c"; + }; + + spi11: spi@a90000 { + compatible =3D "qcom,sa8255p-geni-spi"; + }; + + uart11: serial@a90000 { + compatible =3D "qcom,sa8255p-geni-uart"; + power-domains =3D <&scmi11_pd 11>, <&scmi11_dvfs 11>; + power-domain-names =3D "power", "perf"; + }; + + i2c12: i2c@a94000 { + compatible =3D "qcom,sa8255p-geni-i2c"; + }; + + spi12: spi@a94000 { + compatible =3D "qcom,sa8255p-geni-spi"; + }; + + uart12: serial@a94000 { + compatible =3D "qcom,sa8255p-geni-uart"; + power-domains =3D <&scmi11_pd 12>, <&scmi11_dvfs 12>; + power-domain-names =3D "power", "perf"; + }; + + i2c13: i2c@a98000 { + compatible =3D "qcom,sa8255p-geni-i2c"; + }; + }; + + qupv3_id_3: geniqup@bc0000 { + compatible =3D "qcom,sa8255p-geni-se-qup"; + + i2c21: i2c@b80000 { + compatible =3D "qcom,sa8255p-geni-i2c"; + }; + + spi21: spi@b80000 { + compatible =3D "qcom,sa8255p-geni-spi"; + }; + + uart21: serial@b80000 { + compatible =3D "qcom,sa8255p-geni-uart"; + power-domains =3D <&scmi11_pd 21>, <&scmi11_dvfs 21>; + power-domain-names =3D "power", "perf"; + }; + }; + + pcie0_ep: pcie-ep@1c00000 { + compatible =3D "qcom,sa8255p-pcie-ep"; + power-domains =3D <&scmi5_pd 1>; + /delete-property/ linux,pci-domain; + }; + + pcie1_ep: pcie-ep@1c10000 { + compatible =3D "qcom,sa8255p-pcie-ep"; + power-domains =3D <&scmi6_pd 1>; + /delete-property/ linux,pci-domain; + }; + + ufs_mem_hc: ufshc@1d84000 { + compatible =3D "qcom,sa8255p-ufshc"; + power-domains =3D <&scmi3_pd 0>; + }; + + adreno_smmu: iommu@3da0000 { + power-domains =3D <&scmi15_pd 0>; + }; + + cpufreq_hw: cpufreq@18591000 { + clocks =3D <&bi_tcxo_div2>, <&gpll0_board_clk>; + clock-names =3D "xo", "alternate"; + }; + }; +}; --=20 2.43.0 From nobody Mon Jun 15 09:40:21 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8DE853AE713 for ; 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[199.106.103.52]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2ca78df8942sm31265060eec.2.2026.04.09.02.12.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Apr 2026 02:12:11 -0700 (PDT) From: Shawn Guo To: Bjorn Andersson Cc: Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bartosz Golaszewski , Deepti Jaggi , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Nikunj Kela , Krzysztof Kozlowski , Shawn Guo Subject: [PATCH 7/8] dt-bindings: arm: qcom: add SA8255p Ride board Date: Thu, 9 Apr 2026 17:10:59 +0800 Message-ID: <20260409091100.474358-8-shengchao.guo@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260409091100.474358-1-shengchao.guo@oss.qualcomm.com> References: <20260409091100.474358-1-shengchao.guo@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: MB8r0kxZle4NxVOfVX2wsyb9YDgIFBBq X-Proofpoint-GUID: MB8r0kxZle4NxVOfVX2wsyb9YDgIFBBq X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDA5MDA4MSBTYWx0ZWRfXz1R4YnLYUYmJ cXQYXUz/XeGyoJQnaGMXLLNI1NScWwQhKBc9laWsXe1xedNRWI8z8BufWhKyYphSz9yfDYfZCUR Rz1QCzu7X2hNhryjBxN3MDY0z1rPVrieLkpQNtRF54+UyWgmJsvkLX/VGoDdjvF7aSRHPdXGyKo FbgmNh8j0NuiE3pbc7yCGucqwVpQpLo22RVxwWtVfMdz01KvTYjduSgQMOrQm8U0oS7zd+qbKcE RHgygSt8YTUioPse9ChfN5VDkLgTmECmnRr/D7ud+KeWOi/wO1g8KXqyfTh4SRC/3Gsere9eTX0 dlf1LfGL2x9dtNkBEi29zIX0Oa/AqVLsJflbwthnDbhFoK1Q2QgMPDIP45r/ITlNBt2wmPwXvd+ IUPo4xdvO9YzHObj5UdgIiT+ea4XvD/zXYALnU7zzI1E5fz8qQZJaT/LOtZcoke4StRkga21KSL aVdkYmizmytomg9UMUg== X-Authority-Analysis: v=2.4 cv=TZemcxQh c=1 sm=1 tr=0 ts=69d76d6c cx=c_pps a=Uww141gWH0fZj/3QKPojxA==:117 a=b9+bayejhc3NMeqCNyeLQQ==:17 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=COk6AnOGAAAA:8 a=KKAkSRfTAAAA:8 a=EUspDBNiAAAA:8 a=uytbUiI1na4GE1GmpowA:9 a=PxkB5W3o20Ba91AHUih5:22 a=TjNXssC_j7lpFel5tvFf:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-09_02,2026-04-09_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 lowpriorityscore=0 priorityscore=1501 suspectscore=0 malwarescore=0 phishscore=0 bulkscore=0 spamscore=0 impostorscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604010000 definitions=main-2604090081 Content-Type: text/plain; charset="utf-8" From: Nikunj Kela Document the SA8255p SoC and its reference board: sa8255p-ride. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Nikunj Kela Signed-off-by: Deepti Jaggi Reviewed-by: Bartosz Golaszewski Signed-off-by: Shawn Guo Tested-by: Deepti Jaggi # sa8255p-ride board --- Documentation/devicetree/bindings/arm/qcom.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentatio= n/devicetree/bindings/arm/qcom.yaml index 9f9930fb9a5e..9cb4a8623060 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -927,6 +927,11 @@ properties: - qcom,sa8155p-adp - const: qcom,sa8155p =20 + - items: + - enum: + - qcom,sa8255p-ride + - const: qcom,sa8255p + - items: - enum: - qcom,sa8295p-adp --=20 2.43.0 From nobody Mon Jun 15 09:40:21 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 875993AF664 for ; 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[199.106.103.52]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2ca78df8942sm31265060eec.2.2026.04.09.02.12.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Apr 2026 02:12:15 -0700 (PDT) From: Shawn Guo To: Bjorn Andersson Cc: Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bartosz Golaszewski , Deepti Jaggi , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Nikunj Kela , Shazad Hussain , Shawn Guo Subject: [PATCH 8/8] arm64: dts: qcom: sa8255p: Enable sa8255p-ride board support Date: Thu, 9 Apr 2026 17:11:00 +0800 Message-ID: <20260409091100.474358-9-shengchao.guo@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260409091100.474358-1-shengchao.guo@oss.qualcomm.com> References: <20260409091100.474358-1-shengchao.guo@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDA5MDA4MSBTYWx0ZWRfX8ZaxuJl8y2DD THK2MwO084RQqX7LHhdo5obdYQAquHOHXcstVcSEdRmOlwTAX2pbO5XyDewpchK7TnNjEw6MHGD +AV7rifrKlNrtgudndz5XG1fAUG8pEhL4Ac68hJkInXPgxVFDT2UfhyW6hiJfoWLDtl+xOo3U+Y ITWuLRwJpTIheQNBREZL+tNRFFE4OLimhJtMnjS46ctpsL5K6UtbCkAYrsgMf/WbR6gUOuDitO6 UKIxdQjvng+97cKBzuhnPUxT1DRP2jl+m5lHhkCfZUFjeT77oYkSXi4X+9mZh3IS9Wi+JA7/SEt cMPehHvonVlzJgcbhxUXNjwghldOUIi58ZtdZh+jGGt0ma36jBCkJ8wKZWfR0nE/qlZLf65qYLt f+MOfAgH6WSWxI5kIvkx0TqI1lJGTyCAJ4PIp6l0MKfAEtRt8AeQyqvyAVq/eg5QvK7nt8yHF6D u8U+tH2kdSAO73eN6WA== X-Authority-Analysis: v=2.4 cv=eKIjSnp1 c=1 sm=1 tr=0 ts=69d76d71 cx=c_pps a=Uww141gWH0fZj/3QKPojxA==:117 a=b9+bayejhc3NMeqCNyeLQQ==:17 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=MNDMu2h6GyehcEZcpm4A:9 a=PxkB5W3o20Ba91AHUih5:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: J4VuyOjkLjJC53dGWI4xowc6jGhVezWH X-Proofpoint-ORIG-GUID: J4VuyOjkLjJC53dGWI4xowc6jGhVezWH X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-09_02,2026-04-09_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 impostorscore=0 phishscore=0 priorityscore=1501 lowpriorityscore=0 clxscore=1015 spamscore=0 suspectscore=0 malwarescore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604010000 definitions=main-2604090081 Content-Type: text/plain; charset="utf-8" From: Nikunj Kela Add initial device tree support for the SA8255P Ride board. Enable UFS storage, UART10 as the serial console, PCIe EP interfaces, thermal zones for PMM8654AU sensors, and SCMI protocol nodes. Co-developed-by: Shazad Hussain Signed-off-by: Shazad Hussain Signed-off-by: Nikunj Kela Co-developed-by: Deepti Jaggi Signed-off-by: Deepti Jaggi Reviewed-by: Bartosz Golaszewski Signed-off-by: Shawn Guo Tested-by: Deepti Jaggi # sa8255p-ride board --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/sa8255p-ride.dts | 222 ++++++++++++++++++++++ 2 files changed, 223 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sa8255p-ride.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index d69e5f3132c4..722532f4e82f 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -201,6 +201,7 @@ qrb5165-rb5-vision-mezzanine-dtbs :=3D qrb5165-rb5.dtb = qrb5165-rb5-vision-mezzanin dtb-$(CONFIG_ARCH_QCOM) +=3D qrb5165-rb5-vision-mezzanine.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D qru1000-idp.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sa8155p-adp.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D sa8255p-ride.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sa8295p-adp.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sa8540p-ride.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sa8775p-ride.dtb diff --git a/arch/arm64/boot/dts/qcom/sa8255p-ride.dts b/arch/arm64/boot/dt= s/qcom/sa8255p-ride.dts new file mode 100644 index 000000000000..9b83ccf32664 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sa8255p-ride.dts @@ -0,0 +1,222 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; + +#include + +#include "lemans-sa8255p.dtsi" + +/ { + model =3D "Qualcomm Technologies, Inc. SA8255P Ride"; + compatible =3D "qcom,sa8255p-ride", "qcom,sa8255p"; + + aliases { + serial0 =3D &uart10; + serial1 =3D &uart4; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + thermal-zones { + pmm8654au_0_thermal: pm8255-0-thermal { + polling-delay-passive =3D <100>; + thermal-sensors =3D <&scmi23_sensor 0>; + + trips { + trip0 { + temperature =3D <105000>; + hysteresis =3D <0>; + type =3D "passive"; + }; + + trip1 { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + pmm8654au_1_thermal: pm8255-1-thermal { + polling-delay-passive =3D <100>; + thermal-sensors =3D <&scmi23_sensor 1>; + + trips { + trip0 { + temperature =3D <105000>; + hysteresis =3D <0>; + type =3D "passive"; + }; + + trip1 { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + pmm8654au_2_thermal: pm8255-2-thermal { + polling-delay-passive =3D <100>; + thermal-sensors =3D <&scmi23_sensor 2>; + + trips { + trip0 { + temperature =3D <105000>; + hysteresis =3D <0>; + type =3D "passive"; + }; + + trip1 { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + pmm8654au_3_thermal: pm8255-3-thermal { + polling-delay-passive =3D <100>; + thermal-sensors =3D <&scmi23_sensor 3>; + + trips { + trip0 { + temperature =3D <105000>; + hysteresis =3D <0>; + type =3D "passive"; + }; + + trip1 { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + }; +}; + +&gpll0_board_clk { + clock-frequency =3D <300000000>; +}; + +&pcie0_ep { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie0_ep_clkreq_default &pcie0_ep_perst_default + &pcie0_ep_wake_default>; + reset-gpios =3D <&tlmm 2 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&tlmm 0 GPIO_ACTIVE_HIGH>; +}; + +&pcie1_ep { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie1_ep_clkreq_default &pcie1_ep_perst_default + &pcie1_ep_wake_default>; + reset-gpios =3D <&tlmm 4 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&tlmm 5 GPIO_ACTIVE_HIGH>; +}; + +&qupv3_id_0 { + status =3D "okay"; +}; + +&qupv3_id_1 { + status =3D "okay"; +}; + +&scmi3 { + status =3D "okay"; +}; + +&scmi4 { + status =3D "okay"; +}; + +&scmi5 { + status =3D "okay"; +}; + +&scmi6 { + status =3D "okay"; +}; + +&scmi11 { + status =3D "okay"; +}; + +&scmi15 { + status =3D "okay"; +}; + +&scmi23 { + status =3D "okay"; +}; + +&sleep_clk { + clock-frequency =3D <32000>; +}; + +&uart4 { + status =3D "okay"; +}; + +&uart10 { + status =3D "okay"; +}; + +&tlmm { + pcie0_ep_clkreq_default: pcie0-ep-clkreq-default-state { + pins =3D "gpio1"; + function =3D "pcie0_clkreq"; + drive-strength =3D <2>; + bias-disable; + }; + + pcie0_ep_perst_default: pcie0-ep-perst-default-state { + pins =3D "gpio2"; + function =3D "gpio"; + drive-strength =3D <16>; + bias-pull-down; + }; + + pcie0_ep_wake_default: pcie0-ep-wake-default-state { + pins =3D "gpio0"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + pcie1_ep_clkreq_default: pcie1-ep-clkreq-default-state { + pins =3D "gpio3"; + function =3D "pcie1_clkreq"; + drive-strength =3D <2>; + bias-disable; + }; + + pcie1_ep_perst_default: pcie1-ep-perst-default-state { + pins =3D "gpio4"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + }; + + pcie1_ep_wake_default: pcie1-ep-wake-default-state { + pins =3D "gpio5"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; +}; + +&ufs_mem_hc { + status =3D "okay"; +}; + +&xo_board_clk { + clock-frequency =3D <38400000>; +}; --=20 2.43.0