From nobody Thu Apr 9 16:29:27 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 723163C3422 for ; Thu, 9 Apr 2026 11:44:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775735089; cv=none; b=GOW1RQxCKaxJGksKEE8jlspLkhUZsow6JSEBVZcadSqNChJ77lNL3kjhyhJxEbaaWVjaY1o8DE23nfHivELED3JG6p27PnKSyf8M1a3KW7EIxXo5mNdJ/gB9zlQu4XiRKCKCsRcRxkUhrwhpmf7Ktt9ejCLeDqmeb/ULtbiM4wc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775735089; c=relaxed/simple; bh=3XHgcSRng10PQalp+4T3zNZuirhzNRsRGe4tsfJoq24=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=f2X8LFUSWuf3X6mQyTm4JbAjPCIeAmuGOJPZzi/9tDcFgtRo2WXQt6fkdtbxqlkbnP5o4ms5vXKLf2g2g/im8ISei7zIHJdiWemw/SbDWPigQJq+y4vVhY25RPAZhKmawIYXIPTf0Dz/Csg4amyYmC/+OW1TVuD/0iVAyjTyyFM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=VmxJQleO; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=Jliwo2YM; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="VmxJQleO"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="Jliwo2YM" Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 6397MoZc4046994 for ; Thu, 9 Apr 2026 11:44:47 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= rKSy/85A70XkSZk9VI18GBLszleodgD9VRhwuaEGsDI=; b=VmxJQleOwdaNBDy6 F/C2vuXJCaX5IexCHIXWTrueJxYC/1wmnTXbodWW/fCrpdzQeSxJFfPuWfdPZmxj Q0k5E67UVCBRLBCFta+luY03MF+EBBglvVVGQvzk9+GNVSysLPLRZF1w3QdrZmha 0R+nArISSqFr9wjHXsA1fE4/xjmfYOnugZdZip4IRLsfzrPvC290Jk+70U37oKB4 /V8MG0ZSgcoBfRjuRbKgeCPvGNlmnk/b/+g1zB066jFxjSa4mrTWXD5dhi+Jit8D vHRxbIStrmsXkiSnE6XCsVLtTdbvrGnxRxdzv2btDI3GLupPH3Ik652hJe8uo6bE r19d/g== Received: from mail-pl1-f200.google.com (mail-pl1-f200.google.com [209.85.214.200]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4ddtd73tuv-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Thu, 09 Apr 2026 11:44:47 +0000 (GMT) Received: by mail-pl1-f200.google.com with SMTP id d9443c01a7336-2b2454fc131so15451685ad.3 for ; Thu, 09 Apr 2026 04:44:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1775735086; x=1776339886; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=rKSy/85A70XkSZk9VI18GBLszleodgD9VRhwuaEGsDI=; b=Jliwo2YMQSa8M26b7QcsBU7zsq2mQcAPoDXdryeaUbiJDPIl4Tf3wzPYTLOkhVQLPh 3eB7Qzm1TrfFbLYQLEdtG0TBV7qTG/64bJvnR0celoNgIqFVQ9RFXc6+6QbOgzfxa4MG 1FeUrSqu2CJpHl0uNMZ2jkaE394jacWjT4hP6isjVzHpvpmxW2LuXfV5O3NMv/uYER2X u3D7gzISCRDAfnyqm+XVoQUBlXQMnXNTs7d0ltF6+Cxn5UhxCOGokTJ8d4DZp4Z1HV4Y Ut+6lA2ECJAD5DtNmzeqo8P2U81/h53S9NgD26Je+RiFLtF3LL9F+RYQjFvgR7GFOjYn ijcg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1775735086; x=1776339886; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=rKSy/85A70XkSZk9VI18GBLszleodgD9VRhwuaEGsDI=; b=PFvX6KwI+SHMHYRq81j28Qtw3xiCVACGoeZriUnbgom9c4O8OHEdy3CCogHFik4b3D JMzQEdE2ezIKTYw13eUZck2hsXHQBDEN4xl+SxF3wzxpknCgNxaKD/2EB9oytIdSs+yQ 5ibtMRfkqDWS8yg99tlEm3tkOlzVtdOMLIbD9hjB9e2h6t+hd0Fjaay/C0Vdjly0sZYr jaRt2ak7LSMD03uSApYBB2OcpBtHIDnJwh0Bl2v6X9dCeinBlzOnPj080bx8KQ6XmiaH a9JjXhI0oEu5UXToxteM4aIiqykpISYkD/SXc6pdEW4HNliIezMzZjAqcYsVqa4OJ696 Ro2Q== X-Forwarded-Encrypted: i=1; AJvYcCXa0cqm5xWL8ZqGiNpEO5YR2vPF0pUDaDTaRiZMGA7/+CUTIThJ9xU2cF73PrpPi51kIYv2+Qe7ntgp1xk=@vger.kernel.org X-Gm-Message-State: AOJu0YyuVYruyNVr5SCdh8w0rJTq+/07oluAkCUNO3pSW1IQA6kSYL10 SRNS5oep9SV3n8U1tNdLefgWKTowyTp0ebx0W5kTE+0eYpAo2U7uzQ8RNG8rTVoUshOqL4jJdEx kEmab+TnjpAbvhRxAft4fywKcDyK2CG9romqCSk9u++DICFzYLRlXwUF9BbjQqqbvSnQ= X-Gm-Gg: AeBDietFoF2lmjpKGLjOapoEUv4CpszX/G3Gsx1BmjGLnQmGyv7GIEL1RLvt0y7nPBq NQD4pE8wzgGq+fMCf15NU9GsCzoQ/xJGeR7lpna4jckob9NLF07/XFH0qZm/UKmGhrrVZf/Kwqh S886dEWMLdYSyB48Yq86HBKQIdUYJkY84xV35+qoUdEbmQmWPav0daCKlxh698U7uPAGZpV0pSh xn2eU4M9YvXJodwD++44O60E5O4lWk54pL2EC0Mg9RQUq0Hil0TvMwG0C6088SuN7uBehOFdbUg ZvKhgzzPRm8K8gXlBapg0EyYMt+6SU7m4C7oUb+KCAAAkCtWhUoJC6kltkp7jRIAxg29CerePia n+SizMLjkq6O7CZnWV8xcNslEZZZSd0jaujO2T8WWIjT9+Cfd/eheGerOAM4= X-Received: by 2002:a17:903:3586:b0:2b2:6b58:9317 with SMTP id d9443c01a7336-2b28194ec0fmr255741325ad.39.1775735086294; Thu, 09 Apr 2026 04:44:46 -0700 (PDT) X-Received: by 2002:a17:903:3586:b0:2b2:6b58:9317 with SMTP id d9443c01a7336-2b28194ec0fmr255740925ad.39.1775735085788; Thu, 09 Apr 2026 04:44:45 -0700 (PDT) Received: from hu-arakshit-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2b2749cbd9fsm230957355ad.75.2026.04.09.04.44.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Apr 2026 04:44:45 -0700 (PDT) From: Abhinaba Rakshit Date: Thu, 09 Apr 2026 17:14:08 +0530 Subject: [PATCH v8 1/5] soc: qcom: ice: Add OPP-based clock scaling support for ICE Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260409-enable-ice-clock-scaling-v8-1-ca1129798606@oss.qualcomm.com> References: <20260409-enable-ice-clock-scaling-v8-0-ca1129798606@oss.qualcomm.com> In-Reply-To: <20260409-enable-ice-clock-scaling-v8-0-ca1129798606@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Manivannan Sadhasivam , "James E.J. Bottomley" , "Martin K. Petersen" , Adrian Hunter , Ulf Hansson , Neeraj Soni , Harshal Dev , Kuldeep Singh , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, Abhinaba Rakshit X-Mailer: b4 0.14.2 X-Authority-Analysis: v=2.4 cv=QoRuG1yd c=1 sm=1 tr=0 ts=69d7912f cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=EUspDBNiAAAA:8 a=zlodBCVASgOsPZHI1q0A:9 a=QEXdDO2ut3YA:10 a=uG9DUKGECoFWVXl0Dc02:22 X-Proofpoint-ORIG-GUID: cFUHwvtF612cbQKd__xfDDw-78JvuqcR X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDA5MDEwNSBTYWx0ZWRfXz3QtN5QQVMi7 9a5JFYWUjvvOJsEY3i9l3E4kSAa9hTh+ZOnpusBD4Ur0PFljJynUrmVIZVzwlf8/uEenn+r2+y2 njF1Hji1i8wBWHsiFVZb/aZchObE9Z5D7CUpZ0u/L0kesjPtOrrqHpT+vQSpxcs7ACEork0jh9E nS5rNmCDgL6XAq07asmfuaZ9fqRgb2KI7Jvsw/zB/GZKK9cOio2DXo96x0Tr31iUqgVMh7tjVzO xbCmF5ITHbdzrGLGtIWRkHDjvkuIFtPBjLAJl9L+uSHiKfV9S5juKJehSRQa3TfrLDERt995zP9 wPZk+yxqtUHFRVN3IK3PuOG+S6JWSEOo+Kggqqc9XvG6K3aR22Iforu+6YLX5BCEiOtAEsJeU6C 1nDrt9QZM5SxjnwIno5zDRi9kCHuWNVRnV5U3zjPWbU+KfYf2uUpxYF2LzpVZqzp2S/j7VGtJ1T 19huEnmvbJfZUZOcFAg== X-Proofpoint-GUID: cFUHwvtF612cbQKd__xfDDw-78JvuqcR X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-09_03,2026-04-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 bulkscore=0 impostorscore=0 lowpriorityscore=0 suspectscore=0 priorityscore=1501 adultscore=0 malwarescore=0 phishscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604010000 definitions=main-2604090105 Register optional operation-points-v2 table for ICE device during device probe. Attach the OPP-table with only the ICE core clock. Since, dtbinding is on a trasition phase to include iface clock and clock-names, attaching the opp-table to core clock remains options such that it does not cause probe failures. Introduce clock scaling API qcom_ice_scale_clk which scale ICE core clock based on the target frequency provided and if a valid OPP-table is registered. Use round_ceil passed to decide on the rounding of the clock freq against OPP-table. Clock scaling is disabled when a valid OPP-table is not registered. This ensures when an ICE-device specific OPP table is available, use the PM OPP framework to manage frequency scaling and maintain proper power-domain constraints. Also, ensure to drop the votes in suspend to prevent power/thermal retention. Subsequently restore the frequency in resume from core_clk_freq which stores the last ICE core clock operating frequency. Signed-off-by: Abhinaba Rakshit --- drivers/soc/qcom/ice.c | 92 ++++++++++++++++++++++++++++++++++++++++++++++= ++++ include/soc/qcom/ice.h | 2 ++ 2 files changed, 94 insertions(+) diff --git a/drivers/soc/qcom/ice.c b/drivers/soc/qcom/ice.c index bf4ab2d9e5c0360d8fe6135cc35f93b6b09e7a0e..9e869e6abc6300c7608b4d9a18e= 7f3e80c93f5e7 100644 --- a/drivers/soc/qcom/ice.c +++ b/drivers/soc/qcom/ice.c @@ -16,6 +16,7 @@ #include #include #include +#include =20 #include =20 @@ -112,6 +113,8 @@ struct qcom_ice { bool use_hwkm; bool hwkm_init_complete; u8 hwkm_version; + unsigned long core_clk_freq; + bool has_opp; }; =20 static bool qcom_ice_check_supported(struct qcom_ice *ice) @@ -311,6 +314,10 @@ int qcom_ice_resume(struct qcom_ice *ice) struct device *dev =3D ice->dev; int err; =20 + /* Restore the ICE core clk freq */ + if (ice->has_opp && ice->core_clk_freq) + dev_pm_opp_set_rate(ice->dev, ice->core_clk_freq); + err =3D clk_prepare_enable(ice->core_clk); if (err) { dev_err(dev, "Failed to enable core clock: %d\n", err); @@ -331,6 +338,11 @@ int qcom_ice_suspend(struct qcom_ice *ice) { clk_disable_unprepare(ice->iface_clk); clk_disable_unprepare(ice->core_clk); + + /* Drop the clock votes while suspend */ + if (ice->has_opp) + dev_pm_opp_set_rate(ice->dev, 0); + ice->hwkm_init_complete =3D false; =20 return 0; @@ -556,6 +568,51 @@ int qcom_ice_import_key(struct qcom_ice *ice, } EXPORT_SYMBOL_GPL(qcom_ice_import_key); =20 +/** + * qcom_ice_scale_clk() - Scale ICE clock for DVFS-aware operations + * @ice: ICE driver data + * @target_freq: requested frequency in Hz + * @round_ceil: when true, selects nearest freq >=3D @target_freq; + * otherwise, selects nearest freq <=3D @target_freq + * + * Selects an OPP frequency based on @target_freq and the rounding directi= on + * specified by @round_ceil, then programs it using dev_pm_opp_set_rate(), + * including any voltage or power-domain transitions handled by the OPP + * framework. Updates ice->core_clk_freq on success. + * + * Return: 0 on success; -EOPNOTSUPP if no OPP table; or error from + * dev_pm_opp_set_rate()/OPP lookup. + */ +int qcom_ice_scale_clk(struct qcom_ice *ice, unsigned long target_freq, + bool round_ceil) +{ + unsigned long ice_freq =3D target_freq; + struct dev_pm_opp *opp; + int ret; + + if (!ice->has_opp) + return -EOPNOTSUPP; + + if (round_ceil) + opp =3D dev_pm_opp_find_freq_ceil(ice->dev, &ice_freq); + else + opp =3D dev_pm_opp_find_freq_floor(ice->dev, &ice_freq); + + if (IS_ERR(opp)) + return PTR_ERR(opp); + dev_pm_opp_put(opp); + + ret =3D dev_pm_opp_set_rate(ice->dev, ice_freq); + if (ret) { + dev_err(ice->dev, "Unable to scale ICE clock rate\n"); + return ret; + } + ice->core_clk_freq =3D ice_freq; + + return ret; +} +EXPORT_SYMBOL_GPL(qcom_ice_scale_clk); + static struct qcom_ice *qcom_ice_create(struct device *dev, void __iomem *base) { @@ -731,6 +788,7 @@ static int qcom_ice_probe(struct platform_device *pdev) { struct qcom_ice *engine; void __iomem *base; + int err; =20 base =3D devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(base)) { @@ -742,6 +800,40 @@ static int qcom_ice_probe(struct platform_device *pdev) if (IS_ERR(engine)) return PTR_ERR(engine); =20 + /* qcom_ice_create() may return NULL if scm calls are not available */ + if (!engine) + return -EOPNOTSUPP; + + err =3D devm_pm_opp_set_clkname(&pdev->dev, "core"); + if (err && err !=3D -ENOENT) { + dev_err(&pdev->dev, "Unable to set core clkname to OPP-table\n"); + return err; + } + + /* OPP table is optional */ + err =3D devm_pm_opp_of_add_table(&pdev->dev); + if (err && err !=3D -ENODEV) { + dev_err(&pdev->dev, "Invalid OPP table in Device tree\n"); + return err; + } + + /* + * The OPP table is optional. devm_pm_opp_of_add_table() returns + * -ENODEV when no OPP table is present in DT, which is not treated + * as an error. Therefore, track successful OPP registration only + * when the return value is 0. + */ + engine->has_opp =3D (err =3D=3D 0); + if (!engine->has_opp) + dev_info(&pdev->dev, "ICE OPP table is not registered, please update you= r DT\n"); + + /* + * Store the core clock rate for suspend resume cycles, + * against OPP aware DVFS operations. core_clk_freq will + * have a valid value only for non-legacy bindings. + */ + engine->core_clk_freq =3D clk_get_rate(engine->core_clk); + platform_set_drvdata(pdev, engine); =20 return 0; diff --git a/include/soc/qcom/ice.h b/include/soc/qcom/ice.h index 4bee553f0a59d86ec6ce20f7c7b4bce28a706415..4eb58a264d416e71228ed4b13e7= f53c549261fdc 100644 --- a/include/soc/qcom/ice.h +++ b/include/soc/qcom/ice.h @@ -30,5 +30,7 @@ int qcom_ice_import_key(struct qcom_ice *ice, const u8 *raw_key, size_t raw_key_size, u8 lt_key[BLK_CRYPTO_MAX_HW_WRAPPED_KEY_SIZE]); struct qcom_ice *devm_of_qcom_ice_get(struct device *dev); +int qcom_ice_scale_clk(struct qcom_ice *ice, unsigned long target_freq, + bool round_ceil); =20 #endif /* __QCOM_ICE_H__ */ --=20 2.34.1