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Thu, 09 Apr 2026 11:11:07 -0700 (PDT) Received: from hu-tdas-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-c7921a2d9ebsm66132a12.30.2026.04.09.11.11.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Apr 2026 11:11:07 -0700 (PDT) From: Taniya Das Date: Thu, 09 Apr 2026 23:40:42 +0530 Subject: [PATCH v2 1/8] dt-bindings: clock: qcom: Add video clock controller on Eliza SoC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260409-eliza_mm_cc_v2-v2-1-bc0c6dd77bc5@oss.qualcomm.com> References: <20260409-eliza_mm_cc_v2-v2-0-bc0c6dd77bc5@oss.qualcomm.com> In-Reply-To: <20260409-eliza_mm_cc_v2-v2-0-bc0c6dd77bc5@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Maxime Coquelin , Alexandre Torgue Cc: Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, Taniya Das X-Mailer: b4 0.15-dev-aa3f6 X-Proofpoint-ORIG-GUID: 5sO9I0NhG6pT0MliTig9ySzoMYyyVXa9 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDA5MDE2NyBTYWx0ZWRfX54yiOsS/yj60 W/T7El69epqGK7CaLmbfhGVkleKYP5ZH1WFC7XDeCNmmUQ+8kwIZXXfyV1Cez9i8m8qNbqWEvJH +YYxZNKJmX0V0wAJsybYvJ0aZvVSWc5wRFy8iQ+3nSev0vI8nVi1+pkNNdmehH4KIgrRvyPxiEH oA+NSeE3s22+hGaQKcj3veAtkpJXtcdWaxc4HOT7JRW0L2NM9GQcXgnwf4aNNOZ5+6jwiIyLXhn 5GMqJgaK8k6kKQPlQ0tcdwgViNnb6A/8zBphv7Oc8LFcIG45JwaWxDZaM+INoLAmUyk3HShE8Ct dOuoxLTWI7F21UFzekqvtxvPkC5M6AlWN+nT9CSO6cByVpyNWE2H0k6Zslm8+seBitc4Z9Li2Bc ukcfmifZFBEPhLPKhIAfrQih4wfB+qoX47wSZMa7JfjAj/1w0zbtrp11eWKod3cfONjnQIDQprK MW9gM4LO/x2/GMzDV+A== X-Authority-Analysis: v=2.4 cv=OMcXGyaB c=1 sm=1 tr=0 ts=69d7ebbd cx=c_pps a=oF/VQ+ItUULfLr/lQ2/icg==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=gEfo2CItAAAA:8 a=EUspDBNiAAAA:8 a=O5AFsRJ8ltlpu4YWMHwA:9 a=QEXdDO2ut3YA:10 a=3WC7DwWrALyhR5TkjVHa:22 a=sptkURWiP4Gy88Gu7hUp:22 X-Proofpoint-GUID: 5sO9I0NhG6pT0MliTig9ySzoMYyyVXa9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-09_04,2026-04-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 phishscore=0 clxscore=1015 impostorscore=0 spamscore=0 priorityscore=1501 lowpriorityscore=0 suspectscore=0 malwarescore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604010000 definitions=main-2604090167 Add compatible string for Eliza video clock controller and the bindings for Eliza Qualcomm SoC. Signed-off-by: Taniya Das --- .../bindings/clock/qcom,eliza-videocc.yaml | 51 ++++++++++++++++++= ++++ include/dt-bindings/clock/qcom,eliza-videocc.h | 37 ++++++++++++++++ 2 files changed, 88 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,eliza-videocc.yam= l b/Documentation/devicetree/bindings/clock/qcom,eliza-videocc.yaml new file mode 100644 index 0000000000000000000000000000000000000000..26a0c85f26b13ca8e7a4f5f418e= 8c98235f10558 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,eliza-videocc.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,eliza-videocc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Video Clock & Reset Controller on Eliza + +maintainers: + - Taniya Das + +description: | + Qualcomm video clock control module provides the clocks, resets and power + domains on Eliza. + + See also: include/dt-bindings/clock/qcom,eliza-videocc.h + +properties: + compatible: + const: qcom,eliza-videocc + + clocks: + items: + - description: Board XO source + - description: Sleep clock source + - description: Video AHB clock from GCC + +required: + - compatible + - clocks + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + clock-controller@aaf0000 { + compatible =3D "qcom,eliza-videocc"; + reg =3D <0x0aaf0000 0x10000>; + clocks =3D <&bi_tcxo_div2>, + <&sleep_clk>, + <&gcc GCC_VIDEO_AHB_CLK>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + +... diff --git a/include/dt-bindings/clock/qcom,eliza-videocc.h b/include/dt-bi= ndings/clock/qcom,eliza-videocc.h new file mode 100644 index 0000000000000000000000000000000000000000..1e922250a7fae77f5c996208d50= ff372b252aa51 --- /dev/null +++ b/include/dt-bindings/clock/qcom,eliza-videocc.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_ELIZA_H +#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_ELIZA_H + +/* VIDEO_CC clocks */ +#define VIDEO_CC_AHB_CLK 0 +#define VIDEO_CC_AHB_CLK_SRC 1 +#define VIDEO_CC_MVS0_CLK 2 +#define VIDEO_CC_MVS0_CLK_SRC 3 +#define VIDEO_CC_MVS0_DIV_CLK_SRC 4 +#define VIDEO_CC_MVS0_SHIFT_CLK 5 +#define VIDEO_CC_MVS0C_CLK 6 +#define VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC 7 +#define VIDEO_CC_MVS0C_SHIFT_CLK 8 +#define VIDEO_CC_PLL0 9 +#define VIDEO_CC_SLEEP_CLK 10 +#define VIDEO_CC_SLEEP_CLK_SRC 11 +#define VIDEO_CC_XO_CLK 12 +#define VIDEO_CC_XO_CLK_SRC 13 + +/* VIDEO_CC power domains */ +#define VIDEO_CC_MVS0_GDSC 0 +#define VIDEO_CC_MVS0C_GDSC 1 + +/* VIDEO_CC resets */ +#define VIDEO_CC_INTERFACE_BCR 0 +#define VIDEO_CC_MVS0_CLK_ARES 1 +#define VIDEO_CC_MVS0_BCR 2 +#define VIDEO_CC_MVS0C_CLK_ARES 3 +#define VIDEO_CC_MVS0C_BCR 4 +#define VIDEO_CC_XO_CLK_ARES 5 + +#endif --=20 2.34.1