From nobody Thu Apr 9 21:52:45 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0E5E73DCD99; Thu, 9 Apr 2026 15:28:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775748509; cv=none; b=jE4Kz6AbzLonTlwWgfFiUWKfQ7P6PDncGbsGuRDurG3AEsr4cdk5/qZDKpRWSM268a7wFRrp1o+ZZcIh9uXF4yc07GL8AkLcFxVyHCOTHtgH3XLiHd46B3WFkDjuNxsqU1Y1PfFJpwMjzsLGGCaoFM+hWFN2Pk1UVBwVrZiHluM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775748509; c=relaxed/simple; bh=QBAlX/8xfvy1JTozf9D2BanvnPZ5h9O/HJLH0PkEZa8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=e6i3iP3PvEtoVUQ4k1/gkg0dZ3pYrp1qw+p9h7arZNOMVCzGuECQAGCMSrXwI6ccbkRXs4+AyWe5lFXsxJ2VYUoBR3IgUwb45pCi+ye6Pip0pS6mZIhUcZfIz8FbXbxbwbyhKGOqKDs620jgV1K5wUsRBf8i0vUqZHFsN7lcfAE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=NzozjHzF; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="NzozjHzF" Received: by smtp.kernel.org (Postfix) with ESMTPS id CF2D6C19424; Thu, 9 Apr 2026 15:28:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1775748508; bh=QBAlX/8xfvy1JTozf9D2BanvnPZ5h9O/HJLH0PkEZa8=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=NzozjHzF9VZPvwwcPEhvlkErymxRsqbNMDlSCVNhf1Qc8m3mWm4zs422yxT9phsMP ZkEelVRo/nTSNqJEGPDlhRVe1MMh1Auqe0R4aL8jKKmZikQmy5jl2uyoDnAyyLqqmI NLWDWKk5G4wcbk6lZb/jiwporCVzyrfsVGqlIZJLfFAdxdjv9zLA0tEr4Irjz5jO2g Fc4SpQrXZIPM8joMkkrKpLzTsaAeo3Nm6VaKTDTYWwiwoimiXg8T4GvFVVK0S8qrRE Z66SbU2/gN49GIqiJyKBT+goXELuljzY73ANGkvgJw+YAmlr2ggR/llwdL0MDwAnmN lzurSKBSk7S+Q== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id C419BF31E28; Thu, 9 Apr 2026 15:28:28 +0000 (UTC) From: Radu Sabau via B4 Relay Date: Thu, 09 Apr 2026 18:28:22 +0300 Subject: [PATCH v7 1/6] dt-bindings: iio: adc: add AD4691 family Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260409-ad4692-multichannel-sar-adc-driver-v7-1-be375d4df2c5@analog.com> References: <20260409-ad4692-multichannel-sar-adc-driver-v7-0-be375d4df2c5@analog.com> In-Reply-To: <20260409-ad4692-multichannel-sar-adc-driver-v7-0-be375d4df2c5@analog.com> To: Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , David Lechner , =?utf-8?q?Nuno_S=C3=A1?= , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Liam Girdwood , Mark Brown , Linus Walleij , Bartosz Golaszewski , Philipp Zabel , Jonathan Corbet , Shuah Khan Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pwm@vger.kernel.org, linux-gpio@vger.kernel.org, linux-doc@vger.kernel.org, Radu Sabau X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1775748505; l=6575; i=radu.sabau@analog.com; s=20260220; h=from:subject:message-id; bh=8WQtXGwAJMX9LKjokE7g+NNdM3YBj5DyijsdwhSVWu8=; b=4lG/1xiFSou2/ETXzDjr2ULhec2g3JeIDfNDlIWDFbug0UwU5cjLEHPS5RKTWGygoylCuVT0n PFxP0BPi1+1ApLioju//Vk1QRs0xvlwvBblKXqAfADBtg1+eHFTwBhn X-Developer-Key: i=radu.sabau@analog.com; a=ed25519; pk=lDPQHgn9jTdt0vo58Na9lLxLaE2mb330if71Cn+EvFU= X-Endpoint-Received: by B4 Relay for radu.sabau@analog.com/20260220 with auth_id=642 X-Original-From: Radu Sabau Reply-To: radu.sabau@analog.com From: Radu Sabau Add DT bindings for the Analog Devices AD4691 family of multichannel SAR ADCs (AD4691, AD4692, AD4693, AD4694). The binding describes the hardware connections: - Power domains: avdd-supply (required), vio-supply, ref-supply or refin-supply (external reference; the REFIN path enables the internal reference buffer), and an optional ldo-in-supply, that if absent, means the on-chip internal LDO will be used. - Optional PWM on the CNV pin selects CNV Burst Mode; when absent, Manual Mode is assumed with CNV tied to SPI CS. - An optional reset GPIO (reset-gpios) for hardware reset. - Up to four GP pins (gp0..gp3) usable as interrupt sources, identified in firmware via interrupt-names "gp0".."gp3". - gpio-controller with #gpio-cells =3D <2> for GP pin GPIO usage. - #trigger-source-cells =3D <1>: one cell selecting the GP pin number (0-3) used as the SPI offload trigger source. Two binding examples are provided: CNV Burst Mode with SPI offload (DMA data acquisition driven by DATA_READY on a GP pin), and Manual Mode for CPU-driven triggered-buffer or single-shot capture. Signed-off-by: Radu Sabau Acked-by: Conor Dooley --- .../devicetree/bindings/iio/adc/adi,ad4691.yaml | 162 +++++++++++++++++= ++++ MAINTAINERS | 7 + 2 files changed, 169 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad4691.yaml b/Do= cumentation/devicetree/bindings/iio/adc/adi,ad4691.yaml new file mode 100644 index 000000000000..81d2ca4e0e22 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad4691.yaml @@ -0,0 +1,162 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/adi,ad4691.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices AD4691 Family Multichannel SAR ADCs + +maintainers: + - Radu Sabau + +description: | + The AD4691 family are high-speed, low-power, multichannel successive + approximation register (SAR) analog-to-digital converters (ADCs) with + an SPI-compatible serial interface. The ADC supports CNV Burst Mode, + where an external PWM drives the CNV pin, and Manual Mode, where CNV + is directly tied to the SPI chip-select. + + Datasheets: + * https://www.analog.com/en/products/ad4691.html + * https://www.analog.com/en/products/ad4692.html + * https://www.analog.com/en/products/ad4693.html + * https://www.analog.com/en/products/ad4694.html + +$ref: /schemas/spi/spi-peripheral-props.yaml# + +properties: + compatible: + enum: + - adi,ad4691 + - adi,ad4692 + - adi,ad4693 + - adi,ad4694 + + reg: + maxItems: 1 + + spi-max-frequency: + maximum: 40000000 + + spi-cpol: true + spi-cpha: true + + avdd-supply: + description: Analog power supply (4.5V to 5.5V). + + ldo-in-supply: + description: LDO input supply. When absent, the internal LDO is used. + + vio-supply: + description: I/O voltage supply (1.71V to 1.89V or VDD). + + ref-supply: + description: External reference voltage supply (2.4V to 5.25V). + + refin-supply: + description: Internal reference buffer input supply. + + reset-gpios: + description: + GPIO line controlling the hardware reset pin (active-low). + maxItems: 1 + + pwms: + description: + PWM connected to the CNV pin. When present, selects CNV Burst Mode w= here + the PWM drives the conversion rate. When absent, Manual Mode is used + (CNV tied to SPI CS). + maxItems: 1 + + interrupts: + description: + Interrupt lines connected to the ADC GP pins. Each GP pin can be + physically wired to an interrupt-capable input on the SoC. + maxItems: 4 + + interrupt-names: + description: Names of the interrupt lines, matching the GP pin names. + minItems: 1 + maxItems: 4 + items: + enum: + - gp0 + - gp1 + - gp2 + - gp3 + + gpio-controller: true + + '#gpio-cells': + const: 2 + + '#trigger-source-cells': + description: + This node can act as a trigger source. The single cell in a consumer + reference specifies the GP pin number (0-3) used as the trigger outp= ut. + const: 1 + +required: + - compatible + - reg + - avdd-supply + - vio-supply + +allOf: + # ref-supply and refin-supply are mutually exclusive, one is required + - oneOf: + - required: + - ref-supply + - required: + - refin-supply + +unevaluatedProperties: false + +examples: + - | + #include + /* AD4692 in CNV Burst Mode with SPI offload */ + spi { + #address-cells =3D <1>; + #size-cells =3D <0>; + + adc@0 { + compatible =3D "adi,ad4692"; + reg =3D <0>; + spi-cpol; + spi-cpha; + spi-max-frequency =3D <40000000>; + + avdd-supply =3D <&avdd_supply>; + vio-supply =3D <&vio_supply>; + ref-supply =3D <&ref_5v>; + + reset-gpios =3D <&gpio0 15 GPIO_ACTIVE_LOW>; + + pwms =3D <&pwm_gen 0 0>; + + #trigger-source-cells =3D <1>; + }; + }; + + - | + #include + /* AD4692 in Manual Mode (CNV tied to SPI CS) */ + spi { + #address-cells =3D <1>; + #size-cells =3D <0>; + + adc@0 { + compatible =3D "adi,ad4692"; + reg =3D <0>; + spi-cpol; + spi-cpha; + spi-max-frequency =3D <31250000>; + + avdd-supply =3D <&avdd_supply>; + vio-supply =3D <&vio_supply>; + refin-supply =3D <&refin_supply>; + + reset-gpios =3D <&gpio0 15 GPIO_ACTIVE_LOW>; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 61bf550fd37c..438ca850fa1c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1484,6 +1484,13 @@ W: https://ez.analog.com/linux-software-drivers F: Documentation/devicetree/bindings/iio/adc/adi,ad4170-4.yaml F: drivers/iio/adc/ad4170-4.c =20 +ANALOG DEVICES INC AD4691 DRIVER +M: Radu Sabau +L: linux-iio@vger.kernel.org +S: Supported +W: https://ez.analog.com/linux-software-drivers +F: Documentation/devicetree/bindings/iio/adc/adi,ad4691.yaml + ANALOG DEVICES INC AD4695 DRIVER M: Michael Hennerich M: Nuno S=C3=A1 --=20 2.43.0 From nobody Thu Apr 9 21:52:45 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1D0133DF01A; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260409-ad4692-multichannel-sar-adc-driver-v7-2-be375d4df2c5@analog.com> References: <20260409-ad4692-multichannel-sar-adc-driver-v7-0-be375d4df2c5@analog.com> In-Reply-To: <20260409-ad4692-multichannel-sar-adc-driver-v7-0-be375d4df2c5@analog.com> To: Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , David Lechner , =?utf-8?q?Nuno_S=C3=A1?= , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Liam Girdwood , Mark Brown , Linus Walleij , Bartosz Golaszewski , Philipp Zabel , Jonathan Corbet , Shuah Khan Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pwm@vger.kernel.org, linux-gpio@vger.kernel.org, linux-doc@vger.kernel.org, Radu Sabau X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1775748505; l=23148; i=radu.sabau@analog.com; s=20260220; h=from:subject:message-id; bh=L74Rdgq9fx0vOAIQ985E4sQ6NktejSPlwzbcjbgFXuQ=; b=+Cu77DWJHFjybqNat/gNgjzXAQjKzdpZFxO+OOvudQPQjJ7qvLtwreaRjRXPKMGTmOkmN3NnD l2fneL9Lm33BCEdRGnXgIagTZ7pKMw5DSiRn5jQF7JRY//0dPPozV/d X-Developer-Key: i=radu.sabau@analog.com; a=ed25519; pk=lDPQHgn9jTdt0vo58Na9lLxLaE2mb330if71Cn+EvFU= X-Endpoint-Received: by B4 Relay for radu.sabau@analog.com/20260220 with auth_id=642 X-Original-From: Radu Sabau Reply-To: radu.sabau@analog.com From: Radu Sabau Add support for the Analog Devices AD4691 family of high-speed, low-power multichannel SAR ADCs: AD4691 (16-ch, 500 kSPS), AD4692 (16-ch, 1 MSPS), AD4693 (8-ch, 500 kSPS) and AD4694 (8-ch, 1 MSPS). The driver implements a custom regmap layer over raw SPI to handle the device's mixed 1/2/3/4-byte register widths and uses the standard IIO read_raw/write_raw interface for single-channel reads. The chip idles in Autonomous Mode so that single-shot read_raw can use the internal oscillator without disturbing the hardware configuration. Three voltage supply domains are managed: avdd (required), vio, and a reference supply on either the REF pin (ref-supply, external buffer) or the REFIN pin (refin-supply, uses the on-chip reference buffer; REFBUF_EN is set accordingly). Hardware reset is performed via the reset controller framework; a software reset through SPI_CONFIG_A is used as fallback when no hardware reset is available. Accumulator channel masking for single-shot reads uses ACC_MASK_REG via an ADDR_DESCENDING SPI write, which covers both mask bytes in a single 16-bit transfer. Reviewed-by: David Lechner Signed-off-by: Radu Sabau --- MAINTAINERS | 1 + drivers/iio/adc/Kconfig | 11 + drivers/iio/adc/Makefile | 1 + drivers/iio/adc/ad4691.c | 691 +++++++++++++++++++++++++++++++++++++++++++= ++++ 4 files changed, 704 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 438ca850fa1c..24e4502b8292 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1490,6 +1490,7 @@ L: linux-iio@vger.kernel.org S: Supported W: https://ez.analog.com/linux-software-drivers F: Documentation/devicetree/bindings/iio/adc/adi,ad4691.yaml +F: drivers/iio/adc/ad4691.c =20 ANALOG DEVICES INC AD4695 DRIVER M: Michael Hennerich diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index 60038ae8dfc4..3685a03aa8dc 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -139,6 +139,17 @@ config AD4170_4 To compile this driver as a module, choose M here: the module will be called ad4170-4. =20 +config AD4691 + tristate "Analog Devices AD4691 Family ADC Driver" + depends on SPI + select REGMAP + help + Say yes here to build support for Analog Devices AD4691 Family MuxSAR + SPI analog to digital converters (ADC). + + To compile this driver as a module, choose M here: the module will be + called ad4691. + config AD4695 tristate "Analog Device AD4695 ADC Driver" depends on SPI diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile index c76550415ff1..4ac1ea09d773 100644 --- a/drivers/iio/adc/Makefile +++ b/drivers/iio/adc/Makefile @@ -16,6 +16,7 @@ obj-$(CONFIG_AD4080) +=3D ad4080.o obj-$(CONFIG_AD4130) +=3D ad4130.o obj-$(CONFIG_AD4134) +=3D ad4134.o obj-$(CONFIG_AD4170_4) +=3D ad4170-4.o +obj-$(CONFIG_AD4691) +=3D ad4691.o obj-$(CONFIG_AD4695) +=3D ad4695.o obj-$(CONFIG_AD4851) +=3D ad4851.o obj-$(CONFIG_AD7091R) +=3D ad7091r-base.o diff --git a/drivers/iio/adc/ad4691.c b/drivers/iio/adc/ad4691.c new file mode 100644 index 000000000000..43bd408c3d11 --- /dev/null +++ b/drivers/iio/adc/ad4691.c @@ -0,0 +1,691 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2024-2026 Analog Devices, Inc. + * Author: Radu Sabau + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define AD4691_VREF_uV_MIN 2400000 +#define AD4691_VREF_uV_MAX 5250000 +#define AD4691_VREF_2P5_uV_MAX 2750000 +#define AD4691_VREF_3P0_uV_MAX 3250000 +#define AD4691_VREF_3P3_uV_MAX 3750000 +#define AD4691_VREF_4P096_uV_MAX 4500000 + +#define AD4691_SPI_CONFIG_A_REG 0x000 +#define AD4691_SW_RESET (BIT(7) | BIT(0)) + +#define AD4691_STATUS_REG 0x014 +#define AD4691_CLAMP_STATUS1_REG 0x01A +#define AD4691_CLAMP_STATUS2_REG 0x01B +#define AD4691_DEVICE_SETUP 0x020 +#define AD4691_LDO_EN BIT(4) +#define AD4691_REF_CTRL 0x021 +#define AD4691_REF_CTRL_MASK GENMASK(4, 2) +#define AD4691_REFBUF_EN BIT(0) +#define AD4691_OSC_FREQ_REG 0x023 +#define AD4691_OSC_FREQ_MASK GENMASK(3, 0) +#define AD4691_STD_SEQ_CONFIG 0x025 +#define AD4691_SPARE_CONTROL 0x02A + +#define AD4691_OSC_EN_REG 0x180 +#define AD4691_STATE_RESET_REG 0x181 +#define AD4691_STATE_RESET_ALL 0x01 +#define AD4691_ADC_SETUP 0x182 +#define AD4691_ADC_MODE_MASK GENMASK(1, 0) +#define AD4691_AUTONOMOUS_MODE 0x02 +/* + * ACC_MASK_REG covers both mask bytes via ADDR_DESCENDING SPI: writing a + * 16-bit BE value to 0x185 auto-decrements to 0x184 for the second byte. + */ +#define AD4691_ACC_MASK_REG 0x185 +#define AD4691_ACC_DEPTH_IN(n) (0x186 + (n)) +#define AD4691_GPIO_MODE1_REG 0x196 +#define AD4691_GPIO_MODE2_REG 0x197 +#define AD4691_GPIO_READ 0x1A0 +#define AD4691_ACC_STATUS_FULL1_REG 0x1B0 +#define AD4691_ACC_STATUS_FULL2_REG 0x1B1 +#define AD4691_ACC_STATUS_OVERRUN1_REG 0x1B2 +#define AD4691_ACC_STATUS_OVERRUN2_REG 0x1B3 +#define AD4691_ACC_STATUS_SAT1_REG 0x1B4 +#define AD4691_ACC_STATUS_SAT2_REG 0x1BE +#define AD4691_ACC_SAT_OVR_REG(n) (0x1C0 + (n)) +#define AD4691_AVG_IN(n) (0x201 + (2 * (n))) +#define AD4691_AVG_STS_IN(n) (0x222 + (3 * (n))) +#define AD4691_ACC_IN(n) (0x252 + (3 * (n))) +#define AD4691_ACC_STS_DATA(n) (0x283 + (4 * (n))) + +static const char * const ad4691_supplies[] =3D { "avdd", "vio" }; + +enum ad4691_ref_ctrl { + AD4691_VREF_2P5 =3D 0, + AD4691_VREF_3P0 =3D 1, + AD4691_VREF_3P3 =3D 2, + AD4691_VREF_4P096 =3D 3, + AD4691_VREF_5P0 =3D 4, +}; + +struct ad4691_chip_info { + const struct iio_chan_spec *channels; + const char *name; + unsigned int num_channels; + unsigned int max_rate; +}; + +#define AD4691_CHANNEL(ch) \ + { \ + .type =3D IIO_VOLTAGE, \ + .indexed =3D 1, \ + .info_mask_separate =3D BIT(IIO_CHAN_INFO_RAW) \ + | BIT(IIO_CHAN_INFO_SAMP_FREQ), \ + .info_mask_separate_available =3D \ + BIT(IIO_CHAN_INFO_SAMP_FREQ), \ + .info_mask_shared_by_all =3D BIT(IIO_CHAN_INFO_SCALE), \ + .channel =3D ch, \ + .scan_index =3D ch, \ + .scan_type =3D { \ + .sign =3D 'u', \ + .realbits =3D 16, \ + .storagebits =3D 16, \ + }, \ + } + +static const struct iio_chan_spec ad4691_channels[] =3D { + AD4691_CHANNEL(0), + AD4691_CHANNEL(1), + AD4691_CHANNEL(2), + AD4691_CHANNEL(3), + AD4691_CHANNEL(4), + AD4691_CHANNEL(5), + AD4691_CHANNEL(6), + AD4691_CHANNEL(7), + AD4691_CHANNEL(8), + AD4691_CHANNEL(9), + AD4691_CHANNEL(10), + AD4691_CHANNEL(11), + AD4691_CHANNEL(12), + AD4691_CHANNEL(13), + AD4691_CHANNEL(14), + AD4691_CHANNEL(15), +}; + +static const struct iio_chan_spec ad4693_channels[] =3D { + AD4691_CHANNEL(0), + AD4691_CHANNEL(1), + AD4691_CHANNEL(2), + AD4691_CHANNEL(3), + AD4691_CHANNEL(4), + AD4691_CHANNEL(5), + AD4691_CHANNEL(6), + AD4691_CHANNEL(7), +}; + +/* + * Internal oscillator frequency table. Index is the OSC_FREQ_REG[3:0] val= ue. + * Index 0 (1 MHz) is only valid for AD4692/AD4694; AD4691/AD4693 support + * up to 500 kHz and use index 1 as their highest valid rate. + */ +static const int ad4691_osc_freqs_Hz[] =3D { + [0x0] =3D 1000000, + [0x1] =3D 500000, + [0x2] =3D 400000, + [0x3] =3D 250000, + [0x4] =3D 200000, + [0x5] =3D 167000, + [0x6] =3D 133000, + [0x7] =3D 125000, + [0x8] =3D 100000, + [0x9] =3D 50000, + [0xA] =3D 25000, + [0xB] =3D 12500, + [0xC] =3D 10000, + [0xD] =3D 5000, + [0xE] =3D 2500, + [0xF] =3D 1250, +}; + +static const struct ad4691_chip_info ad4691_chip_info =3D { + .channels =3D ad4691_channels, + .name =3D "ad4691", + .num_channels =3D ARRAY_SIZE(ad4691_channels), + .max_rate =3D 500 * HZ_PER_KHZ, +}; + +static const struct ad4691_chip_info ad4692_chip_info =3D { + .channels =3D ad4691_channels, + .name =3D "ad4692", + .num_channels =3D ARRAY_SIZE(ad4691_channels), + .max_rate =3D 1 * HZ_PER_MHZ, +}; + +static const struct ad4691_chip_info ad4693_chip_info =3D { + .channels =3D ad4693_channels, + .name =3D "ad4693", + .num_channels =3D ARRAY_SIZE(ad4693_channels), + .max_rate =3D 500 * HZ_PER_KHZ, +}; + +static const struct ad4691_chip_info ad4694_chip_info =3D { + .channels =3D ad4693_channels, + .name =3D "ad4694", + .num_channels =3D ARRAY_SIZE(ad4693_channels), + .max_rate =3D 1 * HZ_PER_MHZ, +}; + +struct ad4691_state { + const struct ad4691_chip_info *info; + struct regmap *regmap; + int vref_uV; + bool refbuf_en; + bool ldo_en; + /* + * Synchronize access to members of the driver state, and ensure + * atomicity of consecutive SPI operations. + */ + struct mutex lock; +}; + +static int ad4691_reg_read(void *context, unsigned int reg, unsigned int *= val) +{ + struct spi_device *spi =3D context; + u8 tx[2], rx[4]; + int ret; + + /* Set bit 15 to mark the operation as READ. */ + put_unaligned_be16(0x8000 | reg, tx); + + switch (reg) { + case 0 ... AD4691_OSC_FREQ_REG: + case AD4691_SPARE_CONTROL ... AD4691_ACC_SAT_OVR_REG(15): + ret =3D spi_write_then_read(spi, tx, 2, rx, 1); + if (ret) + return ret; + *val =3D rx[0]; + return 0; + case AD4691_STD_SEQ_CONFIG: + case AD4691_AVG_IN(0) ... AD4691_AVG_IN(15): + ret =3D spi_write_then_read(spi, tx, 2, rx, 2); + if (ret) + return ret; + *val =3D get_unaligned_be16(rx); + return 0; + case AD4691_AVG_STS_IN(0) ... AD4691_AVG_STS_IN(15): + case AD4691_ACC_IN(0) ... AD4691_ACC_IN(15): + ret =3D spi_write_then_read(spi, tx, 2, rx, 3); + if (ret) + return ret; + *val =3D get_unaligned_be24(rx); + return 0; + case AD4691_ACC_STS_DATA(0) ... AD4691_ACC_STS_DATA(15): + ret =3D spi_write_then_read(spi, tx, 2, rx, 4); + if (ret) + return ret; + *val =3D get_unaligned_be32(rx); + return 0; + default: + return -EINVAL; + } +} + +static int ad4691_reg_write(void *context, unsigned int reg, unsigned int = val) +{ + struct spi_device *spi =3D context; + u8 tx[4]; + + put_unaligned_be16(reg, tx); + + switch (reg) { + case 0 ... AD4691_OSC_FREQ_REG: + case AD4691_SPARE_CONTROL ... AD4691_ACC_MASK_REG - 1: + case AD4691_ACC_MASK_REG + 1 ... AD4691_GPIO_MODE2_REG: + if (val > 0xFF) + return -EINVAL; + tx[2] =3D val; + return spi_write_then_read(spi, tx, 3, NULL, 0); + case AD4691_ACC_MASK_REG: + case AD4691_STD_SEQ_CONFIG: + if (val > 0xFFFF) + return -EINVAL; + put_unaligned_be16(val, &tx[2]); + return spi_write_then_read(spi, tx, 4, NULL, 0); + default: + return -EINVAL; + } +} + +static bool ad4691_volatile_reg(struct device *dev, unsigned int reg) +{ + switch (reg) { + case AD4691_STATUS_REG: + case AD4691_CLAMP_STATUS1_REG: + case AD4691_CLAMP_STATUS2_REG: + case AD4691_GPIO_READ: + case AD4691_ACC_STATUS_FULL1_REG ... AD4691_ACC_STATUS_SAT2_REG: + case AD4691_ACC_SAT_OVR_REG(0) ... AD4691_ACC_SAT_OVR_REG(15): + case AD4691_AVG_IN(0) ... AD4691_AVG_IN(15): + case AD4691_AVG_STS_IN(0) ... AD4691_AVG_STS_IN(15): + case AD4691_ACC_IN(0) ... AD4691_ACC_IN(15): + case AD4691_ACC_STS_DATA(0) ... AD4691_ACC_STS_DATA(15): + return true; + default: + return false; + } +} + +static bool ad4691_readable_reg(struct device *dev, unsigned int reg) +{ + switch (reg) { + case 0 ... AD4691_OSC_FREQ_REG: + case AD4691_SPARE_CONTROL ... AD4691_ACC_SAT_OVR_REG(15): + case AD4691_STD_SEQ_CONFIG: + case AD4691_AVG_IN(0) ... AD4691_AVG_IN(15): + case AD4691_AVG_STS_IN(0) ... AD4691_AVG_STS_IN(15): + case AD4691_ACC_IN(0) ... AD4691_ACC_IN(15): + case AD4691_ACC_STS_DATA(0) ... AD4691_ACC_STS_DATA(15): + return true; + default: + return false; + } +} + +static bool ad4691_writeable_reg(struct device *dev, unsigned int reg) +{ + switch (reg) { + case 0 ... AD4691_OSC_FREQ_REG: + case AD4691_STD_SEQ_CONFIG: + case AD4691_SPARE_CONTROL ... AD4691_GPIO_MODE2_REG: + return true; + default: + return false; + } +} + +static const struct regmap_config ad4691_regmap_config =3D { + .reg_bits =3D 16, + .val_bits =3D 32, + .reg_read =3D ad4691_reg_read, + .reg_write =3D ad4691_reg_write, + .volatile_reg =3D ad4691_volatile_reg, + .readable_reg =3D ad4691_readable_reg, + .writeable_reg =3D ad4691_writeable_reg, + .max_register =3D AD4691_ACC_STS_DATA(15), + .cache_type =3D REGCACHE_MAPLE, +}; + +static int ad4691_get_sampling_freq(struct ad4691_state *st, int *val) +{ + unsigned int reg_val; + int ret; + + ret =3D regmap_read(st->regmap, AD4691_OSC_FREQ_REG, ®_val); + if (ret) + return ret; + + *val =3D ad4691_osc_freqs_Hz[FIELD_GET(AD4691_OSC_FREQ_MASK, reg_val)]; + return IIO_VAL_INT; +} + +static int ad4691_set_sampling_freq(struct iio_dev *indio_dev, int freq) +{ + struct ad4691_state *st =3D iio_priv(indio_dev); + unsigned int start =3D (st->info->max_rate =3D=3D 1 * HZ_PER_MHZ) ? 0 : 1; + + IIO_DEV_ACQUIRE_DIRECT_MODE(indio_dev, claim); + if (IIO_DEV_ACQUIRE_FAILED(claim)) + return -EBUSY; + + for (unsigned int i =3D start; i < ARRAY_SIZE(ad4691_osc_freqs_Hz); i++) { + if (ad4691_osc_freqs_Hz[i] !=3D freq) + continue; + return regmap_update_bits(st->regmap, AD4691_OSC_FREQ_REG, + AD4691_OSC_FREQ_MASK, i); + } + + return -EINVAL; +} + +static int ad4691_read_avail(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + const int **vals, int *type, + int *length, long mask) +{ + struct ad4691_state *st =3D iio_priv(indio_dev); + unsigned int start =3D (st->info->max_rate =3D=3D 1 * HZ_PER_MHZ) ? 0 : 1; + + switch (mask) { + case IIO_CHAN_INFO_SAMP_FREQ: + *vals =3D &ad4691_osc_freqs_Hz[start]; + *type =3D IIO_VAL_INT; + *length =3D ARRAY_SIZE(ad4691_osc_freqs_Hz) - start; + return IIO_AVAIL_LIST; + default: + return -EINVAL; + } +} + +static int ad4691_single_shot_read(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, int *val) +{ + struct ad4691_state *st =3D iio_priv(indio_dev); + unsigned int reg_val, osc_idx, period_us; + int ret; + + guard(mutex)(&st->lock); + + /* Use AUTONOMOUS mode for single-shot reads. */ + ret =3D regmap_write(st->regmap, AD4691_STATE_RESET_REG, + AD4691_STATE_RESET_ALL); + if (ret) + return ret; + + ret =3D regmap_write(st->regmap, AD4691_STD_SEQ_CONFIG, + BIT(chan->channel)); + if (ret) + return ret; + + ret =3D regmap_write(st->regmap, AD4691_ACC_MASK_REG, + ~BIT(chan->channel) & GENMASK(15, 0)); + if (ret) + return ret; + + ret =3D regmap_read(st->regmap, AD4691_OSC_FREQ_REG, ®_val); + if (ret) + return ret; + + ret =3D regmap_write(st->regmap, AD4691_OSC_EN_REG, 1); + if (ret) + return ret; + + osc_idx =3D FIELD_GET(AD4691_OSC_FREQ_MASK, reg_val); + /* Wait 2 oscillator periods for the conversion to complete. */ + period_us =3D DIV_ROUND_UP(2UL * USEC_PER_SEC, ad4691_osc_freqs_Hz[osc_id= x]); + fsleep(period_us); + + ret =3D regmap_write(st->regmap, AD4691_OSC_EN_REG, 0); + if (ret) + return ret; + + ret =3D regmap_read(st->regmap, AD4691_AVG_IN(chan->channel), ®_val); + if (ret) + return ret; + + *val =3D reg_val; + + ret =3D regmap_write(st->regmap, AD4691_STATE_RESET_REG, AD4691_STATE_RES= ET_ALL); + if (ret) + return ret; + + return IIO_VAL_INT; +} + +static int ad4691_read_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, int *val, + int *val2, long info) +{ + struct ad4691_state *st =3D iio_priv(indio_dev); + + switch (info) { + case IIO_CHAN_INFO_RAW: { + IIO_DEV_ACQUIRE_DIRECT_MODE(indio_dev, claim); + if (IIO_DEV_ACQUIRE_FAILED(claim)) + return -EBUSY; + + return ad4691_single_shot_read(indio_dev, chan, val); + } + case IIO_CHAN_INFO_SAMP_FREQ: + return ad4691_get_sampling_freq(st, val); + case IIO_CHAN_INFO_SCALE: + *val =3D st->vref_uV / (MICRO / MILLI); + *val2 =3D chan->scan_type.realbits; + return IIO_VAL_FRACTIONAL_LOG2; + default: + return -EINVAL; + } +} + +static int ad4691_write_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int val, int val2, long mask) +{ + switch (mask) { + case IIO_CHAN_INFO_SAMP_FREQ: + return ad4691_set_sampling_freq(indio_dev, val); + default: + return -EINVAL; + } +} + +static int ad4691_reg_access(struct iio_dev *indio_dev, unsigned int reg, + unsigned int writeval, unsigned int *readval) +{ + struct ad4691_state *st =3D iio_priv(indio_dev); + + guard(mutex)(&st->lock); + + if (readval) + return regmap_read(st->regmap, reg, readval); + + return regmap_write(st->regmap, reg, writeval); +} + +static const struct iio_info ad4691_info =3D { + .read_raw =3D &ad4691_read_raw, + .write_raw =3D &ad4691_write_raw, + .read_avail =3D &ad4691_read_avail, + .debugfs_reg_access =3D &ad4691_reg_access, +}; + +static int ad4691_regulator_setup(struct ad4691_state *st) +{ + struct device *dev =3D regmap_get_device(st->regmap); + int ret; + + ret =3D devm_regulator_bulk_get_enable(dev, ARRAY_SIZE(ad4691_supplies), + ad4691_supplies); + if (ret) + return dev_err_probe(dev, ret, "Failed to get and enable supplies\n"); + + ret =3D devm_regulator_get_enable(dev, "ldo-in"); + if (ret =3D=3D -ENODEV) + st->ldo_en =3D true; + else if (ret) + return dev_err_probe(dev, ret, "Failed to get and enable LDO-IN\n"); + + st->vref_uV =3D devm_regulator_get_enable_read_voltage(dev, "ref"); + if (st->vref_uV =3D=3D -ENODEV) { + st->vref_uV =3D devm_regulator_get_enable_read_voltage(dev, "refin"); + st->refbuf_en =3D true; + } + if (st->vref_uV < 0) + return dev_err_probe(dev, st->vref_uV, + "Failed to get reference supply\n"); + + if (st->vref_uV < AD4691_VREF_uV_MIN || st->vref_uV > AD4691_VREF_uV_MAX) + return dev_err_probe(dev, -EINVAL, + "vref(%d) must be in the range [%u...%u]\n", + st->vref_uV, AD4691_VREF_uV_MIN, + AD4691_VREF_uV_MAX); + + return 0; +} + +static int ad4691_reset(struct ad4691_state *st) +{ + struct device *dev =3D regmap_get_device(st->regmap); + struct reset_control *rst; + + rst =3D devm_reset_control_get_optional_exclusive(dev, NULL); + if (IS_ERR(rst)) + return dev_err_probe(dev, PTR_ERR(rst), "Failed to get reset\n"); + + if (rst) { + /* + * The GPIO is already asserted by reset_gpio_probe(). + * Wait for the reset pulse width required by the chip. + * See datasheet Table 5. + */ + fsleep(300); + return reset_control_deassert(rst); + } + + /* No hardware reset available, fall back to software reset. */ + return regmap_write(st->regmap, AD4691_SPI_CONFIG_A_REG, + AD4691_SW_RESET); +} + +static int ad4691_config(struct ad4691_state *st) +{ + struct device *dev =3D regmap_get_device(st->regmap); + enum ad4691_ref_ctrl ref_val; + unsigned int val; + int ret; + + switch (st->vref_uV) { + case AD4691_VREF_uV_MIN ... AD4691_VREF_2P5_uV_MAX: + ref_val =3D AD4691_VREF_2P5; + break; + case AD4691_VREF_2P5_uV_MAX + 1 ... AD4691_VREF_3P0_uV_MAX: + ref_val =3D AD4691_VREF_3P0; + break; + case AD4691_VREF_3P0_uV_MAX + 1 ... AD4691_VREF_3P3_uV_MAX: + ref_val =3D AD4691_VREF_3P3; + break; + case AD4691_VREF_3P3_uV_MAX + 1 ... AD4691_VREF_4P096_uV_MAX: + ref_val =3D AD4691_VREF_4P096; + break; + case AD4691_VREF_4P096_uV_MAX + 1 ... AD4691_VREF_uV_MAX: + ref_val =3D AD4691_VREF_5P0; + break; + default: + return dev_err_probe(dev, -EINVAL, + "Unsupported vref voltage: %d uV\n", + st->vref_uV); + } + + val =3D FIELD_PREP(AD4691_REF_CTRL_MASK, ref_val); + if (st->refbuf_en) + val |=3D AD4691_REFBUF_EN; + + ret =3D regmap_update_bits(st->regmap, AD4691_REF_CTRL, + AD4691_REF_CTRL_MASK | AD4691_REFBUF_EN, val); + if (ret) + return dev_err_probe(dev, ret, "Failed to write REF_CTRL\n"); + + ret =3D regmap_assign_bits(st->regmap, AD4691_DEVICE_SETUP, + AD4691_LDO_EN, st->ldo_en); + if (ret) + return dev_err_probe(dev, ret, "Failed to write DEVICE_SETUP\n"); + + /* + * Set the internal oscillator to the highest rate this chip supports. + * Index 0 (1 MHz) exceeds the 500 kHz max of AD4691/AD4693, so those + * chips start at index 1 (500 kHz). + */ + ret =3D regmap_assign_bits(st->regmap, AD4691_OSC_FREQ_REG, + AD4691_OSC_FREQ_MASK, + (st->info->max_rate =3D=3D 1 * HZ_PER_MHZ) ? 0 : 1); + if (ret) + return dev_err_probe(dev, ret, "Failed to write OSC_FREQ\n"); + + ret =3D regmap_update_bits(st->regmap, AD4691_ADC_SETUP, + AD4691_ADC_MODE_MASK, AD4691_AUTONOMOUS_MODE); + if (ret) + return dev_err_probe(dev, ret, "Failed to write ADC_SETUP\n"); + + return 0; +} + +static int ad4691_probe(struct spi_device *spi) +{ + struct device *dev =3D &spi->dev; + struct iio_dev *indio_dev; + struct ad4691_state *st; + int ret; + + indio_dev =3D devm_iio_device_alloc(&spi->dev, sizeof(*st)); + if (!indio_dev) + return -ENOMEM; + + st =3D iio_priv(indio_dev); + st->info =3D spi_get_device_match_data(spi); + + ret =3D devm_mutex_init(dev, &st->lock); + if (ret) + return ret; + + st->regmap =3D devm_regmap_init(dev, NULL, spi, &ad4691_regmap_config); + if (IS_ERR(st->regmap)) + return dev_err_probe(dev, PTR_ERR(st->regmap), + "Failed to initialize regmap\n"); + + ret =3D ad4691_regulator_setup(st); + if (ret) + return ret; + + ret =3D ad4691_reset(st); + if (ret) + return ret; + + ret =3D ad4691_config(st); + if (ret) + return ret; + + indio_dev->name =3D st->info->name; + indio_dev->info =3D &ad4691_info; + indio_dev->modes =3D INDIO_DIRECT_MODE; + + indio_dev->channels =3D st->info->channels; + indio_dev->num_channels =3D st->info->num_channels; + + return devm_iio_device_register(dev, indio_dev); +} + +static const struct of_device_id ad4691_of_match[] =3D { + { .compatible =3D "adi,ad4691", .data =3D &ad4691_chip_info }, + { .compatible =3D "adi,ad4692", .data =3D &ad4692_chip_info }, + { .compatible =3D "adi,ad4693", .data =3D &ad4693_chip_info }, + { .compatible =3D "adi,ad4694", .data =3D &ad4694_chip_info }, + { } +}; +MODULE_DEVICE_TABLE(of, ad4691_of_match); + +static const struct spi_device_id ad4691_id[] =3D { + { "ad4691", (kernel_ulong_t)&ad4691_chip_info }, + { "ad4692", (kernel_ulong_t)&ad4692_chip_info }, + { "ad4693", (kernel_ulong_t)&ad4693_chip_info }, + { "ad4694", (kernel_ulong_t)&ad4694_chip_info }, + { } +}; +MODULE_DEVICE_TABLE(spi, ad4691_id); + +static struct spi_driver ad4691_driver =3D { + .driver =3D { + .name =3D "ad4691", + .of_match_table =3D ad4691_of_match, + }, + .probe =3D ad4691_probe, + .id_table =3D ad4691_id, +}; +module_spi_driver(ad4691_driver); + +MODULE_AUTHOR("Radu Sabau "); +MODULE_DESCRIPTION("Analog Devices AD4691 Family ADC Driver"); +MODULE_LICENSE("GPL"); --=20 2.43.0 From nobody Thu Apr 9 21:52:45 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 33A473DFC74; Thu, 9 Apr 2026 15:28:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775748509; cv=none; b=fihNkGE5ub1Pks2zU5agV1FH2+ZnILfonFY6ZuYoR8vtue++M/E1H5ZXZ/GWfAFlfnBkt4Zlzyng3AKBn/IHlL5ROeR58krTlpbwYYEp+wA3SvHDbbt44e/246QZO2R82wgDr+ezbDjTwRuGbIIecxRVDseMxM65Yy19xrBMn/s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775748509; c=relaxed/simple; bh=QfH9u6O8rzKFyCCXKwsytcBG/RDh9kxkD/2YsQb2msI=; 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Thu, 9 Apr 2026 15:28:28 +0000 (UTC) From: Radu Sabau via B4 Relay Date: Thu, 09 Apr 2026 18:28:24 +0300 Subject: [PATCH v7 3/6] iio: adc: ad4691: add triggered buffer support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260409-ad4692-multichannel-sar-adc-driver-v7-3-be375d4df2c5@analog.com> References: <20260409-ad4692-multichannel-sar-adc-driver-v7-0-be375d4df2c5@analog.com> In-Reply-To: <20260409-ad4692-multichannel-sar-adc-driver-v7-0-be375d4df2c5@analog.com> To: Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , David Lechner , =?utf-8?q?Nuno_S=C3=A1?= , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Liam Girdwood , Mark Brown , Linus Walleij , Bartosz Golaszewski , Philipp Zabel , Jonathan Corbet , Shuah Khan Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pwm@vger.kernel.org, linux-gpio@vger.kernel.org, linux-doc@vger.kernel.org, Radu Sabau X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1775748505; l=24317; i=radu.sabau@analog.com; s=20260220; h=from:subject:message-id; bh=F0QB2cO663nAuEzGsci2CDTXdKrVe4mcBWEFDCaotLE=; b=hjT+EWQDRvx/lIHzm99pn53d3cbYXUXLxgPcrpA7t/36ZuWLZzEctBvA0RcyOu729EbnF4iDT HzymbZUq+JBDh84w2eqpBybvTO78Z3XsnoJwLMYO7nSSU/5D9exjSVW X-Developer-Key: i=radu.sabau@analog.com; a=ed25519; pk=lDPQHgn9jTdt0vo58Na9lLxLaE2mb330if71Cn+EvFU= X-Endpoint-Received: by B4 Relay for radu.sabau@analog.com/20260220 with auth_id=642 X-Original-From: Radu Sabau Reply-To: radu.sabau@analog.com From: Radu Sabau Add buffered capture support using the IIO triggered buffer framework. CNV Burst Mode: the GP pin identified by interrupt-names in the device tree is configured as DATA_READY output. The IRQ handler stops conversions and fires the IIO trigger; the trigger handler executes a pre-built SPI message that reads all active channels from the AVG_IN accumulator registers and then resets accumulator state and restarts conversions for the next cycle. Manual Mode: CNV is tied to SPI CS so each transfer simultaneously reads the previous result and starts the next conversion (pipelined N+1 scheme). At preenable time a pre-built, optimised SPI message of N+1 transfers is constructed (N channel reads plus one NOOP to drain the pipeline). The trigger handler executes the message in a single spi_sync() call and collects the results. An external trigger (e.g. iio-trig-hrtimer) is required to drive the trigger at the desired sample rate. Both modes share the same trigger handler and push a complete scan =E2=80= =94 one u16 slot per channel at its scan_index position, followed by a timestamp =E2=80=94 to the IIO buffer via iio_push_to_buffers_with_ts(). The CNV Burst Mode sampling frequency (PWM period) is exposed as a buffer-level attribute via IIO_DEVICE_ATTR. Signed-off-by: Radu Sabau --- drivers/iio/adc/Kconfig | 2 + drivers/iio/adc/ad4691.c | 553 +++++++++++++++++++++++++++++++++++++++++++= ++-- 2 files changed, 540 insertions(+), 15 deletions(-) diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index 3685a03aa8dc..d498f16c0816 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -142,6 +142,8 @@ config AD4170_4 config AD4691 tristate "Analog Devices AD4691 Family ADC Driver" depends on SPI + select IIO_BUFFER + select IIO_TRIGGERED_BUFFER select REGMAP help Say yes here to build support for Analog Devices AD4691 Family MuxSAR diff --git a/drivers/iio/adc/ad4691.c b/drivers/iio/adc/ad4691.c index 43bd408c3d11..3e5caa0972eb 100644 --- a/drivers/iio/adc/ad4691.c +++ b/drivers/iio/adc/ad4691.c @@ -5,15 +5,19 @@ */ #include #include -#include +#include #include #include #include #include +#include #include +#include #include #include #include +#include +#include #include #include #include @@ -21,7 +25,14 @@ #include #include =20 +#include +#include +#include #include +#include +#include +#include +#include =20 #define AD4691_VREF_uV_MIN 2400000 #define AD4691_VREF_uV_MAX 5250000 @@ -30,6 +41,9 @@ #define AD4691_VREF_3P3_uV_MAX 3750000 #define AD4691_VREF_4P096_uV_MAX 4500000 =20 +#define AD4691_CNV_DUTY_CYCLE_NS 380 +#define AD4691_CNV_HIGH_TIME_NS 430 + #define AD4691_SPI_CONFIG_A_REG 0x000 #define AD4691_SW_RESET (BIT(7) | BIT(0)) =20 @@ -37,6 +51,7 @@ #define AD4691_CLAMP_STATUS1_REG 0x01A #define AD4691_CLAMP_STATUS2_REG 0x01B #define AD4691_DEVICE_SETUP 0x020 +#define AD4691_MANUAL_MODE BIT(2) #define AD4691_LDO_EN BIT(4) #define AD4691_REF_CTRL 0x021 #define AD4691_REF_CTRL_MASK GENMASK(4, 2) @@ -44,13 +59,18 @@ #define AD4691_OSC_FREQ_REG 0x023 #define AD4691_OSC_FREQ_MASK GENMASK(3, 0) #define AD4691_STD_SEQ_CONFIG 0x025 +#define AD4691_SEQ_ALL_CHANNELS_OFF 0x00 #define AD4691_SPARE_CONTROL 0x02A =20 +#define AD4691_NOOP 0x00 +#define AD4691_ADC_CHAN(ch) ((0x10 + (ch)) << 3) + #define AD4691_OSC_EN_REG 0x180 #define AD4691_STATE_RESET_REG 0x181 #define AD4691_STATE_RESET_ALL 0x01 #define AD4691_ADC_SETUP 0x182 #define AD4691_ADC_MODE_MASK GENMASK(1, 0) +#define AD4691_CNV_BURST_MODE 0x01 #define AD4691_AUTONOMOUS_MODE 0x02 /* * ACC_MASK_REG covers both mask bytes via ADDR_DESCENDING SPI: writing a @@ -60,6 +80,8 @@ #define AD4691_ACC_DEPTH_IN(n) (0x186 + (n)) #define AD4691_GPIO_MODE1_REG 0x196 #define AD4691_GPIO_MODE2_REG 0x197 +#define AD4691_GP_MODE_MASK GENMASK(3, 0) +#define AD4691_GP_MODE_DATA_READY 0x06 #define AD4691_GPIO_READ 0x1A0 #define AD4691_ACC_STATUS_FULL1_REG 0x1B0 #define AD4691_ACC_STATUS_FULL2_REG 0x1B1 @@ -83,19 +105,23 @@ enum ad4691_ref_ctrl { AD4691_VREF_5P0 =3D 4, }; =20 -struct ad4691_chip_info { +struct ad4691_channel_info { const struct iio_chan_spec *channels; - const char *name; unsigned int num_channels; +}; + +struct ad4691_chip_info { + const char *name; unsigned int max_rate; + const struct ad4691_channel_info *sw_info; }; =20 #define AD4691_CHANNEL(ch) \ { \ .type =3D IIO_VOLTAGE, \ .indexed =3D 1, \ - .info_mask_separate =3D BIT(IIO_CHAN_INFO_RAW) \ - | BIT(IIO_CHAN_INFO_SAMP_FREQ), \ + .info_mask_separate =3D BIT(IIO_CHAN_INFO_RAW) | \ + BIT(IIO_CHAN_INFO_SAMP_FREQ), \ .info_mask_separate_available =3D \ BIT(IIO_CHAN_INFO_SAMP_FREQ), \ .info_mask_shared_by_all =3D BIT(IIO_CHAN_INFO_SCALE), \ @@ -105,6 +131,7 @@ struct ad4691_chip_info { .sign =3D 'u', \ .realbits =3D 16, \ .storagebits =3D 16, \ + .endianness =3D IIO_BE, \ }, \ } =20 @@ -125,6 +152,7 @@ static const struct iio_chan_spec ad4691_channels[] =3D= { AD4691_CHANNEL(13), AD4691_CHANNEL(14), AD4691_CHANNEL(15), + IIO_CHAN_SOFT_TIMESTAMP(16), }; =20 static const struct iio_chan_spec ad4693_channels[] =3D { @@ -136,6 +164,17 @@ static const struct iio_chan_spec ad4693_channels[] = =3D { AD4691_CHANNEL(5), AD4691_CHANNEL(6), AD4691_CHANNEL(7), + IIO_CHAN_SOFT_TIMESTAMP(8), +}; + +static const struct ad4691_channel_info ad4691_sw_info =3D { + .channels =3D ad4691_channels, + .num_channels =3D ARRAY_SIZE(ad4691_channels), +}; + +static const struct ad4691_channel_info ad4693_sw_info =3D { + .channels =3D ad4693_channels, + .num_channels =3D ARRAY_SIZE(ad4693_channels), }; =20 /* @@ -162,38 +201,43 @@ static const int ad4691_osc_freqs_Hz[] =3D { [0xF] =3D 1250, }; =20 +static const char * const ad4691_gp_names[] =3D { "gp0", "gp1", "gp2", "gp= 3" }; + static const struct ad4691_chip_info ad4691_chip_info =3D { - .channels =3D ad4691_channels, .name =3D "ad4691", - .num_channels =3D ARRAY_SIZE(ad4691_channels), .max_rate =3D 500 * HZ_PER_KHZ, + .sw_info =3D &ad4691_sw_info, }; =20 static const struct ad4691_chip_info ad4692_chip_info =3D { - .channels =3D ad4691_channels, .name =3D "ad4692", - .num_channels =3D ARRAY_SIZE(ad4691_channels), .max_rate =3D 1 * HZ_PER_MHZ, + .sw_info =3D &ad4691_sw_info, }; =20 static const struct ad4691_chip_info ad4693_chip_info =3D { - .channels =3D ad4693_channels, .name =3D "ad4693", - .num_channels =3D ARRAY_SIZE(ad4693_channels), .max_rate =3D 500 * HZ_PER_KHZ, + .sw_info =3D &ad4693_sw_info, }; =20 static const struct ad4691_chip_info ad4694_chip_info =3D { - .channels =3D ad4693_channels, .name =3D "ad4694", - .num_channels =3D ARRAY_SIZE(ad4693_channels), .max_rate =3D 1 * HZ_PER_MHZ, + .sw_info =3D &ad4693_sw_info, }; =20 struct ad4691_state { const struct ad4691_chip_info *info; struct regmap *regmap; + struct spi_device *spi; + + struct pwm_device *conv_trigger; + int irq; int vref_uV; + u32 cnv_period_ns; + + bool manual_mode; bool refbuf_en; bool ldo_en; /* @@ -201,8 +245,45 @@ struct ad4691_state { * atomicity of consecutive SPI operations. */ struct mutex lock; + /* + * Per-buffer-enable lifetime resources: + * Manual Mode - a pre-built SPI message that clocks out N+1 + * transfers in one go. + * CNV Burst Mode - a pre-built SPI message that clocks out 2*N + * transfers in one go. + */ + struct spi_message scan_msg; + /* max 16 + 1 NOOP (manual) or 2*16 + 2 (CNV burst). */ + struct spi_transfer scan_xfers[34]; + /* + * CNV burst: 16 AVG_IN addresses + state-reset address + state-reset + * value =3D 18. Manual: 16 channel cmds + 1 NOOP =3D 17. + */ + __be16 scan_tx[18]; + /* Scan buffer: one BE16 slot per channel (rx'd directly), plus timestamp= */ + struct { + __be16 vals[16]; + aligned_s64 ts; + } scan; }; =20 +/* + * Configure the given GP pin (0-3) as DATA_READY output. + * GP0/GP1 =E2=86=92 GPIO_MODE1_REG, GP2/GP3 =E2=86=92 GPIO_MODE2_REG. + * Even pins occupy bits [3:0], odd pins bits [7:4]. + */ +static int ad4691_gpio_setup(struct ad4691_state *st, unsigned int gp_num) +{ + unsigned int bit_off =3D gp_num % 2; + unsigned int reg_off =3D gp_num / 2; + unsigned int shift =3D 4 * bit_off; + + return regmap_update_bits(st->regmap, + AD4691_GPIO_MODE1_REG + reg_off, + AD4691_GP_MODE_MASK << shift, + AD4691_GP_MODE_DATA_READY << shift); +} + static int ad4691_reg_read(void *context, unsigned int reg, unsigned int *= val) { struct spi_device *spi =3D context; @@ -486,6 +567,346 @@ static int ad4691_reg_access(struct iio_dev *indio_de= v, unsigned int reg, return regmap_write(st->regmap, reg, writeval); } =20 +static int ad4691_set_pwm_freq(struct ad4691_state *st, int freq) +{ + if (!freq) + return -EINVAL; + + st->cnv_period_ns =3D DIV_ROUND_UP(NSEC_PER_SEC, freq); + return 0; +} + +static int ad4691_sampling_enable(struct ad4691_state *st, bool enable) +{ + struct pwm_state conv_state =3D { + .period =3D st->cnv_period_ns, + .duty_cycle =3D AD4691_CNV_DUTY_CYCLE_NS, + .polarity =3D PWM_POLARITY_NORMAL, + .enabled =3D enable, + }; + + return pwm_apply_might_sleep(st->conv_trigger, &conv_state); +} + +/* + * ad4691_enter_conversion_mode - Switch the chip to its buffer conversion= mode. + * + * Configures the ADC hardware registers for the mode selected at probe + * (CNV_BURST or MANUAL). Called from buffer preenable before starting + * sampling. The chip is in AUTONOMOUS mode during idle (for read_raw). + */ +static int ad4691_enter_conversion_mode(struct ad4691_state *st) +{ + int ret; + + if (st->manual_mode) + return regmap_update_bits(st->regmap, AD4691_DEVICE_SETUP, + AD4691_MANUAL_MODE, AD4691_MANUAL_MODE); + + ret =3D regmap_update_bits(st->regmap, AD4691_ADC_SETUP, + AD4691_ADC_MODE_MASK, AD4691_CNV_BURST_MODE); + if (ret) + return ret; + + return regmap_write(st->regmap, AD4691_STATE_RESET_REG, + AD4691_STATE_RESET_ALL); +} + +/* + * ad4691_exit_conversion_mode - Return the chip to AUTONOMOUS mode. + * + * Called from buffer postdisable to restore the chip to the + * idle state used by read_raw. Clears the sequencer and resets state. + */ +static int ad4691_exit_conversion_mode(struct ad4691_state *st) +{ + if (st->manual_mode) + return regmap_update_bits(st->regmap, AD4691_DEVICE_SETUP, + AD4691_MANUAL_MODE, 0); + + return regmap_update_bits(st->regmap, AD4691_ADC_SETUP, + AD4691_ADC_MODE_MASK, AD4691_AUTONOMOUS_MODE); +} + +static int ad4691_manual_buffer_preenable(struct iio_dev *indio_dev) +{ + struct ad4691_state *st =3D iio_priv(indio_dev); + unsigned int n_active; + unsigned int n_xfers; + unsigned int prev_i, k, i; + bool first; + int ret; + + n_active =3D bitmap_weight(indio_dev->active_scan_mask, iio_get_masklengt= h(indio_dev)); + n_xfers =3D n_active + 1; + + memset(st->scan_xfers, 0, n_xfers * sizeof(st->scan_xfers[0])); + memset(st->scan_tx, 0, n_xfers * sizeof(st->scan_tx[0])); + + spi_message_init(&st->scan_msg); + + first =3D true; + prev_i =3D 0; + k =3D 0; + iio_for_each_active_channel(indio_dev, i) { + st->scan_tx[k] =3D cpu_to_be16(AD4691_ADC_CHAN(i)); + st->scan_xfers[k].tx_buf =3D &st->scan_tx[k]; + /* + * The pipeline means xfer[0] receives the residual from the + * previous sequence, not a valid sample for channel i. Point + * it at vals[i] anyway; xfer[1] (or the NOOP when only one + * channel is active) will overwrite that slot with the real + * result, so no separate dummy buffer is needed. + */ + if (first) { + st->scan_xfers[k].rx_buf =3D &st->scan.vals[i]; + first =3D false; + } else { + st->scan_xfers[k].rx_buf =3D &st->scan.vals[prev_i]; + } + st->scan_xfers[k].len =3D sizeof(__be16); + st->scan_xfers[k].cs_change =3D 1; + spi_message_add_tail(&st->scan_xfers[k], &st->scan_msg); + prev_i =3D i; + k++; + } + + /* Final NOOP transfer retrieves the last channel's result. */ + st->scan_xfers[k].tx_buf =3D &st->scan_tx[k]; /* scan_tx[k] =3D=3D 0 =3D= =3D NOOP */ + st->scan_xfers[k].rx_buf =3D &st->scan.vals[prev_i]; + st->scan_xfers[k].len =3D sizeof(__be16); + spi_message_add_tail(&st->scan_xfers[k], &st->scan_msg); + + ret =3D spi_optimize_message(st->spi, &st->scan_msg); + if (ret) + return ret; + + ret =3D ad4691_enter_conversion_mode(st); + if (ret) { + spi_unoptimize_message(&st->scan_msg); + return ret; + } + + return 0; +} + +static int ad4691_manual_buffer_postdisable(struct iio_dev *indio_dev) +{ + struct ad4691_state *st =3D iio_priv(indio_dev); + int ret; + + ret =3D ad4691_exit_conversion_mode(st); + spi_unoptimize_message(&st->scan_msg); + return ret; +} + +static const struct iio_buffer_setup_ops ad4691_manual_buffer_setup_ops = =3D { + .preenable =3D &ad4691_manual_buffer_preenable, + .postdisable =3D &ad4691_manual_buffer_postdisable, +}; + +static int ad4691_cnv_burst_buffer_preenable(struct iio_dev *indio_dev) +{ + struct ad4691_state *st =3D iio_priv(indio_dev); + unsigned int n_active; + unsigned int k, i; + int ret; + + n_active =3D bitmap_weight(indio_dev->active_scan_mask, iio_get_masklengt= h(indio_dev)); + + memset(st->scan_xfers, 0, (2 * n_active + 2) * sizeof(st->scan_xfers[0])); + memset(st->scan_tx, 0, (n_active + 2) * sizeof(st->scan_tx[0])); + + spi_message_init(&st->scan_msg); + + /* + * Each AVG_IN read needs two transfers: a 2-byte address write phase + * followed by a 2-byte data read phase. CS toggles between channels + * (cs_change=3D1 on the read phase of all but the last channel). + */ + k =3D 0; + iio_for_each_active_channel(indio_dev, i) { + st->scan_tx[k] =3D cpu_to_be16(0x8000 | AD4691_AVG_IN(i)); + st->scan_xfers[2 * k].tx_buf =3D &st->scan_tx[k]; + st->scan_xfers[2 * k].len =3D sizeof(__be16); + spi_message_add_tail(&st->scan_xfers[2 * k], &st->scan_msg); + st->scan_xfers[2 * k + 1].rx_buf =3D &st->scan.vals[i]; + st->scan_xfers[2 * k + 1].len =3D sizeof(__be16); + st->scan_xfers[2 * k + 1].cs_change =3D 1; + spi_message_add_tail(&st->scan_xfers[2 * k + 1], &st->scan_msg); + k++; + } + + st->scan_tx[k] =3D cpu_to_be16(AD4691_STATE_RESET_REG); + st->scan_xfers[2 * k].tx_buf =3D &st->scan_tx[k]; + st->scan_xfers[2 * k].len =3D sizeof(__be16); + spi_message_add_tail(&st->scan_xfers[2 * k], &st->scan_msg); + st->scan_tx[k + 1] =3D cpu_to_be16(AD4691_STATE_RESET_ALL << 8); + st->scan_xfers[2 * k + 1].tx_buf =3D &st->scan_tx[k + 1]; + st->scan_xfers[2 * k + 1].len =3D sizeof(__be16); + st->scan_xfers[2 * k + 1].cs_change =3D 1; + spi_message_add_tail(&st->scan_xfers[2 * k + 1], &st->scan_msg); + + ret =3D spi_optimize_message(st->spi, &st->scan_msg); + if (ret) + goto err_unoptimize; + + ret =3D regmap_write(st->regmap, AD4691_STD_SEQ_CONFIG, + bitmap_read(indio_dev->active_scan_mask, 0, + iio_get_masklength(indio_dev))); + if (ret) + goto err_unoptimize; + + ret =3D regmap_write(st->regmap, AD4691_ACC_MASK_REG, + ~bitmap_read(indio_dev->active_scan_mask, 0, + iio_get_masklength(indio_dev)) & GENMASK(15, 0)); + if (ret) + goto err_unoptimize; + + ret =3D ad4691_enter_conversion_mode(st); + if (ret) + goto err_unoptimize; + + ret =3D ad4691_sampling_enable(st, true); + if (ret) + goto err_exit_conv; + + enable_irq(st->irq); + return 0; + +err_exit_conv: + ad4691_exit_conversion_mode(st); +err_unoptimize: + spi_unoptimize_message(&st->scan_msg); + return ret; +} + +static int ad4691_cnv_burst_buffer_postdisable(struct iio_dev *indio_dev) +{ + struct ad4691_state *st =3D iio_priv(indio_dev); + int ret; + + disable_irq(st->irq); + + ret =3D ad4691_sampling_enable(st, false); + if (ret) + return ret; + + ret =3D ad4691_exit_conversion_mode(st); + if (ret) + return ret; + + ret =3D regmap_write(st->regmap, AD4691_STD_SEQ_CONFIG, + AD4691_SEQ_ALL_CHANNELS_OFF); + spi_unoptimize_message(&st->scan_msg); + return ret; +} + +static const struct iio_buffer_setup_ops ad4691_cnv_burst_buffer_setup_ops= =3D { + .preenable =3D &ad4691_cnv_burst_buffer_preenable, + .postdisable =3D &ad4691_cnv_burst_buffer_postdisable, +}; + +static ssize_t sampling_frequency_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct iio_dev *indio_dev =3D dev_to_iio_dev(dev); + struct ad4691_state *st =3D iio_priv(indio_dev); + + return sysfs_emit(buf, "%u\n", NSEC_PER_SEC / st->cnv_period_ns); +} + +static ssize_t sampling_frequency_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t len) +{ + struct iio_dev *indio_dev =3D dev_to_iio_dev(dev); + struct ad4691_state *st =3D iio_priv(indio_dev); + int freq, ret; + + ret =3D kstrtoint(buf, 10, &freq); + if (ret) + return ret; + + ret =3D iio_device_claim_direct(indio_dev); + if (ret) + return ret; + + ret =3D ad4691_set_pwm_freq(st, freq); + iio_device_release_direct(indio_dev); + if (ret) + return ret; + + return len; +} + +static IIO_DEVICE_ATTR_RW(sampling_frequency, 0); + +static const struct iio_dev_attr *ad4691_buffer_attrs[] =3D { + &iio_dev_attr_sampling_frequency, + NULL +}; + +static irqreturn_t ad4691_irq(int irq, void *private) +{ + struct iio_dev *indio_dev =3D private; + struct ad4691_state *st =3D iio_priv(indio_dev); + + iio_trigger_poll(indio_dev->trig); + /* + * Keep the DATA_READY IRQ disabled until the trigger handler has + * finished reading the scan, to prevent a new assertion mid-transfer. + * The PWM continues running uninterrupted; the IRQ is re-enabled in + * ad4691_trigger_handler once spi_sync completes. + * + * IRQF_ONESHOT already masks the hardware line during this threaded + * handler, so disable_irq_nosync here ensures the IRQ stays disabled + * even after IRQF_ONESHOT unmasks on return. + */ + disable_irq_nosync(st->irq); + + return IRQ_HANDLED; +} + +static const struct iio_trigger_ops ad4691_trigger_ops =3D { + .validate_device =3D iio_trigger_validate_own_device, +}; + +static int ad4691_read_scan(struct iio_dev *indio_dev, s64 timestamp) +{ + struct ad4691_state *st =3D iio_priv(indio_dev); + int ret; + + guard(mutex)(&st->lock); + + ret =3D spi_sync(st->spi, &st->scan_msg); + if (ret) + return ret; + + /* + * rx_buf pointers in scan_xfers point directly into scan.vals, so no + * copy is needed. The scan_msg already includes a STATE_RESET at the + * end (appended in preenable), so no explicit reset is needed here. + */ + iio_push_to_buffers_with_ts(indio_dev, &st->scan, sizeof(st->scan), + timestamp); + return 0; +} + +static irqreturn_t ad4691_trigger_handler(int irq, void *p) +{ + struct iio_poll_func *pf =3D p; + struct iio_dev *indio_dev =3D pf->indio_dev; + struct ad4691_state *st =3D iio_priv(indio_dev); + + ad4691_read_scan(indio_dev, pf->timestamp); + if (!st->manual_mode) + enable_irq(st->irq); + iio_trigger_notify_done(indio_dev->trig); + return IRQ_HANDLED; +} + static const struct iio_info ad4691_info =3D { .read_raw =3D &ad4691_read_raw, .write_raw =3D &ad4691_write_raw, @@ -493,6 +914,18 @@ static const struct iio_info ad4691_info =3D { .debugfs_reg_access =3D &ad4691_reg_access, }; =20 +static int ad4691_pwm_setup(struct ad4691_state *st) +{ + struct device *dev =3D regmap_get_device(st->regmap); + + st->conv_trigger =3D devm_pwm_get(dev, "cnv"); + if (IS_ERR(st->conv_trigger)) + return dev_err_probe(dev, PTR_ERR(st->conv_trigger), + "Failed to get cnv pwm\n"); + + return ad4691_set_pwm_freq(st, st->info->max_rate); +} + static int ad4691_regulator_setup(struct ad4691_state *st) { struct device *dev =3D regmap_get_device(st->regmap); @@ -558,6 +991,22 @@ static int ad4691_config(struct ad4691_state *st) unsigned int val; int ret; =20 + /* + * Determine buffer conversion mode from DT: if a PWM is provided it + * drives the CNV pin (CNV_BURST_MODE); otherwise CNV is tied to CS + * and each SPI transfer triggers a conversion (MANUAL_MODE). + * Both modes idle in AUTONOMOUS mode so that read_raw can use the + * internal oscillator without disturbing the hardware configuration. + */ + if (device_property_present(dev, "pwms")) { + st->manual_mode =3D false; + ret =3D ad4691_pwm_setup(st); + if (ret) + return ret; + } else { + st->manual_mode =3D true; + } + switch (st->vref_uV) { case AD4691_VREF_uV_MIN ... AD4691_VREF_2P5_uV_MAX: ref_val =3D AD4691_VREF_2P5; @@ -613,6 +1062,76 @@ static int ad4691_config(struct ad4691_state *st) return 0; } =20 +static int ad4691_setup_triggered_buffer(struct iio_dev *indio_dev, + struct ad4691_state *st) +{ + struct device *dev =3D regmap_get_device(st->regmap); + struct iio_trigger *trig; + unsigned int i; + int irq, ret; + + trig =3D devm_iio_trigger_alloc(dev, "%s-dev%d", + indio_dev->name, + iio_device_id(indio_dev)); + if (!trig) + return -ENOMEM; + + trig->ops =3D &ad4691_trigger_ops; + iio_trigger_set_drvdata(trig, st); + + ret =3D devm_iio_trigger_register(dev, trig); + if (ret) + return dev_err_probe(dev, ret, "IIO trigger register failed\n"); + + indio_dev->trig =3D iio_trigger_get(trig); + + if (st->manual_mode) + return devm_iio_triggered_buffer_setup(dev, indio_dev, + &iio_pollfunc_store_time, + &ad4691_trigger_handler, + &ad4691_manual_buffer_setup_ops); + + /* + * The GP pin named in interrupt-names asserts at end-of-conversion. + * The IRQ handler stops conversions and fires the IIO trigger so + * the trigger handler can read and push the sample to the buffer. + * The IRQ is kept disabled until the buffer is enabled. + */ + irq =3D -ENXIO; + for (i =3D 0; i < ARRAY_SIZE(ad4691_gp_names); i++) { + irq =3D fwnode_irq_get_byname(dev_fwnode(dev), + ad4691_gp_names[i]); + if (irq > 0) + break; + } + if (irq < 0) + return dev_err_probe(dev, irq, "failed to get GP interrupt\n"); + + st->irq =3D irq; + + ret =3D ad4691_gpio_setup(st, i); + if (ret) + return ret; + + /* + * IRQ is kept disabled until the buffer is enabled to prevent + * spurious DATA_READY events before the SPI message is set up. + */ + ret =3D devm_request_threaded_irq(dev, irq, NULL, + &ad4691_irq, + IRQF_ONESHOT | IRQF_NO_AUTOEN, + indio_dev->name, indio_dev); + if (ret) + return ret; + + return devm_iio_triggered_buffer_setup_ext(dev, indio_dev, + &iio_pollfunc_store_time, + &ad4691_trigger_handler, + IIO_BUFFER_DIRECTION_IN, + &ad4691_cnv_burst_buffer_setup_ops, + ad4691_buffer_attrs); +} + static int ad4691_probe(struct spi_device *spi) { struct device *dev =3D &spi->dev; @@ -625,6 +1144,7 @@ static int ad4691_probe(struct spi_device *spi) return -ENOMEM; =20 st =3D iio_priv(indio_dev); + st->spi =3D spi; st->info =3D spi_get_device_match_data(spi); =20 ret =3D devm_mutex_init(dev, &st->lock); @@ -652,8 +1172,11 @@ static int ad4691_probe(struct spi_device *spi) indio_dev->info =3D &ad4691_info; indio_dev->modes =3D INDIO_DIRECT_MODE; =20 - indio_dev->channels =3D st->info->channels; - indio_dev->num_channels =3D st->info->num_channels; + indio_dev->channels =3D st->info->sw_info->channels; + indio_dev->num_channels =3D st->info->sw_info->num_channels; + ret =3D ad4691_setup_triggered_buffer(indio_dev, st); + if (ret) + return ret; =20 return devm_iio_device_register(dev, indio_dev); } --=20 2.43.0 From nobody Thu Apr 9 21:52:45 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 66D073E0C73; Thu, 9 Apr 2026 15:28:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260409-ad4692-multichannel-sar-adc-driver-v7-4-be375d4df2c5@analog.com> References: <20260409-ad4692-multichannel-sar-adc-driver-v7-0-be375d4df2c5@analog.com> In-Reply-To: <20260409-ad4692-multichannel-sar-adc-driver-v7-0-be375d4df2c5@analog.com> To: Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , David Lechner , =?utf-8?q?Nuno_S=C3=A1?= , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Liam Girdwood , Mark Brown , Linus Walleij , Bartosz Golaszewski , Philipp Zabel , Jonathan Corbet , Shuah Khan Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pwm@vger.kernel.org, linux-gpio@vger.kernel.org, linux-doc@vger.kernel.org, Radu Sabau X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1775748505; l=20066; i=radu.sabau@analog.com; s=20260220; h=from:subject:message-id; bh=Ousdf/UUlNDEkFs02oWb2zGh3S08PDZ2UYODcd0dY2M=; b=YazVMq8egOV5J2t0sFtya0WAQ6bOi+1C+akpV85XA7eNZwq+4bdg+Vb718mslBmS6x8nIgDXm DXOgDb4vDIIB2O36DwtR8TILGD0MaKqH4KkZEXpiig5dApKtmDVM/dR X-Developer-Key: i=radu.sabau@analog.com; a=ed25519; pk=lDPQHgn9jTdt0vo58Na9lLxLaE2mb330if71Cn+EvFU= X-Endpoint-Received: by B4 Relay for radu.sabau@analog.com/20260220 with auth_id=642 X-Original-From: Radu Sabau Reply-To: radu.sabau@analog.com From: Radu Sabau Add SPI offload support to enable DMA-based, CPU-independent data acquisition using the SPI Engine offload framework. When an SPI offload is available (devm_spi_offload_get() succeeds), the driver registers a DMA engine IIO buffer and uses dedicated buffer setup operations. If no offload is available the existing software triggered buffer path is used unchanged. Both CNV Burst Mode and Manual Mode support offload, but use different trigger mechanisms: CNV Burst Mode: the SPI Engine is triggered by the ADC's DATA_READY signal on the GP pin specified by the trigger-source consumer reference in the device tree (one cell =3D GP pin number 0-3). For this mode the driver acts as both an SPI offload consumer (DMA RX stream, message optimization) and a trigger source provider: it registers the GP/DATA_READY output via devm_spi_offload_trigger_register() so the offload framework can match the '#trigger-source-cells' phandle and automatically fire the SPI Engine DMA transfer at end-of-conversion. Manual Mode: the SPI Engine is triggered by a periodic trigger at the configured sampling frequency. The pre-built SPI message uses the pipelined CNV-on-CS protocol: N+1 16-bit transfers are issued for N active channels (the first result is discarded as garbage from the pipeline flush) and the remaining N results are captured by DMA. All offload transfers use 16-bit frames (bits_per_word=3D16, len=3D2). The channel scan_type (storagebits=3D16, shift=3D0, IIO_BE) is shared between the software triggered-buffer and offload paths; no separate scan_type or channel array is needed for the offload case. The ad4691_manual_channels[] array introduced in the triggered-buffer commit is reused here: it hides the IIO_CHAN_INFO_OVERSAMPLING_RATIO attribute, which is not applicable in Manual Mode. Kconfig gains a dependency on IIO_BUFFER_DMAENGINE. Signed-off-by: Radu Sabau --- drivers/iio/adc/Kconfig | 2 + drivers/iio/adc/ad4691.c | 398 +++++++++++++++++++++++++++++++++++++++++++= +++- 2 files changed, 395 insertions(+), 5 deletions(-) diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index d498f16c0816..fdc6565933c5 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -143,8 +143,10 @@ config AD4691 tristate "Analog Devices AD4691 Family ADC Driver" depends on SPI select IIO_BUFFER + select IIO_BUFFER_DMAENGINE select IIO_TRIGGERED_BUFFER select REGMAP + select SPI_OFFLOAD help Say yes here to build support for Analog Devices AD4691 Family MuxSAR SPI analog to digital converters (ADC). diff --git a/drivers/iio/adc/ad4691.c b/drivers/iio/adc/ad4691.c index 3e5caa0972eb..839ea7f44c78 100644 --- a/drivers/iio/adc/ad4691.c +++ b/drivers/iio/adc/ad4691.c @@ -22,6 +22,8 @@ #include #include #include +#include +#include #include #include =20 @@ -43,6 +45,11 @@ =20 #define AD4691_CNV_DUTY_CYCLE_NS 380 #define AD4691_CNV_HIGH_TIME_NS 430 +/* + * Conservative default for the manual offload periodic trigger. Low enough + * to work safely out of the box across all OSR and channel count combinat= ions. + */ +#define AD4691_OFFLOAD_INITIAL_TRIGGER_HZ (100 * HZ_PER_KHZ) =20 #define AD4691_SPI_CONFIG_A_REG 0x000 #define AD4691_SW_RESET (BIT(7) | BIT(0)) @@ -95,6 +102,8 @@ #define AD4691_ACC_IN(n) (0x252 + (3 * (n))) #define AD4691_ACC_STS_DATA(n) (0x283 + (4 * (n))) =20 +#define AD4691_OFFLOAD_BITS_PER_WORD 16 + static const char * const ad4691_supplies[] =3D { "avdd", "vio" }; =20 enum ad4691_ref_ctrl { @@ -114,6 +123,7 @@ struct ad4691_chip_info { const char *name; unsigned int max_rate; const struct ad4691_channel_info *sw_info; + const struct ad4691_channel_info *offload_info; }; =20 #define AD4691_CHANNEL(ch) \ @@ -177,6 +187,18 @@ static const struct ad4691_channel_info ad4693_sw_info= =3D { .num_channels =3D ARRAY_SIZE(ad4693_channels), }; =20 +static const struct ad4691_channel_info ad4691_offload_info =3D { + .channels =3D ad4691_channels, + /* No soft timestamp; num_channels caps access to 16. */ + .num_channels =3D 16, +}; + +static const struct ad4691_channel_info ad4693_offload_info =3D { + .channels =3D ad4693_channels, + /* No soft timestamp; num_channels caps access to 8. */ + .num_channels =3D 8, +}; + /* * Internal oscillator frequency table. Index is the OSC_FREQ_REG[3:0] val= ue. * Index 0 (1 MHz) is only valid for AD4692/AD4694; AD4691/AD4693 support @@ -207,24 +229,36 @@ static const struct ad4691_chip_info ad4691_chip_info= =3D { .name =3D "ad4691", .max_rate =3D 500 * HZ_PER_KHZ, .sw_info =3D &ad4691_sw_info, + .offload_info =3D &ad4691_offload_info, }; =20 static const struct ad4691_chip_info ad4692_chip_info =3D { .name =3D "ad4692", .max_rate =3D 1 * HZ_PER_MHZ, .sw_info =3D &ad4691_sw_info, + .offload_info =3D &ad4691_offload_info, }; =20 static const struct ad4691_chip_info ad4693_chip_info =3D { .name =3D "ad4693", .max_rate =3D 500 * HZ_PER_KHZ, .sw_info =3D &ad4693_sw_info, + .offload_info =3D &ad4693_offload_info, }; =20 static const struct ad4691_chip_info ad4694_chip_info =3D { .name =3D "ad4694", .max_rate =3D 1 * HZ_PER_MHZ, .sw_info =3D &ad4693_sw_info, + .offload_info =3D &ad4693_offload_info, +}; + +struct ad4691_offload_state { + struct spi_offload *spi; + struct spi_offload_trigger *trigger; + u64 trigger_hz; + u8 tx_cmd[17][2]; + u8 tx_reset[4]; }; =20 struct ad4691_state { @@ -253,7 +287,10 @@ struct ad4691_state { * transfers in one go. */ struct spi_message scan_msg; - /* max 16 + 1 NOOP (manual) or 2*16 + 2 (CNV burst). */ + /* + * Non-offload: max 16 + 1 NOOP (manual) or 2*16 + 2 (CNV burst). + * Offload reuses this array =E2=80=94 both paths are mutually exclusive. + */ struct spi_transfer scan_xfers[34]; /* * CNV burst: 16 AVG_IN addresses + state-reset address + state-reset @@ -265,6 +302,8 @@ struct ad4691_state { __be16 vals[16]; aligned_s64 ts; } scan; + /* NULL when no SPI offload hardware is present */ + struct ad4691_offload_state *offload; }; =20 /* @@ -284,6 +323,46 @@ static int ad4691_gpio_setup(struct ad4691_state *st, = unsigned int gp_num) AD4691_GP_MODE_DATA_READY << shift); } =20 +static const struct spi_offload_config ad4691_offload_config =3D { + .capability_flags =3D SPI_OFFLOAD_CAP_TRIGGER | + SPI_OFFLOAD_CAP_RX_STREAM_DMA, +}; + +static bool ad4691_offload_trigger_match(struct spi_offload_trigger *trigg= er, + enum spi_offload_trigger_type type, + u64 *args, u32 nargs) +{ + return type =3D=3D SPI_OFFLOAD_TRIGGER_DATA_READY && + nargs =3D=3D 1 && args[0] <=3D 3; +} + +static int ad4691_offload_trigger_request(struct spi_offload_trigger *trig= ger, + enum spi_offload_trigger_type type, + u64 *args, u32 nargs) +{ + struct ad4691_state *st =3D spi_offload_trigger_get_priv(trigger); + + if (nargs !=3D 1) + return -EINVAL; + + return ad4691_gpio_setup(st, args[0]); +} + +static int ad4691_offload_trigger_validate(struct spi_offload_trigger *tri= gger, + struct spi_offload_trigger_config *config) +{ + if (config->type !=3D SPI_OFFLOAD_TRIGGER_DATA_READY) + return -EINVAL; + + return 0; +} + +static const struct spi_offload_trigger_ops ad4691_offload_trigger_ops =3D= { + .match =3D ad4691_offload_trigger_match, + .request =3D ad4691_offload_trigger_request, + .validate =3D ad4691_offload_trigger_validate, +}; + static int ad4691_reg_read(void *context, unsigned int reg, unsigned int *= val) { struct spi_device *spi =3D context; @@ -807,6 +886,214 @@ static const struct iio_buffer_setup_ops ad4691_cnv_b= urst_buffer_setup_ops =3D { .postdisable =3D &ad4691_cnv_burst_buffer_postdisable, }; =20 +static int ad4691_manual_offload_buffer_postenable(struct iio_dev *indio_d= ev) +{ + struct ad4691_state *st =3D iio_priv(indio_dev); + struct ad4691_offload_state *offload =3D st->offload; + struct device *dev =3D regmap_get_device(st->regmap); + struct spi_device *spi =3D to_spi_device(dev); + struct spi_offload_trigger_config config =3D { + .type =3D SPI_OFFLOAD_TRIGGER_PERIODIC, + }; + unsigned int bit, k; + int ret; + + ret =3D ad4691_enter_conversion_mode(st); + if (ret) + return ret; + + memset(st->scan_xfers, 0, sizeof(st->scan_xfers)); + + /* + * N+1 transfers for N channels. Each CS-low period triggers + * a conversion AND returns the previous result (pipelined). + * TX: [AD4691_ADC_CHAN(n), 0x00] + * RX: [data_hi, data_lo] (storagebits=3D16, shift=3D0) + * Transfer 0 RX is garbage; transfers 1..N carry real data. + */ + k =3D 0; + iio_for_each_active_channel(indio_dev, bit) { + offload->tx_cmd[k][0] =3D AD4691_ADC_CHAN(bit); + st->scan_xfers[k].tx_buf =3D offload->tx_cmd[k]; + st->scan_xfers[k].len =3D sizeof(offload->tx_cmd[k]); + st->scan_xfers[k].bits_per_word =3D AD4691_OFFLOAD_BITS_PER_WORD; + st->scan_xfers[k].cs_change =3D 1; + st->scan_xfers[k].cs_change_delay.value =3D AD4691_CNV_HIGH_TIME_NS; + st->scan_xfers[k].cs_change_delay.unit =3D SPI_DELAY_UNIT_NSECS; + /* First transfer RX is garbage =E2=80=94 skip it. */ + if (k > 0) + st->scan_xfers[k].offload_flags =3D SPI_OFFLOAD_XFER_RX_STREAM; + k++; + } + + /* Final NOOP to flush pipeline and capture last channel. */ + offload->tx_cmd[k][0] =3D AD4691_NOOP; + st->scan_xfers[k].tx_buf =3D offload->tx_cmd[k]; + st->scan_xfers[k].len =3D sizeof(offload->tx_cmd[k]); + st->scan_xfers[k].bits_per_word =3D AD4691_OFFLOAD_BITS_PER_WORD; + st->scan_xfers[k].offload_flags =3D SPI_OFFLOAD_XFER_RX_STREAM; + k++; + + spi_message_init_with_transfers(&st->scan_msg, st->scan_xfers, k); + st->scan_msg.offload =3D offload->spi; + + ret =3D spi_optimize_message(spi, &st->scan_msg); + if (ret) + goto err_exit_conversion; + + config.periodic.frequency_hz =3D offload->trigger_hz; + ret =3D spi_offload_trigger_enable(offload->spi, offload->trigger, &confi= g); + if (ret) + goto err_unoptimize; + + return 0; + +err_unoptimize: + spi_unoptimize_message(&st->scan_msg); +err_exit_conversion: + ad4691_exit_conversion_mode(st); + return ret; +} + +static int ad4691_manual_offload_buffer_predisable(struct iio_dev *indio_d= ev) +{ + struct ad4691_state *st =3D iio_priv(indio_dev); + struct ad4691_offload_state *offload =3D st->offload; + + spi_offload_trigger_disable(offload->spi, offload->trigger); + spi_unoptimize_message(&st->scan_msg); + + return ad4691_exit_conversion_mode(st); +} + +static const struct iio_buffer_setup_ops ad4691_manual_offload_buffer_setu= p_ops =3D { + .postenable =3D &ad4691_manual_offload_buffer_postenable, + .predisable =3D &ad4691_manual_offload_buffer_predisable, +}; + +static int ad4691_cnv_burst_offload_buffer_postenable(struct iio_dev *indi= o_dev) +{ + struct ad4691_state *st =3D iio_priv(indio_dev); + struct ad4691_offload_state *offload =3D st->offload; + struct device *dev =3D regmap_get_device(st->regmap); + struct spi_device *spi =3D to_spi_device(dev); + struct spi_offload_trigger_config config =3D { + .type =3D SPI_OFFLOAD_TRIGGER_DATA_READY, + }; + unsigned int n_active; + unsigned int bit, k; + int ret; + + n_active =3D bitmap_weight(indio_dev->active_scan_mask, iio_get_masklengt= h(indio_dev)); + + ret =3D regmap_write(st->regmap, AD4691_STD_SEQ_CONFIG, + bitmap_read(indio_dev->active_scan_mask, 0, + iio_get_masklength(indio_dev))); + if (ret) + return ret; + + ret =3D regmap_write(st->regmap, AD4691_ACC_MASK_REG, + ~bitmap_read(indio_dev->active_scan_mask, 0, + iio_get_masklength(indio_dev)) & GENMASK(15, 0)); + if (ret) + return ret; + + ret =3D ad4691_enter_conversion_mode(st); + if (ret) + return ret; + + memset(st->scan_xfers, 0, sizeof(st->scan_xfers)); + + /* + * Each AVG_IN register read uses two 16-bit transfers: + * TX: [reg_hi | 0x80, reg_lo] (address, CS stays asserted) + * RX: [data_hi, data_lo] (data, storagebits=3D16, shift=3D0) + * The state reset is also split into two 16-bit transfers + * (address then value) to keep bits_per_word uniform throughout. + */ + k =3D 0; + iio_for_each_active_channel(indio_dev, bit) { + put_unaligned_be16(0x8000 | AD4691_AVG_IN(bit), offload->tx_cmd[k]); + + /* TX: address phase, CS stays asserted into data phase */ + st->scan_xfers[2 * k].tx_buf =3D offload->tx_cmd[k]; + st->scan_xfers[2 * k].len =3D sizeof(offload->tx_cmd[k]); + st->scan_xfers[2 * k].bits_per_word =3D AD4691_OFFLOAD_BITS_PER_WORD; + + /* RX: data phase, CS toggles after to delimit the next register op */ + st->scan_xfers[2 * k + 1].len =3D sizeof(offload->tx_cmd[k]); + st->scan_xfers[2 * k + 1].bits_per_word =3D AD4691_OFFLOAD_BITS_PER_WORD; + st->scan_xfers[2 * k + 1].offload_flags =3D SPI_OFFLOAD_XFER_RX_STREAM; + st->scan_xfers[2 * k + 1].cs_change =3D 1; + k++; + } + + /* State reset to re-arm DATA_READY for the next scan. */ + put_unaligned_be16(AD4691_STATE_RESET_REG, offload->tx_reset); + offload->tx_reset[2] =3D AD4691_STATE_RESET_ALL; + + st->scan_xfers[2 * k].tx_buf =3D offload->tx_reset; + st->scan_xfers[2 * k].len =3D sizeof(offload->tx_cmd[k]); + st->scan_xfers[2 * k].bits_per_word =3D AD4691_OFFLOAD_BITS_PER_WORD; + + st->scan_xfers[2 * k + 1].tx_buf =3D &offload->tx_reset[2]; + st->scan_xfers[2 * k + 1].len =3D sizeof(offload->tx_cmd[k]); + st->scan_xfers[2 * k + 1].bits_per_word =3D AD4691_OFFLOAD_BITS_PER_WORD; + st->scan_xfers[2 * k + 1].cs_change =3D 1; + + spi_message_init_with_transfers(&st->scan_msg, st->scan_xfers, 2 * k + 2); + st->scan_msg.offload =3D offload->spi; + + ret =3D spi_optimize_message(spi, &st->scan_msg); + if (ret) + goto err_exit_conversion; + + ret =3D ad4691_sampling_enable(st, true); + if (ret) + goto err_unoptimize; + + ret =3D spi_offload_trigger_enable(offload->spi, offload->trigger, &confi= g); + if (ret) + goto err_sampling_disable; + + return 0; + +err_sampling_disable: + ad4691_sampling_enable(st, false); +err_unoptimize: + spi_unoptimize_message(&st->scan_msg); +err_exit_conversion: + ad4691_exit_conversion_mode(st); + return ret; +} + +static int ad4691_cnv_burst_offload_buffer_predisable(struct iio_dev *indi= o_dev) +{ + struct ad4691_state *st =3D iio_priv(indio_dev); + struct ad4691_offload_state *offload =3D st->offload; + int ret; + + spi_offload_trigger_disable(offload->spi, offload->trigger); + + ret =3D ad4691_sampling_enable(st, false); + if (ret) + return ret; + + ret =3D regmap_write(st->regmap, AD4691_STD_SEQ_CONFIG, + AD4691_SEQ_ALL_CHANNELS_OFF); + if (ret) + return ret; + + spi_unoptimize_message(&st->scan_msg); + + return ad4691_exit_conversion_mode(st); +} + +static const struct iio_buffer_setup_ops ad4691_cnv_burst_offload_buffer_s= etup_ops =3D { + .postenable =3D &ad4691_cnv_burst_offload_buffer_postenable, + .predisable =3D &ad4691_cnv_burst_offload_buffer_predisable, +}; + static ssize_t sampling_frequency_show(struct device *dev, struct device_attribute *attr, char *buf) @@ -814,7 +1101,10 @@ static ssize_t sampling_frequency_show(struct device = *dev, struct iio_dev *indio_dev =3D dev_to_iio_dev(dev); struct ad4691_state *st =3D iio_priv(indio_dev); =20 - return sysfs_emit(buf, "%u\n", NSEC_PER_SEC / st->cnv_period_ns); + if (st->manual_mode && st->offload) + return sysfs_emit(buf, "%llu\n", st->offload->trigger_hz); + + return sysfs_emit(buf, "%lu\n", NSEC_PER_SEC / st->cnv_period_ns); } =20 static ssize_t sampling_frequency_store(struct device *dev, @@ -833,6 +1123,23 @@ static ssize_t sampling_frequency_store(struct device= *dev, if (ret) return ret; =20 + if (st->manual_mode && st->offload) { + struct spi_offload_trigger_config config =3D { + .type =3D SPI_OFFLOAD_TRIGGER_PERIODIC, + .periodic =3D { .frequency_hz =3D freq }, + }; + + ret =3D spi_offload_trigger_validate(st->offload->trigger, &config); + if (ret) { + iio_device_release_direct(indio_dev); + return ret; + } + + st->offload->trigger_hz =3D config.periodic.frequency_hz; + iio_device_release_direct(indio_dev); + return len; + } + ret =3D ad4691_set_pwm_freq(st, freq); iio_device_release_direct(indio_dev); if (ret) @@ -1132,9 +1439,75 @@ static int ad4691_setup_triggered_buffer(struct iio_= dev *indio_dev, ad4691_buffer_attrs); } =20 +static int ad4691_setup_offload(struct iio_dev *indio_dev, + struct ad4691_state *st, + struct spi_offload *spi_offload) +{ + struct device *dev =3D regmap_get_device(st->regmap); + struct ad4691_offload_state *offload; + struct dma_chan *rx_dma; + int ret; + + offload =3D devm_kzalloc(dev, sizeof(*offload), GFP_KERNEL); + if (!offload) + return -ENOMEM; + + offload->spi =3D spi_offload; + st->offload =3D offload; + + if (st->manual_mode) { + offload->trigger =3D + devm_spi_offload_trigger_get(dev, offload->spi, + SPI_OFFLOAD_TRIGGER_PERIODIC); + if (IS_ERR(offload->trigger)) + return dev_err_probe(dev, PTR_ERR(offload->trigger), + "Failed to get periodic offload trigger\n"); + + offload->trigger_hz =3D AD4691_OFFLOAD_INITIAL_TRIGGER_HZ; + } else { + struct spi_offload_trigger_info trigger_info =3D { + .fwnode =3D dev_fwnode(dev), + .ops =3D &ad4691_offload_trigger_ops, + .priv =3D st, + }; + + ret =3D devm_spi_offload_trigger_register(dev, &trigger_info); + if (ret) + return dev_err_probe(dev, ret, + "Failed to register offload trigger\n"); + + offload->trigger =3D + devm_spi_offload_trigger_get(dev, offload->spi, + SPI_OFFLOAD_TRIGGER_DATA_READY); + if (IS_ERR(offload->trigger)) + return dev_err_probe(dev, PTR_ERR(offload->trigger), + "Failed to get DATA_READY offload trigger\n"); + } + + rx_dma =3D devm_spi_offload_rx_stream_request_dma_chan(dev, offload->spi); + if (IS_ERR(rx_dma)) + return dev_err_probe(dev, PTR_ERR(rx_dma), + "Failed to get offload RX DMA channel\n"); + + if (st->manual_mode) + indio_dev->setup_ops =3D &ad4691_manual_offload_buffer_setup_ops; + else + indio_dev->setup_ops =3D &ad4691_cnv_burst_offload_buffer_setup_ops; + + ret =3D devm_iio_dmaengine_buffer_setup_with_handle(dev, indio_dev, rx_dm= a, + IIO_BUFFER_DIRECTION_IN); + if (ret) + return ret; + + indio_dev->buffer->attrs =3D ad4691_buffer_attrs; + + return 0; +} + static int ad4691_probe(struct spi_device *spi) { struct device *dev =3D &spi->dev; + struct spi_offload *spi_offload; struct iio_dev *indio_dev; struct ad4691_state *st; int ret; @@ -1168,13 +1541,26 @@ static int ad4691_probe(struct spi_device *spi) if (ret) return ret; =20 + spi_offload =3D devm_spi_offload_get(dev, spi, &ad4691_offload_config); + ret =3D PTR_ERR_OR_ZERO(spi_offload); + if (ret =3D=3D -ENODEV) + spi_offload =3D NULL; + else if (ret) + return dev_err_probe(dev, ret, "Failed to get SPI offload\n"); + indio_dev->name =3D st->info->name; indio_dev->info =3D &ad4691_info; indio_dev->modes =3D INDIO_DIRECT_MODE; =20 - indio_dev->channels =3D st->info->sw_info->channels; - indio_dev->num_channels =3D st->info->sw_info->num_channels; - ret =3D ad4691_setup_triggered_buffer(indio_dev, st); + if (spi_offload) { + indio_dev->channels =3D st->info->offload_info->channels; + indio_dev->num_channels =3D st->info->offload_info->num_channels; + ret =3D ad4691_setup_offload(indio_dev, st, spi_offload); + } else { + indio_dev->channels =3D st->info->sw_info->channels; + indio_dev->num_channels =3D st->info->sw_info->num_channels; + ret =3D ad4691_setup_triggered_buffer(indio_dev, st); + } if (ret) return ret; =20 @@ -1212,3 +1598,5 @@ module_spi_driver(ad4691_driver); MODULE_AUTHOR("Radu Sabau "); MODULE_DESCRIPTION("Analog Devices AD4691 Family ADC Driver"); MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS("IIO_DMA_BUFFER"); +MODULE_IMPORT_NS("IIO_DMAENGINE_BUFFER"); --=20 2.43.0 From nobody Thu Apr 9 21:52:45 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7A0F73E0C7D; Thu, 9 Apr 2026 15:28:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260409-ad4692-multichannel-sar-adc-driver-v7-5-be375d4df2c5@analog.com> References: <20260409-ad4692-multichannel-sar-adc-driver-v7-0-be375d4df2c5@analog.com> In-Reply-To: <20260409-ad4692-multichannel-sar-adc-driver-v7-0-be375d4df2c5@analog.com> To: Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , David Lechner , =?utf-8?q?Nuno_S=C3=A1?= , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Liam Girdwood , Mark Brown , Linus Walleij , Bartosz Golaszewski , Philipp Zabel , Jonathan Corbet , Shuah Khan Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pwm@vger.kernel.org, linux-gpio@vger.kernel.org, linux-doc@vger.kernel.org, Radu Sabau X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1775748505; l=9894; i=radu.sabau@analog.com; s=20260220; h=from:subject:message-id; bh=eB6uvSJZMwxlszpLMEXiVdwqo2+1DAbz0m1ETwwp1E8=; b=Q9j9fNUH+gyIVtPhmTXEJpOmAQAIZwPDs3DvcRhKK3vjvmaqorlbeSfKFkBOsWJcG4pAwxb5U ENfshks7CfnBUWaVta7dRxuHpc0ypqzrtQRNwA4SpgDL2BydQYuRE81 X-Developer-Key: i=radu.sabau@analog.com; a=ed25519; pk=lDPQHgn9jTdt0vo58Na9lLxLaE2mb330if71Cn+EvFU= X-Endpoint-Received: by B4 Relay for radu.sabau@analog.com/20260220 with auth_id=642 X-Original-From: Radu Sabau Reply-To: radu.sabau@analog.com From: Radu Sabau Add per-channel oversampling ratio (OSR) support for CNV burst mode. The accumulator depth register (ACC_DEPTH_IN) is programmed with the selected OSR at buffer enable time and before each single-shot read. Supported OSR values: 1, 2, 4, 8, 16, 32. Introduce AD4691_MANUAL_CHANNEL() for manual mode channels, which do not expose the oversampling ratio attribute since OSR is not applicable in that mode. A separate manual_channels array is added to struct ad4691_channel_info and selected at probe time; offload paths reuse the same arrays with num_channels capping access before the soft timestamp entry. The reported sampling frequency accounts for the active OSR: effective_freq =3D oscillator_freq / osr OSR defaults to 1 (no accumulation) for all channels. Signed-off-by: Radu Sabau --- drivers/iio/adc/ad4691.c | 137 +++++++++++++++++++++++++++++++++++++++++++= ---- 1 file changed, 128 insertions(+), 9 deletions(-) diff --git a/drivers/iio/adc/ad4691.c b/drivers/iio/adc/ad4691.c index 839ea7f44c78..ef96d736996e 100644 --- a/drivers/iio/adc/ad4691.c +++ b/drivers/iio/adc/ad4691.c @@ -116,6 +116,7 @@ enum ad4691_ref_ctrl { =20 struct ad4691_channel_info { const struct iio_chan_spec *channels; + const struct iio_chan_spec *manual_channels; unsigned int num_channels; }; =20 @@ -126,7 +127,34 @@ struct ad4691_chip_info { const struct ad4691_channel_info *offload_info; }; =20 +/* CNV burst mode channel =E2=80=94 exposes oversampling ratio. */ #define AD4691_CHANNEL(ch) \ + { \ + .type =3D IIO_VOLTAGE, \ + .indexed =3D 1, \ + .info_mask_separate =3D BIT(IIO_CHAN_INFO_RAW) | \ + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO) | \ + BIT(IIO_CHAN_INFO_SAMP_FREQ), \ + .info_mask_separate_available =3D \ + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO) | \ + BIT(IIO_CHAN_INFO_SAMP_FREQ), \ + .info_mask_shared_by_all =3D BIT(IIO_CHAN_INFO_SCALE), \ + .channel =3D ch, \ + .scan_index =3D ch, \ + .scan_type =3D { \ + .sign =3D 'u', \ + .realbits =3D 16, \ + .storagebits =3D 16, \ + .endianness =3D IIO_BE, \ + }, \ + } + +/* + * Manual mode channel =E2=80=94 no oversampling ratio attribute. OSR is n= ot + * supported in manual mode; ACC_DEPTH_IN is not configured during manual + * buffer enable. + */ +#define AD4691_MANUAL_CHANNEL(ch) \ { \ .type =3D IIO_VOLTAGE, \ .indexed =3D 1, \ @@ -177,25 +205,65 @@ static const struct iio_chan_spec ad4693_channels[] = =3D { IIO_CHAN_SOFT_TIMESTAMP(8), }; =20 +static const struct iio_chan_spec ad4691_manual_channels[] =3D { + AD4691_MANUAL_CHANNEL(0), + AD4691_MANUAL_CHANNEL(1), + AD4691_MANUAL_CHANNEL(2), + AD4691_MANUAL_CHANNEL(3), + AD4691_MANUAL_CHANNEL(4), + AD4691_MANUAL_CHANNEL(5), + AD4691_MANUAL_CHANNEL(6), + AD4691_MANUAL_CHANNEL(7), + AD4691_MANUAL_CHANNEL(8), + AD4691_MANUAL_CHANNEL(9), + AD4691_MANUAL_CHANNEL(10), + AD4691_MANUAL_CHANNEL(11), + AD4691_MANUAL_CHANNEL(12), + AD4691_MANUAL_CHANNEL(13), + AD4691_MANUAL_CHANNEL(14), + AD4691_MANUAL_CHANNEL(15), + IIO_CHAN_SOFT_TIMESTAMP(16), +}; + +static const struct iio_chan_spec ad4693_manual_channels[] =3D { + AD4691_MANUAL_CHANNEL(0), + AD4691_MANUAL_CHANNEL(1), + AD4691_MANUAL_CHANNEL(2), + AD4691_MANUAL_CHANNEL(3), + AD4691_MANUAL_CHANNEL(4), + AD4691_MANUAL_CHANNEL(5), + AD4691_MANUAL_CHANNEL(6), + AD4691_MANUAL_CHANNEL(7), + IIO_CHAN_SOFT_TIMESTAMP(8), +}; + +static const int ad4691_oversampling_ratios[] =3D { 1, 2, 4, 8, 16, 32 }; + static const struct ad4691_channel_info ad4691_sw_info =3D { .channels =3D ad4691_channels, + .manual_channels =3D ad4691_manual_channels, .num_channels =3D ARRAY_SIZE(ad4691_channels), }; =20 static const struct ad4691_channel_info ad4693_sw_info =3D { .channels =3D ad4693_channels, + .manual_channels =3D ad4693_manual_channels, .num_channels =3D ARRAY_SIZE(ad4693_channels), }; =20 static const struct ad4691_channel_info ad4691_offload_info =3D { .channels =3D ad4691_channels, - /* No soft timestamp; num_channels caps access to 16. */ + /* + * Offload paths share the SW channel arrays. num_channels caps access + * before the soft timestamp entry, so no separate array is needed. + */ + .manual_channels =3D ad4691_manual_channels, .num_channels =3D 16, }; =20 static const struct ad4691_channel_info ad4693_offload_info =3D { .channels =3D ad4693_channels, - /* No soft timestamp; num_channels caps access to 8. */ + .manual_channels =3D ad4693_manual_channels, .num_channels =3D 8, }; =20 @@ -270,6 +338,8 @@ struct ad4691_state { int irq; int vref_uV; u32 cnv_period_ns; + /* Per-channel oversampling ratio; always 1 in manual mode. */ + u8 osr[16]; =20 bool manual_mode; bool refbuf_en; @@ -490,7 +560,8 @@ static const struct regmap_config ad4691_regmap_config = =3D { .cache_type =3D REGCACHE_MAPLE, }; =20 -static int ad4691_get_sampling_freq(struct ad4691_state *st, int *val) +static int ad4691_get_sampling_freq(struct ad4691_state *st, int *val, + unsigned int osr) { unsigned int reg_val; int ret; @@ -499,7 +570,7 @@ static int ad4691_get_sampling_freq(struct ad4691_state= *st, int *val) if (ret) return ret; =20 - *val =3D ad4691_osc_freqs_Hz[FIELD_GET(AD4691_OSC_FREQ_MASK, reg_val)]; + *val =3D ad4691_osc_freqs_Hz[FIELD_GET(AD4691_OSC_FREQ_MASK, reg_val)] / = osr; return IIO_VAL_INT; } =20 @@ -536,6 +607,11 @@ static int ad4691_read_avail(struct iio_dev *indio_dev, *type =3D IIO_VAL_INT; *length =3D ARRAY_SIZE(ad4691_osc_freqs_Hz) - start; return IIO_AVAIL_LIST; + case IIO_CHAN_INFO_OVERSAMPLING_RATIO: + *vals =3D ad4691_oversampling_ratios; + *type =3D IIO_VAL_INT; + *length =3D ARRAY_SIZE(ad4691_oversampling_ratios); + return IIO_AVAIL_LIST; default: return -EINVAL; } @@ -566,6 +642,11 @@ static int ad4691_single_shot_read(struct iio_dev *ind= io_dev, if (ret) return ret; =20 + ret =3D regmap_write(st->regmap, AD4691_ACC_DEPTH_IN(chan->channel), + st->osr[chan->channel]); + if (ret) + return ret; + ret =3D regmap_read(st->regmap, AD4691_OSC_FREQ_REG, ®_val); if (ret) return ret; @@ -575,8 +656,9 @@ static int ad4691_single_shot_read(struct iio_dev *indi= o_dev, return ret; =20 osc_idx =3D FIELD_GET(AD4691_OSC_FREQ_MASK, reg_val); - /* Wait 2 oscillator periods for the conversion to complete. */ - period_us =3D DIV_ROUND_UP(2UL * USEC_PER_SEC, ad4691_osc_freqs_Hz[osc_id= x]); + /* Wait osr oscillator periods for all accumulator samples to complete. */ + period_us =3D DIV_ROUND_UP((unsigned long)st->osr[chan->channel] * USEC_P= ER_SEC, + ad4691_osc_freqs_Hz[osc_idx]); fsleep(period_us); =20 ret =3D regmap_write(st->regmap, AD4691_OSC_EN_REG, 0); @@ -611,7 +693,10 @@ static int ad4691_read_raw(struct iio_dev *indio_dev, return ad4691_single_shot_read(indio_dev, chan, val); } case IIO_CHAN_INFO_SAMP_FREQ: - return ad4691_get_sampling_freq(st, val); + return ad4691_get_sampling_freq(st, val, st->osr[chan->channel]); + case IIO_CHAN_INFO_OVERSAMPLING_RATIO: + *val =3D st->osr[chan->channel]; + return IIO_VAL_INT; case IIO_CHAN_INFO_SCALE: *val =3D st->vref_uV / (MICRO / MILLI); *val2 =3D chan->scan_type.realbits; @@ -625,9 +710,24 @@ static int ad4691_write_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int val, int val2, long mask) { + struct ad4691_state *st =3D iio_priv(indio_dev); + switch (mask) { case IIO_CHAN_INFO_SAMP_FREQ: return ad4691_set_sampling_freq(indio_dev, val); + case IIO_CHAN_INFO_OVERSAMPLING_RATIO: { + IIO_DEV_ACQUIRE_DIRECT_MODE(indio_dev, claim); + if (IIO_DEV_ACQUIRE_FAILED(claim)) + return -EBUSY; + + for (unsigned int i =3D 0; i < ARRAY_SIZE(ad4691_oversampling_ratios); i= ++) { + if (ad4691_oversampling_ratios[i] !=3D val) + continue; + st->osr[chan->channel] =3D val; + return 0; + } + return -EINVAL; + } default: return -EINVAL; } @@ -842,6 +942,12 @@ static int ad4691_cnv_burst_buffer_preenable(struct ii= o_dev *indio_dev) if (ret) goto err_unoptimize; =20 + iio_for_each_active_channel(indio_dev, i) { + ret =3D regmap_write(st->regmap, AD4691_ACC_DEPTH_IN(i), st->osr[i]); + if (ret) + goto err_unoptimize; + } + ret =3D ad4691_enter_conversion_mode(st); if (ret) goto err_unoptimize; @@ -998,6 +1104,12 @@ static int ad4691_cnv_burst_offload_buffer_postenable= (struct iio_dev *indio_dev) if (ret) return ret; =20 + iio_for_each_active_channel(indio_dev, bit) { + ret =3D regmap_write(st->regmap, AD4691_ACC_DEPTH_IN(bit), st->osr[bit]); + if (ret) + return ret; + } + ret =3D ad4691_enter_conversion_mode(st); if (ret) return ret; @@ -1519,6 +1631,7 @@ static int ad4691_probe(struct spi_device *spi) st =3D iio_priv(indio_dev); st->spi =3D spi; st->info =3D spi_get_device_match_data(spi); + memset(st->osr, 1, sizeof(st->osr)); =20 ret =3D devm_mutex_init(dev, &st->lock); if (ret) @@ -1553,11 +1666,17 @@ static int ad4691_probe(struct spi_device *spi) indio_dev->modes =3D INDIO_DIRECT_MODE; =20 if (spi_offload) { - indio_dev->channels =3D st->info->offload_info->channels; + if (st->manual_mode) + indio_dev->channels =3D st->info->offload_info->manual_channels; + else + indio_dev->channels =3D st->info->offload_info->channels; indio_dev->num_channels =3D st->info->offload_info->num_channels; ret =3D ad4691_setup_offload(indio_dev, st, spi_offload); } else { - indio_dev->channels =3D st->info->sw_info->channels; + if (st->manual_mode) + indio_dev->channels =3D st->info->sw_info->manual_channels; + else + indio_dev->channels =3D st->info->sw_info->channels; indio_dev->num_channels =3D st->info->sw_info->num_channels; ret =3D ad4691_setup_triggered_buffer(indio_dev, st); } --=20 2.43.0 From nobody Thu Apr 9 21:52:45 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 91D433E1215; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260409-ad4692-multichannel-sar-adc-driver-v7-6-be375d4df2c5@analog.com> References: <20260409-ad4692-multichannel-sar-adc-driver-v7-0-be375d4df2c5@analog.com> In-Reply-To: <20260409-ad4692-multichannel-sar-adc-driver-v7-0-be375d4df2c5@analog.com> To: Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , David Lechner , =?utf-8?q?Nuno_S=C3=A1?= , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Liam Girdwood , Mark Brown , Linus Walleij , Bartosz Golaszewski , Philipp Zabel , Jonathan Corbet , Shuah Khan Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pwm@vger.kernel.org, linux-gpio@vger.kernel.org, linux-doc@vger.kernel.org, Radu Sabau X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1775748505; l=13101; i=radu.sabau@analog.com; s=20260220; h=from:subject:message-id; bh=IptN2OXLuNKyo/j556/GPrsAWPRNvypfZxc/oV4K/08=; b=yxWNyMKAMFayikY2a8aPmPC4cimWIh1kYwt4nLnqEZ9DNF8VoWaaJarr5ZW6UCY0He4TzRChQ WrEhManA9QIBRGiv61DldWe7xEDDPeSa9eLlyz8yQ+vSnm6CaUtcPGM X-Developer-Key: i=radu.sabau@analog.com; a=ed25519; pk=lDPQHgn9jTdt0vo58Na9lLxLaE2mb330if71Cn+EvFU= X-Endpoint-Received: by B4 Relay for radu.sabau@analog.com/20260220 with auth_id=642 X-Original-From: Radu Sabau Reply-To: radu.sabau@analog.com From: Radu Sabau Add RST documentation for the AD4691 family ADC driver covering supported devices, IIO channels, operating modes, oversampling, reference voltage, LDO supply, reset, GP pins, SPI offload support, and buffer data format. Signed-off-by: Radu Sabau --- Documentation/iio/ad4691.rst | 283 +++++++++++++++++++++++++++++++++++++++= ++++ Documentation/iio/index.rst | 1 + MAINTAINERS | 1 + 3 files changed, 285 insertions(+) diff --git a/Documentation/iio/ad4691.rst b/Documentation/iio/ad4691.rst new file mode 100644 index 000000000000..a1012c8b78a3 --- /dev/null +++ b/Documentation/iio/ad4691.rst @@ -0,0 +1,283 @@ +.. SPDX-License-Identifier: GPL-2.0-only + +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +AD4691 driver +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +ADC driver for Analog Devices Inc. AD4691 family of multichannel SAR ADCs. +The module name is ``ad4691``. + + +Supported devices +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +The following chips are supported by this driver: + +* `AD4691 `_ =E2=80=94 16-= channel, 500 kSPS +* `AD4692 `_ =E2=80=94 16-= channel, 1 MSPS +* `AD4693 `_ =E2=80=94 8-c= hannel, 500 kSPS +* `AD4694 `_ =E2=80=94 8-c= hannel, 1 MSPS + + +IIO channels +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +Each physical ADC input maps to one IIO voltage channel. The AD4691 and AD= 4692 +expose 16 channels (``voltage0`` through ``voltage15``); the AD4693 and AD= 4694 +expose 8 channels (``voltage0`` through ``voltage7``). + +All channels share a common scale (``in_voltage_scale``), derived from the +reference voltage. Each channel independently exposes: + +* ``in_voltageN_raw`` =E2=80=94 single-shot ADC result +* ``in_voltageN_sampling_frequency`` =E2=80=94 per-channel effective conve= rsion rate. + In CNV Burst Mode this equals the internal oscillator frequency divided = by + the channel's oversampling ratio. In Manual Mode (where oversampling is = not + supported) it equals the oscillator frequency directly. +* ``in_voltageN_sampling_frequency_available`` =E2=80=94 list of valid osc= illator + frequencies + +The following attributes are only available in CNV Burst Mode: + +* ``in_voltageN_oversampling_ratio`` =E2=80=94 per-channel hardware accumu= lation depth +* ``in_voltageN_oversampling_ratio_available`` =E2=80=94 list of valid rat= ios: 1, 2, 4, + 8, 16, 32 + + +Operating modes +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +The driver supports two operating modes, auto-detected from the device tre= e at +probe time. Both modes transition to and from an internal Autonomous Mode = idle +state when the IIO buffer is enabled and disabled. + +Manual Mode +----------- + +Selected when no ``pwms`` property is present in the device tree. The CNV = pin +is tied to the SPI chip-select: every CS assertion both triggers a new +conversion and returns the result of the previous one (pipelined N+1 schem= e). + +To read N channels the driver issues N+1 SPI transfers in a single optimis= ed +message: + +* Transfers 0 to N-1 each carry ``AD4691_ADC_CHAN(n)`` in the TX byte to + select the next channel; the RX byte of transfer ``k+1`` contains the re= sult + of the channel selected in transfer ``k``. +* Transfer N is a NOOP (0x00) to flush the last conversion result out of t= he + pipeline. + +A user-defined IIO trigger (e.g. hrtimer trigger) drives the trigger handl= er, +which executes the pre-built SPI message and pushes the scan to the buffer. + +Oversampling is not supported in Manual Mode. + +CNV Burst Mode +-------------- + +Selected when a ``pwms`` property is present in the device tree. The PWM d= rives +the CNV pin independently of SPI at the configured conversion rate, and a = GP +pin (identified by ``interrupt-names``) asserts DATA_READY at end-of-burst= to +signal that the AVG_IN result registers are ready to be read. + +The IRQ handler fires the IIO trigger without stopping the PWM, then disab= les +itself to prevent a second DATA_READY assertion while the trigger handler = is +running. The trigger handler reads all active ``AVG_IN(n)`` registers in a +single optimised SPI message, pushes the scan to the buffer, and re-enables +the IRQ. + +The buffer sampling frequency (i.e. the PWM rate) is controlled by the +``sampling_frequency`` attribute on the IIO buffer. Valid values span from= the +chip's minimum oscillator rate up to its maximum conversion rate (500 kSPS= for +AD4691/AD4693, 1 MSPS for AD4692/AD4694). In practice, without SPI offload, +the SPI read overhead between DATA_READY and the start of the next PWM per= iod +limits the achievable rate; the PWM frequency should be set low enough to +accommodate the SPI transfer time. + +Autonomous Mode (idle / single-shot) +------------------------------------- + +The chip idles in Autonomous Mode whenever the IIO buffer is disabled. In = this +state, ``read_raw`` requests (``in_voltageN_raw``) use the internal oscill= ator +to perform a single conversion on the requested channel and read back the +result from the ``AVG_IN(N)`` register. The oscillator is started and stop= ped +for each read to save power. + + +Oversampling +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +In CNV Burst Mode each channel has an independent hardware accumulator +(ACC_DEPTH_IN) that averages a configurable number of successive conversio= ns +before DATA_READY asserts. The result is always returned as a 16-bit mean = from +the ``AVG_IN`` register, so the IIO ``realbits`` and ``storagebits`` are +unaffected by the oversampling ratio. + +Valid ratios are 1, 2, 4, 8, 16 and 32. The default is 1 (no averaging). +Oversampling is not supported in Manual Mode. + +.. code-block:: bash + + # Set oversampling ratio to 16 on channel 0 + echo 16 > /sys/bus/iio/devices/iio:device0/in_voltage0_oversampling_ra= tio + +When OSR > 1 the effective conversion rate reported by +``in_voltageN_sampling_frequency`` and used for ``read_raw`` is reduced +accordingly, since each output sample requires OSR successive conversions. + + +Reference voltage +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +The driver supports two reference configurations, mutually exclusive: + +* **External reference** (``ref-supply``): a voltage between 2.4 V and 5.2= 5 V + supplied externally. The internal reference buffer is disabled. +* **Buffered internal reference** (``refin-supply``): An internal reference + buffer is used. The driver enables ``REFBUF_EN`` in the REF_CTRL register + when this supply is used. + +Exactly one of ``ref-supply`` or ``refin-supply`` must be present in the +device tree. + +The reference voltage determines the full-scale range: + +.. code-block:: + + full-scale =3D Vref / 2^16 (per LSB) + + +LDO supply +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +The chip contains an internal LDO that powers part of the analog front-end. +The LDO input can be driven externally via the ``ldo-in-supply`` regulator= . If +that supply is absent, the driver enables the internal LDO path (``LDO_EN`` +bit in DEVICE_SETUP). + + +Reset +=3D=3D=3D=3D=3D + +The driver supports two reset mechanisms: + +* **Hardware reset** (``reset-gpios`` in device tree): the GPIO is already + asserted at driver probe by the reset controller framework. The driver w= aits + for the required 300 =C2=B5s reset pulse width and then deasserts. +* **Software reset** (fallback when ``reset-gpios`` is absent): the driver + writes the software-reset pattern to the SPI_CONFIG_A register. + + +GP pins and interrupts +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +The chip exposes up to four general-purpose (GP) pins that can be configur= ed as +interrupt or trigger-source outputs. In CNV Burst Mode (non-offload), one = GP +pin must be wired to an interrupt-capable SoC input and declared in the de= vice +tree using the ``interrupts`` and ``interrupt-names`` properties. + +The ``interrupt-names`` value identifies which GP pin is used (``"gp0"`` +through ``"gp3"``). The driver configures that pin as a DATA_READY output = in +the GPIO_MODE register. + +Example device tree fragment:: + + adc@0 { + compatible =3D "adi,ad4692"; + ... + interrupts =3D <17 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent =3D <&gpio0>; + interrupt-names =3D "gp0"; + }; + + +SPI offload support +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +When a SPI offload engine (e.g. the AXI SPI Engine) is present, the driver +uses DMA-backed transfers for CPU-independent, high-throughput data captur= e. +SPI offload is detected automatically at probe via ``devm_spi_offload_get(= )``; +if no offload hardware is available the driver falls back to the software +triggered-buffer path. + +Two SPI offload sub-modes exist, corresponding to the two operating modes: + +CNV Burst offload +----------------- + +Used when a ``pwms`` property is present and SPI offload is available. + +The PWM drives CNV at the configured rate. On DATA_READY the SPI offload +engine automatically executes a pre-built message that reads all active +``AVG_IN`` registers and streams the data directly to an IIO DMA buffer wi= th +no CPU involvement. A final state-reset transfer re-arms DATA_READY for the +next burst. + +The GP pin used as DATA_READY trigger is supplied by the trigger-source +consumer (via ``#trigger-source-cells``) at buffer enable time; no +``interrupt-names`` entry is required in this path. + +The buffer sampling frequency is controlled by the ``sampling_frequency`` +attribute on the IIO buffer (same as the non-offload CNV Burst path). + +Manual offload +-------------- + +Used when no ``pwms`` property is present and SPI offload is available. + +A periodic SPI offload trigger controls the conversion rate. On each trigg= er +period, the SPI engine executes an N+1 transfer message (same pipelined sc= heme +as software Manual Mode) and streams the 16-bit ADC results directly to the +IIO DMA buffer. Each transfer sends a 16-bit TX word (channel command byte= in +the upper byte, zero in the lower byte); the chip returns the 16-bit ADC +result on MISO. The first transfer's RX is discarded (pipeline flush); res= ults +from transfers 1 through N are streamed to the DMA buffer. + +The ``sampling_frequency`` attribute on the IIO buffer controls the trigger +rate (in Hz). The initial rate is 100 kHz =E2=80=94 a conservative default= chosen +because the N+1 SPI transfer overhead in this mode limits the achievable r= ate +relative to the chip's maximum conversion rate. + +Oversampling is not supported in Manual Mode. + + +Buffer data format +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +The IIO buffer data format (``in_voltageN_type``) is the same across all +paths: 16-bit unsigned big-endian samples with no shift. + ++-------------------------+-------------+----------+-------+ +| Path | storagebits | realbits | shift | ++=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D+=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D+=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D+= =3D=3D=3D=3D=3D=3D=3D+ +| Triggered buffer | 16 | 16 | 0 | ++-------------------------+-------------+----------+-------+ +| CNV Burst offload (DMA) | 16 | 16 | 0 | ++-------------------------+-------------+----------+-------+ +| Manual offload (DMA) | 16 | 16 | 0 | ++-------------------------+-------------+----------+-------+ + +In the triggered-buffer path the SPI rx_buf for each transfer points direc= tly +into the scan buffer, so the 16-bit big-endian result is written in place = with +no additional copying. + +In the DMA offload paths the SPI offload engine streams 16-bit words (one = per +active channel) directly into the IIO DMA buffer: + +* **CNV Burst offload**: each channel read uses a 16-bit address phase fol= lowed + by a 16-bit data phase; only the data phase is flagged for DMA streaming= , so + the 16-bit result lands directly in the buffer. +* **Manual offload**: each 16-bit SPI transfer carries the channel command= on + TX and receives the 16-bit ADC result on RX; results are streamed to the + DMA buffer one 16-bit word per channel. + +The ``in_voltageN_type`` sysfs attribute reflects the active scan type. + + +Unimplemented features +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +* GPIO controller functionality of the GP pins +* Clamp status and overrange events +* Raw accumulator (ACC_IN) and accumulator status registers +* ADC_BUSY and overrun status interrupts diff --git a/Documentation/iio/index.rst b/Documentation/iio/index.rst index ba3e609c6a13..007e0a1fcc5a 100644 --- a/Documentation/iio/index.rst +++ b/Documentation/iio/index.rst @@ -23,6 +23,7 @@ Industrial I/O Kernel Drivers ad4000 ad4030 ad4062 + ad4691 ad4695 ad7191 ad7380 diff --git a/MAINTAINERS b/MAINTAINERS index 24e4502b8292..819d8b6eb6bb 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1491,6 +1491,7 @@ S: Supported W: https://ez.analog.com/linux-software-drivers F: Documentation/devicetree/bindings/iio/adc/adi,ad4691.yaml F: drivers/iio/adc/ad4691.c +F: drivers/iio/adc/ad4691.rst =20 ANALOG DEVICES INC AD4695 DRIVER M: Michael Hennerich --=20 2.43.0