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Wed, 08 Apr 2026 02:49:01 -0700 (PDT) Received: from iku.Home ([2a06:5906:61b:2d00:98bc:78d2:5881:a11f]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43d1e4d58e5sm57689153f8f.23.2026.04.08.02.49.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Apr 2026 02:49:01 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Michael Turquette , Stephen Boyd , Geert Uytterhoeven Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH] clk: divider: Fix overflow in clk_divider_bestdiv() for large rate requests Date: Wed, 8 Apr 2026 10:48:14 +0100 Message-ID: <20260408094814.321072-1-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.53.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar clk_divider_bestdiv() clamps maxdiv using: maxdiv =3D min(ULONG_MAX / rate, maxdiv); to avoid overflow in rate * i. However requests like clk_round_rate(clk, ULONG_MAX), which are used to determine the maximum supported rate of a clock, result in maxdiv being clamped to 1. If no valid divider of 1 exists in the table the loop is never entered and bestdiv falls back to the maximum divider with the minimum parent rate, causing clk_round_rate(clk, ULONG_MAX) to incorrectly return the minimum supported rate instead of the maximum. Fix this by replacing the maxdiv clamping and the unprotected rate * i multiplications with check_mul_overflow(), clamping target_parent_rate to ULONG_MAX on overflow. This allows the loop to iterate all valid dividers regardless of the requested rate, and clk_hw_round_rate() with ULONG_MAX will correctly return the maximum supported parent rate. Signed-off-by: Lad Prabhakar --- drivers/clk/clk-divider.c | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c index 45e7ebde4a8b..dc486c2aa946 100644 --- a/drivers/clk/clk-divider.c +++ b/drivers/clk/clk-divider.c @@ -15,6 +15,7 @@ #include #include #include +#include =20 /* * DOC: basic adjustable divider clock that cannot gate @@ -301,6 +302,7 @@ static int clk_divider_bestdiv(struct clk_hw *hw, struc= t clk_hw *parent, int i, bestdiv =3D 0; unsigned long parent_rate, best =3D 0, now, maxdiv; unsigned long parent_rate_saved =3D *best_parent_rate; + unsigned long target_parent_rate; =20 if (!rate) rate =3D 1; @@ -315,15 +317,11 @@ static int clk_divider_bestdiv(struct clk_hw *hw, str= uct clk_hw *parent, return bestdiv; } =20 - /* - * The maximum divider we can use without overflowing - * unsigned long in rate * i below - */ - maxdiv =3D min(ULONG_MAX / rate, maxdiv); - for (i =3D _next_div(table, 0, flags); i <=3D maxdiv; i =3D _next_div(table, i, flags)) { - if (rate * i =3D=3D parent_rate_saved) { + if (check_mul_overflow(rate, (unsigned long)i, &target_parent_rate)) + target_parent_rate =3D ULONG_MAX; + if (target_parent_rate =3D=3D parent_rate_saved) { /* * It's the most ideal case if the requested rate can be * divided from parent clock without needing to change @@ -332,7 +330,7 @@ static int clk_divider_bestdiv(struct clk_hw *hw, struc= t clk_hw *parent, *best_parent_rate =3D parent_rate_saved; return i; } - parent_rate =3D clk_hw_round_rate(parent, rate * i); + parent_rate =3D clk_hw_round_rate(parent, target_parent_rate); now =3D DIV_ROUND_UP_ULL((u64)parent_rate, i); if (_is_best_div(rate, now, best, flags)) { bestdiv =3D i; --=20 2.53.0