From nobody Mon Jun 15 03:55:13 2026 Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9BC3C3624A4; Wed, 8 Apr 2026 02:55:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.75.126.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775616942; cv=none; b=rTri+MY7VgTpfe/ODRGcYlIgtaHqSbdreKZtRfAqt5v8Hv6kBBpaoxUz6GT2lHeZKzJlYN1zgJAPoJCfFvMxt/xgXuQM0yqEN281No78z/j8WLJp64AIiM3Kkt+s8ZWGKtVi7EjPjEDGSsZukdj3OdxWXcBnvk5opaHzvI7rpr0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775616942; c=relaxed/simple; bh=L2IlH+XqJND7EheUfZeGq2LXHHYkaEHvtjIidP59Nmk=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=K2Qip/7D4TKpCL23w632Im7MQtdO3px2/W0PJ4k8MAxxA0d8nN+vSHx5oGKonrxqNmYMyaGG/lil63PnwL8tkmm5jsbEE47kZQD+aIZf28+jjuOXgLX8sTurgiESygGUO3jX/jp7BpnuThzomE7BqQU3xunfyVklXArDjtPfVCw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=realtek.com; spf=pass smtp.mailfrom=realtek.com; dkim=pass (2048-bit key) header.d=realtek.com header.i=@realtek.com header.b=R5Q5mQoa; arc=none smtp.client-ip=211.75.126.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=realtek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=realtek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=realtek.com header.i=@realtek.com header.b="R5Q5mQoa" X-SpamFilter-By: ArmorX SpamTrap 5.80 with qID 6382qjoF72349153, This message is accepted by code: ctloc85258 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=realtek.com; s=dkim; t=1775616765; bh=2Zf8tghgY31ELN1oGicZic8C6mc3PnABGIIZfUK3NRk=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Transfer-Encoding:Content-Type; b=R5Q5mQoa/E6fu+nf2x6zha3XeOFxVYpthbhE1jGMzYLo+81jtmmx9Rgjwmji4kivP Yy9AaGUq0TKSYLtkMlJgtp/ezTX3BrlPdM/XBNPG3N87B19kEkbjEC6UzSf5TvCBz4 kKJ0eBZfYH4uiTQPZmsKLENi/UnJ2o8OB1LYKUzz0Xqnx0mLXdeBtH3lGmqUUsqzF/ QXevYY+IO58IbLa8kDOGtGrfHcoO4qCQ7IAF+/dWgJmGjFsAhF4rX22/0CKTwA7e/g zTU+N0MyrAxc6fiy/04x4hvvk7QsTWJ5Wt1ju6tf81sIvZzbKo7Biry1+XFbfD4YhS geDG+U5LGCSLQ== Received: from mail.realtek.com (rtkexhmbs03.realtek.com.tw[10.21.1.53]) by rtits2.realtek.com.tw (8.15.2/3.26/5.94) with ESMTPS id 6382qjoF72349153 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 8 Apr 2026 10:52:45 +0800 Received: from RTKEXHMBS05.realtek.com.tw (10.21.1.55) by RTKEXHMBS03.realtek.com.tw (10.21.1.53) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 8 Apr 2026 10:52:45 +0800 Received: from RTKEXHMBS05.realtek.com.tw (10.21.1.55) by RTKEXHMBS05.realtek.com.tw (10.21.1.55) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 8 Apr 2026 10:52:45 +0800 Received: from cn1dhc-k02 (172.21.252.101) by RTKEXHMBS05.realtek.com.tw (10.21.1.55) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Wed, 8 Apr 2026 10:52:45 +0800 From: Yu-Chun Lin To: , , , , , , CC: , , , , , , , , Subject: [PATCH v2 1/4] gpio: Remove "default y" in Kconfig Date: Wed, 8 Apr 2026 10:52:40 +0800 Message-ID: <20260408025243.1155482-2-eleanor.lin@realtek.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260408025243.1155482-1-eleanor.lin@realtek.com> References: <20260408025243.1155482-1-eleanor.lin@realtek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Remove the default y to avoid bloating the build for non-Realtek platforms when COMPILE_TEST is enable on other platforms. Signed-off-by: Yu-Chun Lin --- Changes in v2: - New patch. --- drivers/gpio/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index b45fb799e36c..5ee11a889867 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -629,7 +629,6 @@ config GPIO_ROCKCHIP config GPIO_RTD tristate "Realtek DHC GPIO support" depends on ARCH_REALTEK || COMPILE_TEST - default y select GPIOLIB_IRQCHIP help This option enables support for GPIOs found on Realtek DHC(Digital --=20 2.34.1 From nobody Mon Jun 15 03:55:13 2026 Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B95C1366560; Wed, 8 Apr 2026 02:55:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.75.126.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775616942; cv=none; b=ffVnDBcy8nMomWfdvBW4Zk45gZGFOUN3D1KvKh+wvRCyd+JPF9+L1quBQfHvKUxCCRlerfkqIaQ7poc/IU4tvU/kUK5h90mhb/AsE0Crhpaho8WvvBuN903N4J8FKzElMrlpmcAJeH5E4Mj8Y6aq2+rktzBVNGdYtgrmLQNOVzc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775616942; c=relaxed/simple; bh=0c/zh9AL9+FKEmJBDPRVLWMCvnzS5SzgjfQcEgpQHOk=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=II3oj+ppF/yk/gbJNTh+ja/47CX1iszxU9t4bcYWddAspNfNkK0ivWcqZdLCMq8BCMyybgkCU25WlBGgzquvAhEjcomC8xek6ZlPUitHdWbGIJM8Ygy/MOnCiAhPU3mq9UoX9c1qHZ8Z+Do7+2iBmE2mPLct9WAQp7m3yGwaPC4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=realtek.com; spf=pass smtp.mailfrom=realtek.com; dkim=pass (2048-bit key) header.d=realtek.com header.i=@realtek.com header.b=r67pmIvF; arc=none smtp.client-ip=211.75.126.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=realtek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=realtek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=realtek.com header.i=@realtek.com header.b="r67pmIvF" X-SpamFilter-By: ArmorX SpamTrap 5.80 with qID 6382qkBcB2349159, This message is accepted by code: ctloc85258 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=realtek.com; s=dkim; t=1775616766; bh=swGybb+9llsVg/eIQciZTiYrsdseWcN8ezhyU/fBs9k=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Transfer-Encoding:Content-Type; b=r67pmIvFfWZGBZ6/hTkhiLRUlTp4Spt0kNxBRcR+2ojCyeQoW47JNlg3w2X+e2snR sQnYVhvsecUEkYSzyOm9NJdCQ8N5vM2eS+UdkSn/sI1tQgABJO8v33RvO3R04bSBLq qIkhHUMtqvmNY8gY1HnJ8Eu/rLcSeWfNVAfSTV/QG1G2PWJHMZVuQrQz9aXvuvibmE euYhcET2XCJlGk3L5Pg8AAIB4q/zKhpgUEdZXlem+YjYcPkIR8Cwu0EnG6op6V5/Mh aLgVYhJFgl+Qovmkfsj62GJHhw8R7A9jMZ/7auEHaJSBF/3lpdDmnKvdJs25MPHTNV aP2yBhPem60Mw== Received: from mail.realtek.com (rtkexhmbs04.realtek.com.tw[10.21.1.54]) by rtits2.realtek.com.tw (8.15.2/3.26/5.94) with ESMTPS id 6382qkBcB2349159 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 8 Apr 2026 10:52:46 +0800 Received: from RTKEXHMBS05.realtek.com.tw (10.21.1.55) by RTKEXHMBS04.realtek.com.tw (10.21.1.54) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 8 Apr 2026 10:52:46 +0800 Received: from RTKEXHMBS05.realtek.com.tw (10.21.1.55) by RTKEXHMBS05.realtek.com.tw (10.21.1.55) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 8 Apr 2026 10:52:45 +0800 Received: from cn1dhc-k02 (172.21.252.101) by RTKEXHMBS05.realtek.com.tw (10.21.1.55) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Wed, 8 Apr 2026 10:52:45 +0800 From: Yu-Chun Lin To: , , , , , , CC: , , , , , , , , Subject: [PATCH v2 2/4] dt-bindings: gpio: realtek: Add realtek,rtd1625-gpio Date: Wed, 8 Apr 2026 10:52:41 +0800 Message-ID: <20260408025243.1155482-3-eleanor.lin@realtek.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260408025243.1155482-1-eleanor.lin@realtek.com> References: <20260408025243.1155482-1-eleanor.lin@realtek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Tzuyi Chang Add the device tree bindings for the Realtek DHC (Digital Home Center) RTD1625 GPIO controllers. The RTD1625 GPIO controller features a per-pin register architecture that differs significantly from previous generations. It utilizes separate register blocks for GPIO configuration and interrupt control. Signed-off-by: Tzuyi Chang Signed-off-by: Yu-Chun Lin Reviewed-by: Krzysztof Kozlowski --- Changes in v2: - Merge two memory regions into one. - Add a description for the reg region. --- .../bindings/gpio/realtek,rtd1625-gpio.yaml | 82 +++++++++++++++++++ 1 file changed, 82 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpio/realtek,rtd1625-= gpio.yaml diff --git a/Documentation/devicetree/bindings/gpio/realtek,rtd1625-gpio.ya= ml b/Documentation/devicetree/bindings/gpio/realtek,rtd1625-gpio.yaml new file mode 100644 index 000000000000..de873876b8c6 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/realtek,rtd1625-gpio.yaml @@ -0,0 +1,82 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2023 Realtek Semiconductor Corporation +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio/realtek,rtd1625-gpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Realtek DHC RTD1625 GPIO controller + +maintainers: + - Tzuyi Chang + +description: | + GPIO controller for the Realtek RTD1625 SoC, featuring a per-pin register + architecture that differs significantly from earlier RTD series controll= ers. + Each GPIO has dedicated registers for configuration (direction, input/ou= tput + values, debounce), and interrupt control supporting edge and level detec= tion + modes. + +properties: + compatible: + enum: + - realtek,rtd1625-iso-gpio + - realtek,rtd1625-isom-gpio + + reg: + maxItems: 1 + description: | + Memory region containing both interrupt control and GPIO + configuration registers in a contiguous address space. + + For realtek,rtd1625-iso-gpio: + - Base + 0x0 ~ 0xff: Interrupt control registers + - Base + 0x100 ~ 0x397: GPIO configuration registers + + For realtek,rtd1625-isom-gpio: + - Base + 0x0 ~ 0x1f: Interrupt control registers + - Base + 0x20 ~ 0x2f: GPIO configuration registers + + interrupts: + items: + - description: Interrupt number of the assert GPIO interrupt, which = is + triggered when there is a rising edge. + - description: Interrupt number of the deassert GPIO interrupt, whic= h is + triggered when there is a falling edge. + - description: Interrupt number of the level-sensitive GPIO interrup= t, + triggered by a configured logic level. + + interrupt-controller: true + + "#interrupt-cells": + const: 2 + + gpio-ranges: true + + gpio-controller: true + + "#gpio-cells": + const: 2 + +required: + - compatible + - reg + - gpio-ranges + - gpio-controller + - "#gpio-cells" + +additionalProperties: false + +examples: + - | + gpio@89100 { + compatible =3D "realtek,rtd1625-isom-gpio"; + reg =3D <0x89100 0x30>; + interrupt-parent =3D <&iso_m_irq_mux>; + interrupts =3D <0>, <1>, <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + gpio-ranges =3D <&isom_pinctrl 0 0 4>; + gpio-controller; + #gpio-cells =3D <2>; + }; --=20 2.34.1 From nobody Mon Jun 15 03:55:13 2026 Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E266536A004; Wed, 8 Apr 2026 02:55:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.75.126.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775616944; cv=none; b=dNbpa56//ACaIuJf0g6NnZY3EshkiSICjx4Mvex00SRTda0qK4Ck9y7rKqfF3SlEqncIaPEVFZcwWQvH/rm1UlMXZpvXyYc12JTpjQV1iEl9rZqWHvnmBIsGBf/5iKxwHkGriwFrUt2Qv3ZxBB0TumZUXUe+q17yU1n1tYw7UOY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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Wed, 8 Apr 2026 10:52:46 +0800 Received: from RTKEXHMBS05.realtek.com.tw (10.21.1.55) by RTKEXHMBS05.realtek.com.tw (10.21.1.55) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 8 Apr 2026 10:52:45 +0800 Received: from cn1dhc-k02 (172.21.252.101) by RTKEXHMBS05.realtek.com.tw (10.21.1.55) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Wed, 8 Apr 2026 10:52:45 +0800 From: Yu-Chun Lin To: , , , , , , CC: , , , , , , , , Subject: [PATCH v2 3/4] gpio: realtek: Add driver for Realtek DHC RTD1625 SoC Date: Wed, 8 Apr 2026 10:52:42 +0800 Message-ID: <20260408025243.1155482-4-eleanor.lin@realtek.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260408025243.1155482-1-eleanor.lin@realtek.com> References: <20260408025243.1155482-1-eleanor.lin@realtek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Tzuyi Chang Add support for the GPIO controller found on Realtek DHC RTD1625 SoCs. Unlike the existing Realtek GPIO driver (drivers/gpio/gpio-rtd.c), which manages pins via shared bank registers, the RTD1625 introduces a per-pin register architecture. Each GPIO line now has its own dedicated 32-bit control register to manage configuration independently, including direction, output value, input value, interrupt enable, and debounce. Therefore, this distinct hardware design requires a separate driver. Reviewed-by: Linus Walleij Signed-off-by: Tzuyi Chang Signed-off-by: Yu-Chun Lin --- Changes in v2: - Remove "default y". - Add base_offset member to struct rtd1625_gpio_info to handle merged regio= ns. --- drivers/gpio/Kconfig | 11 + drivers/gpio/Makefile | 1 + drivers/gpio/gpio-rtd1625.c | 584 ++++++++++++++++++++++++++++++++++++ 3 files changed, 596 insertions(+) create mode 100644 drivers/gpio/gpio-rtd1625.c diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 5ee11a889867..281549ad72ac 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -638,6 +638,17 @@ config GPIO_RTD Say yes here to support GPIO functionality and GPIO interrupt on Realtek DHC SoCs. =20 +config GPIO_RTD1625 + tristate "Realtek DHC RTD1625 GPIO support" + depends on ARCH_REALTEK || COMPILE_TEST + select GPIOLIB_IRQCHIP + help + This option enables support for the GPIO controller on Realtek + DHC (Digital Home Center) RTD1625 SoC. + + Say yes here to support both basic GPIO line functionality + and GPIO interrupt handling capabilities for this platform. + config GPIO_SAMA5D2_PIOBU tristate "SAMA5D2 PIOBU GPIO support" depends on MFD_SYSCON diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index c05f7d795c43..c95ba218d53a 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -159,6 +159,7 @@ obj-$(CONFIG_GPIO_REALTEK_OTTO) +=3D gpio-realtek-otto= .o obj-$(CONFIG_GPIO_REG) +=3D gpio-reg.o obj-$(CONFIG_GPIO_ROCKCHIP) +=3D gpio-rockchip.o obj-$(CONFIG_GPIO_RTD) +=3D gpio-rtd.o +obj-$(CONFIG_GPIO_RTD1625) +=3D gpio-rtd1625.o obj-$(CONFIG_ARCH_SA1100) +=3D gpio-sa1100.o obj-$(CONFIG_GPIO_SAMA5D2_PIOBU) +=3D gpio-sama5d2-piobu.o obj-$(CONFIG_GPIO_SCH311X) +=3D gpio-sch311x.o diff --git a/drivers/gpio/gpio-rtd1625.c b/drivers/gpio/gpio-rtd1625.c new file mode 100644 index 000000000000..bcc1bbb115fa --- /dev/null +++ b/drivers/gpio/gpio-rtd1625.c @@ -0,0 +1,584 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Realtek DHC RTD1625 gpio driver + * + * Copyright (c) 2023 Realtek Semiconductor Corp. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define RTD1625_GPIO_DIR BIT(0) +#define RTD1625_GPIO_OUT BIT(2) +#define RTD1625_GPIO_IN BIT(4) +#define RTD1625_GPIO_EDGE_INT_DP BIT(6) +#define RTD1625_GPIO_EDGE_INT_EN BIT(8) +#define RTD1625_GPIO_LEVEL_INT_EN BIT(16) +#define RTD1625_GPIO_LEVEL_INT_DP BIT(18) +#define RTD1625_GPIO_DEBOUNCE GENMASK(30, 28) +#define RTD1625_GPIO_DEBOUNCE_WREN BIT(31) + +#define RTD1625_GPIO_WREN(x) ((x) << 1) + +/* Write-enable masks for all GPIO configs and reserved hardware bits */ +#define RTD1625_ISO_GPIO_WREN_ALL 0x8000aa8a +#define RTD1625_ISOM_GPIO_WREN_ALL 0x800aaa8a + +#define RTD1625_GPIO_DEBOUNCE_1US 0 +#define RTD1625_GPIO_DEBOUNCE_10US 1 +#define RTD1625_GPIO_DEBOUNCE_100US 2 +#define RTD1625_GPIO_DEBOUNCE_1MS 3 +#define RTD1625_GPIO_DEBOUNCE_10MS 4 +#define RTD1625_GPIO_DEBOUNCE_20MS 5 +#define RTD1625_GPIO_DEBOUNCE_30MS 6 +#define RTD1625_GPIO_DEBOUNCE_50MS 7 + +#define GPIO_CONTROL(gpio) ((gpio) * 4) + +/** + * struct rtd1625_gpio_info - Specific GPIO register information + * @num_gpios: The number of GPIOs + * @irq_type_support: Supported IRQ types + * @gpa_offset: Offset for GPIO assert interrupt status registers + * @gpda_offset: Offset for GPIO deassert interrupt status registers + * @level_offset: Offset of level interrupt status register + * @write_en_all: Write-enable mask for all configurable bits + */ +struct rtd1625_gpio_info { + unsigned int num_gpios; + unsigned int irq_type_support; + unsigned int base_offset; + unsigned int gpa_offset; + unsigned int gpda_offset; + unsigned int level_offset; + unsigned int write_en_all; +}; + +struct rtd1625_gpio { + struct gpio_chip gpio_chip; + const struct rtd1625_gpio_info *info; + void __iomem *base; + void __iomem *irq_base; + unsigned int irqs[3]; + raw_spinlock_t lock; + unsigned int *save_regs; +}; + +static unsigned int rtd1625_gpio_gpa_offset(struct rtd1625_gpio *data, uns= igned int offset) +{ + return data->info->gpa_offset + ((offset / 32) * 4); +} + +static unsigned int rtd1625_gpio_gpda_offset(struct rtd1625_gpio *data, un= signed int offset) +{ + return data->info->gpda_offset + ((offset / 32) * 4); +} + +static unsigned int rtd1625_gpio_level_offset(struct rtd1625_gpio *data, u= nsigned int offset) +{ + return data->info->level_offset + ((offset / 32) * 4); +} + +static unsigned int rtd1625_gpio_set_debounce(struct gpio_chip *chip, unsi= gned int offset, + unsigned int debounce) +{ + struct rtd1625_gpio *data =3D gpiochip_get_data(chip); + u8 deb_val; + u32 val; + + switch (debounce) { + case 1: + deb_val =3D RTD1625_GPIO_DEBOUNCE_1US; + break; + case 10: + deb_val =3D RTD1625_GPIO_DEBOUNCE_10US; + break; + case 100: + deb_val =3D RTD1625_GPIO_DEBOUNCE_100US; + break; + case 1000: + deb_val =3D RTD1625_GPIO_DEBOUNCE_1MS; + break; + case 10000: + deb_val =3D RTD1625_GPIO_DEBOUNCE_10MS; + break; + case 20000: + deb_val =3D RTD1625_GPIO_DEBOUNCE_20MS; + break; + case 30000: + deb_val =3D RTD1625_GPIO_DEBOUNCE_30MS; + break; + case 50000: + deb_val =3D RTD1625_GPIO_DEBOUNCE_50MS; + break; + default: + return -ENOTSUPP; + } + + val =3D FIELD_PREP(RTD1625_GPIO_DEBOUNCE, deb_val) | RTD1625_GPIO_DEBOUNC= E_WREN; + + guard(raw_spinlock_irqsave)(&data->lock); + writel_relaxed(val, data->base + GPIO_CONTROL(offset)); + + return 0; +} + +static int rtd1625_gpio_set_config(struct gpio_chip *chip, unsigned int of= fset, + unsigned long config) +{ + int debounce; + + if (pinconf_to_config_param(config) =3D=3D PIN_CONFIG_INPUT_DEBOUNCE) { + debounce =3D pinconf_to_config_argument(config); + return rtd1625_gpio_set_debounce(chip, offset, debounce); + } + + return gpiochip_generic_config(chip, offset, config); +} + +static int rtd1625_gpio_set(struct gpio_chip *chip, unsigned int offset, i= nt value) +{ + struct rtd1625_gpio *data =3D gpiochip_get_data(chip); + u32 val =3D RTD1625_GPIO_WREN(RTD1625_GPIO_OUT); + + if (value) + val |=3D RTD1625_GPIO_OUT; + + guard(raw_spinlock_irqsave)(&data->lock); + writel_relaxed(val, data->base + GPIO_CONTROL(offset)); + + return 0; +} + +static int rtd1625_gpio_get(struct gpio_chip *chip, unsigned int offset) +{ + struct rtd1625_gpio *data =3D gpiochip_get_data(chip); + u32 val; + + guard(raw_spinlock_irqsave)(&data->lock); + val =3D readl_relaxed(data->base + GPIO_CONTROL(offset)); + + if (val & RTD1625_GPIO_DIR) + return !!(val & RTD1625_GPIO_OUT); + else + return !!(val & RTD1625_GPIO_IN); +} + +static int rtd1625_gpio_get_direction(struct gpio_chip *chip, unsigned int= offset) +{ + struct rtd1625_gpio *data =3D gpiochip_get_data(chip); + u32 val; + + guard(raw_spinlock_irqsave)(&data->lock); + val =3D readl_relaxed(data->base + GPIO_CONTROL(offset)); + + if (val & RTD1625_GPIO_DIR) + return GPIO_LINE_DIRECTION_OUT; + + return GPIO_LINE_DIRECTION_IN; +} + +static int rtd1625_gpio_set_direction(struct gpio_chip *chip, unsigned int= offset, bool out) +{ + struct rtd1625_gpio *data =3D gpiochip_get_data(chip); + u32 val =3D RTD1625_GPIO_WREN(RTD1625_GPIO_DIR); + + if (out) + val |=3D RTD1625_GPIO_DIR; + + guard(raw_spinlock_irqsave)(&data->lock); + writel_relaxed(val, data->base + GPIO_CONTROL(offset)); + + return 0; +} + +static int rtd1625_gpio_direction_input(struct gpio_chip *chip, unsigned i= nt offset) +{ + return rtd1625_gpio_set_direction(chip, offset, false); +} + +static int rtd1625_gpio_direction_output(struct gpio_chip *chip, unsigned = int offset, int value) +{ + rtd1625_gpio_set(chip, offset, value); + + return rtd1625_gpio_set_direction(chip, offset, true); +} + +static void rtd1625_gpio_irq_handle(struct irq_desc *desc) +{ + unsigned int (*get_reg_offset)(struct rtd1625_gpio *gpio, unsigned int of= fset); + struct rtd1625_gpio *data =3D irq_desc_get_handler_data(desc); + struct irq_domain *domain =3D data->gpio_chip.irq.domain; + struct irq_chip *chip =3D irq_desc_get_chip(desc); + unsigned int irq =3D irq_desc_get_irq(desc); + unsigned long status; + unsigned int reg_offset, i, j; + unsigned int girq; + irq_hw_number_t hwirq; + u32 irq_type; + + if (irq =3D=3D data->irqs[0]) + get_reg_offset =3D &rtd1625_gpio_gpa_offset; + else if (irq =3D=3D data->irqs[1]) + get_reg_offset =3D &rtd1625_gpio_gpda_offset; + else if (irq =3D=3D data->irqs[2]) + get_reg_offset =3D &rtd1625_gpio_level_offset; + else + return; + + chained_irq_enter(chip, desc); + + for (i =3D 0; i < data->info->num_gpios; i +=3D 32) { + reg_offset =3D get_reg_offset(data, i); + status =3D readl_relaxed(data->irq_base + reg_offset); + + /* Clear edge interrupts; level interrupts are cleared in ->irq_ack() */ + if (irq !=3D data->irqs[2]) + writel_relaxed(status, data->irq_base + reg_offset); + + for_each_set_bit(j, &status, 32) { + hwirq =3D i + j; + girq =3D irq_find_mapping(domain, hwirq); + irq_type =3D irq_get_trigger_type(girq); + + if (irq =3D=3D data->irqs[1] && irq_type !=3D IRQ_TYPE_EDGE_BOTH) + continue; + + generic_handle_domain_irq(domain, hwirq); + } + } + + chained_irq_exit(chip, desc); +} + +static void rtd1625_gpio_ack_irq(struct irq_data *d) +{ + struct rtd1625_gpio *data =3D irq_data_get_irq_chip_data(d); + irq_hw_number_t hwirq =3D irqd_to_hwirq(d); + u32 irq_type =3D irqd_get_trigger_type(d); + u32 bit_mask =3D BIT(hwirq % 32); + int reg_offset; + + if (irq_type & IRQ_TYPE_LEVEL_MASK) { + reg_offset =3D rtd1625_gpio_level_offset(data, hwirq); + writel_relaxed(bit_mask, data->irq_base + reg_offset); + } +} + +static void rtd1625_gpio_enable_edge_irq(struct rtd1625_gpio *data, irq_hw= _number_t hwirq) +{ + int gpda_reg_offset =3D rtd1625_gpio_gpda_offset(data, hwirq); + int gpa_reg_offset =3D rtd1625_gpio_gpa_offset(data, hwirq); + u32 clr_mask =3D BIT(hwirq % 32); + u32 val; + + guard(raw_spinlock_irqsave)(&data->lock); + writel_relaxed(clr_mask, data->irq_base + gpa_reg_offset); + writel_relaxed(clr_mask, data->irq_base + gpda_reg_offset); + val =3D RTD1625_GPIO_EDGE_INT_EN | RTD1625_GPIO_WREN(RTD1625_GPIO_EDGE_IN= T_EN); + writel_relaxed(val, data->base + GPIO_CONTROL(hwirq)); +} + +static void rtd1625_gpio_disable_edge_irq(struct rtd1625_gpio *data, irq_h= w_number_t hwirq) +{ + u32 val; + + guard(raw_spinlock_irqsave)(&data->lock); + val =3D RTD1625_GPIO_WREN(RTD1625_GPIO_EDGE_INT_EN); + writel_relaxed(val, data->base + GPIO_CONTROL(hwirq)); +} + +static void rtd1625_gpio_enable_level_irq(struct rtd1625_gpio *data, irq_h= w_number_t hwirq) +{ + int level_reg_offset =3D rtd1625_gpio_level_offset(data, hwirq); + u32 clr_mask =3D BIT(hwirq % 32); + u32 val; + + guard(raw_spinlock_irqsave)(&data->lock); + writel_relaxed(clr_mask, data->irq_base + level_reg_offset); + val =3D RTD1625_GPIO_LEVEL_INT_EN | RTD1625_GPIO_WREN(RTD1625_GPIO_LEVEL_= INT_EN); + writel_relaxed(val, data->base + GPIO_CONTROL(hwirq)); +} + +static void rtd1625_gpio_disable_level_irq(struct rtd1625_gpio *data, irq_= hw_number_t hwirq) +{ + u32 val; + + guard(raw_spinlock_irqsave)(&data->lock); + val =3D RTD1625_GPIO_WREN(RTD1625_GPIO_LEVEL_INT_EN); + writel_relaxed(val, data->base + GPIO_CONTROL(hwirq)); +} + +static void rtd1625_gpio_enable_irq(struct irq_data *d) +{ + struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); + struct rtd1625_gpio *data =3D gpiochip_get_data(gc); + irq_hw_number_t hwirq =3D irqd_to_hwirq(d); + u32 irq_type =3D irqd_get_trigger_type(d); + + gpiochip_enable_irq(gc, hwirq); + + if (irq_type & IRQ_TYPE_EDGE_BOTH) + rtd1625_gpio_enable_edge_irq(data, hwirq); + else if (irq_type & IRQ_TYPE_LEVEL_MASK) + rtd1625_gpio_enable_level_irq(data, hwirq); +} + +static void rtd1625_gpio_disable_irq(struct irq_data *d) +{ + struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); + struct rtd1625_gpio *data =3D gpiochip_get_data(gc); + irq_hw_number_t hwirq =3D irqd_to_hwirq(d); + u32 irq_type =3D irqd_get_trigger_type(d); + + if (irq_type & IRQ_TYPE_EDGE_BOTH) + rtd1625_gpio_disable_edge_irq(data, hwirq); + else if (irq_type & IRQ_TYPE_LEVEL_MASK) + rtd1625_gpio_disable_level_irq(data, hwirq); + + gpiochip_disable_irq(gc, hwirq); +} + +static int rtd1625_gpio_irq_set_level_type(struct irq_data *d, bool level) +{ + struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); + struct rtd1625_gpio *data =3D gpiochip_get_data(gc); + irq_hw_number_t hwirq =3D irqd_to_hwirq(d); + u32 val =3D RTD1625_GPIO_WREN(RTD1625_GPIO_LEVEL_INT_DP); + + if (!(data->info->irq_type_support & IRQ_TYPE_LEVEL_MASK)) + return -EINVAL; + + scoped_guard(raw_spinlock_irqsave, &data->lock) { + if (level) + val |=3D RTD1625_GPIO_LEVEL_INT_DP; + writel_relaxed(val, data->base + GPIO_CONTROL(hwirq)); + } + + irq_set_handler_locked(d, handle_level_irq); + + return 0; +} + +static int rtd1625_gpio_irq_set_edge_type(struct irq_data *d, bool polarit= y) +{ + struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); + struct rtd1625_gpio *data =3D gpiochip_get_data(gc); + irq_hw_number_t hwirq =3D irqd_to_hwirq(d); + u32 val =3D RTD1625_GPIO_WREN(RTD1625_GPIO_EDGE_INT_DP); + + if (!(data->info->irq_type_support & IRQ_TYPE_EDGE_BOTH)) + return -EINVAL; + + scoped_guard(raw_spinlock_irqsave, &data->lock) { + if (polarity) + val |=3D RTD1625_GPIO_EDGE_INT_DP; + writel_relaxed(val, data->base + GPIO_CONTROL(hwirq)); + } + + irq_set_handler_locked(d, handle_edge_irq); + + return 0; +} + +static int rtd1625_gpio_irq_set_type(struct irq_data *d, unsigned int type) +{ + int ret; + + switch (type & IRQ_TYPE_SENSE_MASK) { + case IRQ_TYPE_EDGE_RISING: + ret =3D rtd1625_gpio_irq_set_edge_type(d, 1); + break; + case IRQ_TYPE_EDGE_FALLING: + ret =3D rtd1625_gpio_irq_set_edge_type(d, 0); + break; + case IRQ_TYPE_EDGE_BOTH: + ret =3D rtd1625_gpio_irq_set_edge_type(d, 1); + break; + case IRQ_TYPE_LEVEL_HIGH: + ret =3D rtd1625_gpio_irq_set_level_type(d, 0); + break; + case IRQ_TYPE_LEVEL_LOW: + ret =3D rtd1625_gpio_irq_set_level_type(d, 1); + break; + default: + ret =3D -EINVAL; + } + + return ret; +} + +static struct irq_chip rtd1625_iso_gpio_irq_chip =3D { + .name =3D "rtd1625-gpio", + .irq_ack =3D rtd1625_gpio_ack_irq, + .irq_mask =3D rtd1625_gpio_disable_irq, + .irq_unmask =3D rtd1625_gpio_enable_irq, + .irq_set_type =3D rtd1625_gpio_irq_set_type, + .flags =3D IRQCHIP_IMMUTABLE | IRQCHIP_SKIP_SET_WAKE, + GPIOCHIP_IRQ_RESOURCE_HELPERS, +}; + +static int rtd1625_gpio_setup_irq(struct platform_device *pdev, struct rtd= 1625_gpio *data) +{ + struct gpio_irq_chip *irq_chip; + int num_irqs; + int irq; + int i; + + irq =3D platform_get_irq_optional(pdev, 0); + if (irq =3D=3D -ENXIO) + return 0; + if (irq < 0) + return irq; + + num_irqs =3D (data->info->irq_type_support & IRQ_TYPE_LEVEL_MASK) ? 3 : 2; + data->irqs[0] =3D irq; + + for (i =3D 1; i < num_irqs; i++) { + irq =3D platform_get_irq(pdev, i); + if (irq < 0) + return irq; + data->irqs[i] =3D irq; + } + + irq_chip =3D &data->gpio_chip.irq; + irq_chip->handler =3D handle_bad_irq; + irq_chip->default_type =3D IRQ_TYPE_NONE; + irq_chip->parent_handler =3D rtd1625_gpio_irq_handle; + irq_chip->parent_handler_data =3D data; + irq_chip->num_parents =3D num_irqs; + irq_chip->parents =3D data->irqs; + + gpio_irq_chip_set_chip(irq_chip, &rtd1625_iso_gpio_irq_chip); + + return 0; +} + +static int rtd1625_gpio_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct rtd1625_gpio *data; + void __iomem *irq_base; + int ret; + + data =3D devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + data->info =3D device_get_match_data(dev); + if (!data->info) + return -EINVAL; + + raw_spin_lock_init(&data->lock); + + irq_base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(irq_base)) + return PTR_ERR(irq_base); + + data->irq_base =3D irq_base; + data->base =3D irq_base + data->info->base_offset; + + data->save_regs =3D devm_kzalloc(dev, data->info->num_gpios * + sizeof(*data->save_regs), GFP_KERNEL); + if (!data->save_regs) + return -ENOMEM; + + data->gpio_chip.label =3D dev_name(dev); + data->gpio_chip.base =3D -1; + data->gpio_chip.ngpio =3D data->info->num_gpios; + data->gpio_chip.request =3D gpiochip_generic_request; + data->gpio_chip.free =3D gpiochip_generic_free; + data->gpio_chip.get_direction =3D rtd1625_gpio_get_direction; + data->gpio_chip.direction_input =3D rtd1625_gpio_direction_input; + data->gpio_chip.direction_output =3D rtd1625_gpio_direction_output; + data->gpio_chip.set =3D rtd1625_gpio_set; + data->gpio_chip.get =3D rtd1625_gpio_get; + data->gpio_chip.set_config =3D rtd1625_gpio_set_config; + data->gpio_chip.parent =3D dev; + + ret =3D rtd1625_gpio_setup_irq(pdev, data); + if (ret) + return ret; + + platform_set_drvdata(pdev, data); + + return devm_gpiochip_add_data(dev, &data->gpio_chip, data); +} + +static const struct rtd1625_gpio_info rtd1625_iso_gpio_info =3D { + .num_gpios =3D 166, + .irq_type_support =3D IRQ_TYPE_EDGE_BOTH, + .base_offset =3D 0x100, + .gpa_offset =3D 0x0, + .gpda_offset =3D 0x20, + .write_en_all =3D RTD1625_ISO_GPIO_WREN_ALL, +}; + +static const struct rtd1625_gpio_info rtd1625_isom_gpio_info =3D { + .num_gpios =3D 4, + .irq_type_support =3D IRQ_TYPE_EDGE_BOTH | IRQ_TYPE_LEVEL_LOW | + IRQ_TYPE_LEVEL_HIGH, + .base_offset =3D 0x20, + .gpa_offset =3D 0x0, + .gpda_offset =3D 0x4, + .level_offset =3D 0x18, + .write_en_all =3D RTD1625_ISOM_GPIO_WREN_ALL, +}; + +static const struct of_device_id rtd1625_gpio_of_matches[] =3D { + { .compatible =3D "realtek,rtd1625-iso-gpio", .data =3D &rtd1625_iso_gpio= _info }, + { .compatible =3D "realtek,rtd1625-isom-gpio", .data =3D &rtd1625_isom_gp= io_info }, + { } +}; +MODULE_DEVICE_TABLE(of, rtd1625_gpio_of_matches); + +static int rtd1625_gpio_suspend(struct device *dev) +{ + struct rtd1625_gpio *data =3D dev_get_drvdata(dev); + const struct rtd1625_gpio_info *info =3D data->info; + int i; + + for (i =3D 0; i < info->num_gpios; i++) + data->save_regs[i] =3D readl_relaxed(data->base + GPIO_CONTROL(i)); + + return 0; +} + +static int rtd1625_gpio_resume(struct device *dev) +{ + struct rtd1625_gpio *data =3D dev_get_drvdata(dev); + const struct rtd1625_gpio_info *info =3D data->info; + int i; + + for (i =3D 0; i < info->num_gpios; i++) + writel_relaxed(data->save_regs[i] | info->write_en_all, + data->base + GPIO_CONTROL(i)); + + return 0; +} + +DEFINE_NOIRQ_DEV_PM_OPS(rtd1625_gpio_pm_ops, rtd1625_gpio_suspend, rtd1625= _gpio_resume); + +static struct platform_driver rtd1625_gpio_platform_driver =3D { + .driver =3D { + .name =3D "gpio-rtd1625", + .of_match_table =3D rtd1625_gpio_of_matches, + .pm =3D pm_sleep_ptr(&rtd1625_gpio_pm_ops), + }, + .probe =3D rtd1625_gpio_probe, +}; +module_platform_driver(rtd1625_gpio_platform_driver); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Realtek Semiconductor Corporation"); +MODULE_DESCRIPTION("Realtek DHC SoC RTD1625 gpio driver"); --=20 2.34.1 From nobody Mon Jun 15 03:55:13 2026 Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8C87F202C29; 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Wed, 8 Apr 2026 10:52:46 +0800 Received: from RTKEXHMBS05.realtek.com.tw (10.21.1.55) by RTKEXHMBS03.realtek.com.tw (10.21.1.53) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 8 Apr 2026 10:52:47 +0800 Received: from RTKEXHMBS05.realtek.com.tw (10.21.1.55) by RTKEXHMBS05.realtek.com.tw (10.21.1.55) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 8 Apr 2026 10:52:46 +0800 Received: from cn1dhc-k02 (172.21.252.101) by RTKEXHMBS05.realtek.com.tw (10.21.1.55) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Wed, 8 Apr 2026 10:52:46 +0800 From: Yu-Chun Lin To: , , , , , , CC: , , , , , , , , Subject: [PATCH v2 4/4] arm64: dts: realtek: Add GPIO support for RTD1625 Date: Wed, 8 Apr 2026 10:52:43 +0800 Message-ID: <20260408025243.1155482-5-eleanor.lin@realtek.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260408025243.1155482-1-eleanor.lin@realtek.com> References: <20260408025243.1155482-1-eleanor.lin@realtek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the GPIO node for the Realtek RTD1625 SoC. Signed-off-by: Yu-Chun Lin Reviewed-by: Bartosz Golaszewski --- Changes in v2: - Merge two reg memory regions. - Remove redundant status setting. --- arch/arm64/boot/dts/realtek/kent.dtsi | 39 +++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/arm64/boot/dts/realtek/kent.dtsi b/arch/arm64/boot/dts/re= altek/kent.dtsi index 8d4293cd4c03..dafe56ce7d71 100644 --- a/arch/arm64/boot/dts/realtek/kent.dtsi +++ b/arch/arm64/boot/dts/realtek/kent.dtsi @@ -151,6 +151,37 @@ uart0: serial@7800 { status =3D "disabled"; }; =20 + gpio: gpio@31000 { + compatible =3D "realtek,rtd1625-iso-gpio"; + reg =3D <0x31000 0x398>; + gpio-controller; + gpio-ranges =3D <&isom_pinctrl 0 0 2>, + <&ve4_pinctrl 2 0 6>, + <&iso_pinctrl 8 0 4>, + <&ve4_pinctrl 12 6 2>, + <&main2_pinctrl 14 0 2>, + <&ve4_pinctrl 16 8 4>, + <&main2_pinctrl 20 2 3>, + <&ve4_pinctrl 23 12 3>, + <&iso_pinctrl 26 4 2>, + <&isom_pinctrl 28 2 2>, + <&ve4_pinctrl 30 15 6>, + <&main2_pinctrl 36 5 6>, + <&ve4_pinctrl 42 21 3>, + <&iso_pinctrl 45 6 6>, + <&ve4_pinctrl 51 24 1>, + <&iso_pinctrl 52 12 1>, + <&ve4_pinctrl 53 25 11>, + <&main2_pinctrl 64 11 28>, + <&ve4_pinctrl 92 36 2>, + <&iso_pinctrl 94 13 19>, + <&iso_pinctrl 128 32 4>, + <&ve4_pinctrl 132 38 13>, + <&iso_pinctrl 145 36 19>, + <&ve4_pinctrl 164 51 2>; + #gpio-cells =3D <2>; + }; + iso_pinctrl: pinctrl@4e000 { compatible =3D "realtek,rtd1625-iso-pinctrl"; reg =3D <0x4e000 0x1a4>; @@ -161,6 +192,14 @@ main2_pinctrl: pinctrl@4f200 { reg =3D <0x4f200 0x50>; }; =20 + iso_m_gpio: gpio@89100 { + compatible =3D "realtek,rtd1625-isom-gpio"; + reg =3D <0x89100 0x30>; + gpio-controller; + gpio-ranges =3D <&isom_pinctrl 0 0 4>; + #gpio-cells =3D <2>; + }; + isom_pinctrl: pinctrl@146200 { compatible =3D "realtek,rtd1625-isom-pinctrl"; reg =3D <0x146200 0x34>; --=20 2.34.1