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[46.193.119.166]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43d1e2c54bdsm58725449f8f.16.2026.04.08.04.57.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Apr 2026 04:57:42 -0700 (PDT) From: Fidelio Lawson X-Google-Original-From: Fidelio Lawson Date: Wed, 08 Apr 2026 13:57:14 +0200 Subject: [PATCH v2] net: dsa: microchip: implement KSZ87xx Module 3 low-loss cable errata Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260408-ksz87xx_errata_low_loss_connections-v2-1-9cfe38691713@exotec.com> X-B4-Tracking: v=1; b=H4sIAJlC1mkC/42Oyw7CIBBFf8WwFkOh0taV/2GahuLU4gMMgxVt+ u/SGvcuZnGSe++ZkSB4A0h2q5F4GAwaZxPw9YroXtkTUHNMTDjjkgku6AXfZRFjA96roJqre6Z DbLSzFnRIdaSt3EIhgbc5EyQt3T10Ji6WQ/1lfLTnFJ+n50RvMDj/Wt4Ysjn3M8q/jENGGS0qJ auyy4Xkcg/RBdAb7W6knqbpA+S6QkHpAAAA X-Change-ID: 20260323-ksz87xx_errata_low_loss_connections-b65e76e2b403 To: Woojung Huh , UNGLinuxDriver@microchip.com, Andrew Lunn , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Marek Vasut , Maxime Chevallier Cc: Woojung Huh , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Fidelio Lawson X-Mailer: b4 0.15.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1775649461; l=8279; i=fidelio.lawson@exotec.com; s=20260326; h=from:subject:message-id; bh=XscSiaVsdQ3yMiKaqacmUk9OOVbjAySHjfpWMwLEhAc=; b=Rw92b+YLQ9gSnS0Y38tU/Ek6tWP8M5BVekkDAcvvEwsevqsJb+KnGjhS9YPSJ6qDt0p5voWYD Hw4wnvjXZOvD3rzuSi1vXDABpcwKiwMiWBX9hWvYv8PSunDFkmsj1lQ X-Developer-Key: i=fidelio.lawson@exotec.com; a=ed25519; pk=866eH9Bmmpjc+ctgkr5T1uXxBefZzob3tEEuiVWZ6BI= Implement the "Module 3: Equalizer fix for short cables" erratum from Microchip document DS80000687C for KSZ87xx switches. The issue affects short or low-loss cable links (e.g. CAT5e/CAT6), where the PHY receiver equalizer may amplify high-amplitude signals excessively, resulting in internal distortion and link establishment failures. KSZ87xx devices require a workaround for the Module 3 low-loss cable condition, controlled through the switch TABLE_LINK_MD_V indirect registers. The affected registers are part of the switch address space and are not directly accessible from the PHY driver. To keep the PHY-facing API clean and avoid leaking switch-specific details, model this errata control as vendor-specific Clause 22 PHY registers. Two vendor-defined bits are introduced in PHY_REG_LOW_LOSS_CTRL, and ksz8_r_phy() / ksz8_w_phy() translate accesses to these bits into the appropriate indirect TABLE_LINK_MD_V accesses. The control register defines the following modes: bits [1:0]: 00 =3D workaround disabled 01 =3D workaround 1 (DSP EQ training adjustment, LinkMD reg 0x3c) 10 =3D workaround 2 (receiver LPF bandwidth, LinkMD reg 0x4c) Workaround 1: Adjusts the DSP EQ training behavior via LinkMD register 0x3C. Widens and optimizes the DSP EQ compensation range, and is expected to solve most short/low-loss cable issues. Workaround 2: for the cases where Workaround 1 is not sufficient. This one adjusts the receiver low-pass filter bandwidth, effectively reducing the high-frequency component of the received signal The register is accessible through standard PHY read/write operations (e.g. phytool), without requiring any switch-specific userspace interface. This allows robust link establishment on short or low-loss cabling without requiring DTS properties and without constraining hardware design choices. The erratum affects the shared PHY analog front-end and therefore applies globally to the switch. Signed-off-by: Fidelio Lawson --- Hello, This patch implements the =E2=80=9CModule 3: Equalizer fix for short cables= =E2=80=9D erratum described in Microchip document DS80000687C for KSZ87xx switches. According to the erratum, the embedded PHY receiver in KSZ87xx switches is tuned by default for long, high-loss Ethernet cables. When operating with short or low-loss cables (for example CAT5e or CAT6), the PHY equalizer may over-amplify the incoming signal, leading to internal distortion and link establishment failures. Microchip provides two workarounds, each requiring a write to a different indirect PHY register access mechanism. The workaround requires programming internal PHY/DSP registers located in t= he LinkMD table, accessed through the KSZ8 indirect register mechanism. Since = these registers belong to the switch address space and are not directly accessible from a standalone PHY driver, the erratum control is modeled as a vendor-sp= ecific Clause 22 PHY register, virtualized by the KSZ8 DSA driver. Reads and writes to this register are intercepted by ksz8_r_phy() / ksz8_w_phy() and translated into the required TABLE_LINK_MD_V indirect acce= sses. The erratum affects the shared PHY analog front-end and therefore applies globally to the switch. The register defines three modes: - 0x0: workaround disabled - 0x1: workaround 1 (DSP EQ training adjustment) - 0x2: workaround 2 (receiver low-pass filter bandwidth reduction) The register can be read and written from userspace via standard Clause 22 = PHY accesses (for example using phytool) on DSA user ports. This series is based on Linux v7.0-rc1. --- Changes in v2: - Dropped the device tree approache based on review feedback - Modeled the errata control as a vendor-specific Clause 22 PHY register - Added KSZ87xx-specific guards and replaced magic values with named macros - Rebased on Linux v7.0-rc1 - Link to v1: https://patch.msgid.link/20260326-ksz87xx_errata_low_loss_con= nections-v1-0-79a698f43626@exotec.com --- drivers/net/dsa/microchip/ksz8.c | 33 ++++++++++++++++++++++++++++++= +++ drivers/net/dsa/microchip/ksz8_reg.h | 20 +++++++++++++++++++- drivers/net/dsa/microchip/ksz_common.h | 3 +++ 3 files changed, 55 insertions(+), 1 deletion(-) diff --git a/drivers/net/dsa/microchip/ksz8.c b/drivers/net/dsa/microchip/k= sz8.c index c354abdafc1b..d11da6e9ff54 100644 --- a/drivers/net/dsa/microchip/ksz8.c +++ b/drivers/net/dsa/microchip/ksz8.c @@ -1058,6 +1058,11 @@ int ksz8_r_phy(struct ksz_device *dev, u16 phy, u16 = reg, u16 *val) if (ret) return ret; =20 + break; + case PHY_REG_KSZ87XX_LOW_LOSS: + if (!ksz_is_ksz87xx(dev)) + return -EOPNOTSUPP; + data =3D dev->low_loss_wa_mode; break; default: processed =3D false; @@ -1271,6 +1276,34 @@ int ksz8_w_phy(struct ksz_device *dev, u16 phy, u16 = reg, u16 val) if (ret) return ret; break; + case PHY_REG_KSZ87XX_LOW_LOSS: + if (!ksz_is_ksz87xx(dev)) + return -EOPNOTSUPP; + + switch (val & PHY_KSZ87XX_LOW_LOSS_MASK) { + case PHY_LOW_LOSS_ERRATA_DISABLED: + ret =3D ksz8_ind_write8(dev, TABLE_LINK_MD, KSZ87XX_REG_EQ_TRAIN, + KSZ87XX_EQ_TRAIN_DEFAULT); + if (!ret) + ret =3D ksz8_ind_write8(dev, TABLE_LINK_MD, + KSZ87XX_REG_PHY_LPF, + KSZ87XX_PHY_LPF_DEFAULT); + break; + case KSZ87XX_LOW_LOSS_WA_EQ: + ret =3D ksz8_ind_write8(dev, TABLE_LINK_MD, KSZ87XX_REG_EQ_TRAIN, + KSZ87XX_EQ_TRAIN_LOW_LOSS); + break; + case KSZ87XX_LOW_LOSS_WA_LPF: + ret =3D ksz8_ind_write8(dev, TABLE_LINK_MD, KSZ87XX_REG_PHY_LPF, + KSZ87XX_PHY_LPF_62MHZ); + break; + default: + return -EINVAL; + } + + if (!ret) + dev->low_loss_wa_mode =3D val & PHY_KSZ87XX_LOW_LOSS_MASK; + return ret; default: break; } diff --git a/drivers/net/dsa/microchip/ksz8_reg.h b/drivers/net/dsa/microch= ip/ksz8_reg.h index 332408567b47..cd1092aa0eaf 100644 --- a/drivers/net/dsa/microchip/ksz8_reg.h +++ b/drivers/net/dsa/microchip/ksz8_reg.h @@ -202,6 +202,10 @@ #define REG_PORT_3_STATUS_0 0x38 #define REG_PORT_4_STATUS_0 0x48 =20 +/* KSZ87xx LinkMD registers (TABLE_LINK_MD_V) */ +#define KSZ87XX_REG_EQ_TRAIN 0x3C +#define KSZ87XX_REG_PHY_LPF 0x4C + /* For KSZ8765. */ #define PORT_REMOTE_ASYM_PAUSE BIT(5) #define PORT_REMOTE_SYM_PAUSE BIT(4) @@ -342,7 +346,7 @@ #define TABLE_EEE (TABLE_EEE_V << TABLE_EXT_SELECT_S) #define TABLE_ACL (TABLE_ACL_V << TABLE_EXT_SELECT_S) #define TABLE_PME (TABLE_PME_V << TABLE_EXT_SELECT_S) -#define TABLE_LINK_MD (TABLE_LINK_MD << TABLE_EXT_SELECT_S) +#define TABLE_LINK_MD (TABLE_LINK_MD_V << TABLE_EXT_SELECT_S) #define TABLE_READ BIT(4) #define TABLE_SELECT_S 2 #define TABLE_STATIC_MAC_V 0 @@ -729,6 +733,20 @@ #define PHY_POWER_SAVING_ENABLE BIT(2) #define PHY_REMOTE_LOOPBACK BIT(1) =20 +/* Equalizer low-loss workaround */ +/* bits [1:0]: 00 =3D disabled, 01 =3D workaround 1, 10 =3D workaround 2 */ +#define PHY_REG_KSZ87XX_LOW_LOSS 0x1C +#define PHY_KSZ87XX_LOW_LOSS_MASK GENMASK(1, 0) + +#define PHY_LOW_LOSS_ERRATA_DISABLED 0 +#define KSZ87XX_LOW_LOSS_WA_EQ 1 +#define KSZ87XX_LOW_LOSS_WA_LPF 2 + +#define KSZ87XX_EQ_TRAIN_DEFAULT 0x0A +#define KSZ87XX_EQ_TRAIN_LOW_LOSS 0x15 +#define KSZ87XX_PHY_LPF_DEFAULT 0x00 +#define KSZ87XX_PHY_LPF_62MHZ 0x40 + /* KSZ8463 specific registers. */ #define P1MBCR 0x4C #define P1MBSR 0x4E diff --git a/drivers/net/dsa/microchip/ksz_common.h b/drivers/net/dsa/micro= chip/ksz_common.h index 929aff4c55de..729996c7160c 100644 --- a/drivers/net/dsa/microchip/ksz_common.h +++ b/drivers/net/dsa/microchip/ksz_common.h @@ -219,6 +219,9 @@ struct ksz_device { * the switch=E2=80=99s internal PHYs, bypassing the main SPI interface. */ struct mii_bus *parent_mdio_bus; + + /* Equalizer low-loss workaround tunable */ + u8 low_loss_wa_mode; /* bits [1:0]: 00 =3D disabled, 01 =3D workaround 1,= 10 =3D workaround 2 */ }; =20 /* List of supported models */ --- base-commit: 2d1373e4246da3b58e1df058374ed6b101804e07 change-id: 20260323-ksz87xx_errata_low_loss_connections-b65e76e2b403 Best regards, -- =20 Fidelio Lawson