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Signed-off-by: Josua Mayer Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/fsl.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation= /devicetree/bindings/arm/fsl.yaml index 5716d701292cf..c7a885159318f 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1376,6 +1376,13 @@ properties: - fsl,imx8dxl-evk # i.MX8DXL EVK Board - const: fsl,imx8dxl =20 + - description: SolidRun i.MX8DXL SoM based boards + items: + - enum: + - solidrun,imx8dxl-hummingboard-telematics # SolidRun i.MX8D= XL SoM EVK Board + - const: solidrun,imx8dxl-sr-som + - const: fsl,imx8dxl + - description: i.MX8QXP/i.MX8DX Boards with Toradex Colibri iMX8X Mo= dules items: - enum: --=20 2.51.0 From nobody Mon Jun 15 07:35:32 2026 Received: from AS8PR04CU009.outbound.protection.outlook.com (mail-westeuropeazon11021094.outbound.protection.outlook.com [52.101.70.94]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DD80C3D4134; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: dJyN6uLI2DoqnB4N5mZCp+56eVY6+dtUybasw1bsRekn++ikJqneY+6A2D5FSfKq2P6Tf0zlSVgcf5Ut5BTRcU/iiBSnpYx1kOj/59xA3R0L+jZeZ6S2g6dj1XCDUbVAqFzN7GdmftkrsXGFYoqe8ZrUL7HRXLbZIU/N0qIEwuKr8y0d8NL8OudqmlrlIR7a3oX1orjoUNm94iRRm4WcnQUbAh7bIKxTwYvWMX9WDiWcXc4g92hhyUyVzHd/O3XLIiDGHuOUGdgbMLIssvodEqMoXIwj87rF1GI1doHj9gvXF12swVQtm8G7fvoCkwK5mArmJPeM6R61RF3g4C+CJCoDpwvO2ACMGqNBRi6pXAckIRNSiav800n/At0nGIEOrccDIwFlXUqlsIC314PKQ+gp+CxTf8lay68Mlehcm9uPHP+AYOBDnV5Ng/rTlg8j X-OriginatorOrg: solid-run.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Apr 2026 18:38:56.3953 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2af2aa1d-99eb-43ea-4374-08de959e1782 X-MS-Exchange-CrossTenant-Id: a4a8aaf3-fd27-4e27-add2-604707ce5b82 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=a4a8aaf3-fd27-4e27-add2-604707ce5b82;Ip=[52.17.62.50];Helo=[eu-dlp.cloud-sec-av.com] X-MS-Exchange-CrossTenant-AuthSource: AMS1EPF0000004A.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB9PR04MB11661 Add support for the SolidRun i.MX8DXL System-on-Module (revision 2.1) and its corresponding evaluation carrier board, the HummingBoard Telematics (revision 2.0). The SoM features: - eMMC - GNSS with 1PPS - V2X DSRC Radio - Secure Element for V2X Applications - Inertial Sensor - Pressure Sensor - Compass The HummingBoard Telematics carrier board features: - Cellular Modem - WiFi & Bluetooth - RTC with backup battery - CAN - 100Base-TX Ethernet - 100Base-T1 Ethernet - Multi-interface I/O connector - Multi-interface add-on board connector The multi-interface I/O connector supplies power and provides basic I/O (Console UART, 100Base-TX, 100Base-T1, CAN, and power-supply logic level GPIOs). The SolidRun Evaluation Kit includes a suitable cable and adapter board that breaks these out into RJ45, USB Type-A, microUSB Console, and Terminal Block connectors. The multi-interface add-on board connector provides additional interfaces (4x 100Base-T1, 2x SGMII, USB 2.0 shared with the cellular modem, CAN, MDIO, SPI, UART, PCIe, I2C, and GPIO). These add-on interfaces are disabled by default in the base device tree and are intended to be enabled and extended via device tree overlays. Note that a few components physically present on the SoM were omitted from this description due to a lack of upstream bindings and drivers: - Pressure Sensor - V2X DSRC Radio - Secure Element Signed-off-by: Josua Mayer --- arch/arm64/boot/dts/freescale/Makefile | 2 + .../freescale/imx8dxl-hummingboard-telematics.dts | 536 +++++++++++++++++= ++++ arch/arm64/boot/dts/freescale/imx8dxl-sr-som.dtsi | 460 ++++++++++++++++++ arch/arm64/boot/dts/freescale/imx8mp-sr-som.dtsi | 1 - 4 files changed, 998 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/f= reescale/Makefile index 700bab4d3e600..12b946c08400b 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -111,6 +111,8 @@ dtb-$(CONFIG_ARCH_MXC) +=3D imx8dxl-evk.dtb =20 imx8dxl-evk-pcie-ep-dtbs +=3D imx8dxl-evk.dtb imx-pcie0-ep.dtbo dtb-$(CONFIG_ARCH_MXC) +=3D imx8dxl-evk-pcie-ep.dtb +DTC_FLAGS_imx8dxl-hummingboard-telematics :=3D -@ +dtb-$(CONFIG_ARCH_MXC) +=3D imx8dxl-hummingboard-telematics.dtb =20 dtb-$(CONFIG_ARCH_MXC) +=3D imx8dxp-tqma8xdp-mba8xx.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8dxp-tqma8xdps-mb-smarc-2.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-hummingboard-telematics.= dts b/arch/arm64/boot/dts/freescale/imx8dxl-hummingboard-telematics.dts new file mode 100644 index 0000000000000..ad2371f3c2632 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dxl-hummingboard-telematics.dts @@ -0,0 +1,536 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022-2026 Josua Mayer + */ + +/dts-v1/; + +#include "imx8dxl-sr-som.dtsi" + +/ { + compatible =3D "solidrun,imx8dxl-hummingboard-telematics", + "solidrun,imx8dxl-sr-som", "fsl,imx8dxl"; + model =3D "SolidRun i.MX8DXL HummingBoard Telematics"; + + aliases { + /* override ethernat aliases from imx8dxl.dtsi */ + ethernet0 =3D &eqos; + /delete-property/ ethernet1; + gpio8 =3D &tca6408_u2; + mmc2 =3D &usdhc3; + rtc0 =3D &carrier_rtc; + rtc1 =3D &rtc; + serial1 =3D &lpuart1; + }; + + v_1_1: regulator-1-1 { + compatible =3D "regulator-fixed"; + regulator-name =3D "1v1"; + pinctrl-0 =3D <®ulator_1v1_pins>; + pinctrl-names =3D "default"; + regulator-always-on; + regulator-max-microvolt =3D <1100000>; + regulator-min-microvolt =3D <1100000>; + vin-supply =3D <&v_5_0>; + gpio =3D <&lsio_gpio4 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + v_5_0: regulator-5-0 { + compatible =3D "regulator-fixed"; + regulator-name =3D "5v0"; + regulator-max-microvolt =3D <5000000>; + regulator-min-microvolt =3D <5000000>; + }; + + /* can transceiver builtin regulator (STBN1 pin) */ + reg_flexcan1_stby: regulator-flexcan1-standby { + compatible =3D "regulator-fixed"; + regulator-name =3D "flexcan1-standby"; + regulator-max-microvolt =3D <3300000>; + regulator-min-microvolt =3D <3300000>; + gpio =3D <&tca6408_u2 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + /* can transceiver builtin regulator (STBN2 pin) */ + reg_flexcan2_stby: regulator-flexcan2-standby { + compatible =3D "regulator-fixed"; + regulator-name =3D "flexcan2-standby"; + regulator-max-microvolt =3D <3300000>; + regulator-min-microvolt =3D <3300000>; + gpio =3D <&tca6408_u2 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + modem_vbat: regulator-modem-vbat { + compatible =3D "regulator-fixed"; + regulator-name =3D "vbat"; + pinctrl-0 =3D <®ulator_modem_vbat_pins>; + pinctrl-names =3D "default"; + regulator-max-microvolt =3D <3600000>; + regulator-min-microvolt =3D <3600000>; + vin-supply =3D <&v_5_0>; + gpio =3D <&lsio_gpio0 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vbus1: regulator-vbus-1 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vbus1"; + pinctrl-0 =3D <®ulator_usb1_vbus_pins>; + pinctrl-names =3D "default"; + regulator-max-microvolt =3D <5000000>; + regulator-min-microvolt =3D <5000000>; + gpio =3D <&lsio_gpio0 16 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + usdhc3_pwrseq: usdhc3-pwrseq { + compatible =3D "mmc-pwrseq-simple"; + reset-gpios =3D <&lsio_gpio0 15 GPIO_ACTIVE_LOW>; + }; +}; + +&dma_apbh { + status =3D "disabled"; +}; + +&eqos { + phy-mode =3D "rgmii-id"; + pinctrl-0 =3D <&eqos_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; + + fixed-link { + full-duplex; + speed =3D <1000>; + }; +}; + +&flexcan1 { + pinctrl-0 =3D <&flexcan1_pins>; + pinctrl-names =3D "default"; + xceiver-supply =3D <®_flexcan1_stby>; + status =3D "okay"; + + can-transceiver { + max-bitrate =3D <5000000>; + }; +}; + +&flexcan2 { + pinctrl-0 =3D <&flexcan2_pins>; + pinctrl-names =3D "default"; + xceiver-supply =3D <®_flexcan2_stby>; + status =3D "okay"; + + can-transceiver { + max-bitrate =3D <5000000>; + }; +}; + +&i2c2 { + /* routed to J14: SDA(51), SCL(53) */ + + /* regulator@18 */ + + tca6408_u2: gpio@20 { + compatible =3D "ti,tca6408"; + reg =3D <0x20>; + #interrupt-cells =3D <2>; + interrupt-controller; + #gpio-cells =3D <2>; + gpio-controller; + gpio-line-names =3D "DIG_IN1", "DIG_IN2", "CAN_STNB1", "CAN_STNB2", + "DIG_OUT1", "DIG_OUT2", "", ""; + interrupts-extended =3D <&lsio_gpio0 20 IRQ_TYPE_EDGE_FALLING>; + pinctrl-0 =3D <&tca6408_u2_int_pins>; + pinctrl-names =3D "default"; + }; + + carrier_rtc: rtc@32 { + compatible =3D "epson,rx8111"; + reg =3D <0x32>; + }; +}; + +&iomuxc { + bluetooth_pins: pinctrl-bluetooth-grp { + fsl,pins =3D < + /* BT_REG_ON: io without pull (module integrates pd) */ + IMX8DXL_SPI3_SCK_LSIO_GPIO0_IO13 0x0000061 + >; + }; + + eqos_pins: pinctrl-eqos-grp { + fsl,pins =3D < + /* MDIO to Switch */ + /* enet0 mdio pads supplied with 3.3v */ + /* IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIOCT */ + IMX8DXL_ENET0_MDC_CONN_EQOS_MDC 0x06000020 + IMX8DXL_ENET0_MDIO_CONN_EQOS_MDIO 0x06000020 + /* RGMII to Switch */ + IMX8DXL_ENET1_RGMII_TX_CTL_CONN_EQOS_RGMII_TX_CTL 0x06000020 + IMX8DXL_ENET1_RGMII_TXC_CONN_EQOS_RGMII_TXC 0x06000020 + IMX8DXL_ENET1_RGMII_TXD0_CONN_EQOS_RGMII_TXD0 0x06000020 + IMX8DXL_ENET1_RGMII_TXD1_CONN_EQOS_RGMII_TXD1 0x06000020 + IMX8DXL_ENET1_RGMII_TXD2_CONN_EQOS_RGMII_TXD2 0x06000020 + IMX8DXL_ENET1_RGMII_TXD3_CONN_EQOS_RGMII_TXD3 0x06000020 + IMX8DXL_ENET1_RGMII_RXC_CONN_EQOS_RGMII_RXC 0x06000020 + IMX8DXL_ENET1_RGMII_RX_CTL_CONN_EQOS_RGMII_RX_CTL 0x06000020 + IMX8DXL_ENET1_RGMII_RXD0_CONN_EQOS_RGMII_RXD0 0x06000020 + IMX8DXL_ENET1_RGMII_RXD1_CONN_EQOS_RGMII_RXD1 0x06000020 + IMX8DXL_ENET1_RGMII_RXD2_CONN_EQOS_RGMII_RXD2 0x06000020 + IMX8DXL_ENET1_RGMII_RXD3_CONN_EQOS_RGMII_RXD3 0x06000020 + >; + }; + + flexcan1_pins: pinctrl-flexcan1-grp { + fsl,pins =3D < + IMX8DXL_FLEXCAN0_TX_ADMA_FLEXCAN0_TX 0x00000021 + IMX8DXL_FLEXCAN0_RX_ADMA_FLEXCAN0_RX 0x00000021 + >; + }; + + flexcan2_pins: pinctrl-flexcan2-grp { + fsl,pins =3D < + IMX8DXL_FLEXCAN1_TX_ADMA_FLEXCAN1_TX 0x00000021 + IMX8DXL_FLEXCAN1_RX_ADMA_FLEXCAN1_RX 0x00000021 + >; + }; + + lpspi0_pins: pinctrl-lpspi0-grp { + fsl,pins =3D < + IMX8DXL_SPI0_SCK_ADMA_SPI0_SCK 0x600004c + IMX8DXL_SPI0_SDO_ADMA_SPI0_SDO 0x600004c + IMX8DXL_SPI0_SDI_ADMA_SPI0_SDI 0x600004c + IMX8DXL_SPI0_CS0_LSIO_GPIO1_IO08 0x0000021 + IMX8DXL_SPI0_CS1_LSIO_GPIO1_IO07 0x0000021 + >; + }; + + lpuart1_pins: pinctrl-lpuart1-grp { + fsl,pins =3D < + IMX8DXL_UART1_RX_ADMA_UART1_RX 0x06000020 + IMX8DXL_UART1_TX_ADMA_UART1_TX 0x06000020 + IMX8DXL_UART1_CTS_B_ADMA_UART1_CTS_B 0x06000020 + IMX8DXL_UART1_RTS_B_ADMA_UART1_RTS_B 0x06000020 + >; + }; + + modem_pins: pinctrl-lte-grp { + fsl,pins =3D < + /* modem RESET_N: io open drain drive 2mA */ + IMX8DXL_ADC_IN3_LSIO_GPIO1_IO11 0x2000061 + + /* modem PWRKEY: io open drain with pull-up, drive 2mA */ + IMX8DXL_ADC_IN2_LSIO_GPIO1_IO12 0x2000021 + >; + }; + + regulator_1v1_pins: pinctrl-regulator-1-1-grp { + fsl,pins =3D < + /* SW_PE: io without pull-up */ + IMX8DXL_USB_SS3_TC2_LSIO_GPIO4_IO05 0x0000061 + >; + }; + + regulator_modem_vbat_pins: pinctrl-regulator-modem-vbat-grp { + fsl,pins =3D < + /* + * RF_PWR: io without pull-up, + * has either external pull-up (R1117) or pull-down (R1118). + * With pull-up Modem will boot at system power-up, + * with pull-down modem will enter power-down mode once + * vbat is enabled -> toggle pwrkey to boot modem. + * Hence pull-up (R1117) is preferred. + */ + IMX8DXL_SPI3_SDO_LSIO_GPIO0_IO14 0x0000061 + >; + }; + + regulator_usb1_vbus_pins: pinctrl-regulator-usb1-vbus-grp { + fsl,pins =3D < + /* regulator enable: open-drain with pull-up & low drive strength */ + IMX8DXL_SPI3_CS0_LSIO_GPIO0_IO16 0x2000021 + >; + }; + + switch_pins: pinctrl-switch-grp { + fsl,pins =3D < + /* SW_RSTn: io without pull-up */ + IMX8DXL_USB_SS3_TC0_LSIO_GPIO4_IO03 0x0000021 + + /* SW_CORE_RSTn: io without pull-up */ + IMX8DXL_USB_SS3_TC1_LSIO_GPIO4_IO04 0x0000021 + + /* INT_N: io without pull-up */ + IMX8DXL_USB_SS3_TC3_LSIO_GPIO4_IO06 0x0000021 + >; + }; + + tca6408_u2_int_pins: pinctrl-tca6408-u2-int-grp { + fsl,pins =3D < + /* gpio-expander interrupt: io with pull-up */ + IMX8DXL_MCLK_OUT0_LSIO_GPIO0_IO20 0x0000021 + >; + }; + + usdhc3_pins: pinctrl-usdhc3-grp { + fsl,pins =3D < + IMX8DXL_ENET0_RGMII_TXC_CONN_USDHC2_CLK 0x06000040 + IMX8DXL_ENET0_RGMII_TX_CTL_CONN_USDHC2_CMD 0x00000021 + IMX8DXL_ENET0_RGMII_TXD0_CONN_USDHC2_DATA0 0x00000021 + IMX8DXL_ENET0_RGMII_TXD1_CONN_USDHC2_DATA1 0x00000021 + IMX8DXL_ENET0_RGMII_TXD2_CONN_USDHC2_DATA2 0x00000021 + IMX8DXL_ENET0_RGMII_TXD3_CONN_USDHC2_DATA3 0x00000021 + >; + }; + + wifi_pins: pinctrl-wifi-grp { + fsl,pins =3D < + /* WL_REG_ON: io without pull (module integrates pd) */ + IMX8DXL_SPI3_SDI_LSIO_GPIO0_IO15 0x0000061 + >; + }; +}; + +&lpspi0 { + cs-gpios =3D <&lsio_gpio1 8 GPIO_ACTIVE_LOW>, <&lsio_gpio1 7 GPIO_ACTIVE_= LOW>; + pinctrl-0 =3D <&lpspi0_pins>, <&switch_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; + + ethernet-switch@0 { + compatible =3D "nxp,sja1110a"; + reg =3D <0>; + reset-gpios =3D <&lsio_gpio4 3 GPIO_ACTIVE_LOW>; + spi-cpol; + spi-max-frequency =3D <4000000>; + + ethernet-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + /* to 100Base-TX on connector J26 */ + port@1 { + reg =3D <0x1>; + label =3D "lan1"; + phy-handle =3D <&switch_port1_base_tx_phy>; + phy-mode =3D "internal"; + status =3D "okay"; + }; + + /* to CPU */ + port@2 { + reg =3D <0x2>; + ethernet =3D <&eqos>; + label =3D "cpu"; + phy-mode =3D "rgmii-id"; + rx-internal-delay-ps =3D <2000>; + tx-internal-delay-ps =3D <2000>; + status =3D "okay"; + + fixed-link { + full-duplex; + speed =3D <1000>; + }; + }; + + /* sgmii on addon board connector J21 */ + port@3 { + reg =3D <0x3>; + label =3D "lan3"; + status =3D "disabled"; + }; + + /* sgmii on addon board connector J21 */ + port@4 { + reg =3D <0x4>; + label =3D "lan4"; + status =3D "disabled"; + }; + + /* 100base-t1 on addon board connector J21 */ + port@5 { + reg =3D <0x5>; + label =3D "trx1"; + phy-handle =3D <&switch_port5_base_t1_phy>; + phy-mode =3D "internal"; + status =3D "disabled"; + }; + + /* 100base-t1 on addon board connector J21 */ + port@6 { + reg =3D <0x6>; + label =3D "trx2"; + phy-handle =3D <&switch_port6_base_t1_phy>; + phy-mode =3D "internal"; + status =3D "disabled"; + }; + + /* 100base-t1 on addon board connector J21 */ + port@7 { + reg =3D <0x7>; + label =3D "trx3"; + phy-handle =3D <&switch_port7_base_t1_phy>; + phy-mode =3D "internal"; + status =3D "disabled"; + }; + + /* 100base-t1 on addon board connector J21 */ + port@8 { + reg =3D <0x8>; + label =3D "trx4"; + phy-handle =3D <&switch_port8_base_t1_phy>; + phy-mode =3D "internal"; + status =3D "disabled"; + }; + + /* 100base-t1 on addon board connector J21 */ + port@9 { + reg =3D <0x9>; + label =3D "trx5"; + phy-handle =3D <&switch_port9_base_t1_phy>; + phy-mode =3D "internal"; + status =3D "disabled"; + }; + + /* 100Base-T1 on connector J26 */ + port@a { + reg =3D <0xa>; + label =3D "trx6"; + phy-handle =3D <&switch_port10_base_t1_phy>; + phy-mode =3D "internal"; + status =3D "okay"; + }; + }; + + mdios { + #address-cells =3D <1>; + #size-cells =3D <0>; + + mdio@0 { + compatible =3D "nxp,sja1110-base-t1-mdio"; + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + /* 100base-t1 on addon board connector J21 */ + switch_port5_base_t1_phy: ethernet-phy@1 { + compatible =3D "ethernet-phy-ieee802.3-c45"; + reg =3D <0x1>; + status =3D "disabled"; + }; + + /* 100base-t1 on addon board connector J21 */ + switch_port6_base_t1_phy: ethernet-phy@2 { + compatible =3D "ethernet-phy-ieee802.3-c45"; + reg =3D <0x2>; + status =3D "disabled"; + }; + + /* 100base-t1 on addon board connector J21 */ + switch_port7_base_t1_phy: ethernet-phy@3 { + compatible =3D "ethernet-phy-ieee802.3-c45"; + reg =3D <0x3>; + status =3D "disabled"; + }; + + /* 100base-t1 on addon board connector J21 */ + switch_port8_base_t1_phy: ethernet-phy@4 { + compatible =3D "ethernet-phy-ieee802.3-c45"; + reg =3D <0x4>; + status =3D "disabled"; + }; + + /* 100base-t1 on addon board connector J21 */ + switch_port9_base_t1_phy: ethernet-phy@5 { + compatible =3D "ethernet-phy-ieee802.3-c45"; + reg =3D <0x5>; + status =3D "disabled"; + }; + + /* 100Base-T1 on connector J26 */ + switch_port10_base_t1_phy: ethernet-phy@6 { + compatible =3D "ethernet-phy-ieee802.3-c45"; + reg =3D <0x6>; + }; + }; + + mdio@1 { + compatible =3D "nxp,sja1110-base-tx-mdio"; + reg =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + /* to 100Base-TX on connector J26 */ + switch_port1_base_tx_phy: ethernet-phy@1 { + reg =3D <0x1>; + }; + }; + }; + }; +}; + +/* bluetooth */ +&lpuart1 { + pinctrl-0 =3D <&lpuart1_pins>, <&bluetooth_pins>; + pinctrl-names =3D "default"; + uart-has-rtscts; + status =3D "okay"; + + bluetooth { + compatible =3D "brcm,bcm4345c5"; + /* Murata 1MW module supports max. 3M baud */ + max-speed =3D <3000000>; + shutdown-gpios =3D <&lsio_gpio0 13 GPIO_ACTIVE_HIGH>; + }; +}; + +&usbotg1 { + vbus-supply =3D <&vbus1>; +}; + +/* cellular modem */ +&usbotg2 { + #address-cells =3D <1>; + #size-cells =3D <0>; + adp-disable; + disable-over-current; + dr_mode =3D "host"; + hnp-disable; + pinctrl-0 =3D <&modem_pins>; + pinctrl-names =3D "default"; + power-active-high; + srp-disable; + vbus-supply =3D <&v_5_0>; + status =3D "okay"; + + usb-device@1 { + compatible =3D "usb2c7c,125"; + reg =3D <1>; + reset-duration-us =3D <150000>; + reset-gpios =3D <&lsio_gpio1 11 GPIO_ACTIVE_LOW>; + vbus-supply =3D <&v_3_3>; + vdd-supply =3D <&modem_vbat>; + }; +}; + +&usbphy2 { + status =3D "okay"; +}; + +/* WiFi */ +&usdhc3 { + bus-width =3D <4>; + mmc-pwrseq =3D <&usdhc3_pwrseq>; + non-removable; + no-sd; + pinctrl-0 =3D <&usdhc3_pins>, <&wifi_pins>; + pinctrl-names =3D "default"; + vmmc-supply =3D <&v_3_3>; + vqmmc-supply =3D <&v_1_8>; + status =3D "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-sr-som.dtsi b/arch/arm64= /boot/dts/freescale/imx8dxl-sr-som.dtsi new file mode 100644 index 0000000000000..d72e960c3e5e3 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dxl-sr-som.dtsi @@ -0,0 +1,460 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022-2026 Josua Mayer + */ + +#include "imx8dxl.dtsi" +/ { + compatible =3D "solidrun,imx8dxl-sr-som", "fsl,imx8dxl"; + model =3D "SolidRun i.MX8DXL SoM"; + + aliases { + i2c2 =3D &i2c2; + i2c3 =3D &i2c3; + mmc0 =3D &usdhc1; + mmc1 =3D &usdhc2; + serial0 =3D &lpuart0; + serial2 =3D &lpuart2; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + imx8dxl-cm4 { + compatible =3D "fsl,imx8qxp-cm4"; + clocks =3D <&clk_dummy>; + mboxes =3D <&lsio_mu5 0 1 &lsio_mu5 1 1 &lsio_mu5 3 1>; + mbox-names =3D "tx", "rx", "rxdb"; + memory-region =3D <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, + <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>; + power-domains =3D <&pd IMX_SC_R_M4_0_PID0>, <&pd IMX_SC_R_M4_0_MU_1A>; + fsl,entry-address =3D <0x34fe0000>; + fsl,resource-id =3D ; + }; + + pps { + compatible =3D "pps-gpio"; + gpios =3D <&lsio_gpio2 6 GPIO_ACTIVE_HIGH>; + pinctrl-0 =3D <&gnss_pps_pins>; + pinctrl-names =3D "default"; + }; + + v_1_2: regulator-1-2 { + compatible =3D "regulator-fixed"; + regulator-name =3D "1v2"; + pinctrl-0 =3D <®ulator_1_2_pins>; + pinctrl-names =3D "default"; + regulator-always-on; + regulator-max-microvolt =3D <1200000>; + regulator-min-microvolt =3D <1200000>; + gpio =3D <&lsio_gpio1 13 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + v_1_6: regulator-1-6 { + compatible =3D "regulator-fixed"; + regulator-name =3D "1v6"; + pinctrl-0 =3D <®ulator_1_6_pins>; + pinctrl-names =3D "default"; + regulator-always-on; + regulator-max-microvolt =3D <1600000>; + regulator-min-microvolt =3D <1600000>; + vin-supply =3D <&v_1_8>; + gpio =3D <&lsio_gpio1 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + v_1_8: regulator-1-8 { + compatible =3D "regulator-fixed"; + regulator-name =3D "1v8"; + regulator-max-microvolt =3D <1800000>; + regulator-min-microvolt =3D <1800000>; + }; + + v_1_8_se: regulator-1-8-secure-element { + compatible =3D "regulator-fixed"; + regulator-name =3D "1v8-se"; + pinctrl-0 =3D <®ulator_1_8_se_pins>; + pinctrl-names =3D "default"; + regulator-max-microvolt =3D <1800000>; + regulator-min-microvolt =3D <1800000>; + vin-supply =3D <&v_1_8>; + gpio =3D <&lsio_gpio3 18 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + v_3_3: regulator-3-3 { + compatible =3D "regulator-fixed"; + regulator-name =3D "3v3"; + regulator-max-microvolt =3D <3300000>; + regulator-min-microvolt =3D <3300000>; + }; + + reserved-memory { + ranges; + #address-cells =3D <2>; + #size-cells =3D <2>; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible =3D "shared-dma-pool"; + alloc-ranges =3D <0 0x98000000 0 0x14000000>; + reusable; + size =3D <0 0x14000000>; + linux,cma-default; + }; + + vdev0vring0: memory0@90000000 { + reg =3D <0 0x90000000 0 0x8000>; + no-map; + }; + + vdev0vring1: memory@90008000 { + reg =3D <0 0x90008000 0 0x8000>; + no-map; + }; + + vdev1vring0: memory@90010000 { + reg =3D <0 0x90010000 0 0x8000>; + no-map; + }; + + vdev1vring1: memory@90018000 { + reg =3D <0 0x90018000 0 0x8000>; + no-map; + }; + + rsc_table: memory-rsc-table@900ff000 { + reg =3D <0 0x900ff000 0 0x1000>; + no-map; + }; + + vdevbuffer: memory-vdevbuffer@90400000 { + compatible =3D "shared-dma-pool"; + reg =3D <0 0x90400000 0 0x100000>; + no-map; + }; + + /* + * Memory reserved for optee usage. Please do not use. + * This will be automatically added to dtb if OP-TEE is installed. + * optee@96000000 { + * reg =3D <0 0x96000000 0 0x2000000>; + * no-map; + * }; + */ + }; + + memory@80000000 { + reg =3D <0x00000000 0x80000000 0 0x40000000>; + device_type =3D "memory"; + }; +}; + +&i2c2 { + #address-cells =3D <1>; + #size-cells =3D <0>; + clock-frequency =3D <100000>; + pinctrl-0 =3D <&i2c2_pins>; + pinctrl-1 =3D <&i2c2_gpio_pins>; + pinctrl-names =3D "default", "gpio"; + scl-gpios =3D <&lsio_gpio3 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios =3D <&lsio_gpio3 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status =3D "okay"; +}; + +&i2c3 { + #address-cells =3D <1>; + #size-cells =3D <0>; + clock-frequency =3D <100000>; + pinctrl-0 =3D <&i2c3_pins>; + pinctrl-1 =3D <&i2c3_gpio_pins>; + pinctrl-names =3D "default", "gpio"; + scl-gpios =3D <&lsio_gpio3 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios =3D <&lsio_gpio3 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status =3D "okay"; + + magnetometer@1e { + compatible =3D "st,iis2mdc"; + reg =3D <0x1e>; + interrupt-parent =3D <&lsio_gpio2>; + interrupts =3D <10 IRQ_TYPE_EDGE_RISING>; + pinctrl-0 =3D <&magnetometer_pins>; + pinctrl-names =3D "default"; + st,drdy-int-pin =3D <1>; + }; + + /* pressure-sensor@5c */ + + inertial-sensor@6b { + compatible =3D "st,ism330dhcx"; + reg =3D <0x6b>; + interrupt-parent =3D <&lsio_gpio2>; + interrupts =3D <11 IRQ_TYPE_EDGE_RISING>; + pinctrl-0 =3D <&imu_pins>; + pinctrl-names =3D "default"; + st,drdy-int-pin =3D <1>; + }; +}; + +&iomuxc { + pinctrl-0 =3D <&pinctrl_hog>; + pinctrl-names =3D "default"; + + pinctrl_hog: hoggrp { + fsl,pins =3D < + IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0 + IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHK_PAD 0x000014a0 + >; + }; + + dsrc_pins: pinctrl-dsrc-grp { + fsl,pins =3D < + /* reset: io without pull */ + IMX8DXL_ADC_IN0_LSIO_GPIO1_IO10 0x0000060 + + /* + * boot0: io without pull + * After reset, this pin selects radio boot media: + * - 0: flash spi + * - 1: slave sdio + * Once the firmware boots however, the radio controls + * this pin for flow-control to signal readiness. + */ + IMX8DXL_ADC_IN1_LSIO_GPIO1_IO09 0x0000060 + >; + }; + + gnss_pins: pinctrl-gnss-grp { + fsl,pins =3D < + /* gps reset: input with pull-up */ + IMX8DXL_SNVS_TAMPER_OUT4_LSIO_GPIO2_IO08_IN 0x0000021 + /* gps interrupt: io without pull-up */ + IMX8DXL_SNVS_TAMPER_IN0_LSIO_GPIO2_IO09_IN 0x0000061 + >; + }; + + gnss_pps_pins: pinctrl-gnss-pps-grp { + fsl,pins =3D < + /* gps timepulse: input without pull-up */ + IMX8DXL_SNVS_TAMPER_OUT2_LSIO_GPIO2_IO06_IN 0x0000061 + >; + }; + + i2c2_gpio_pins: pinctrl-i2c2-gpio-grp { + fsl,pins =3D < + /* io with pull-up and weak drive */ + IMX8DXL_SPI1_SCK_LSIO_GPIO3_IO00 0x00000021 + /* io with pull-up, weak drive, open-drain */ + IMX8DXL_SPI1_SDO_LSIO_GPIO3_IO01 0x02000021 + >; + }; + + i2c2_pins: pinctrl-i2c2-grp { + fsl,pins =3D < + /* io with pull-up and weak drive */ + IMX8DXL_SPI1_SCK_ADMA_I2C2_SDA 0x06000021 + IMX8DXL_SPI1_SDO_ADMA_I2C2_SCL 0x06000021 + >; + }; + + i2c3_gpio_pins: pinctrl-i2c3-gpio-grp { + fsl,pins =3D < + /* io with pull-up and weak drive */ + IMX8DXL_SPI1_CS0_LSIO_GPIO3_IO03 0x00000021 + /* io with pull-up, weak drive, open-drain */ + IMX8DXL_SPI1_SDI_LSIO_GPIO3_IO02 0x02000021 + >; + }; + + i2c3_pins: pinctrl-i2c3-grp { + fsl,pins =3D < + /* io with pull-up and weak drive */ + IMX8DXL_SPI1_CS0_ADMA_I2C3_SDA 0x06000021 + IMX8DXL_SPI1_SDI_ADMA_I2C3_SCL 0x06000021 + >; + }; + + imu_pins: pinctrl-imu-grp { + fsl,pins =3D < + /* interrupt: io with pull-down */ + IMX8DXL_SNVS_TAMPER_IN2_LSIO_GPIO2_IO11_IN 0x0000041 + >; + }; + + lpspi2_pins: pinctrl-lpspi2-grp { + fsl,pins =3D < + IMX8DXL_USDHC1_RESET_B_ADMA_SPI2_SCK 0x600004c + IMX8DXL_USDHC1_VSELECT_ADMA_SPI2_SDO 0x600004c + IMX8DXL_USDHC1_WP_ADMA_SPI2_SDI 0x600004c + IMX8DXL_USDHC1_CD_B_LSIO_GPIO4_IO22 0x6000021 + >; + }; + + lpuart0_pins: pinctrl-lpuart0-grp { + fsl,pins =3D < + IMX8DXL_UART0_RX_ADMA_UART0_RX 0x06000020 + IMX8DXL_UART0_TX_ADMA_UART0_TX 0x06000020 + >; + }; + + lpuart2_pins: pinctrl-lpuart2-grp { + fsl,pins =3D < + IMX8DXL_UART2_TX_ADMA_UART2_TX 0x06000020 + IMX8DXL_UART2_RX_ADMA_UART2_RX 0x06000020 + >; + }; + + magnetometer_pins: pinctrl-magnetometer-grp { + fsl,pins =3D < + /* interrupt: io with pull-down */ + IMX8DXL_SNVS_TAMPER_IN1_LSIO_GPIO2_IO10_IN 0x0000041 + >; + }; + + regulator_1_2_pins: pinctrl-regulator-1-2-grp { + fsl,pins =3D < + /* io without pull-up */ + /* has etxernal pull-down */ + IMX8DXL_ADC_IN5_LSIO_GPIO1_IO13 0x0000061 + >; + }; + + regulator_1_6_pins: pinctrl-regulator-1-6-grp { + fsl,pins =3D < + /* io without pull-up */ + /* has etxernal pull-down */ + IMX8DXL_ADC_IN4_LSIO_GPIO1_IO14 0x0000061 + >; + }; + + regulator_1_8_se_pins: pinctrl-regulator-1-8-secure-element-grp { + fsl,pins =3D < + /* v2x-secure-element power switch: io with pull-down */ + IMX8DXL_QSPI0B_DATA0_LSIO_GPIO3_IO18 0x0000041 + >; + }; + + se_pins: pinctrl-secure-element-grp { + fsl,pins =3D < + /* v2x-secure-element reset: io with pull-up */ + IMX8DXL_QSPI0B_DATA1_LSIO_GPIO3_IO19 0x0000021 + + /* + * v2x-secure-element gpio0: io with pull-up + * pulled low by sxf after boot indicating ready for commands + */ + IMX8DXL_QSPI0B_DATA2_LSIO_GPIO3_IO20 0x0000021 + + /* v2x-secure-element gpio1: io with pull-up */ + IMX8DXL_QSPI0B_DATA3_LSIO_GPIO3_IO21 0x0000021 + >; + }; + + usdhc1_pins: pinctrl-usdhc1-grp { + fsl,pins =3D < + IMX8DXL_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + IMX8DXL_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + IMX8DXL_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + IMX8DXL_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + IMX8DXL_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + IMX8DXL_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + IMX8DXL_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + IMX8DXL_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + IMX8DXL_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + IMX8DXL_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + IMX8DXL_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + IMX8DXL_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000061 + >; + }; + + usdhc2_pins: pinctrl-usdhc2-grp { + fsl,pins =3D < + IMX8DXL_ENET0_RGMII_RXC_CONN_USDHC1_CLK 0x06000040 + IMX8DXL_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD 0x00000021 + IMX8DXL_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 0x00000021 + IMX8DXL_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 0x00000021 + IMX8DXL_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 0x00000021 + IMX8DXL_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 0x00000021 + >; + }; +}; + +&lpspi2 { + cs-gpios =3D <&lsio_gpio4 22 GPIO_ACTIVE_LOW>; + num-cs =3D <1>; + pinctrl-0 =3D <&lpspi2_pins>, <&se_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +/* console */ +&lpuart0 { + pinctrl-0 =3D <&lpuart0_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +/* gnss */ +&lpuart2 { + pinctrl-0 =3D <&lpuart2_pins>, <&gnss_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&lsio_gpio3 { + gpio-line-names =3D "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "SXF_RST", "SXF_GPIO0", "SXF_GPIO1", "", "", + "", "", "", "", "", "", "", ""; +}; + +&lsio_mu5 { + status =3D "okay"; +}; + +/* OTG port for boot */ +&usbotg1 { + adp-disable; + disable-over-current; + dr_mode =3D "peripheral"; + hnp-disable; + power-active-high; + srp-disable; + status =3D "okay"; +}; + +&usbphy1 { + status =3D "okay"; +}; + +/* eMMC */ +&usdhc1 { + bus-width =3D <8>; + cap-mmc-hw-reset; + non-removable; + no-sd; + no-sdio; + pinctrl-0 =3D <&usdhc1_pins>; + pinctrl-1 =3D <&usdhc1_pins>; + pinctrl-2 =3D <&usdhc1_pins>; + pinctrl-names =3D "default", "state_100mhz", "state_200mhz"; + vmmc-supply =3D <&v_3_3>; + vqmmc-supply =3D <&v_1_8>; + status =3D "okay"; +}; + +/* DSRC Radio */ +&usdhc2 { + bus-width =3D <4>; + keep-power-in-suspend; + max-frequency =3D <40000000>; + non-removable; + no-sd; + pinctrl-0 =3D <&usdhc2_pins>, <&dsrc_pins>; + pinctrl-names =3D "default"; + vmmc-supply =3D <&v_3_3>; + vqmmc-supply =3D <&v_1_8>; + status =3D "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-sr-som.dtsi b/arch/arm64/= boot/dts/freescale/imx8mp-sr-som.dtsi index 3cdb0bc0ab721..16d4280a1ae65 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-sr-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-sr-som.dtsi @@ -10,7 +10,6 @@ / { compatible =3D "solidrun,imx8mp-sr-som", "fsl,imx8mp"; =20 chosen { - bootargs =3D "earlycon=3Dec_imx6q,0x30890000,115200"; stdout-path =3D &uart2; }; =20 --=20 2.51.0