From nobody Thu Apr 9 01:10:43 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7BDB137E2FC; Wed, 8 Apr 2026 19:41:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775677287; cv=none; b=VyvRcposw6wgibAmm/TEbrfSSTgBYA4a25yT38peuwuyG7DZ/xrdWqCb8D1ji9URRFT4/b3dKJiEqzAZvCt130syh+DEB4mJIzsilHU1lmu72T7HyL+Mq7fhVfjT3L2gcIxC2d/rYcHh+6Hv0vgoSpHELMxzlcqfbEAlrIeRwUM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775677287; c=relaxed/simple; bh=owyYkRSPmgKR2r1SO/KyPS1mx+dKql64OAp/MSZ4IH8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=CWNVwTD6Ly48WboIlagsNWaBm/fOJuOMDybDbGATHjjJSwqiqje0Lx3GJ5wnkX0x/5Pv7gvgHY8XprcYr7vTA/M/URmhYfMjsCUj4k0cFYWKCD0YazSFmmo2hvu/jw1mUMc6UK0vFH9cL2yY2/12zYd61A3R4ZrQbc52Bb9GNC4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=jK9HWAZu; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="jK9HWAZu" Received: by smtp.kernel.org (Postfix) with ESMTPS id 18957C19425; Wed, 8 Apr 2026 19:41:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1775677287; bh=owyYkRSPmgKR2r1SO/KyPS1mx+dKql64OAp/MSZ4IH8=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=jK9HWAZutxNm4wukmsP+sTyza0TuJ5yg+pVFqkLkKkOu4IgZko47hjcID/z4QSQdh dZNVSe15dEtb0OFLi9nZT/rVcyVouubG3IczkTNKBwCJ3Q7WcuHamzk/DKbajNPePZ 7yrZnOOx5W7BynRlOxPxI5LoidEei1lFssPNbwibJ+HubvcDDRAoZoec7kYRemzYCb kO0iw0oYgVxAKEL4cJEyYzPxYnfJ0TWqtaHlO96Ov/fDXtrOt8yx48ynwwolugQTnE Xz58QghmQDCW2KrL8rsezjvw/rRvUFAl2v8ifKsHDd19kjgfi2TvF+ALeHWYohhARH 7SU32uulph1nQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0761C10F9972; Wed, 8 Apr 2026 19:41:27 +0000 (UTC) From: Aaron Kling via B4 Relay Date: Wed, 08 Apr 2026 14:41:24 -0500 Subject: [PATCH v5 1/6] dt-bindings: vendor-prefixes: Add AYN Technologies Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260408-ayn-qcs8550-v5-1-c90abeb7a152@gmail.com> References: <20260408-ayn-qcs8550-v5-0-c90abeb7a152@gmail.com> In-Reply-To: <20260408-ayn-qcs8550-v5-0-c90abeb7a152@gmail.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Aaron Kling , Xilin Wu , Krzysztof Kozlowski X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1775677286; l=950; i=webgeek1234@gmail.com; s=20250217; h=from:subject:message-id; bh=gOQhZByrG6tU19fKVlrU7N5RaAgEuR2DnSgZYTk4CCU=; b=qHLmbO+XOrMatwGjCrYbwNDhjZtq9AqhQtw4lLAEgY6nT+wuROFu3WyWlFG/61cbnQD/u+mWA 0DrMcSSWHsQCPvVJTpHvrjCKJB4x3Oqn6h1JLgik+z5UF6GARXC9t0+ X-Developer-Key: i=webgeek1234@gmail.com; a=ed25519; pk=TQwd6q26txw7bkK7B8qtI/kcAohZc7bHHGSD7domdrU= X-Endpoint-Received: by B4 Relay for webgeek1234@gmail.com/20250217 with auth_id=342 X-Original-From: Aaron Kling Reply-To: webgeek1234@gmail.com From: Xilin Wu Add an entry for AYN Technologies (https://www.ayntec.com/) Signed-off-by: Xilin Wu Acked-by: Krzysztof Kozlowski Signed-off-by: Aaron Kling --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Docum= entation/devicetree/bindings/vendor-prefixes.yaml index 28784d66ae7ba5..b891d6d41f198a 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -225,6 +225,8 @@ patternProperties: description: Axis Communications AB "^ayaneo,.*": description: Anyun Intelligent Technology (Hong Kong) Co., Ltd + "^ayntec,.*": + description: AYN Technologies Co., Ltd. "^azoteq,.*": description: Azoteq (Pty) Ltd "^azw,.*": --=20 2.53.0 From nobody Thu Apr 9 01:10:43 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7BD3037E2F3; Wed, 8 Apr 2026 19:41:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775677287; cv=none; b=L9k2RcpHuJvVGmb9RoyFSEFhA7pHxIZEp9UvKgS8jCtiQw7DYJmog5PKJkGa/HYpWRdMbSECnPrGATjkMTig7JX4vN1jeBxBYseVCCvsl6pCJR/IChMy+pEs5pV1avzuSI47m3oN6/Jmj89FKJJ9/vTxcLMwo6PaBdPhGNPCyBc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775677287; c=relaxed/simple; bh=1Y/LPpbwhO7cv9vEDbyRgvJvnMnKJWgfUgBbXdmBVdI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; 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Wed, 8 Apr 2026 19:41:27 +0000 (UTC) From: Aaron Kling via B4 Relay Date: Wed, 08 Apr 2026 14:41:25 -0500 Subject: [PATCH v5 2/6] dt-bindings: arm: qcom: Add AYN QCS8550 Devices Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260408-ayn-qcs8550-v5-2-c90abeb7a152@gmail.com> References: <20260408-ayn-qcs8550-v5-0-c90abeb7a152@gmail.com> In-Reply-To: <20260408-ayn-qcs8550-v5-0-c90abeb7a152@gmail.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Aaron Kling , Krzysztof Kozlowski X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1775677286; l=991; i=webgeek1234@gmail.com; s=20250217; h=from:subject:message-id; bh=2rGqOlPqgBo2SVV0is/nScu9jSlRs3IsGD1uogdg7P8=; b=g6se97QCpIRoYUkdGjzmz1JQNjjx0AfUFPWNn8++ljYditgTD39ZVdQN+pfTEUgH9nvVuJn+o +BomwZLzIbnD7bC36KQg+/HRhmzik9s69Dm1M2BCXk9g10W0tQz2BbK X-Developer-Key: i=webgeek1234@gmail.com; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260408-ayn-qcs8550-v5-3-c90abeb7a152@gmail.com> References: <20260408-ayn-qcs8550-v5-0-c90abeb7a152@gmail.com> In-Reply-To: <20260408-ayn-qcs8550-v5-0-c90abeb7a152@gmail.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Aaron Kling , Teguh Sobirin X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1775677286; l=40559; i=webgeek1234@gmail.com; s=20250217; h=from:subject:message-id; bh=KXfpyQrbmrdsqR0Mvw8ZjN7nEAxRJMl+WSD8yMWbR84=; b=M3I6e0pFjbQ3UHwlyBqLKiQUDviRE94C5/wJ4YMkQEelybGeMcB6EwrXxdSnOvlb9MPXC8dMX V3dQDYM+IYXDZmLIg2l6SHBD/piezNW8GurnNLufTFW20IOmDbB+Xmn X-Developer-Key: i=webgeek1234@gmail.com; a=ed25519; pk=TQwd6q26txw7bkK7B8qtI/kcAohZc7bHHGSD7domdrU= X-Endpoint-Received: by B4 Relay for webgeek1234@gmail.com/20250217 with auth_id=342 X-Original-From: Aaron Kling Reply-To: webgeek1234@gmail.com From: Teguh Sobirin This contains everything common between the AYN QCS8550 devices. It will be included by device specific dts'. Signed-off-by: Teguh Sobirin Co-developed-by: Aaron Kling Signed-off-by: Aaron Kling --- .../arm64/boot/dts/qcom/qcs8550-ayntec-common.dtsi | 1762 ++++++++++++++++= ++++ 1 file changed, 1762 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs8550-ayntec-common.dtsi b/arch/arm= 64/boot/dts/qcom/qcs8550-ayntec-common.dtsi new file mode 100644 index 00000000000000..e0befc8dc6dfdc --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qcs8550-ayntec-common.dtsi @@ -0,0 +1,1762 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2025, Teguh Sobirin. + */ + +#include +#include +#include "qcs8550.dtsi" +#include "pm8550.dtsi" +#include "pm8550b.dtsi" +#define PMK8550VE_SID 5 +#include "pm8550ve.dtsi" +#include "pm8550vs.dtsi" +#include "pmk8550.dtsi" + +/delete-node/ &aop_image_mem; +/delete-node/ &aop_config_mem; +/delete-node/ &camera_mem; +/delete-node/ &ipa_fw_mem; +/delete-node/ &ipa_gsi_mem; +/delete-node/ &mpss_dsm_mem; +/delete-node/ &mpss_mem; +/delete-node/ &q6_mpss_dtb_mem; +/delete-node/ &remoteproc_mpss; + +/ { + chassis-type =3D "handset"; + + aliases { + serial0 =3D &uart7; + serial1 =3D &uart14; + }; + + // The tzlog label is required by ABL to apply a dtbo, but it can be on a= ny node + qcom_tzlog: chosen { + stdout-path =3D "serial0:115200n8"; + }; + + gpio_keys: gpio-keys { + compatible =3D "gpio-keys"; + + pinctrl-0 =3D <&volume_up_n>; + pinctrl-names =3D "default"; + + key-volume-up { + label =3D "Volume Up"; + debounce-interval =3D <15>; + gpios =3D <&pm8550_gpios 6 GPIO_ACTIVE_LOW>; + linux,code =3D ; + linux,can-disable; + wakeup-source; + }; + }; + + pmic-glink { + compatible =3D "qcom,sm8550-pmic-glink", "qcom,pmic-glink"; + #address-cells =3D <1>; + #size-cells =3D <0>; + orientation-gpios =3D <&tlmm 11 GPIO_ACTIVE_HIGH>; + + connector@0 { + compatible =3D "usb-c-connector"; + reg =3D <0>; + power-role =3D "dual"; + data-role =3D "dual"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + pmic_glink_hs_in: endpoint { + remote-endpoint =3D <&usb_1_dwc3_hs>; + }; + }; + + port@1 { + reg =3D <1>; + + pmic_glink_ss_in: endpoint { + remote-endpoint =3D <&usb_dp_qmpphy_out>; + }; + }; + + port@2 { + reg =3D <2>; + + pmic_glink_sbu: endpoint { + remote-endpoint =3D <&usb0_sbu_mux>; + }; + }; + }; + }; + }; + + pwm_fan: pwm-fan { + compatible =3D "pwm-fan"; + + fan-supply =3D <&vdd_fan_5v0>; + pwms =3D <&pm8550_pwm 3 50000>; + + pinctrl-0 =3D <&fan_pwm_active>, <&fan_int>; + pinctrl-names =3D "default"; + + pulses-per-revolution =3D <4>; + interrupts-extended =3D <&tlmm 13 IRQ_TYPE_EDGE_FALLING>; + + cooling-levels =3D <0 40 65 75 90 100 120 150 175>; + #cooling-cells =3D <2>; + }; + + reserved-memory { + hyp_mem: hyp-region@80000000 { + reg =3D <0 0x80000000 0 0xa00000>; + no-map; + }; + + cpusys_vm_mem: cpusys-vm-region@80a00000 { + reg =3D <0 0x80a00000 0 0x400000>; + no-map; + }; + + hyp_tags_mem: hyp-tags-region@80e00000 { + reg =3D <0 0x80e00000 0 0x3d0000>; + no-map; + }; + + xbl_sc_mem: xbl-sc-region@d8100000 { + reg =3D <0 0xd8100000 0 0x40000>; + no-map; + }; + + hyp_tags_reserved_mem: hyp-tags-reserved-region@811d0000 { + reg =3D <0 0x811d0000 0 0x30000>; + no-map; + }; + + xbl_dt_log_merged_mem: xbl-dt-log-merged-region@81a00000 { + reg =3D <0 0x81a00000 0 0x260000>; + no-map; + }; + + aop_config_merged_mem: aop-config-merged-region@81c80000 { + reg =3D <0 0x81c80000 0 0x74000>; + no-map; + }; + + chipinfo_mem: chipinfo-region@81cf4000 { + reg =3D <0 0x81cf4000 0 0x1000>; + no-map; + }; + + global_sync_mem: global-sync-region@82600000 { + reg =3D <0 0x82600000 0 0x100000>; + no-map; + }; + + tz_stat_mem: tz-stat-region@82700000 { + reg =3D <0 0x82700000 0 0x100000>; + no-map; + }; + + cpucp_fw_mem: cpucp-fw-region@d8140000 { + reg =3D <0 0xd8140000 0 0x1c0000>; + no-map; + }; + + qtee_mem: qtee-region@d8300000 { + reg =3D <0 0xd8300000 0 0x500000>; + no-map; + }; + + hwfence_shbuf: hwfence-shbuf-region@e6440000 { + reg =3D <0 0xe6440000 0 0x2dd000>; + no-map; + }; + + hyp_ext_reserved_mem: hyp-ext-reserved-region@ff700000 { + reg =3D <0 0xff700000 0 0x100000>; + no-map; + }; + + llcc_lpi_mem: llcc_lpi_region@ff800000 { + reg =3D <0 0xff800000 0 0x600000>; + no-map; + }; + + hyp_ext_tags_mem: hyp-ext-tags-region@fce00000 { + reg =3D <0 0xfce00000 0 0x2900000>; + no-map; + }; + }; + + sound { + compatible =3D "qcom,sm8550-sndcard", "qcom,sm8450-sndcard"; + pinctrl-0 =3D <&lpi_i2s3_active>; + pinctrl-names =3D "default"; + + model =3D "AYN-Odin2"; + audio-routing =3D "IN1_HPHL", "HPHL_OUT", + "IN2_HPHR", "HPHR_OUT", + "AMIC2", "MIC BIAS2", + "TX SWR_INPUT1", "ADC2_OUTPUT"; + + speaker-i2s-dai-link { + link-name =3D "Primary MI2S Playback"; + + codec { + sound-dai =3D <&spk_amp_l>, <&spk_amp_r>; + }; + + cpu { + sound-dai =3D <&q6apmbedai PRIMARY_MI2S_RX>; + }; + + platform { + sound-dai =3D <&q6apm>; + }; + }; + + wcd-playback-dai-link { + link-name =3D "WCD Playback"; + + codec { + sound-dai =3D <&wcd938x 0>, <&swr1 0>, <&lpass_rxmacro 0>; + }; + + cpu { + sound-dai =3D <&q6apmbedai RX_CODEC_DMA_RX_0>; + }; + + platform { + sound-dai =3D <&q6apm>; + }; + }; + + wcd-capture-dai-link { + link-name =3D "WCD Capture"; + + codec { + sound-dai =3D <&wcd938x 1>, <&swr2 0>, <&lpass_txmacro 0>; + }; + + cpu { + sound-dai =3D <&q6apmbedai TX_CODEC_DMA_TX_3>; + }; + + platform { + sound-dai =3D <&q6apm>; + }; + }; + + dp0-dai-link { + link-name =3D "DP0 Playback"; + + codec { + sound-dai =3D <&mdss_dp0>; + }; + + cpu { + sound-dai =3D <&q6apmbedai DISPLAY_PORT_RX_0>; + }; + + platform { + sound-dai =3D <&q6apm>; + }; + }; + }; + + thermal-zones { + cpu0-thermal { + polling-delay =3D <200>; + + trips { + cpuss0_active0: cpu-active0 { + temperature =3D <50000>; + hysteresis =3D <4000>; + type =3D "active"; + }; + + cpuss0_active1: cpu-active1 { + temperature =3D <55000>; + hysteresis =3D <4000>; + type =3D "active"; + }; + + cpuss0_active2: cpu-active2 { + temperature =3D <60000>; + hysteresis =3D <4000>; + type =3D "active"; + }; + + cpuss0_active3: cpu-active3 { + temperature =3D <65000>; + hysteresis =3D <4000>; + type =3D "active"; + }; + + cpuss0_active4: cpu-active4 { + temperature =3D <70000>; + hysteresis =3D <4000>; + type =3D "active"; + }; + + cpuss0_active5: cpu-active5 { + temperature =3D <75000>; + hysteresis =3D <4000>; + type =3D "active"; + }; + + cpuss0_active6: cpu-active6 { + temperature =3D <80000>; + hysteresis =3D <4000>; + type =3D "active"; + }; + + cpuss0_active7: cpu-active7 { + temperature =3D <85000>; + hysteresis =3D <4000>; + type =3D "active"; + }; + }; + + cooling-maps { + map0 { + cooling-device =3D <&pwm_fan 0 1>; + trip =3D <&cpuss0_active0>; + }; + + map1 { + cooling-device =3D <&pwm_fan 1 2>; + trip =3D <&cpuss0_active1>; + }; + + map2 { + cooling-device =3D <&pwm_fan 2 3>; + trip =3D <&cpuss0_active2>; + }; + + map3 { + cooling-device =3D <&pwm_fan 3 4>; + trip =3D <&cpuss0_active3>; + }; + + map4 { + cooling-device =3D <&pwm_fan 4 5>; + trip =3D <&cpuss0_active4>; + }; + + map5 { + cooling-device =3D <&pwm_fan 5 6>; + trip =3D <&cpuss0_active5>; + }; + + map6 { + cooling-device =3D <&pwm_fan 6 7>; + trip =3D <&cpuss0_active6>; + }; + + map7 { + cooling-device =3D <&pwm_fan 7 8>; + trip =3D <&cpuss0_active7>; + }; + }; + }; + + cpu3-bottom-thermal { + polling-delay =3D <200>; + + trips { + cpuss3_active0: cpu-active0 { + temperature =3D <50000>; + hysteresis =3D <4000>; + type =3D "active"; + }; + + cpuss3_active1: cpu-active1 { + temperature =3D <55000>; + hysteresis =3D <4000>; + type =3D "active"; + }; + + cpuss3_active2: cpu-active2 { + temperature =3D <60000>; + hysteresis =3D <4000>; + type =3D "active"; + }; + + cpuss3_active3: cpu-active3 { + temperature =3D <65000>; + hysteresis =3D <4000>; + type =3D "active"; + }; + + cpuss3_active4: cpu-active4 { + temperature =3D <70000>; + hysteresis =3D <4000>; + type =3D "active"; + }; + + cpuss3_active5: cpu-active5 { + temperature =3D <75000>; + hysteresis =3D <4000>; + type =3D "active"; + }; + + cpuss3_active6: cpu-active6 { + temperature =3D <80000>; + hysteresis =3D <4000>; + type =3D "active"; + }; + + cpuss3_active7: cpu-active7 { + temperature =3D <85000>; + hysteresis =3D <4000>; + type =3D "active"; + }; + }; + + cooling-maps { + map0 { + cooling-device =3D <&pwm_fan 0 1>; + trip =3D <&cpuss3_active0>; + }; + + map1 { + cooling-device =3D <&pwm_fan 1 2>; + trip =3D <&cpuss3_active1>; + }; + + map2 { + cooling-device =3D <&pwm_fan 2 3>; + trip =3D <&cpuss3_active2>; + }; + + map3 { + cooling-device =3D <&pwm_fan 3 4>; + trip =3D <&cpuss3_active3>; + }; + + map4 { + cooling-device =3D <&pwm_fan 4 5>; + trip =3D <&cpuss3_active4>; + }; + + map5 { + cooling-device =3D <&pwm_fan 5 6>; + trip =3D <&cpuss3_active5>; + }; + + map6 { + cooling-device =3D <&pwm_fan 6 7>; + trip =3D <&cpuss3_active6>; + }; + + map7 { + cooling-device =3D <&pwm_fan 7 8>; + trip =3D <&cpuss3_active7>; + }; + }; + }; + + cpu7-bottom-thermal { + polling-delay =3D <200>; + + trips { + cpuss7_active0: cpu-active0 { + temperature =3D <50000>; + hysteresis =3D <4000>; + type =3D "active"; + }; + + cpuss7_active1: cpu-active1 { + temperature =3D <55000>; + hysteresis =3D <4000>; + type =3D "active"; + }; + + cpuss7_active2: cpu-active2 { + temperature =3D <60000>; + hysteresis =3D <4000>; + type =3D "active"; + }; + + cpuss7_active3: cpu-active3 { + temperature =3D <65000>; + hysteresis =3D <4000>; + type =3D "active"; + }; + + cpuss7_active4: cpu-active4 { + temperature =3D <70000>; + hysteresis =3D <4000>; + type =3D "active"; + }; + + cpuss7_active5: cpu-active5 { + temperature =3D <75000>; + hysteresis =3D <4000>; + type =3D "active"; + }; + + cpuss7_active6: cpu-active6 { + temperature =3D <80000>; + hysteresis =3D <4000>; + type =3D "active"; + }; + + cpuss7_active7: cpu-active7 { + temperature =3D <85000>; + hysteresis =3D <4000>; + type =3D "active"; + }; + }; + + cooling-maps { + map0 { + cooling-device =3D <&pwm_fan 0 1>; + trip =3D <&cpuss7_active0>; + }; + + map1 { + cooling-device =3D <&pwm_fan 1 2>; + trip =3D <&cpuss7_active1>; + }; + + map2 { + cooling-device =3D <&pwm_fan 2 3>; + trip =3D <&cpuss7_active2>; + }; + + map3 { + cooling-device =3D <&pwm_fan 3 4>; + trip =3D <&cpuss7_active3>; + }; + + map4 { + cooling-device =3D <&pwm_fan 4 5>; + trip =3D <&cpuss7_active4>; + }; + + map5 { + cooling-device =3D <&pwm_fan 5 6>; + trip =3D <&cpuss7_active5>; + }; + + map6 { + cooling-device =3D <&pwm_fan 6 7>; + trip =3D <&cpuss7_active6>; + }; + + map7 { + cooling-device =3D <&pwm_fan 7 8>; + trip =3D <&cpuss7_active7>; + }; + }; + }; + + gpuss-0-thermal { + polling-delay =3D <200>; + + trips { + gpuss0_active0: gpu-active0 { + temperature =3D <50000>; + hysteresis =3D <4000>; + type =3D "active"; + }; + + gpuss0_active1: gpu-active1 { + temperature =3D <55000>; + hysteresis =3D <4000>; + type =3D "active"; + }; + + gpuss0_active2: gpu-active2 { + temperature =3D <60000>; + hysteresis =3D <4000>; + type =3D "active"; + }; + + gpuss0_active3: gpu-active3 { + temperature =3D <65000>; + hysteresis =3D <4000>; + type =3D "active"; + }; + + gpuss0_active4: gpu-active4 { + temperature =3D <70000>; + hysteresis =3D <4000>; + type =3D "active"; + }; + + gpuss0_active5: gpu-active5 { + temperature =3D <75000>; + hysteresis =3D <4000>; + type =3D "active"; + }; + + gpuss0_active6: gpu-active6 { + temperature =3D <80000>; + hysteresis =3D <4000>; + type =3D "active"; + }; + + gpuss0_active7: gpu-active7 { + temperature =3D <85000>; + hysteresis =3D <4000>; + type =3D "active"; + }; + }; + + cooling-maps { + map0 { + cooling-device =3D <&pwm_fan 0 1>; + trip =3D <&gpuss0_active0>; + }; + + map1 { + cooling-device =3D <&pwm_fan 1 2>; + trip =3D <&gpuss0_active1>; + }; + + map2 { + cooling-device =3D <&pwm_fan 2 3>; + trip =3D <&gpuss0_active2>; + }; + + map3 { + cooling-device =3D <&pwm_fan 3 4>; + trip =3D <&gpuss0_active3>; + }; + + map4 { + cooling-device =3D <&pwm_fan 4 5>; + trip =3D <&gpuss0_active4>; + }; + + map5 { + cooling-device =3D <&pwm_fan 5 6>; + trip =3D <&gpuss0_active5>; + }; + + map6 { + cooling-device =3D <&pwm_fan 6 7>; + trip =3D <&gpuss0_active6>; + }; + + map7 { + cooling-device =3D <&pwm_fan 7 8>; + trip =3D <&gpuss0_active7>; + }; + }; + }; + }; + + usb0-sbu-mux { + compatible =3D "pericom,pi3usb102", "gpio-sbu-mux"; + + enable-gpios =3D <&tlmm 140 GPIO_ACTIVE_LOW>; + select-gpios =3D <&tlmm 141 GPIO_ACTIVE_HIGH>; + + pinctrl-0 =3D <&usb0_sbu_default>; + pinctrl-names =3D "default"; + + mode-switch; + orientation-switch; + + port { + usb0_sbu_mux: endpoint { + remote-endpoint =3D <&pmic_glink_sbu>; + }; + }; + }; + + vdd_fan_5v0: vdd-fan-5v0-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vdd_fan_5v0"; + + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + + gpio =3D <&tlmm 109 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 =3D <&fan_pwr_active>; + pinctrl-names =3D "default"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_mcu_3v3: vdd-mcu-3v3-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vdd_mcu_3v3"; + + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + gpio =3D <&tlmm 99 GPIO_ACTIVE_HIGH>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + }; + + vph_pwr: regulator-vph-pwr { + compatible =3D "regulator-fixed"; + regulator-name =3D "vph_pwr"; + regulator-min-microvolt =3D <3700000>; + regulator-max-microvolt =3D <3700000>; + + regulator-always-on; + regulator-boot-on; + }; + + wcd938x: audio-codec { + compatible =3D "qcom,wcd9385-codec"; + + pinctrl-0 =3D <&wcd_default>; + pinctrl-names =3D "default"; + + qcom,micbias1-microvolt =3D <1800000>; + qcom,micbias2-microvolt =3D <1800000>; + qcom,micbias3-microvolt =3D <1800000>; + qcom,micbias4-microvolt =3D <1800000>; + qcom,mbhc-buttons-vthreshold-microvolt =3D <75000 150000 237000 500000 + 500000 500000 500000 500000>; + qcom,mbhc-headset-vthreshold-microvolt =3D <1700000>; + qcom,mbhc-headphone-vthreshold-microvolt =3D <50000>; + qcom,rx-device =3D <&wcd_rx>; + qcom,tx-device =3D <&wcd_tx>; + + reset-gpios =3D <&tlmm 108 GPIO_ACTIVE_LOW>; + + vdd-buck-supply =3D <&vreg_l15b_1p8>; + vdd-rxtx-supply =3D <&vreg_l15b_1p8>; + vdd-io-supply =3D <&vreg_l15b_1p8>; + vdd-mic-bias-supply =3D <&vreg_bob1>; + + #sound-dai-cells =3D <1>; + }; + + wcn7850-pmu { + compatible =3D "qcom,wcn7850-pmu"; + + pinctrl-0 =3D <&wlan_en>, <&bt_default>, <&pmk8550_sleep_clk>; + pinctrl-names =3D "default"; + + wlan-enable-gpios =3D <&tlmm 80 GPIO_ACTIVE_HIGH>; + bt-enable-gpios =3D <&tlmm 81 GPIO_ACTIVE_HIGH>; + + vdd-supply =3D <&vreg_s5g_0p8>; + vddio-supply =3D <&vreg_l15b_1p8>; + vddaon-supply =3D <&vreg_s2g_0p8>; + vdddig-supply =3D <&vreg_s4e_0p95>; + vddrfa1p2-supply =3D <&vreg_s4g_1p3>; + vddrfa1p8-supply =3D <&vreg_s6g_1p8>; + + regulators { + vreg_pmu_rfa_cmn: ldo0 { + regulator-name =3D "vreg_pmu_rfa_cmn"; + }; + + vreg_pmu_aon_0p59: ldo1 { + regulator-name =3D "vreg_pmu_aon_0p59"; + }; + + vreg_pmu_wlcx_0p8: ldo2 { + regulator-name =3D "vreg_pmu_wlcx_0p8"; + }; + + vreg_pmu_wlmx_0p85: ldo3 { + regulator-name =3D "vreg_pmu_wlmx_0p85"; + }; + + vreg_pmu_btcmx_0p85: ldo4 { + regulator-name =3D "vreg_pmu_btcmx_0p85"; + }; + + vreg_pmu_rfa_0p8: ldo5 { + regulator-name =3D "vreg_pmu_rfa_0p8"; + }; + + vreg_pmu_rfa_1p2: ldo6 { + regulator-name =3D "vreg_pmu_rfa_1p2"; + }; + + vreg_pmu_rfa_1p8: ldo7 { + regulator-name =3D "vreg_pmu_rfa_1p8"; + }; + + vreg_pmu_pcie_0p9: ldo8 { + regulator-name =3D "vreg_pmu_pcie_0p9"; + }; + + vreg_pmu_pcie_1p8: ldo9 { + regulator-name =3D "vreg_pmu_pcie_1p8"; + }; + }; + }; + + // The arch_timer label is unused here, but is required by ABL to apply a= dtbo + arch_timer: timer { }; +}; + +&apps_rsc { + regulators-0 { + compatible =3D "qcom,pm8550-rpmh-regulators"; + qcom,pmic-id =3D "b"; + + vdd-bob1-supply =3D <&vph_pwr>; + vdd-bob2-supply =3D <&vph_pwr>; + vdd-l1-l4-l10-supply =3D <&vreg_s6g_1p8>; + vdd-l2-l13-l14-supply =3D <&vreg_bob1>; + vdd-l3-supply =3D <&vreg_s4g_1p3>; + vdd-l5-l16-supply =3D <&vreg_bob1>; + vdd-l6-l7-supply =3D <&vreg_bob1>; + vdd-l8-l9-supply =3D <&vreg_bob1>; + vdd-l11-supply =3D <&vreg_s4g_1p3>; + vdd-l12-supply =3D <&vreg_s6g_1p8>; + vdd-l15-supply =3D <&vreg_s6g_1p8>; + vdd-l17-supply =3D <&vreg_bob2>; + + vreg_bob1: bob1 { + regulator-name =3D "vreg_bob1"; + regulator-min-microvolt =3D <3296000>; + regulator-max-microvolt =3D <3960000>; + regulator-initial-mode =3D ; + }; + + vreg_bob2: bob2 { + regulator-name =3D "vreg_bob2"; + regulator-min-microvolt =3D <2720000>; + regulator-max-microvolt =3D <3960000>; + regulator-initial-mode =3D ; + }; + + vreg_l2b_3p0: ldo2 { + regulator-name =3D "vreg_l2b_3p0"; + regulator-min-microvolt =3D <3008000>; + regulator-max-microvolt =3D <3008000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l5b_3p1: ldo5 { + regulator-name =3D "vreg_l5b_3p1"; + regulator-min-microvolt =3D <3104000>; + regulator-max-microvolt =3D <3104000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l6b_1p8: ldo6 { + regulator-name =3D "vreg_l6b_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3008000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l7b_1p8: ldo7 { + regulator-name =3D "vreg_l7b_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3008000>; + regulator-initial-mode =3D ; + }; + + vreg_l8b_1p8: ldo8 { + regulator-name =3D "vreg_l8b_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3008000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l9b_2p9: ldo9 { + regulator-name =3D "vreg_l9b_2p9"; + regulator-min-microvolt =3D <2960000>; + regulator-max-microvolt =3D <3008000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l11b_1p2: ldo11 { + regulator-name =3D "vreg_l11b_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1504000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l12b_1p8: ldo12 { + regulator-name =3D "vreg_l12b_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l13b_3p0: ldo13 { + regulator-name =3D "vreg_l13b_3p0"; + regulator-min-microvolt =3D <3000000>; + regulator-max-microvolt =3D <3000000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l14b_3p2: ldo14 { + regulator-name =3D "vreg_l14b_3p2"; + regulator-min-microvolt =3D <3200000>; + regulator-max-microvolt =3D <3200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l15b_1p8: ldo15 { + regulator-name =3D "vreg_l15b_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l16b_2p8: ldo16 { + regulator-name =3D "vreg_l16b_2p8"; + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l17b_2p5: ldo17 { + regulator-name =3D "vreg_l17b_2p5"; + regulator-min-microvolt =3D <2504000>; + regulator-max-microvolt =3D <2504000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + }; + + regulators-1 { + compatible =3D "qcom,pm8550vs-rpmh-regulators"; + qcom,pmic-id =3D "c"; + + vdd-l1-supply =3D <&vreg_s4g_1p3>; + vdd-l2-supply =3D <&vreg_s4e_0p95>; + vdd-l3-supply =3D <&vreg_s4e_0p95>; + + vreg_l3c_0p9: ldo3 { + regulator-name =3D "vreg_l3c_0p9"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <912000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + }; + + regulators-2 { + compatible =3D "qcom,pm8550vs-rpmh-regulators"; + qcom,pmic-id =3D "d"; + + vdd-l1-supply =3D <&vreg_s4e_0p95>; + vdd-l2-supply =3D <&vreg_s4e_0p95>; + vdd-l3-supply =3D <&vreg_s4e_0p95>; + + vreg_l1d_0p88: ldo1 { + regulator-name =3D "vreg_l1d_0p88"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <920000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + }; + + regulators-3 { + compatible =3D "qcom,pm8550vs-rpmh-regulators"; + qcom,pmic-id =3D "e"; + + vdd-l1-supply =3D <&vreg_s4e_0p95>; + vdd-l2-supply =3D <&vreg_s4e_0p95>; + vdd-l3-supply =3D <&vreg_s4g_1p3>; + vdd-s4-supply =3D <&vph_pwr>; + vdd-s5-supply =3D <&vph_pwr>; + + vreg_s4e_0p95: smps4 { + regulator-name =3D "vreg_s4e_0p95"; + regulator-min-microvolt =3D <904000>; + regulator-max-microvolt =3D <984000>; + regulator-initial-mode =3D ; + }; + + vreg_s5e_1p08: smps5 { + regulator-name =3D "vreg_s5e_1p08"; + regulator-min-microvolt =3D <1010000>; + regulator-max-microvolt =3D <1120000>; + regulator-initial-mode =3D ; + }; + + vreg_l1e_0p88: ldo1 { + regulator-name =3D "vreg_l1e_0p88"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <912000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l2e_0p9: ldo2 { + regulator-name =3D "vreg_l2e_0p9"; + regulator-min-microvolt =3D <870000>; + regulator-max-microvolt =3D <970000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l3e_1p2: ldo3 { + regulator-name =3D "vreg_l3e_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + }; + + regulators-4 { + compatible =3D "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id =3D "f"; + + vdd-l1-supply =3D <&vreg_s4e_0p95>; + vdd-l2-supply =3D <&vreg_s4e_0p95>; + vdd-l3-supply =3D <&vreg_s4e_0p95>; + vdd-s4-supply =3D <&vph_pwr>; + + vreg_s4f_0p5: smps4 { + regulator-name =3D "vreg_s4f_0p5"; + regulator-min-microvolt =3D <300000>; + regulator-max-microvolt =3D <700000>; + regulator-initial-mode =3D ; + }; + + vreg_l1f_0p9: ldo1 { + regulator-name =3D "vreg_l1f_0p9"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <912000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l2f_0p88: ldo2 { + regulator-name =3D "vreg_l2f_0p88"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <912000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l3f_0p88: ldo3 { + regulator-name =3D "vreg_l3f_0p88"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <912000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + }; + + regulators-5 { + compatible =3D "qcom,pm8550vs-rpmh-regulators"; + qcom,pmic-id =3D "g"; + + vdd-l1-supply =3D <&vreg_s4g_1p3>; + vdd-l2-supply =3D <&vreg_s4g_1p3>; + vdd-l3-supply =3D <&vreg_s4g_1p3>; + vdd-s1-supply =3D <&vph_pwr>; + vdd-s2-supply =3D <&vph_pwr>; + vdd-s3-supply =3D <&vph_pwr>; + vdd-s4-supply =3D <&vph_pwr>; + vdd-s5-supply =3D <&vph_pwr>; + vdd-s6-supply =3D <&vph_pwr>; + + vreg_s1g_1p2: smps1 { + regulator-name =3D "vreg_s1g_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1300000>; + regulator-initial-mode =3D ; + }; + + vreg_s2g_0p8: smps2 { + regulator-name =3D "vreg_s2g_0p8"; + regulator-min-microvolt =3D <800000>; + regulator-max-microvolt =3D <1000000>; + regulator-initial-mode =3D ; + }; + + vreg_s3g_0p7: smps3 { + regulator-name =3D "vreg_s3g_0p7"; + regulator-min-microvolt =3D <300000>; + regulator-max-microvolt =3D <1004000>; + regulator-initial-mode =3D ; + }; + + vreg_s4g_1p3: smps4 { + regulator-name =3D "vreg_s4g_1p3"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1352000>; + regulator-initial-mode =3D ; + }; + + vreg_s5g_0p8: smps5 { + regulator-name =3D "vreg_s5g_0p8"; + regulator-min-microvolt =3D <500000>; + regulator-max-microvolt =3D <1004000>; + regulator-initial-mode =3D ; + }; + + vreg_s6g_1p8: smps6 { + regulator-name =3D "vreg_s6g_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <2000000>; + regulator-initial-mode =3D ; + }; + + vreg_l1g_1p2: ldo1 { + regulator-name =3D "vreg_l1g_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l3g_1p2: ldo3 { + regulator-name =3D "vreg_l3g_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + }; +}; + +&gpi_dma1 { + status =3D "okay"; +}; + +&gpi_dma2 { + status =3D "okay"; +}; + +&gpu { + status =3D "okay"; +}; + +&gpu_zap_shader { + firmware-name =3D "qcom/sm8550/a740_zap.mbn"; +}; + +&i2c_master_hub_0 { + status =3D "okay"; +}; + +&i2c_hub_2 { + clock-frequency =3D <400000>; + + status =3D "okay"; + + spk_amp_l: amplifier@34 { + compatible =3D "awinic,aw88166"; + reg =3D <0x34>; + #sound-dai-cells =3D <0>; + reset-gpios =3D <&tlmm 103 GPIO_ACTIVE_LOW>; + awinic,audio-channel =3D <0>; + awinic,sync-flag; + sound-name-prefix =3D "SPK_L"; + }; + + spk_amp_r: amplifier@35 { + compatible =3D "awinic,aw88166"; + reg =3D <0x35>; + #sound-dai-cells =3D <0>; + reset-gpios =3D <&tlmm 100 GPIO_ACTIVE_LOW>; + awinic,audio-channel =3D <1>; + awinic,sync-flag; + sound-name-prefix =3D "SPK_R"; + }; +}; + +&iris { + status =3D "okay"; +}; + +&lpass_tlmm { + lpi_i2s3_active: lpi_i2s3-active-state { + sck-pins { + pins =3D "gpio12"; + function =3D "i2s3_clk"; + drive-strength =3D <8>; + bias-disable; + output-high; + }; + + ws-pins { + pins =3D "gpio13"; + function =3D "i2s3_ws"; + drive-strength =3D <8>; + bias-disable; + output-high; + }; + + data0-pins { + pins =3D "gpio17"; + function =3D "i2s3_data"; + drive-strength =3D <8>; + bias-disable; + output-high; + }; + + data1-pins { + pins =3D "gpio18"; + function =3D "i2s3_data"; + drive-strength =3D <8>; + bias-disable; + output-high; + }; + }; +}; + +&lpass_vamacro { + qcom,dmic-sample-rate =3D <4800000>; +}; + +&lpass_wsamacro { + status =3D "disabled"; +}; + +&mdss { + status =3D "okay"; +}; + +&mdss_dp0 { + status =3D "okay"; +}; + +&mdss_dsi1 { + vdda-supply =3D <&vreg_l3e_1p2>; + + status =3D "okay"; + + display_panel: panel@0 { + reg =3D <0>; + + port { + panel1_in: endpoint { + remote-endpoint =3D <&mdss_dsi1_out>; + }; + }; + }; +}; + +&mdss_dsi1_out { + remote-endpoint =3D <&panel1_in>; + data-lanes =3D <0 1 2 3>; +}; + +&mdss_dsi1_phy { + vdds-supply =3D <&vreg_l1e_0p88>; + + status =3D "okay"; +}; + +&pcie0 { + perst-gpios =3D <&tlmm 94 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&tlmm 96 GPIO_ACTIVE_HIGH>; + + pinctrl-0 =3D <&pcie0_default_state>; + pinctrl-names =3D "default"; + + status =3D "okay"; +}; + +&pcieport0 { + wifi@0 { + compatible =3D "pci17cb,1107"; + reg =3D <0x10000 0x0 0x0 0x0 0x0>; + + vddrfacmn-supply =3D <&vreg_pmu_rfa_cmn>; + vddaon-supply =3D <&vreg_pmu_aon_0p59>; + vddwlcx-supply =3D <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply =3D <&vreg_pmu_wlmx_0p85>; + vddrfa0p8-supply =3D <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply =3D <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply =3D <&vreg_pmu_rfa_1p8>; + vddpcie0p9-supply =3D <&vreg_pmu_pcie_0p9>; + vddpcie1p8-supply =3D <&vreg_pmu_pcie_1p8>; + }; +}; + +&pcie0_phy { + vdda-phy-supply =3D <&vreg_l1e_0p88>; + vdda-pll-supply =3D <&vreg_l3e_1p2>; + + status =3D "okay"; +}; + +&pm8550_gpios { + fan_pwm_active: fan-pwm-active-state { + pins =3D "gpio8"; + function =3D "func1"; + input-disable; + output-enable; + output-low; + bias-disable; + power-source =3D <1>; + }; + + sdc2_card_det_n: sdc2-card-det-n-state { + pins =3D "gpio12"; + function =3D "normal"; + input-enable; + output-disable; + bias-pull-up; + power-source =3D <1>; + }; + + volume_up_n: volume-up-n-state { + pins =3D "gpio6"; + function =3D "normal"; + power-source =3D <1>; + bias-pull-up; + input-enable; + }; +}; + +&pm8550_pwm { + status =3D "okay"; + + pm8550_multi_led: multi-led { + color =3D ; + function =3D LED_FUNCTION_STATUS; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + led@1 { + reg =3D <1>; + color =3D ; + }; + + led@2 { + reg =3D <2>; + color =3D ; + }; + + led@3 { + reg =3D <3>; + color =3D ; + }; + }; +}; + +&pm8550b_eusb2_repeater { + qcom,tune-usb2-disc-thres =3D /bits/ 8 <0x6>; + qcom,tune-usb2-amplitude =3D /bits/ 8 <0xb>; + qcom,tune-usb2-preem =3D /bits/ 8 <0x3>; + vdd18-supply =3D <&vreg_l15b_1p8>; + vdd3-supply =3D <&vreg_l5b_3p1>; +}; + +&pmk8550_gpios { + pmk8550_sleep_clk: sleep-clk-state { + pins =3D "gpio3"; + function =3D "func1"; + input-disable; + output-enable; + bias-disable; + power-source =3D <0>; + }; + + pwm_backlight_default: pwm-backlight-default-state { + pins =3D "gpio5"; + function =3D "func3"; + input-disable; + output-low; + output-enable; + bias-disable; + power-source =3D <0>; + qcom,drive-strength =3D <2>; + }; +}; + +&pmk8550_rtc { + nvmem-cells =3D <&rtc_offset>; + nvmem-cell-names =3D "offset"; +}; + +&pmk8550_sdam_2 { + rtc_offset: rtc-offset@bc { + reg =3D <0xbc 0x4>; + }; +}; + +&pon_pwrkey { + status =3D "okay"; +}; + +&pon_resin { + linux,code =3D ; + + status =3D "okay"; +}; + +&qupv3_id_0 { + status =3D "okay"; +}; + +&qupv3_id_1 { + status =3D "okay"; +}; + +&remoteproc_cdsp { + firmware-name =3D "qcom/sm8550/ayntec/cdsp.mbn", + "qcom/sm8550/ayntec/cdsp_dtb.mbn"; + + status =3D "okay"; +}; + +&sdhc_2 { + cd-gpios =3D <&pm8550_gpios 12 GPIO_ACTIVE_LOW>; + pinctrl-0 =3D <&sdc2_default &sdc2_card_det_n>; + pinctrl-1 =3D <&sdc2_sleep &sdc2_card_det_n>; + pinctrl-names =3D "default", "sleep"; + vmmc-supply =3D <&vreg_l9b_2p9>; + vqmmc-supply =3D <&vreg_l8b_1p8>; + no-sdio; + no-mmc; + + status =3D "okay"; +}; + +&sleep_clk { + clock-frequency =3D <32764>; +}; + +&swr1 { + status =3D "okay"; + + wcd_rx: codec@0,4 { + compatible =3D "sdw20217010d00"; + reg =3D <0 4>; + qcom,rx-port-mapping =3D <1 2 3 4 5>; + }; +}; + +&swr2 { + status =3D "okay"; + + wcd_tx: codec@0,3 { + compatible =3D "sdw20217010d00"; + reg =3D <0 3>; + qcom,tx-port-mapping =3D <2 2 3 4>; + }; +}; + +&tlmm { + gpio-reserved-ranges =3D <32 8>; + + mcu_en_active: mcu-en-active-state { + pins =3D "gpio12"; + function =3D "gpio"; + bias-pull-down; + }; + + fan_int: fan-int-state { + pins =3D "gpio13"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + ts_s_rst_default: ts-s-rst-default-state { + pins =3D "gpio14"; + function =3D "gpio"; + bias-pull-up; + drive-strength =3D <8>; + }; + + ts_s_rst_sleep: ts-s-rst-sleep-state { + pins =3D "gpio14"; + function =3D "gpio"; + bias-pull-down; + drive-strength =3D <2>; + }; + + ts_s_int_default: ts-s-int-default-state { + pins =3D "gpio15"; + function =3D "gpio"; + bias-pull-up; + drive-strength =3D <8>; + }; + + ts_s_int_sleep: ts-s-int-sleep-state { + pins =3D "gpio15"; + function =3D "gpio"; + bias-pull-down; + drive-strength =3D <2>; + }; + + ts_p_rst_default: ts-p-rst-default-state { + pins =3D "gpio24"; + function =3D "gpio"; + bias-pull-up; + drive-strength =3D <8>; + }; + + ts_p_rst_sleep: ts-p-rst-sleep-state { + pins =3D "gpio24"; + function =3D "gpio"; + bias-pull-down; + drive-strength =3D <2>; + }; + + ts_p_int_default: ts-p-int-default-state { + pins =3D "gpio25"; + function =3D "gpio"; + bias-pull-up; + drive-strength =3D <8>; + }; + + ts_p_int_sleep: ts-p-int-sleep-state { + pins =3D "gpio25"; + function =3D "gpio"; + bias-pull-down; + drive-strength =3D <2>; + }; + + wlan_en: wlan-en-state { + pins =3D "gpio80"; + function =3D "gpio"; + drive-strength =3D <8>; + bias-pull-down; + }; + + bt_default: bt-default-state { + bt-en-pins { + pins =3D "gpio81"; + function =3D "gpio"; + drive-strength =3D <16>; + bias-disable; + }; + + sw-ctrl-pins { + pins =3D "gpio82"; + function =3D "gpio"; + bias-pull-down; + }; + }; + + dsi_p_te_active: dsi-p-te-active-state { + pins =3D "gpio86"; + function =3D "mdp_vsync"; + drive-strength =3D <2>; + bias-pull-down; + }; + + dsi_p_te_suspend: dsi-s-te-suspend-state { + pins =3D "gpio86"; + function =3D "mdp_vsync"; + drive-strength =3D <2>; + bias-pull-down; + }; + + dsi_s_te_active: dsi-s-te-active-state { + pins =3D "gpio87"; + function =3D "mdp_vsync"; + drive-strength =3D <2>; + bias-pull-down; + }; + + dsi_s_te_suspend: dsi-s-te-suspend-state { + pins =3D "gpio87"; + function =3D "mdp_vsync"; + drive-strength =3D <2>; + bias-pull-down; + }; + + wcd_default: wcd-reset-n-active-state { + pins =3D "gpio108"; + function =3D "gpio"; + drive-strength =3D <16>; + bias-disable; + output-low; + }; + + fan_pwr_active: fan-pwr-active-state { + pins =3D "gpio109"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + output-low; + }; + + dsi_p_rst_active: dsi-p-rst-active-state { + pins =3D "gpio133"; + function =3D "gpio"; + drive-strength =3D <8>; + bias-disable; + }; + + dsi_p_rst_suspend: dsi-p-rst-suspend-state { + pins =3D "gpio133"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + }; + + dsi_s_rst_active: dsi-s-rst-active-state { + pins =3D "gpio137"; + function =3D "gpio"; + drive-strength =3D <8>; + bias-disable; + }; + + dsi_s_rst_suspend: dsi-s-rst-suspend-state { + pins =3D "gpio137"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + }; + + usb0_sbu_default: usb0-sbu-state { + oe-n-pins { + pins =3D "gpio140"; + function =3D "gpio"; + bias-disable; + drive-strength =3D <16>; + output-high; + }; + + sel-pins { + pins =3D "gpio141"; + function =3D "gpio"; + bias-disable; + drive-strength =3D <16>; + }; + }; +}; + +&uart7 { + status =3D "okay"; +}; + +&uart14 { + status =3D "okay"; + + bluetooth { + compatible =3D "qcom,wcn7850-bt"; + + vddrfacmn-supply =3D <&vreg_pmu_rfa_cmn>; + vddaon-supply =3D <&vreg_pmu_aon_0p59>; + vddwlcx-supply =3D <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply =3D <&vreg_pmu_wlmx_0p85>; + vddrfa0p8-supply =3D <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply =3D <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply =3D <&vreg_pmu_rfa_1p8>; + + max-speed =3D <3200000>; + }; +}; + +&ufs_mem_hc { + reset-gpios =3D <&tlmm 210 GPIO_ACTIVE_LOW>; + vcc-supply =3D <&vreg_l17b_2p5>; + vcc-max-microamp =3D <1300000>; + vccq-supply =3D <&vreg_l1g_1p2>; + vccq-max-microamp =3D <1200000>; + vdd-hba-supply =3D <&vreg_l3g_1p2>; + + status =3D "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply =3D <&vreg_l1d_0p88>; + vdda-pll-supply =3D <&vreg_l3e_1p2>; + + status =3D "okay"; +}; + +&usb_1 { + status =3D "okay"; +}; + +&usb_1_dwc3_hs { + remote-endpoint =3D <&pmic_glink_hs_in>; +}; + +&usb_1_hsphy { + phys =3D <&pm8550b_eusb2_repeater>; + + vdd-supply =3D <&vreg_l1e_0p88>; + vdda12-supply =3D <&vreg_l3e_1p2>; + + status =3D "okay"; +}; + +&usb_dp_qmpphy { + vdda-phy-supply =3D <&vreg_l3e_1p2>; + vdda-pll-supply =3D <&vreg_l3f_0p88>; + + status =3D "okay"; +}; + +&usb_dp_qmpphy_out { + remote-endpoint =3D <&pmic_glink_ss_in>; +}; + +&xo_board { + clock-frequency =3D <76800000>; +}; --=20 2.53.0 From nobody Thu Apr 9 01:10:43 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7BE6D37E304; Wed, 8 Apr 2026 19:41:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260408-ayn-qcs8550-v5-4-c90abeb7a152@gmail.com> References: <20260408-ayn-qcs8550-v5-0-c90abeb7a152@gmail.com> In-Reply-To: <20260408-ayn-qcs8550-v5-0-c90abeb7a152@gmail.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Aaron Kling , Teguh Sobirin , Konrad Dybcio X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1775677286; l=2485; i=webgeek1234@gmail.com; s=20250217; h=from:subject:message-id; bh=hvP9BgkF6tPhwnSOK85AN090trYQSQgH+S/xQKgJ9aQ=; b=Ut1B5uBbckEOpo9WJ5xa9NzkL6T/Psa4cRxX+7DsKV7UMP3l5Ei2Fys4pSnvGSCqmQTVs0OG7 g41p/DcrhibCy+hB5GksxessIGoAMgrFFkVhNhk7jaIfyw9ov6a5CbW X-Developer-Key: i=webgeek1234@gmail.com; a=ed25519; pk=TQwd6q26txw7bkK7B8qtI/kcAohZc7bHHGSD7domdrU= X-Endpoint-Received: by B4 Relay for webgeek1234@gmail.com/20250217 with auth_id=342 X-Original-From: Aaron Kling Reply-To: webgeek1234@gmail.com From: Teguh Sobirin The AYN Odin 2 Mini is a high-performance Android-based handheld gaming console powered by the Qualcomm Snapdragon 8 Gen 2 processor featuring a 5-inch mini-led touchscreen. Signed-off-by: Teguh Sobirin Co-developed-by: Aaron Kling Signed-off-by: Aaron Kling Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../boot/dts/qcom/qcs8550-ayntec-odin2mini.dts | 44 ++++++++++++++++++= ++++ 2 files changed, 45 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index 4ba8e730641949..aceb84a060f80e 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -184,6 +184,7 @@ qcs8300-ride-el2-dtbs :=3D qcs8300-ride.dtb monaco-el2.= dtbo =20 dtb-$(CONFIG_ARCH_QCOM) +=3D qcs8300-ride-el2.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D qcs8550-aim300-aiot.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D qcs8550-ayntec-odin2mini.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D qcs9100-ride.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D qcs9100-ride-r3.dtb =20 diff --git a/arch/arm64/boot/dts/qcom/qcs8550-ayntec-odin2mini.dts b/arch/a= rm64/boot/dts/qcom/qcs8550-ayntec-odin2mini.dts new file mode 100644 index 00000000000000..cc894bdd0c9020 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qcs8550-ayntec-odin2mini.dts @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2025, Teguh Sobirin. + */ + +/dts-v1/; + +#include +#include +#include "qcs8550-ayntec-common.dtsi" + +&{/} { + model =3D "AYN Odin 2 Mini"; + compatible =3D "ayntec,odin2mini", "qcom,qcs8550", "qcom,sm8550"; + + vdd_disp_2v8: vdd-disp-2v8-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vdd_disp_2v8"; + + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + + gpio =3D <&tlmm 142 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +/* There is an hdmi bridge on i2c_hub_0@48, but it is not currently suppor= ted */ + +&remoteproc_adsp { + firmware-name =3D "qcom/sm8550/ayntec/odin2mini/adsp.mbn", + "qcom/sm8550/ayntec/odin2mini/adsp_dtb.mbn"; + + status =3D "okay"; +}; + +&spk_amp_l { + firmware-name =3D "qcom/sm8550/ayntec/odin2mini/aw883xx_acf.bin"; +}; + +&spk_amp_r { + firmware-name =3D "qcom/sm8550/ayntec/odin2mini/aw883xx_acf.bin"; +}; + --=20 2.53.0 From nobody Thu Apr 9 01:10:43 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7BC4237E2EE; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260408-ayn-qcs8550-v5-5-c90abeb7a152@gmail.com> References: <20260408-ayn-qcs8550-v5-0-c90abeb7a152@gmail.com> In-Reply-To: <20260408-ayn-qcs8550-v5-0-c90abeb7a152@gmail.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Aaron Kling , Teguh Sobirin , Konrad Dybcio X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1775677286; l=3427; i=webgeek1234@gmail.com; s=20250217; h=from:subject:message-id; bh=2+SChY6IQHBKh8njjJBPKeyneYyYCGd/QTq8yhLM+4k=; b=Woe42hFR9yvCxBywCB+rnup0xs+mj2NQmxeNXaK65s6rky1z9q2/RLQQgfAm2wN+Pxwgcbg5n 7aVngrtsTpiAMsYvOawANHvjAPfrhbFxeX9Go4jWcDZ3d4BB64iSET+ X-Developer-Key: i=webgeek1234@gmail.com; a=ed25519; pk=TQwd6q26txw7bkK7B8qtI/kcAohZc7bHHGSD7domdrU= X-Endpoint-Received: by B4 Relay for webgeek1234@gmail.com/20250217 with auth_id=342 X-Original-From: Aaron Kling Reply-To: webgeek1234@gmail.com From: Teguh Sobirin The AYN Odin 2 Portal is a high-performance Android-based handheld gaming console powered by the Qualcomm Snapdragon 8 Gen 2 processor featuring a 7-inch OLED touchscreen. Signed-off-by: Teguh Sobirin Co-developed-by: Aaron Kling Signed-off-by: Aaron Kling Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../boot/dts/qcom/qcs8550-ayntec-odin2portal.dts | 84 ++++++++++++++++++= ++++ 2 files changed, 85 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index aceb84a060f80e..6bfc4554580bd5 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -185,6 +185,7 @@ qcs8300-ride-el2-dtbs :=3D qcs8300-ride.dtb monaco-el2.= dtbo dtb-$(CONFIG_ARCH_QCOM) +=3D qcs8300-ride-el2.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D qcs8550-aim300-aiot.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D qcs8550-ayntec-odin2mini.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D qcs8550-ayntec-odin2portal.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D qcs9100-ride.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D qcs9100-ride-r3.dtb =20 diff --git a/arch/arm64/boot/dts/qcom/qcs8550-ayntec-odin2portal.dts b/arch= /arm64/boot/dts/qcom/qcs8550-ayntec-odin2portal.dts new file mode 100644 index 00000000000000..bd6ba0ab941d33 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qcs8550-ayntec-odin2portal.dts @@ -0,0 +1,84 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2025, Teguh Sobirin. + */ + +/dts-v1/; + +#include +#include +#include "qcs8550-ayntec-common.dtsi" + +&{/} { + model =3D "AYN Odin 2 Portal"; + compatible =3D "ayntec,odin2portal", "qcom,qcs8550", "qcom,sm8550"; + + vdd_bl_5v0: vdd-bl-5v0-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vdd_bl_5v0"; + + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + + gpio =3D <&tlmm 52 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vdd_disp_2v8: vdd-disp-2v8-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vdd_disp_2v8"; + + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + + gpio =3D <&tlmm 142 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&i2c4 { + clock-frequency =3D <400000>; + + status =3D "okay"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + touchscreen@38 { + compatible =3D "focaltech,ft5426"; + reg =3D <0x38>; + + interrupt-parent =3D <&tlmm>; + interrupts =3D <25 IRQ_TYPE_EDGE_FALLING>; + + reset-gpios =3D <&tlmm 24 GPIO_ACTIVE_LOW>; + + vcc-supply =3D <&vreg_l14b_3p2>; + iovcc-supply =3D <&vreg_l12b_1p8>; + + pinctrl-0 =3D <&ts_p_rst_default &ts_p_int_default>; + pinctrl-1 =3D <&ts_p_rst_sleep &ts_p_int_sleep>; + pinctrl-names =3D "default", "sleep"; + + touchscreen-size-x =3D <1080>; + touchscreen-size-y =3D <1920>; + touchscreen-swapped-x-y; + touchscreen-inverted-y; + }; +}; + +&remoteproc_adsp { + firmware-name =3D "qcom/sm8550/ayntec/odin2portal/adsp.mbn", + "qcom/sm8550/ayntec/odin2portal/adsp_dtb.mbn"; + + status =3D "okay"; +}; + +&spk_amp_l { + firmware-name =3D "qcom/sm8550/ayntec/odin2portal/aw883xx_acf.bin"; +}; + +&spk_amp_r { + firmware-name =3D "qcom/sm8550/ayntec/odin2portal/aw883xx_acf.bin"; +}; + --=20 2.53.0 From nobody Thu Apr 9 01:10:43 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9CDD637F00B; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260408-ayn-qcs8550-v5-6-c90abeb7a152@gmail.com> References: <20260408-ayn-qcs8550-v5-0-c90abeb7a152@gmail.com> In-Reply-To: <20260408-ayn-qcs8550-v5-0-c90abeb7a152@gmail.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Aaron Kling , Teguh Sobirin X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1775677286; l=6227; i=webgeek1234@gmail.com; s=20250217; h=from:subject:message-id; bh=Aoe59zShJAm9LqsbtTeOAxSKG37xMv+KPZP6UxGeHpY=; b=TnYgTj4ONJW/MeTXekyaFtLywM/uLCwfmFzvYiNestD5W23vlw29ze5VVijdkOJntbgodkJ8p 6HV/h6szrT0AqwnR7z+xXTc6+MTn3NMvUqsYudbxR2gV1OrmErMz+Ta X-Developer-Key: i=webgeek1234@gmail.com; a=ed25519; pk=TQwd6q26txw7bkK7B8qtI/kcAohZc7bHHGSD7domdrU= X-Endpoint-Received: by B4 Relay for webgeek1234@gmail.com/20250217 with auth_id=342 X-Original-From: Aaron Kling Reply-To: webgeek1234@gmail.com From: Teguh Sobirin The AYN Thor is a high-performance Android-based handheld gaming console powered by the Qualcomm Snapdragon 8 Gen 2 processor featuring dual AMOLED touchscreens. Signed-off-by: Teguh Sobirin Co-developed-by: Aaron Kling Signed-off-by: Aaron Kling --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/qcs8550-ayntec-thor.dts | 227 +++++++++++++++++++= ++++ 2 files changed, 228 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index 6bfc4554580bd5..6feecd62e01546 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -186,6 +186,7 @@ dtb-$(CONFIG_ARCH_QCOM) +=3D qcs8300-ride-el2.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D qcs8550-aim300-aiot.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D qcs8550-ayntec-odin2mini.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D qcs8550-ayntec-odin2portal.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D qcs8550-ayntec-thor.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D qcs9100-ride.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D qcs9100-ride-r3.dtb =20 diff --git a/arch/arm64/boot/dts/qcom/qcs8550-ayntec-thor.dts b/arch/arm64/= boot/dts/qcom/qcs8550-ayntec-thor.dts new file mode 100644 index 00000000000000..641146a9a7798e --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qcs8550-ayntec-thor.dts @@ -0,0 +1,227 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2025, Teguh Sobirin. + */ + +/dts-v1/; + +#include +#include +#include +#include "qcs8550-ayntec-common.dtsi" + +&{/} { + model =3D "AYN Thor"; + compatible =3D "ayntec,thor", "qcom,qcs8550", "qcom,sm8550"; + + vdd_bl_5v0: vdd-bl-5v0-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vdd_bl_5v0"; + + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + + gpio =3D <&tlmm 52 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vdd_disp_1v8: vdd-disp-1v8-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vdd_disp_1v8"; + + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + gpio =3D <&tlmm 70 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vdd_disp1_2v8: vdd-disp1-2v8-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vdd_disp1_2v8"; + + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + + gpio =3D <&tlmm 142 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vdd_disp2_2v8: vdd-disp2-2v8-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vdd_disp2_2v8"; + + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + + gpio =3D <&tlmm 143 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vdd_ts_3v0: vdd-ts-3v0-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vdd_ts_3v0"; + + regulator-min-microvolt =3D <3000000>; + regulator-max-microvolt =3D <3000000>; + + gpio =3D <&tlmm 144 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vdd_ts_1v8: vdd-ts-1v8-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vdd_ts_1v8"; + + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + gpio =3D <&tlmm 102 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&gpio_keys { + pinctrl-0 =3D <&volume_up_n &key_ayn_n>; + + key-ayn { + label =3D "AYN Key"; + debounce-interval =3D <15>; + gpios =3D <&tlmm 41 GPIO_ACTIVE_LOW>; + linux,code =3D ; + linux,can-disable; + }; + + switch-lid { + label =3D "Hall Lid Sensor"; + gpios =3D <&tlmm 17 GPIO_ACTIVE_LOW>; + linux,input-type =3D ; + linux,code =3D ; + linux,can-disable; + wakeup-source; + }; +}; + +&i2c4 { + clock-frequency =3D <400000>; + + status =3D "okay"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + touchscreen@38 { + compatible =3D "focaltech,ft5426"; + reg =3D <0x38>; + + interrupt-parent =3D <&tlmm>; + interrupts =3D <25 IRQ_TYPE_EDGE_FALLING>; + + reset-gpios =3D <&tlmm 24 GPIO_ACTIVE_LOW>; + + vcc-supply =3D <&vreg_l14b_3p2>; + iovcc-supply =3D <&vreg_l12b_1p8>; + + pinctrl-0 =3D <&ts_p_rst_default &ts_p_int_default>; + pinctrl-1 =3D <&ts_p_rst_sleep &ts_p_int_sleep>; + pinctrl-names =3D "default", "sleep"; + + touchscreen-size-x =3D <1080>; + touchscreen-size-y =3D <1920>; + touchscreen-swapped-x-y; + touchscreen-inverted-x; + }; +}; + +&i2c_hub_3 { + clock-frequency =3D <100000>; + + status =3D "okay"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + touchscreen@38 { + compatible =3D "focaltech,ft5452"; + reg =3D <0x38>; + + interrupt-parent =3D <&tlmm>; + interrupts =3D <15 IRQ_TYPE_EDGE_FALLING>; + + reset-gpios =3D <&tlmm 14 GPIO_ACTIVE_LOW>; + + vcc-supply =3D <&vdd_ts_3v0>; + iovcc-supply =3D <&vdd_ts_1v8>; + + pinctrl-0 =3D <&ts_s_rst_default &ts_s_int_default>; + pinctrl-1 =3D <&ts_s_rst_sleep &ts_s_int_sleep>; + pinctrl-names =3D "default", "sleep"; + + touchscreen-size-x =3D <1080>; + touchscreen-size-y =3D <1240>; + touchscreen-swapped-x-y; + touchscreen-inverted-x; + }; +}; + +&mdss_dsi0 { + vdda-supply =3D <&vreg_l3e_1p2>; + + status =3D "okay"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + panel@0 { + reg =3D <0>; + + port { + panel0_in: endpoint { + remote-endpoint =3D <&mdss_dsi0_out>; + }; + }; + }; +}; + +&mdss_dsi0_out { + remote-endpoint =3D <&panel0_in>; + data-lanes =3D <0 1 2 3>; +}; + +&mdss_dsi0_phy { + vdds-supply =3D <&vreg_l1e_0p88>; + + status =3D "okay"; +}; + +&mdss_dsi1_out { + qcom,te-source =3D "mdp_vsync_s"; +}; + +&pm8550_multi_led { + status =3D "disabled"; +}; + +&remoteproc_adsp { + firmware-name =3D "qcom/sm8550/ayntec/thor/adsp.mbn", + "qcom/sm8550/ayntec/thor/adsp_dtb.mbn"; + + status =3D "okay"; +}; + +&spk_amp_l { + firmware-name =3D "qcom/sm8550/ayntec/thor/aw883xx_acf.bin"; +}; + +&spk_amp_r { + firmware-name =3D "qcom/sm8550/ayntec/thor/aw883xx_acf.bin"; +}; + +&tlmm { + key_ayn_n: key-ayn-n-state { + pins =3D "gpio41"; + function =3D "gpio"; + bias-pull-up; + output-disable; + }; +}; --=20 2.53.0