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d="scan'208";a="728510294" Received: from rcdn-l-core-09.cisco.com ([173.37.255.146]) by alln-iport-3.cisco.com with ESMTP/TLS/TLS_AES_256_GCM_SHA384; 07 Apr 2026 23:39:34 +0000 Received: from sjc-ads-2636.cisco.com (sjc-ads-2636.cisco.com [171.70.32.71]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by rcdn-l-core-09.cisco.com (Postfix) with ESMTPS id 80FA8180004A8; Tue, 7 Apr 2026 23:39:34 +0000 (GMT) Received: by sjc-ads-2636.cisco.com (Postfix, from userid 470863) id 27872CBEF83; Tue, 7 Apr 2026 16:39:34 -0700 (PDT) From: Nishanth Sampath Kumar To: broonie@kernel.org Cc: brgl@bgdev.pl, linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org, gregkh@linuxfoundation.org, rafael@kernel.org, arnd@arndb.de, Nishanth Sampath Kumar Subject: [PATCH v2] regmap-i2c: add SMBus byte/word reg16 bus for adapters lacking I2C_FUNC_I2C Date: Tue, 7 Apr 2026 16:39:27 -0700 Message-Id: <20260407233927.498932-1-nissampa@cisco.com> X-Mailer: git-send-email 2.35.6 In-Reply-To: <20260404021920.359902-1-nissampa@cisco.com> References: <20260404021920.359902-1-nissampa@cisco.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Outbound-Client-TLS: ANONYMOUS;sjc-ads-2636.cisco.com [171.70.32.71];TLSv1.3;TLS_AES_256_GCM_SHA384;256 X-Outbound-SMTP-Client: 171.70.32.71, sjc-ads-2636.cisco.com X-Outbound-Node: rcdn-l-core-09.cisco.com Content-Type: text/plain; charset="utf-8" AMD PIIX4 SMBus adapters, present on AMD SP5/EPYC-based platforms (including Cisco 8000 series routers), support SMBUS_BYTE_DATA and SMBUS_WORD_DATA but lack I2C_FUNC_I2C and I2C_FUNC_SMBUS_I2C_BLOCK. When at24 (or any driver) requests a regmap with reg_bits=3D16 and val_bits=3D8 on such an adapter, regmap_get_i2c_bus() finds no matching bus and returns -ENOTSUPP. The existing regmap_i2c_smbus_i2c_block_reg16 bus type already implements 16-bit addressed reads using only write_byte_data() + read_byte() primitives, but its selection is gated on I2C_FUNC_SMBUS_I2C_BLOCK which these adapters lack. Add a new regmap_smbus_byte_word_reg16 bus that: READ: reuses regmap_i2c_smbus_i2c_read_reg16() -- sets the 16-bit address via write_byte_data(addr_lo, addr_hi), then reads bytes sequentially via read_byte() (EEPROM auto-increments). Requires only SMBUS_BYTE_DATA. WRITE: uses write_word_data(addr_hi, (data << 8) | addr_lo) to encode one data byte per SMBus WORD transaction. Requires only SMBUS_WORD_DATA. Single-byte writes only. The new bus is selected in regmap_get_i2c_bus() when reg_bits=3D16, val_bits=3D8, and the adapter has SMBUS_BYTE_DATA | SMBUS_WORD_DATA but not I2C_FUNC_I2C or SMBUS_I2C_BLOCK. The branch is placed after the existing I2C_BLOCK_reg16 check so adapters with full block support continue to use the faster path. This fixes at24 EEPROM probe failures on PIIX4: at24 3-0055: probe with driver at24 failed with error -524 No driver changes are required -- at24 already passes reg_bits=3D16 to devm_regmap_init_i2c(), which now succeeds. Signed-off-by: Nishanth Sampath Kumar --- v1 -> v2: Moved fix from at24 driver into regmap-i2c core per review feedback from Bartosz Golaszewski and Mark Brown. drivers/base/regmap/regmap-i2c.c | 49 ++++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) --- a/drivers/base/regmap/regmap-i2c.c +++ b/drivers/base/regmap/regmap-i2c.c @@ -303,6 +303,50 @@ .max_raw_write =3D I2C_SMBUS_BLOCK_MAX - 2, }; =20 +/* + * SMBus byte/word reg16 support for adapters that have SMBUS_BYTE_DATA + * and SMBUS_WORD_DATA but lack I2C_FUNC_I2C and I2C_FUNC_SMBUS_I2C_BLOCK, + * such as the AMD PIIX4. + * + * READ: set 16-bit EEPROM address via write_byte_data(addr_lo, addr_hi), + * then sequentially read bytes via read_byte() (EEPROM auto- + * increments the address pointer). Same as the I2C-block reg16 + * read path above. + * + * WRITE: encode the low address byte and data into a word transaction: + * write_word_data(addr_hi, (data_byte << 8) | addr_lo). + * Only single-byte writes are supported (one value per transaction= ). + */ +static int regmap_smbus_word_write_reg16(void *context, const void *data, + size_t count) +{ + struct device *dev =3D context; + struct i2c_client *i2c =3D to_i2c_client(dev); + u8 addr_hi, addr_lo, val; + + /* + * data layout: [addr_hi, addr_lo, val0, val1, ...]. + * Only single-byte value writes are supported; multi-byte would + * require raw I2C (or repeated word writes with incrementing address). + */ + if (count !=3D 3) + return -EINVAL; + + addr_hi =3D ((u8 *)data)[0]; + addr_lo =3D ((u8 *)data)[1]; + val =3D ((u8 *)data)[2]; + + return i2c_smbus_write_word_data(i2c, addr_hi, + cpu_to_le16(((u16)val << 8) | addr_lo)); +} + +static const struct regmap_bus regmap_smbus_byte_word_reg16 =3D { + .write =3D regmap_smbus_word_write_reg16, + .read =3D regmap_i2c_smbus_i2c_read_reg16, + .max_raw_read =3D I2C_SMBUS_BLOCK_MAX - 2, + .max_raw_write =3D 1, +}; + static const struct regmap_bus *regmap_get_i2c_bus(struct i2c_client *i2c, const struct regmap_config *config) { @@ -321,6 +365,11 @@ i2c_check_functionality(i2c->adapter, I2C_FUNC_SMBUS_I2C_BLOCK)) bus =3D ®map_i2c_smbus_i2c_block_reg16; + else if (config->val_bits =3D=3D 8 && config->reg_bits =3D=3D 16 && + i2c_check_functionality(i2c->adapter, + I2C_FUNC_SMBUS_BYTE_DATA | + I2C_FUNC_SMBUS_WORD_DATA)) + bus =3D ®map_smbus_byte_word_reg16; else if (config->val_bits =3D=3D 16 && config->reg_bits =3D=3D 8 && i2c_check_functionality(i2c->adapter, I2C_FUNC_SMBUS_WORD_DATA))