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Introduce a property that specifies the base address of the shared memory region from which the driver should read SCT descriptors provided by firmware. Signed-off-by: Francisco Munoz Ruiz Reviewed-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski --- .../devicetree/bindings/cache/qcom,llcc.yaml | 19 +++++++++++++++= ++++ 1 file changed, 19 insertions(+) diff --git a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml b/Docum= entation/devicetree/bindings/cache/qcom,llcc.yaml index 995d57815781..40b737ad2230 100644 --- a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml +++ b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml @@ -21,6 +21,7 @@ properties: compatible: enum: - qcom,glymur-llcc + - qcom,hawi-llcc - qcom,ipq5424-llcc - qcom,kaanapali-llcc - qcom,qcs615-llcc @@ -57,6 +58,11 @@ properties: interrupts: maxItems: 1 =20 + memory-region: + maxItems: 1 + description: handle to a reserved-memory node used for firmware-popula= ted + SLC/SCT shared memory. + nvmem-cells: items: - description: Reference to an nvmem node for multi channel DDR @@ -318,6 +324,7 @@ allOf: contains: enum: - qcom,kaanapali-llcc + - qcom,hawi-llcc - qcom,sm8450-llcc - qcom,sm8550-llcc - qcom,sm8650-llcc @@ -340,6 +347,18 @@ allOf: - const: llcc3_base - const: llcc_broadcast_base - const: llcc_broadcast_and_base + - if: + properties: + compatible: + contains: + enum: + - qcom,hawi-llcc + then: + required: + - memory-region + else: + properties: + memory-region: false =20 additionalProperties: false =20 --=20 2.34.1 From nobody Sun Jun 14 08:19:48 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EBF5C37E2FF for ; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-12bfea5f860sm16224123c88.2.2026.04.07.14.52.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Apr 2026 14:52:07 -0700 (PDT) From: Francisco Munoz Ruiz Date: Tue, 07 Apr 2026 14:51:48 -0700 Subject: [PATCH v2 2/3] soc: qcom: llcc-qcom: get SCT descriptors from fw-populated memory Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260407-external_llcc_changes2set-v2-2-b5017ce2020b@oss.qualcomm.com> References: <20260407-external_llcc_changes2set-v2-0-b5017ce2020b@oss.qualcomm.com> In-Reply-To: <20260407-external_llcc_changes2set-v2-0-b5017ce2020b@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Krzysztof Kozlowski , Conor Dooley , Jonathan Cameron , Rob Herring , Kees Cook , "Gustavo A. R. Silva" Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-hardening@vger.kernel.org, Francisco Munoz Ruiz , Konrad Dybcio X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1775598723; l=14020; i=francisco.ruiz@oss.qualcomm.com; s=20260305; h=from:subject:message-id; bh=VRvociPdZzkn2LBvWUuRQKKAFjnlqZ3T0gECO7AzEzs=; b=n0TiBSuLo+qhCiWOhTgCk0zfuR7u0nm9C37W5zwK/YhpUxyT1a/RL1+l3wCgIQBmIRFRNNt3P W263K0ALZOlAwFdIeGkilCFTSsj7pXebBa1V9qZvRBNERK8Qu4CfzW7 X-Developer-Key: i=francisco.ruiz@oss.qualcomm.com; a=ed25519; pk=Gcv2CX7iHozjnQ4oK+9fINmBiQTmVC4SpaZzoM63CHE= X-Authority-Analysis: v=2.4 cv=drPrzVg4 c=1 sm=1 tr=0 ts=69d57c8a cx=c_pps a=PfFC4Oe2JQzmKTvty2cRDw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=EUspDBNiAAAA:8 a=mueQnyBuSmwt3Ye5OMMA:9 a=QEXdDO2ut3YA:10 a=6Ab_bkdmUrQuMsNx7PHu:22 X-Proofpoint-ORIG-GUID: 5WcsAs3aj0VA61z1hyNed8Jh87dva4RG X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDA3MDIwMCBTYWx0ZWRfX0rm+M3+/+8IA fA/cWMfhypdppYDr+c458sKnhNa2fhBvFYBbVolAyeSMOC6LigMMEiYv/FLHRYtF4gh/CWwxd6G vexZsAT2jq+aQNQnAJhT3Z4C1oPPL+fUpZla2KEkfzG9TFQ8nDU2XzBTG6MtLl0DZHbRrn5dGuZ ybPMcKBX0Pbhm+tu/paqB92nmLUFb50dTMD6Y40xS+07HsBUbpwNEw/89JIw3mDYDfwqet/SnHp XvDvL68BZvXQ5XPDWGuXa3ivcGsaybkRXtWJ8wk7Hwa7UK7SseKtfIEPLARXP9qZMja+WW8vVA+ eINpABQNCuuNB9tOI0iBhnJJkGYOEfxcrGuaf+Ih1NFFPF7la1chBwekDQG4ypnGQHhcddqzVIg 12Ihj6XlCkNij2Y0mYeD7Unh9IDe1F7G5WvLMkU0L70hXQYUrCbn5BxFHCuWeZqwabjgHQW8BaW OZGp+LcxhC8sLlY+ApA== X-Proofpoint-GUID: 5WcsAs3aj0VA61z1hyNed8Jh87dva4RG X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-07_05,2026-04-07_05,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 lowpriorityscore=0 spamscore=0 clxscore=1015 malwarescore=0 bulkscore=0 impostorscore=0 phishscore=0 priorityscore=1501 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604010000 definitions=main-2604070200 Retrieve System Cache Table (SCT) descriptors from a shared memory region populated by firmware. SCT initialization and programming are performed entirely by firmware outside of Linux. The LLCC driver only consumes the pre-initialized descriptor data and does not configure SCT itself. Support this mechanism for future SoCs that provide SCT programming via firmware. Signed-off-by: Francisco Munoz Ruiz Reviewed-by: Konrad Dybcio --- drivers/soc/qcom/llcc-qcom.c | 269 ++++++++++++++++++++++++++++++++-= ---- include/linux/soc/qcom/llcc-qcom.h | 8 +- 2 files changed, 240 insertions(+), 37 deletions(-) diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c index 0161ceec8842..f8cd35b205eb 100644 --- a/drivers/soc/qcom/llcc-qcom.c +++ b/drivers/soc/qcom/llcc-qcom.c @@ -5,7 +5,6 @@ */ =20 #include -#include #include #include #include @@ -14,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -76,6 +76,12 @@ #define LLCC_VERSION_4_1_0_0 0x04010000 #define LLCC_VERSION_6_0_0_0 0X06000000 =20 +#define SLC_SCT_MEM_LAYOUT_VERSION1 1 /* SCT Memory layout version */ +#define SLC_SCT_DONE 0x00534354444f4e45 /* SCT programmin= g OK */ +#define SLC_SCT_FAIL 0x005343544641494c /* SCT programmin= g failed */ +#define SLC_SCT_NAME_LEN 15 +#define SLC_SCT_SLICE_ACT_ON_BOOT BIT(25) + /** * struct llcc_slice_config - Data associated with the llcc slice * @usecase_id: Unique id for the client's use case @@ -143,6 +149,87 @@ struct llcc_slice_config { u32 parent_slice_id; }; =20 +/* + * struct slc_sct_error - Represents SCT error + * @code: FW code status + * @param: Holds the SCT programming error + */ +struct slc_sct_error { + __le64 code; + __le64 param; +} __packed; + +/* + * struct slc_sct_status - SCT programming status + * @program_status: Indicates programming success or failure + * @version: SCT mem layout version + * @error: Error enum and its param + */ +struct slc_sct_status { + __le64 program_status; + /* Use the lower 8 bits */ + __le64 version; + struct slc_sct_error error; +} __packed; + +/* + * struct slc_sct_details - SCT details + * @revision: revision of the SCT table + * @name: name of the SCT table + */ +struct slc_sct_details { + u8 revision; + char name[SLC_SCT_NAME_LEN]; +} __packed; + +/* + * struct tcm_mem_info - SC TCM Shared memory details + * @is_present: is TCM region present + * @offset: offset of TCM shared memory details + */ +struct slc_tcm_mem_info { + __le32 is_present; + __le32 offset; +} __packed; + +/* + * struct slc_sct_slice_desc - Slice descriptor definition used in shmem + * @slice_id: SCID of the slice + * @usecase_id: Usecase ID of the slice + * @slice_properties: + * slice_size: Contains the slice descriptor size - 20 bit wide + * rsvd: Reserved space - 4 bit wide + * flags: Flags for descriptors - 3 bit wide + * MPAM SCID: Bit 24 + * Activate on boot: Bit 25 + * Non-HLOS SCID: Bit 26 + * HWMutex: Ensures only one processor (CPU or MCU) at a time can + * access the LLCC hardware resources - 5 bit wide + */ +struct slc_sct_slice_desc { + __le16 slice_id; + __le16 usecase_id; + __le32 slice_properties; +} __packed; + +/* + * struct slc_sct_mem - Shared memory structure + * @sct_status: Status of SCT programming + * @sct_details: Sct revision and name details + * @tcm_mem_info: TCM shared memory presence & offset info + * @slice_descs_count: Number of slice desc present in SCT + * @scid_max: Maximum no. of SCIDs supported + * @slice_descs: Array of SCT slice desc + */ +struct slc_sct_mem { + struct slc_sct_status sct_status; + struct slc_sct_details sct_details; + struct slc_tcm_mem_info tcm_mem_info; + __le32 slice_descs_count; + __le32 scid_max; + struct slc_sct_slice_desc slice_descs[] __counted_by_le(slice_descs_count= ); +} __packed; + struct qcom_llcc_config { const struct llcc_slice_config *sct_data; const u32 *reg_offset; @@ -4141,6 +4228,15 @@ static const u32 llcc_v6_reg_offset[] =3D { [LLCC_TRP_WRS_CACHEABLE_EN] =3D 0x00042088, }; =20 +static const struct qcom_llcc_config hawi_sct_cfg[] =3D { + { + .sct_data =3D NULL, + .size =3D 0, + .reg_offset =3D llcc_v6_reg_offset, + .edac_reg_offset =3D &llcc_v6_edac_reg_offset, + }, +}; + static const struct qcom_llcc_config kaanapali_cfg[] =3D { { .sct_data =3D kaanapali_data, @@ -4397,6 +4493,11 @@ static const struct qcom_llcc_config x1e80100_cfg[] = =3D { }, }; =20 +static const struct qcom_sct_config hawi_sct_cfgs =3D { + .llcc_config =3D hawi_sct_cfg, + .num_config =3D ARRAY_SIZE(hawi_sct_cfg), +}; + static const struct qcom_sct_config kaanapali_cfgs =3D { .llcc_config =3D kaanapali_cfg, .num_config =3D ARRAY_SIZE(kaanapali_cfg), @@ -4533,23 +4634,20 @@ static struct llcc_drv_data *drv_data =3D (void *) = -EPROBE_DEFER; */ struct llcc_slice_desc *llcc_slice_getd(u32 uid) { - const struct llcc_slice_config *cfg; - u32 sz, i; - if (IS_ERR(drv_data)) return ERR_CAST(drv_data); =20 - cfg =3D drv_data->cfg; - sz =3D drv_data->cfg_size; + if (IS_ERR_OR_NULL(drv_data->desc)) + return ERR_PTR(-ENODEV); =20 - for (i =3D 0; cfg && i < sz; i++, cfg++) - if (cfg->usecase_id =3D=3D uid) - break; + for (u32 i =3D 0; i < drv_data->cfg_size; i++) { + if (uid =3D=3D drv_data->desc[i].uid) + return &drv_data->desc[i]; + } =20 - if (i =3D=3D sz) - return ERR_PTR(-ENODEV); + dev_err(drv_data->dev, "Failed to get slice desc for uid: %u\n", uid); =20 - return &drv_data->desc[i]; + return ERR_PTR(-EINVAL); } EXPORT_SYMBOL_GPL(llcc_slice_getd); =20 @@ -5029,6 +5127,12 @@ static int qcom_llcc_cfg_program(struct platform_dev= ice *pdev, sz =3D drv_data->cfg_size; llcc_table =3D drv_data->cfg; =20 + for (i =3D 0; i < sz; i++) { + drv_data->desc[i].uid =3D llcc_table[i].usecase_id; + drv_data->desc[i].slice_id =3D llcc_table[i].slice_id; + drv_data->desc[i].slice_size =3D llcc_table[i].max_cap; + } + if (drv_data->version >=3D LLCC_VERSION_6_0_0_0) { for (i =3D 0; i < sz; i++) { ret =3D _qcom_llcc_cfg_program_v6(&llcc_table[i], cfg); @@ -5064,6 +5168,101 @@ static int qcom_llcc_get_cfg_index(struct platform_= device *pdev, u8 *cfg_index, return ret; } =20 +static int qcom_llcc_verify_fw_config(struct device *dev, + const struct slc_sct_mem *slc_mem) +{ + u64 program_status; + + program_status =3D le64_to_cpu(slc_mem->sct_status.program_status); + + if (program_status =3D=3D SLC_SCT_DONE) { + u32 desc_count =3D le32_to_cpu(slc_mem->slice_descs_count); + u32 scid_max =3D le32_to_cpu(slc_mem->scid_max); + + if (desc_count > scid_max) { + dev_err(dev, "Descriptor count above max limit (%u > %u)\n", + desc_count, scid_max); + return -EINVAL; + } + + u8 revision =3D slc_mem->sct_details.revision; + char name_buf[SLC_SCT_NAME_LEN]; + + memcpy(name_buf, slc_mem->sct_details.name, + SLC_SCT_NAME_LEN - 1); + name_buf[SLC_SCT_NAME_LEN - 1] =3D '\0'; + + dev_dbg(dev, "SCT init: desc_count=3D%u, rev=3D%u, name=3D%s\n", + desc_count, revision, name_buf); + + return 0; + } else if (program_status =3D=3D SLC_SCT_FAIL) { + u8 version =3D (u8)(le64_to_cpu(slc_mem->sct_status.version)); + u64 code =3D le64_to_cpu(slc_mem->sct_status.error.code); + u64 param =3D le64_to_cpu(slc_mem->sct_status.error.param); + + if (version =3D=3D SLC_SCT_MEM_LAYOUT_VERSION1) { + dev_err(dev, "SCT init failed: code =3D %llu, param =3D %llu, version = =3D 0x%x\n", + code, param, version); + } else { + dev_err(dev, "Found unsupported version %u\n", version); + } + } else { + dev_err(dev, "Unknown SCT Initialization error\n"); + } + + return -EINVAL; +} + +static int qcom_llcc_get_fw_config(struct platform_device *pdev) +{ + const struct slc_sct_mem *slc_mem =3D NULL; + const struct slc_sct_slice_desc *memslice; + struct device *dev =3D &pdev->dev; + u32 slice_properties; + struct resource res; + u32 i, sz; + int ret; + + ret =3D of_reserved_mem_region_to_resource(dev->of_node, 0, &res); + if (ret) { + dev_err(dev, "Unable to locate DT /reserved-memory resource\n"); + return ret; + } + + slc_mem =3D devm_memremap(dev, res.start, resource_size(&res), MEMREMAP_W= B); + if (!slc_mem) { + dev_err(dev, "Failed to memremap SLC shared memory\n"); + return -ENOMEM; + } + + ret =3D qcom_llcc_verify_fw_config(dev, slc_mem); + if (ret) + return ret; + + sz =3D le32_to_cpu(slc_mem->slice_descs_count); + + drv_data->desc =3D devm_kcalloc(dev, sz, sizeof(struct llcc_slice_desc), + GFP_KERNEL); + if (!drv_data->desc) + return -ENOMEM; + + for (i =3D 0; i < sz; i++) { + memslice =3D &slc_mem->slice_descs[i]; + drv_data->desc[i].slice_id =3D le16_to_cpu(memslice->slice_id); + drv_data->desc[i].uid =3D le16_to_cpu(memslice->usecase_id); + slice_properties =3D le32_to_cpu(memslice->slice_properties); + /* Set refcount to 1 if FW already activated this descriptor */ + if (FIELD_GET(SLC_SCT_SLICE_ACT_ON_BOOT, slice_properties)) + refcount_set(&drv_data->desc[i].refcount, 1); + } + + drv_data->cfg =3D NULL; + drv_data->cfg_size =3D sz; + + return 0; +} + static void qcom_llcc_remove(struct platform_device *pdev) { /* Set the global pointer to a error code to avoid referencing it */ @@ -5096,8 +5295,6 @@ static int qcom_llcc_probe(struct platform_device *pd= ev) struct platform_device *llcc_edac; const struct qcom_sct_config *cfgs; const struct qcom_llcc_config *cfg; - const struct llcc_slice_config *llcc_cfg; - u32 sz; u8 cfg_index; u32 version; struct regmap *regmap; @@ -5190,32 +5387,31 @@ static int qcom_llcc_probe(struct platform_device *= pdev) } } =20 - llcc_cfg =3D cfg->sct_data; - sz =3D cfg->size; - drv_data->desc =3D devm_kcalloc(dev, sz, sizeof(struct llcc_slice_desc), = GFP_KERNEL); - if (!drv_data->desc) { - ret =3D -ENOMEM; - goto err; - } + mutex_init(&drv_data->lock); + if (!cfg->size) { + ret =3D qcom_llcc_get_fw_config(pdev); + if (ret) + goto err; + } else { + drv_data->cfg =3D cfg->sct_data; + drv_data->cfg_size =3D cfg->size; + drv_data->desc =3D devm_kcalloc(dev, cfg->size, + sizeof(struct llcc_slice_desc), GFP_KERNEL); =20 - for (i =3D 0; i < sz; i++) { - drv_data->desc[i].slice_id =3D llcc_cfg[i].slice_id; - drv_data->desc[i].slice_size =3D llcc_cfg[i].max_cap; - refcount_set(&drv_data->desc[i].refcount, 0); + if (!drv_data->desc) { + ret =3D -ENOMEM; + goto err; + } + + ret =3D qcom_llcc_cfg_program(pdev, cfg); + if (ret) + goto err; } =20 - drv_data->cfg =3D llcc_cfg; - drv_data->cfg_size =3D sz; + drv_data->ecc_irq =3D platform_get_irq_optional(pdev, 0); drv_data->edac_reg_offset =3D cfg->edac_reg_offset; drv_data->ecc_irq_configured =3D cfg->irq_configured; - mutex_init(&drv_data->lock); - platform_set_drvdata(pdev, drv_data); - - ret =3D qcom_llcc_cfg_program(pdev, cfg); - if (ret) - goto err; - - drv_data->ecc_irq =3D platform_get_irq_optional(pdev, 0); + drv_data->dev =3D dev; =20 /* * On some platforms, the access to EDAC registers will be locked by @@ -5231,6 +5427,8 @@ static int qcom_llcc_probe(struct platform_device *pd= ev) dev_err(dev, "Failed to register llcc edac driver\n"); } =20 + platform_set_drvdata(pdev, drv_data); + return 0; err: drv_data =3D ERR_PTR(-ENODEV); @@ -5239,6 +5437,7 @@ static int qcom_llcc_probe(struct platform_device *pd= ev) =20 static const struct of_device_id qcom_llcc_of_match[] =3D { { .compatible =3D "qcom,glymur-llcc", .data =3D &glymur_cfgs }, + { .compatible =3D "qcom,hawi-llcc", .data =3D &hawi_sct_cfgs }, { .compatible =3D "qcom,ipq5424-llcc", .data =3D &ipq5424_cfgs}, { .compatible =3D "qcom,kaanapali-llcc", .data =3D &kaanapali_cfgs}, { .compatible =3D "qcom,qcs615-llcc", .data =3D &qcs615_cfgs}, diff --git a/include/linux/soc/qcom/llcc-qcom.h b/include/linux/soc/qcom/ll= cc-qcom.h index 227125d84318..b5e917154998 100644 --- a/include/linux/soc/qcom/llcc-qcom.h +++ b/include/linux/soc/qcom/llcc-qcom.h @@ -90,11 +90,13 @@ /** * struct llcc_slice_desc - Cache slice descriptor * @slice_id: llcc slice id + * @uid: Unique ID associated with the llcc device * @slice_size: Size allocated for the llcc slice * @refcount: Atomic counter to track activate/deactivate calls */ struct llcc_slice_desc { u32 slice_id; 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Silva" Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-hardening@vger.kernel.org, Francisco Munoz Ruiz , Konrad Dybcio X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1775598723; l=8946; i=francisco.ruiz@oss.qualcomm.com; s=20260305; h=from:subject:message-id; bh=2Y3ZNVnqNzvGn4NwizHcAhPQrYo7GkEd/vnRF4b+W5o=; b=IxUukN8806itKMrKByDZN01avDTh3nItvCv15dyMmUgM3ou7zZvG8plz2MqOg88Rf8HP5xkPK AGTqhhkTj0UBVIpxNmoN8H4ySp1J2wB4yQzSOSjFJJL7fKFbc6RYN7s X-Developer-Key: i=francisco.ruiz@oss.qualcomm.com; a=ed25519; pk=Gcv2CX7iHozjnQ4oK+9fINmBiQTmVC4SpaZzoM63CHE= X-Proofpoint-GUID: izHb2RumLY-apt5voRZwf75GCWk9gMFF X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDA3MDIwMCBTYWx0ZWRfX8a458gY+Js7w nsOR7LCueM2HFdM1AsHRqH1IffiLW2EpBpAyIeM0+TyEP1sfmubiR5Da9MAelSXfMCtwzaalYjz DGvzNiOLc1BeYpodxzAWOdvWDbsFT7q/8xkj5q+FGzKSxkcBzAUswFiVmra6DiRvx0QIyB1dhn/ +qssVVvKiMSzj+t7IWnWVyJr3l9BfncgxGpMkUJoLhamfcVz6Q98i0bOXzb2ZLD5kDoUtPWCQtx TLxfqO+xmh5HvsLV3Bisck1MrjSbD/u+QKDE1QAA0By9uZtW04pt7a8Ku3j9cp4YRNC7gF74i66 o1c0MiZGAmQG9ALXStcc2TR0VkAG58lZUGkqrpJp2dg+Ax/zPusfUKH2+e/S4T064POzNIiKyrC Rg7tLvZCjWWN9gtfy0Tgk3jz0mRMDj+DirIiQ9vcOQU0GhFL1lJRKkWXk0OoIUca/LteBSJDrEm hr9/lA4czjSxC3XR4Gw== X-Proofpoint-ORIG-GUID: izHb2RumLY-apt5voRZwf75GCWk9gMFF X-Authority-Analysis: v=2.4 cv=DNS/JSNb c=1 sm=1 tr=0 ts=69d57c8b cx=c_pps a=JYo30EpNSr/tUYqK9jHPoA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=EUspDBNiAAAA:8 a=19UnNs3dAo88WjIHmoIA:9 a=QEXdDO2ut3YA:10 a=Fk4IpSoW4aLDllm1B1p-:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-07_05,2026-04-07_05,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 spamscore=0 lowpriorityscore=0 adultscore=0 priorityscore=1501 impostorscore=0 clxscore=1015 bulkscore=0 phishscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604010000 definitions=main-2604070200 Capitalize occurrences of the acronym "LLCC" and "EDAC" in comments and diagnostic text to improve consistency and readability. Signed-off-by: Francisco Munoz Ruiz Reviewed-by: Konrad Dybcio Reviewed-by: Mukesh Ojha --- drivers/soc/qcom/llcc-qcom.c | 32 ++++++++++++++--------------- include/linux/soc/qcom/llcc-qcom.h | 42 +++++++++++++++++++---------------= ---- 2 files changed, 37 insertions(+), 37 deletions(-) diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c index f8cd35b205eb..dcc08f63e020 100644 --- a/drivers/soc/qcom/llcc-qcom.c +++ b/drivers/soc/qcom/llcc-qcom.c @@ -83,9 +83,9 @@ #define SLC_SCT_SLICE_ACT_ON_BOOT BIT(25) =20 /** - * struct llcc_slice_config - Data associated with the llcc slice + * struct llcc_slice_config - Data associated with the LLCC slice * @usecase_id: Unique id for the client's use case - * @slice_id: llcc slice id for each client + * @slice_id: LLCC slice id for each client * @max_cap: The maximum capacity of the cache slice provided in KB * @priority: Priority of the client used to select victim line for replac= ement * @fixed_size: Boolean indicating if the slice has a fixed capacity @@ -99,7 +99,7 @@ * slice: normal or TCM(Tightly Coupled Memory) * @probe_target_ways: Determines what ways to probe for access hit. When * configured to 1 only bonus and reserved ways are pro= bed. - * When configured to 0 all ways in llcc are probed. + * When configured to 0 all ways in LLCC are probed. * @dis_cap_alloc: Disable capacity based allocation for a client * @retain_on_pc: If this bit is set and client has maintained active vote * then the ways assigned to this client are not flushed on = power @@ -4626,10 +4626,10 @@ static const struct qcom_sct_config x1e80100_cfgs = =3D { static struct llcc_drv_data *drv_data =3D (void *) -EPROBE_DEFER; =20 /** - * llcc_slice_getd - get llcc slice descriptor + * llcc_slice_getd - get LLCC slice descriptor * @uid: usecase_id for the client * - * A pointer to llcc slice descriptor will be returned on success + * A pointer to LLCC slice descriptor will be returned on success * and error pointer is returned on failure */ struct llcc_slice_desc *llcc_slice_getd(u32 uid) @@ -4652,8 +4652,8 @@ struct llcc_slice_desc *llcc_slice_getd(u32 uid) EXPORT_SYMBOL_GPL(llcc_slice_getd); =20 /** - * llcc_slice_putd - llcc slice descriptor - * @desc: Pointer to llcc slice descriptor + * llcc_slice_putd - LLCC slice descriptor + * @desc: Pointer to LLCC slice descriptor */ void llcc_slice_putd(struct llcc_slice_desc *desc) { @@ -4716,8 +4716,8 @@ static int llcc_update_act_ctrl(u32 sid, } =20 /** - * llcc_slice_activate - Activate the llcc slice - * @desc: Pointer to llcc slice descriptor + * llcc_slice_activate - Activate the LLCC slice + * @desc: Pointer to LLCC slice descriptor * * A value of zero will be returned on success and a negative errno will * be returned in error cases @@ -4752,8 +4752,8 @@ int llcc_slice_activate(struct llcc_slice_desc *desc) EXPORT_SYMBOL_GPL(llcc_slice_activate); =20 /** - * llcc_slice_deactivate - Deactivate the llcc slice - * @desc: Pointer to llcc slice descriptor + * llcc_slice_deactivate - Deactivate the LLCC slice + * @desc: Pointer to LLCC slice descriptor * * A value of zero will be returned on success and a negative errno will * be returned in error cases @@ -4789,7 +4789,7 @@ EXPORT_SYMBOL_GPL(llcc_slice_deactivate); =20 /** * llcc_get_slice_id - return the slice id - * @desc: Pointer to llcc slice descriptor + * @desc: Pointer to LLCC slice descriptor */ int llcc_get_slice_id(struct llcc_slice_desc *desc) { @@ -4802,7 +4802,7 @@ EXPORT_SYMBOL_GPL(llcc_get_slice_id); =20 /** * llcc_get_slice_size - return the slice id - * @desc: Pointer to llcc slice descriptor + * @desc: Pointer to LLCC slice descriptor */ size_t llcc_get_slice_size(struct llcc_slice_desc *desc) { @@ -4836,9 +4836,9 @@ static int _qcom_llcc_cfg_program(const struct llcc_s= lice_config *config, /* * LLCC instances can vary for each target. * The SW writes to broadcast register which gets propagated - * to each llcc instance (llcc0,.. llccN). + * to each LLCC instance (llcc0,.. llccN). * Since the size of the memory is divided equally amongst the - * llcc instances, we need to configure the max cap accordingly. + * LLCC instances, we need to configure the max cap accordingly. */ max_cap_cacheline =3D max_cap_cacheline / drv_data->num_banks; max_cap_cacheline >>=3D CACHE_LINE_SIZE_SHIFT; @@ -5424,7 +5424,7 @@ static int qcom_llcc_probe(struct platform_device *pd= ev) "qcom_llcc_edac", -1, drv_data, sizeof(*drv_data)); if (IS_ERR(llcc_edac)) - dev_err(dev, "Failed to register llcc edac driver\n"); + dev_err(dev, "Failed to register LLCC EDAC driver\n"); } =20 platform_set_drvdata(pdev, drv_data); diff --git a/include/linux/soc/qcom/llcc-qcom.h b/include/linux/soc/qcom/ll= cc-qcom.h index b5e917154998..f3ed63e475ab 100644 --- a/include/linux/soc/qcom/llcc-qcom.h +++ b/include/linux/soc/qcom/llcc-qcom.h @@ -89,9 +89,9 @@ =20 /** * struct llcc_slice_desc - Cache slice descriptor - * @slice_id: llcc slice id - * @uid: Unique ID associated with the llcc device - * @slice_size: Size allocated for the llcc slice + * @slice_id: LLCC slice id + * @uid: Unique ID associated with the LLCC device + * @slice_size: Size allocated for the LLCC slice * @refcount: Atomic counter to track activate/deactivate calls */ struct llcc_slice_desc { @@ -102,7 +102,7 @@ struct llcc_slice_desc { }; =20 /** - * struct llcc_edac_reg_data - llcc edac registers data for each error type + * struct llcc_edac_reg_data - LLCC EDAC registers data for each error type * @name: Name of the error * @reg_cnt: Number of registers * @count_mask: Mask value to get the error count @@ -148,17 +148,17 @@ struct llcc_edac_reg_offset { }; =20 /** - * struct llcc_drv_data - Data associated with the llcc driver - * @dev: device back-pointer for this llcc instance - * @regmaps: regmaps associated with the llcc device - * @bcast_regmap: regmap associated with llcc broadcast OR offset - * @bcast_and_regmap: regmap associated with llcc broadcast AND offset + * struct llcc_drv_data - Data associated with the LLCC driver + * @dev: device back-pointer for this LLCC instance + * @regmaps: regmaps associated with the LLCC device + * @bcast_regmap: regmap associated with LLCC broadcast OR offset + * @bcast_and_regmap: regmap associated with LLCC broadcast AND offset * @cfg: pointer to the data structure for slice configuration * @edac_reg_offset: Offset of the LLCC EDAC registers * @lock: mutex associated with each slice * @cfg_size: size of the config data table - * @num_banks: Number of llcc banks - * @ecc_irq: interrupt for llcc cache error detection and reporting + * @num_banks: Number of LLCC banks + * @ecc_irq: interrupt for LLCC cache error detection and reporting * @ecc_irq_configured: 'True' if firmware has already configured the irq = propagation * @version: Indicates the LLCC version * @desc: Array pointer of pre-allocated LLCC slice descriptors @@ -181,38 +181,38 @@ struct llcc_drv_data { =20 #if IS_ENABLED(CONFIG_QCOM_LLCC) /** - * llcc_slice_getd - get llcc slice descriptor + * llcc_slice_getd - get LLCC slice descriptor * @uid: usecase_id of the client */ struct llcc_slice_desc *llcc_slice_getd(u32 uid); =20 /** - * llcc_slice_putd - llcc slice descriptor - * @desc: Pointer to llcc slice descriptor + * llcc_slice_putd - LLCC slice descriptor + * @desc: Pointer to LLCC slice descriptor */ void llcc_slice_putd(struct llcc_slice_desc *desc); =20 /** * llcc_get_slice_id - get slice id - * @desc: Pointer to llcc slice descriptor + * @desc: Pointer to LLCC slice descriptor */ int llcc_get_slice_id(struct llcc_slice_desc *desc); =20 /** - * llcc_get_slice_size - llcc slice size - * @desc: Pointer to llcc slice descriptor + * llcc_get_slice_size - LLCC slice size + * @desc: Pointer to LLCC slice descriptor */ size_t llcc_get_slice_size(struct llcc_slice_desc *desc); =20 /** - * llcc_slice_activate - Activate the llcc slice - * @desc: Pointer to llcc slice descriptor + * llcc_slice_activate - Activate the LLCC slice + * @desc: Pointer to LLCC slice descriptor */ int llcc_slice_activate(struct llcc_slice_desc *desc); =20 /** - * llcc_slice_deactivate - Deactivate the llcc slice - * @desc: Pointer to llcc slice descriptor + * llcc_slice_deactivate - Deactivate the LLCC slice + * @desc: Pointer to LLCC slice descriptor */ int llcc_slice_deactivate(struct llcc_slice_desc *desc); =20 --=20 2.34.1