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Tue, 07 Apr 2026 06:03:34 -0700 (PDT) Received: from hu-krichai-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2b2749794e8sm181564885ad.53.2026.04.07.06.03.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Apr 2026 06:03:33 -0700 (PDT) From: Krishna Chaitanya Chundru Date: Tue, 07 Apr 2026 18:33:10 +0530 Subject: [PATCH v4 3/5] PCI: qcom: Power down PHY via PARF_PHY_CTRL before disabling rails/clocks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260407-d3cold-v4-3-bb171f75b465@oss.qualcomm.com> References: <20260407-d3cold-v4-0-bb171f75b465@oss.qualcomm.com> In-Reply-To: <20260407-d3cold-v4-0-bb171f75b465@oss.qualcomm.com> To: Jingoo Han , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Will Deacon Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, jonathanh@nvidia.com, bjorn.andersson@oss.qualcomm.com, Krishna Chaitanya Chundru X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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When the link is later transitioned towards D3cold and the driver disables PCIe clocks and/or regulators without explicitly re-asserting PHY_TEST_PWR_DOWN, the PHY can remain partially powered, leading to avoidable power leakage. Update the init-path comments to reflect that PARF_PHY_CTRL is used to power the PHY on. Also, for controller revisions that enable PHY power in init (2.3.2, 2.3.3, 2.7.0 and 2.9.0), explicitly power the PHY down via PARF_PHY_CTRL in the deinit path before disabling clocks/regulators. This ensures the PHY is put into a defined low-power state prior to removing its supplies, preventing leakage when entering D3cold. Signed-off-by: Krishna Chaitanya Chundru --- drivers/pci/controller/dwc/pcie-qcom.c | 32 +++++++++++++++++++++++++++++-= -- 1 file changed, 29 insertions(+), 3 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controlle= r/dwc/pcie-qcom.c index b00bf46637a5ff803a845719c5b0b5b82739244b..c14c3eb70f356b6ad8a2ffe48b1= 07327d2babf77 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -513,7 +513,7 @@ static int qcom_pcie_post_init_2_1_0(struct qcom_pcie *= pcie) u32 val; int ret; =20 - /* enable PCIe clocks and resets */ + /* Force PHY out of lowest power state */ val =3D readl(pcie->parf + PARF_PHY_CTRL); val &=3D ~PHY_TEST_PWR_DOWN; writel(val, pcie->parf + PARF_PHY_CTRL); @@ -680,6 +680,12 @@ static int qcom_pcie_get_resources_2_3_2(struct qcom_p= cie *pcie) static void qcom_pcie_deinit_2_3_2(struct qcom_pcie *pcie) { struct qcom_pcie_resources_2_3_2 *res =3D &pcie->res.v2_3_2; + u32 val; + + /* Force PHY to lowest power state*/ + val =3D readl(pcie->parf + PARF_PHY_CTRL); + val |=3D PHY_TEST_PWR_DOWN; + writel(val, pcie->parf + PARF_PHY_CTRL); =20 clk_bulk_disable_unprepare(res->num_clks, res->clks); regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); @@ -712,7 +718,7 @@ static int qcom_pcie_post_init_2_3_2(struct qcom_pcie *= pcie) { u32 val; =20 - /* enable PCIe clocks and resets */ + /* Force PHY out of lowest power state */ val =3D readl(pcie->parf + PARF_PHY_CTRL); val &=3D ~PHY_TEST_PWR_DOWN; writel(val, pcie->parf + PARF_PHY_CTRL); @@ -844,6 +850,12 @@ static int qcom_pcie_get_resources_2_3_3(struct qcom_p= cie *pcie) static void qcom_pcie_deinit_2_3_3(struct qcom_pcie *pcie) { struct qcom_pcie_resources_2_3_3 *res =3D &pcie->res.v2_3_3; + u32 val; + + /* Force PHY to lowest power state */ + val =3D readl(pcie->parf + PARF_PHY_CTRL); + val |=3D PHY_TEST_PWR_DOWN; + writel(val, pcie->parf + PARF_PHY_CTRL); =20 clk_bulk_disable_unprepare(res->num_clks, res->clks); } @@ -899,6 +911,7 @@ static int qcom_pcie_post_init_2_3_3(struct qcom_pcie *= pcie) u16 offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); u32 val; =20 + /* Force PHY out of lowest power state */ val =3D readl(pcie->parf + PARF_PHY_CTRL); val &=3D ~PHY_TEST_PWR_DOWN; writel(val, pcie->parf + PARF_PHY_CTRL); @@ -994,7 +1007,7 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) /* configure PCIe to RC mode */ writel(DEVICE_TYPE_RC, pcie->parf + PARF_DEVICE_TYPE); =20 - /* enable PCIe clocks and resets */ + /* Force PHY out of lowest power state */ val =3D readl(pcie->parf + PARF_PHY_CTRL); val &=3D ~PHY_TEST_PWR_DOWN; writel(val, pcie->parf + PARF_PHY_CTRL); @@ -1065,6 +1078,12 @@ static void qcom_pcie_host_post_init_2_7_0(struct qc= om_pcie *pcie) static void qcom_pcie_deinit_2_7_0(struct qcom_pcie *pcie) { struct qcom_pcie_resources_2_7_0 *res =3D &pcie->res.v2_7_0; + u32 val; + + /* Force PHY to lowest power state */ + val =3D readl(pcie->parf + PARF_PHY_CTRL); + val |=3D PHY_TEST_PWR_DOWN; + writel(val, pcie->parf + PARF_PHY_CTRL); =20 clk_bulk_disable_unprepare(res->num_clks, res->clks); =20 @@ -1169,6 +1188,12 @@ static int qcom_pcie_get_resources_2_9_0(struct qcom= _pcie *pcie) static void qcom_pcie_deinit_2_9_0(struct qcom_pcie *pcie) { struct qcom_pcie_resources_2_9_0 *res =3D &pcie->res.v2_9_0; + u32 val; + + /* Force PHY to lowest power state */ + val =3D readl(pcie->parf + PARF_PHY_CTRL); + val |=3D PHY_TEST_PWR_DOWN; + writel(val, pcie->parf + PARF_PHY_CTRL); =20 clk_bulk_disable_unprepare(res->num_clks, res->clks); } @@ -1209,6 +1234,7 @@ static int qcom_pcie_post_init_2_9_0(struct qcom_pcie= *pcie) u32 val; int i; =20 + /* Force PHY out of lowest power state */ val =3D readl(pcie->parf + PARF_PHY_CTRL); val &=3D ~PHY_TEST_PWR_DOWN; writel(val, pcie->parf + PARF_PHY_CTRL); --=20 2.34.1