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Tue, 7 Apr 2026 11:16:45 +0000 (UTC) From: rohan1sj via B4 Relay Date: Tue, 07 Apr 2026 16:48:20 +0530 Subject: [PATCH 1/2] mmc: cqe: Add CQE DT support for cadence controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260407-cdns_sdhci_cqe-support-v1-1-13efc0810631@cadence.com> References: <20260407-cdns_sdhci_cqe-support-v1-0-13efc0810631@cadence.com> In-Reply-To: <20260407-cdns_sdhci_cqe-support-v1-0-13efc0810631@cadence.com> To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Masahiro Yamada , Adrian Hunter Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Milind Parab , Swapnil Jakhade , Manikandan Pillai , rohan1sj X-Mailer: b4 0.15.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1775560710; l=1838; i=rohan1sj@cadence.com; s=20260406; h=from:subject:message-id; bh=2Nj43iUADBM6GdTZZUu58CP25EFDyw5xiqmEYK92Vd0=; b=nkSD9fkbW9vT4GqqWqXoFMbK5JQFU/fqX4Xm9VfD4l2exop9Us/vV5je4LEJrlWRnzxc/GpjC HDyWZUi/5W0BjyCFmIddTaO8zl07qhjNZW0WIC7jeGoetIA0SevFhFy X-Developer-Key: i=rohan1sj@cadence.com; a=ed25519; pk=YuwylizMVlVj8I4+VPMZ6xrFR2wyqJAWZyj90OVZgD0= X-Endpoint-Received: by B4 Relay for rohan1sj@cadence.com/20260406 with auth_id=723 X-Original-From: rohan1sj Reply-To: rohan1sj@cadence.com From: rohan1sj Add DT config required to support CQE as present in cadence eMMC host controller Signed-off-by: rohan1sj --- .../devicetree/bindings/mmc/cdns,sdhci.yaml | 32 ++++++++++++++++++= +++- 1 file changed, 31 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml b/Docume= ntation/devicetree/bindings/mmc/cdns,sdhci.yaml index ac75d694611a..c0d8aefe20c2 100644 --- a/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml +++ b/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml @@ -24,6 +24,10 @@ properties: minItems: 1 maxItems: 2 =20 + reg-names: + minItems: 1 + maxItems: 2 + interrupts: maxItems: 1 =20 @@ -139,7 +143,19 @@ allOf: else: properties: reg: - maxItems: 1 + oneOf: + - items: + - description: Host controller registers + - items: + - description: Host controller registers + - description: CQE (Command Queue Engine) registers + reg-names: + oneOf: + - items: + - const: sdhci + - items: + - const: sdhci + - const: cqhci =20 unevaluatedProperties: false =20 @@ -156,3 +172,17 @@ examples: mmc-hs400-1_8v; cdns,phy-dll-delay-sdclk =3D <0>; }; + + - | + emmc_cqe: mmc@5b000000 { + compatible =3D "socionext,uniphier-sd4hc", "cdns,sd4hc"; + reg =3D <0x5b000000 0x400>, <0x5b000400 0x060>; + reg-names =3D "sdhci", "cqhci"; + interrupts =3D <0 79 4>; + clocks =3D <&clk 4>; + bus-width =3D <8>; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + cdns,phy-dll-delay-sdclk =3D <0>; + }; --=20 2.34.1 From nobody Mon Jun 15 01:45:08 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2D9583932C6; Tue, 7 Apr 2026 11:16:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775560606; cv=none; b=qmEA/lIn1VZzKk2nVlncJQ9PG25AIvSp4SwRTLwj0X6OMuU5rJI1vhjvnUIKLA6TQMbzzDmKFQN0Lc6ZkW+XX3j+fPSjM3ue1anF55uGbGc6uAP3tlb/w3A30ZK6yTNCgvhq6YFnSn9TjUI1/pUf94pcE7f5Nlk0gEDcy4ucoPY= ARC-Message-Signature: i=1; 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b=D6DZkCN0BppF71iPb8Y2vP8shIGxjQGJz9XyrjkWxXSCP6TLayQ0Ii41k+rjBltax GaPk9WfP+4MlIyY4lH33qwR4+BW5Uki9eJJx+T7qiKAGrhUf5/TLOxkbtXCM90d3Uk 5O+2ARF15rbeIm0n4DnD8Jjww6kEhGiQW0YBqInsGl4RcUL9uzfip9YAkEuWH3pXSp 5ZEaiBU9Lx8GH4jZbv6YZULO6og3NTC9IvDUykBUNtzM3L+wSB2waGoReA40/icPDw AEkwLttLpDISpUSQAVJt4d2R1Da5tMkeMbLvItmF+EUTV+BOmymb4rTQmT9lBdHKrg SWMqdsYQpQ4cw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id E923FFEEF22; Tue, 7 Apr 2026 11:16:45 +0000 (UTC) From: rohan1sj via B4 Relay Date: Tue, 07 Apr 2026 16:48:21 +0530 Subject: [PATCH 2/2] mmc: cqe: Add CQE support for cadence mmc driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260407-cdns_sdhci_cqe-support-v1-2-13efc0810631@cadence.com> References: <20260407-cdns_sdhci_cqe-support-v1-0-13efc0810631@cadence.com> In-Reply-To: <20260407-cdns_sdhci_cqe-support-v1-0-13efc0810631@cadence.com> To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Masahiro Yamada , Adrian Hunter Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Milind Parab , Swapnil Jakhade , Manikandan Pillai , rohan1sj X-Mailer: b4 0.15.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1775560710; l=5735; i=rohan1sj@cadence.com; s=20260406; h=from:subject:message-id; bh=+nntUDDhfZrkeAothBnZqBPjeq631rcfgQpUyhq1PVY=; b=DYrbPxdOtQqGfIBg0RzUJn6ts17OhHL//tR+bKlqui/yeqXZ9fR4+J41FljP318txpo86EeVI JVSi1D3T+GTBfO9bewQhazLhkmi+QznaYEC6K05pYe+bvWiiY5DxNR1 X-Developer-Key: i=rohan1sj@cadence.com; a=ed25519; pk=YuwylizMVlVj8I4+VPMZ6xrFR2wyqJAWZyj90OVZgD0= X-Endpoint-Received: by B4 Relay for rohan1sj@cadence.com/20260406 with auth_id=723 X-Original-From: rohan1sj Reply-To: rohan1sj@cadence.com From: rohan1sj Add Command Queuing Engine (CQE) support for cadence driver Signed-off-by: rohan1sj --- drivers/mmc/host/sdhci-cadence.c | 118 +++++++++++++++++++++++++++++++++++= +++- 1 file changed, 115 insertions(+), 3 deletions(-) diff --git a/drivers/mmc/host/sdhci-cadence.c b/drivers/mmc/host/sdhci-cade= nce.c index 435603c8c00b..14b12272dae9 100644 --- a/drivers/mmc/host/sdhci-cadence.c +++ b/drivers/mmc/host/sdhci-cadence.c @@ -15,6 +15,8 @@ #include =20 #include "sdhci-pltfm.h" +#include "sdhci-cqhci.h" +#include "cqhci.h" =20 /* HRS - Host Register Set (specific to Cadence) */ #define SDHCI_CDNS_HRS04 0x10 /* PHY access port */ @@ -36,6 +38,10 @@ #define SDHCI_CDNS_HRS06_MODE_MMC_HS400 0x5 #define SDHCI_CDNS_HRS06_MODE_MMC_HS400ES 0x6 =20 +/* Host capabilities not covered by the standard capability registers (SRS= 16-SRS18) */ +#define SDHCI_CDNS_HRS30 0x78 /* Host capabilities */ +#define SDHCI_CDNS_HRS30_CQE_SUPPORTED BIT(0) + /* Read block gap */ #define SDHCI_CDNS_HRS37 0x94 /* interface mode select */ #define SDHCI_CDNS_HRS37_MODE_DS 0x0 @@ -88,6 +94,7 @@ struct sdhci_cdns_priv { void __iomem *ctl_addr; /* write control */ spinlock_t wrlock; /* write lock */ bool enhanced_strobe; + bool cqe_support; /* Command Queuing Engine support */ void (*priv_writel)(struct sdhci_cdns_priv *priv, u32 val, void __iomem *= reg); struct reset_control *rst_hw; unsigned int nr_phy_params; @@ -385,6 +392,73 @@ static void sdhci_cdns_set_uhs_signaling(struct sdhci_= host *host, sdhci_set_uhs_signaling(host, timing); } =20 +static u32 sdhci_cdns_cqhci_irq(struct sdhci_host *host, u32 intmask) +{ + int cmd_err =3D 0; + int data_err =3D 0; + + /* return original intmask to be handled by other handlers if it's not a = CQE interrupt */ + if (!sdhci_cqe_irq(host, intmask, &cmd_err, &data_err)) + return intmask; + + cqhci_irq(host->mmc, intmask, cmd_err, data_err); + + return 0; +} + +static const struct cqhci_host_ops sdhci_cdns_cqhci_ops =3D { + .enable =3D sdhci_cqe_enable, + .disable =3D sdhci_cqe_disable, +}; + +static int sdhci_cdns_cqe_add_host(struct sdhci_host *host, struct platfor= m_device *pdev) +{ + struct cqhci_host *cq_host; + bool dma64; + int ret; + + /* setup SDHCI host first */ + ret =3D sdhci_setup_host(host); + + if (ret) + return ret; + + /* Init CQE */ + cq_host =3D cqhci_pltfm_init(pdev); + if (IS_ERR(cq_host)) { + ret =3D PTR_ERR(cq_host); + goto cleanup; + } + + dma64 =3D host->flags & SDHCI_USE_64_BIT_DMA; + if (dma64) + cq_host->caps |=3D CQHCI_TASK_DESC_SZ_128; + + cq_host->ops =3D &sdhci_cdns_cqhci_ops; + + host->mmc->caps2 |=3D MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; + + /* Finally initialize CQHCI */ + ret =3D cqhci_init(cq_host, host->mmc, dma64); + if (ret) { + dev_err(mmc_dev(host->mmc), "Failed to initialize CQHCI: %d\n", ret); + goto cleanup; + } + + /* add host to MMC subsystem */ + ret =3D __sdhci_add_host(host); + if (ret) + goto cleanup; + + dev_info(mmc_dev(host->mmc), "CQE init: success\n"); + return 0; + +cleanup: + dev_err(mmc_dev(host->mmc), "CQE init: failed for %s\n", mmc_hostname(hos= t->mmc)); + sdhci_cleanup_host(host); + return ret; +} + /* Elba control register bits [6:3] are byte-lane enables */ #define ELBA_BYTE_ENABLE_MASK(x) ((x) << 3) =20 @@ -474,9 +548,10 @@ static const struct sdhci_ops sdhci_cdns_ops =3D { .set_clock =3D sdhci_set_clock, .get_timeout_clock =3D sdhci_cdns_get_timeout_clock, .set_bus_width =3D sdhci_set_bus_width, - .reset =3D sdhci_reset, + .reset =3D sdhci_and_cqhci_reset, .platform_execute_tuning =3D sdhci_cdns_execute_tuning, .set_uhs_signaling =3D sdhci_cdns_set_uhs_signaling, + .irq =3D sdhci_cdns_cqhci_irq, }; =20 static const struct sdhci_cdns_drv_data sdhci_cdns_uniphier_drv_data =3D { @@ -553,6 +628,8 @@ static int sdhci_cdns_probe(struct platform_device *pde= v) int ret; struct device *dev =3D &pdev->dev; static const u16 version =3D SDHCI_SPEC_400 << SDHCI_SPEC_VER_SHIFT; + bool cqe_enabled; + u32 host_caps; =20 clk =3D devm_clk_get_enabled(dev, NULL); if (IS_ERR(clk)) @@ -608,7 +685,35 @@ static int sdhci_cdns_probe(struct platform_device *pd= ev) host->mmc_host_ops.card_hw_reset =3D sdhci_cdns_mmc_hw_reset; } =20 - return sdhci_add_host(host); + host_caps =3D readl(priv->hrs_addr + SDHCI_CDNS_HRS30); + cqe_enabled =3D host_caps & SDHCI_CDNS_HRS30_CQE_SUPPORTED; + + if (cqe_enabled) { + priv->cqe_support =3D true; + ret =3D sdhci_cdns_cqe_add_host(host, pdev); + } else { + ret =3D sdhci_add_host(host); + } + + return ret; +} + +static int sdhci_cdns_suspend(struct device *dev) +{ + struct sdhci_host *host =3D dev_get_drvdata(dev); + struct sdhci_pltfm_host *pltfm_host =3D sdhci_priv(host); + struct sdhci_cdns_priv *priv =3D sdhci_pltfm_priv(pltfm_host); + int ret; + + if (priv->cqe_support) { + ret =3D cqhci_suspend(host->mmc); + if (ret) + return ret; + } + + ret =3D sdhci_pltfm_suspend(dev); + + return ret; } =20 static int sdhci_cdns_resume(struct device *dev) @@ -630,6 +735,13 @@ static int sdhci_cdns_resume(struct device *dev) if (ret) goto disable_clk; =20 + /* Resume CQE if enabled */ + if (priv->cqe_support) { + ret =3D cqhci_resume(host->mmc); + if (ret) + goto disable_clk; + } + return 0; =20 disable_clk: @@ -638,7 +750,7 @@ static int sdhci_cdns_resume(struct device *dev) return ret; } =20 -static DEFINE_SIMPLE_DEV_PM_OPS(sdhci_cdns_pm_ops, sdhci_pltfm_suspend, sd= hci_cdns_resume); +static DEFINE_SIMPLE_DEV_PM_OPS(sdhci_cdns_pm_ops, sdhci_cdns_suspend, sdh= ci_cdns_resume); =20 static const struct of_device_id sdhci_cdns_match[] =3D { { --=20 2.34.1