From nobody Sun Jun 21 04:17:37 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 19B3C3BADB2; Tue, 7 Apr 2026 14:30:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775572211; cv=none; b=VAEHLEUX2lUqM+odqUML2WU/wK15iAh2IDIEFXaC5OWEIqnwVyuU4q1NOBjTuwW+SFewjqTq86I1r3VR+9VOV3FQCHroHvc/A9m787m0xQyn5ZBsJFUYZTcWO4V/g3jWv/sDO4Z+bce9k5Vb2+Vvo5kRgmtroY+1yjKn5MyAClQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775572211; c=relaxed/simple; bh=H/ZjhYgrW3VND0oifQK7yUnQ24qHMPGKHi0BUoEY5sc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=OpCvh10qD7m2IheSAHkO7lYFz3F+WeqJejuHi558CkVi2CVHSYWcHeax4VF/lnZjv8M4u9fEURqXyXch4z8bWOZEhLwQD+YKrvc2Tfhg7HtHjgvJvZjBhjTfzo0j/gDzjvAummGymW/LJF562ldA5v/yNeL3x3KBe0o4jCEyu2g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=LvCt7trh; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="LvCt7trh" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C6D1AC2BCB0; Tue, 7 Apr 2026 14:30:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1775572211; bh=H/ZjhYgrW3VND0oifQK7yUnQ24qHMPGKHi0BUoEY5sc=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=LvCt7trhYrin7vmw0KGlxThv1JqXPC/SnLO0rfKa8S1mowBnzeXYbGqNm+DGZDIPm Ve+KHt7WItbaxsfYzUsa6aVYZw8eMMZYEM7p/t86J88d+81PryhHYYUzpz84r3DqKb 6lyviNyMOSHm4QrUDAhsaAqeDpx0R1kfs5RohacPgzLpQ4szxwJX05DuAZIxDQTfbn KMG0XZhgn9y+5R94Tmw2lrWVdH00wkMbO9Iltfgg+x72Ny6RrYmb2sB11vAzkRdab0 0p9I3pwQ72lkrxInh1wj80M+GVT/mesFaizqDmEJlGlWs8DfR0uf2wHtOYbWa2SBI9 hZXx36JxqEvyA== From: "Rob Herring (Arm)" Date: Tue, 07 Apr 2026 09:29:43 -0500 Subject: [PATCH v4 1/6] arm64: hw_breakpoint: Disallow breakpoints in no kprobe code Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260407-arm-debug-8-9-v4-1-a4864e69b0ea@kernel.org> References: <20260407-arm-debug-8-9-v4-0-a4864e69b0ea@kernel.org> In-Reply-To: <20260407-arm-debug-8-9-v4-0-a4864e69b0ea@kernel.org> To: Will Deacon , Mark Rutland , Catalin Marinas , Jonathan Corbet , Shuah Khan Cc: Anshuman Khandual , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org X-Mailer: b4 0.15-dev Taking debug exceptions while manipulating the breakpoints is likely to be unsafe. The setting kprobes in the breakpoint code is already forbidden, but the setting of h/w breakpoints is not. Copy what x86 does and exclude breakpoints that fall within the kprobe section. Signed-off-by: Rob Herring (Arm) --- arch/arm64/kernel/hw_breakpoint.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/kernel/hw_breakpoint.c b/arch/arm64/kernel/hw_break= point.c index ab76b36dce82..38fbd67b2a6e 100644 --- a/arch/arm64/kernel/hw_breakpoint.c +++ b/arch/arm64/kernel/hw_breakpoint.c @@ -418,6 +418,16 @@ static int arch_build_bp_info(struct perf_event *bp, /* Type */ switch (attr->bp_type) { case HW_BREAKPOINT_X: + /* + * We don't allow kernel breakpoints in places that are not + * acceptable for kprobes. On non-kprobes kernels, we don't + * allow kernel breakpoints at all. + */ + if (attr->bp_addr >=3D TASK_SIZE_MAX) { + if (within_kprobe_blacklist(attr->bp_addr)) + return -EINVAL; + } + hw->ctrl.type =3D ARM_BREAKPOINT_EXECUTE; break; case HW_BREAKPOINT_R: --=20 2.53.0 From nobody Sun Jun 21 04:17:37 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D39F025A2B5; Tue, 7 Apr 2026 14:30:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775572212; cv=none; b=bAKY0iY0oXKOWbO9JEZDwsFB4vTd0MMvxrtm+x/op+w29/8izjFhLax2v+IQLSS/A3zePsijYOFdsiFa2VAxHyeomVhuXa0AwG67n9QafcenJ/QgxW67JnTYvkdp2Jy/YPkleoH/CravaReDTjWc3MH8GHWzlOYQcdKRqKjgtU4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775572212; c=relaxed/simple; bh=zXlPjSjJdZ1ja9eNaaYsLbU6jHV6bkXu/LbF2O2Rslk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=jO76tDAaMJ4EB02Za2worB7mYo0mtgc5k3ubvT+vL3arR16W7/eWIHHofk97jGQ6Vzy8ji6TARNV60xQNg3udehAN1rkkNLjYDGVcrT33Z97wSr1FRbaO65qxIIv5uDO3MXETNNlTmvhKu5WLRjLLirCWRFHaY9LagIgfz8UIew= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=SRPEz+/S; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="SRPEz+/S" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 49D43C116C6; Tue, 7 Apr 2026 14:30:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1775572212; bh=zXlPjSjJdZ1ja9eNaaYsLbU6jHV6bkXu/LbF2O2Rslk=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=SRPEz+/S9/dK0A8JDQ5OuY1+2hVd/bEf8LIdeTo7yHf322NXXtQM1BkEBJRBU6diL sqNBr7Q12MAkwoYlQv6IXEBdjZYQ9i/gFuGZ0C9w+0uLaeDzKsdSwhMLBtc9a/9w3C C58O4MbwdDhqHYhs0gWMDXWdiUhEEhsdkeRnqRfM0L2+Ei2U5zY9keavYeAgwikSks /CMaDawUPm6w3swEDWL05/694l8lod7hNgg+bQ2OOpqPzacLlylJjLtqmNTUfU4T3G AZSvD76WdsKm/aciB9ija91/NZUydkwXgzY35IOCVMfhbTOT/Jm31wR2v+DoVjO0iS 2OejfP+JtlXQw== From: "Rob Herring (Arm)" Date: Tue, 07 Apr 2026 09:29:44 -0500 Subject: [PATCH v4 2/6] arm64: hw_breakpoint: Add additional kprobe excluded functions Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260407-arm-debug-8-9-v4-2-a4864e69b0ea@kernel.org> References: <20260407-arm-debug-8-9-v4-0-a4864e69b0ea@kernel.org> In-Reply-To: <20260407-arm-debug-8-9-v4-0-a4864e69b0ea@kernel.org> To: Will Deacon , Mark Rutland , Catalin Marinas , Jonathan Corbet , Shuah Khan Cc: Anshuman Khandual , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org X-Mailer: b4 0.15-dev Everything that either runs during exceptions or touches the breakpoint/watchpoint registers should be excluded from kprobes and breakpoints. The static functions are may or may not end up in the no kprobe section depending on whether the compiler inlines them or not. They are likely inlined, but make it explicit to ensure that they always are. Unfortunately, it is not possible to leave the inlining decision up to the compiler and place code within the no kprobes section. Parts of what hw_breakpoint_control() calls are excluded already. Just exclude all of it to be safe. Signed-off-by: Rob Herring (Arm) --- arch/arm64/kernel/hw_breakpoint.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/arch/arm64/kernel/hw_breakpoint.c b/arch/arm64/kernel/hw_break= point.c index 38fbd67b2a6e..bb39bc759810 100644 --- a/arch/arm64/kernel/hw_breakpoint.c +++ b/arch/arm64/kernel/hw_breakpoint.c @@ -187,9 +187,9 @@ static int is_compat_bp(struct perf_event *bp) * -ENOSPC if no slot is available/matches * -EINVAL on wrong operations parameter */ -static int hw_breakpoint_slot_setup(struct perf_event **slots, int max_slo= ts, - struct perf_event *bp, - enum hw_breakpoint_ops ops) +static nokprobe_inline int +hw_breakpoint_slot_setup(struct perf_event **slots, int max_slots, + struct perf_event *bp, enum hw_breakpoint_ops ops) { int i; struct perf_event **slot; @@ -283,6 +283,7 @@ static int hw_breakpoint_control(struct perf_event *bp, =20 return 0; } +NOKPROBE_SYMBOL(hw_breakpoint_control); =20 /* * Install a perf counter breakpoint. @@ -718,8 +719,8 @@ NOKPROBE_SYMBOL(do_breakpoint); * The function returns the distance of the address from the bytes watched= by * the watchpoint. In case of an exact match, it returns 0. */ -static u64 get_distance_from_watchpoint(unsigned long addr, u64 val, - struct arch_hw_breakpoint_ctrl *ctrl) +static nokprobe_inline u64 get_distance_from_watchpoint(unsigned long addr= , u64 val, + struct arch_hw_breakpoint_ctrl *ctrl) { u64 wp_low, wp_high; u32 lens, lene; @@ -739,8 +740,8 @@ static u64 get_distance_from_watchpoint(unsigned long a= ddr, u64 val, return 0; } =20 -static int watchpoint_report(struct perf_event *wp, unsigned long addr, - struct pt_regs *regs) +static nokprobe_inline int watchpoint_report(struct perf_event *wp, unsign= ed long addr, + struct pt_regs *regs) { int step =3D is_default_overflow_handler(wp); struct arch_hw_breakpoint *info =3D counter_arch_bp(wp); --=20 2.53.0 From nobody Sun Jun 21 04:17:37 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 69FCA3BD258; Tue, 7 Apr 2026 14:30:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775572214; cv=none; b=Llw10X76YmQdcpdFzoWPH7x+MOUpYTYhB94UyFDng+3F4efI/3NEwgaMyvJ99IJAvH19bWSSGSVghI4VMix9rSb3YnajyNF3V7NHNwZo0Kl0+qqhtARWWR0ms0AiT7NI1labxoNyNlOy3m63uFZnmoIfjHgOwUfILXqo/mos9zE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775572214; c=relaxed/simple; bh=2mBdtCMg5XJhO2It05OyZWImRJfyjVt9ZDQUn9Uv+L8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=glkJ2hhirsXFaTXtaNBg5c2nPmvlVHI8M30muXaorN0p6o8boCTwjJA3/CJ1R23myaC9SPv5z9TqvVXNmYzD5mHKRAPBrl/RWAGWKv0FI3KAG0+3dqvzvD2jBSxil1IrTJqZ12VhEbzQjakXZczs3Ls+p+hQyVxDyXSpfRigmUI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=P5rUk0l1; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="P5rUk0l1" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C939DC2BCB2; Tue, 7 Apr 2026 14:30:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1775572214; bh=2mBdtCMg5XJhO2It05OyZWImRJfyjVt9ZDQUn9Uv+L8=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=P5rUk0l17s8TR/KCexB3phw3iVAAw23OVADZWDCjcg1bB08aGDgI4zPKMy1oLe5bs viE39t/tVnQSD21ApcnfZ0RNMwbq+DSQDctZlMR3sjHAvdllC8fDW1TtCxa2NfGlc1 FLtai55m3VKhyc5TnXNphhf7fVspNz1aQm4TF2Bhwgt663SUsvRljb3P63Yv2cImNK mfwkuB8PgNOgQ7n4C96Rrzz6tGPfWMJKDqShG20TTCrOkzCQXXQ/VeiI9B8FRQjSc0 Ino1vjGOmwJl9Oheg1jZ2jaPKwlG07F/8IG6MmBQc++Ua/MrvUC574ZL1DfiSevXdk xcCMoGn71QsJQ== From: "Rob Herring (Arm)" Date: Tue, 07 Apr 2026 09:29:45 -0500 Subject: [PATCH v4 3/6] arm64: hw_breakpoint: Add lockdep_assert_irqs_disabled() on install/uninstall Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260407-arm-debug-8-9-v4-3-a4864e69b0ea@kernel.org> References: <20260407-arm-debug-8-9-v4-0-a4864e69b0ea@kernel.org> In-Reply-To: <20260407-arm-debug-8-9-v4-0-a4864e69b0ea@kernel.org> To: Will Deacon , Mark Rutland , Catalin Marinas , Jonathan Corbet , Shuah Khan Cc: Anshuman Khandual , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org X-Mailer: b4 0.15-dev The breakpoint install/uninstall/restore code depends on interrupts being disabled. Make this requirement explicit with a lockdep_assert_irqs_disabled() assertion. Signed-off-by: Rob Herring (Arm) --- arch/arm64/kernel/hw_breakpoint.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/kernel/hw_breakpoint.c b/arch/arm64/kernel/hw_break= point.c index bb39bc759810..a9266dc710b4 100644 --- a/arch/arm64/kernel/hw_breakpoint.c +++ b/arch/arm64/kernel/hw_breakpoint.c @@ -231,6 +231,8 @@ static int hw_breakpoint_control(struct perf_event *bp, enum dbg_active_el dbg_el =3D debug_exception_level(info->ctrl.privilege); u32 ctrl; =20 + lockdep_assert_irqs_disabled(); + if (info->ctrl.type =3D=3D ARM_BREAKPOINT_EXECUTE) { /* Breakpoint */ ctrl_reg =3D AARCH64_DBG_REG_BCR; --=20 2.53.0 From nobody Sun Jun 21 04:17:37 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4EF563BED79; Tue, 7 Apr 2026 14:30:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775572216; cv=none; b=oVZHccz72ONcmQkWtLjoWO6ix1RCOTk+AsU2ApBFcrDQ+yCi7L+L15Q7dCTeQfXuFtQmwZ4GlXB7Ocmq7FNLNRqBNfVtbHRCHW/n2j7JChcPpC9ieMtUPaGJqtRf4GaY1FGxce8Q6jZ9D61TCP19UWFfZtRKS9kpPfzQ7KSalL0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775572216; c=relaxed/simple; bh=uUvq9MVXp8cNAvU8/2GcbzCtpuny4H9rPPxomu7v7sY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=bXj9XSbSbbd8kIWZH7iNlgoEL1N4RAupmrG1PfRT36VZCIsd6qrEaKlHdggiWRd7iGV4av68TkQ3y8EKE3uFX1zI9r3m2HRbXTQwzyvKPhDqViWJeCjys9pXih9JCWM/XNhKAm8Y9XXZi4VBoU0A7S1VF27M37tZ+bT1SeYe0qQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=jy/SsEhE; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="jy/SsEhE" Received: by smtp.kernel.org (Postfix) with ESMTPSA id B5AE5C2BCB2; Tue, 7 Apr 2026 14:30:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1775572215; bh=uUvq9MVXp8cNAvU8/2GcbzCtpuny4H9rPPxomu7v7sY=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=jy/SsEhEUWFlpfnTq1KI4r1d6pxJti65E4Z1yn9omGYV4MzOcFY8gZkxjuawQCxf1 CQYvaEMbRdpdqMQl9EZVxBq2fyZJ4AVEY+0rS3WmwSnNIV3E9WB5VJEFHCMDea2lvu Z1nlthzoAQtoXaEB2jxZSQ51VxbZzwBA/34jzuXhinCjuUWz7SMwhqrfLTopdi9n6Z TU/bL5LZShtuIzau4bkAoSoZlZmIozavChyCxCkEaIGUw8jTFpra6NbpLP603qlmCY F7M6BC0qngv3ZR76nax53PV+PAkBdjj5ah/atADVYZVXHUC/JfKYjpokg4GwwbaikS qJod4SznuhSZA== From: "Rob Herring (Arm)" Date: Tue, 07 Apr 2026 09:29:46 -0500 Subject: [PATCH v4 4/6] arm64/cpufeature: Add field details for ID_AA64DFR1_EL1 register Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260407-arm-debug-8-9-v4-4-a4864e69b0ea@kernel.org> References: <20260407-arm-debug-8-9-v4-0-a4864e69b0ea@kernel.org> In-Reply-To: <20260407-arm-debug-8-9-v4-0-a4864e69b0ea@kernel.org> To: Will Deacon , Mark Rutland , Catalin Marinas , Jonathan Corbet , Shuah Khan Cc: Anshuman Khandual , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org X-Mailer: b4 0.15-dev From: Anshuman Khandual This adds required field details for ID_AA64DFR1_EL1, and also drops dummy ftr_raz[] array which is now redundant. These register fields will be used to enable increased breakpoint and watchpoint registers via FEAT_Debugv8p9 later. The register fields have been marked as FTR_STRICT, unless there is a known variation in practice. Signed-off-by: Anshuman Khandual Signed-off-by: Rob Herring (Arm) --- arch/arm64/kernel/cpufeature.c | 21 ++++++++++++++++----- 1 file changed, 16 insertions(+), 5 deletions(-) diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index c31f8e17732a..24c8e9147e35 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -570,6 +570,21 @@ static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = =3D { ARM64_FTR_END, }; =20 +static const struct arm64_ftr_bits ftr_id_aa64dfr1[] =3D { + ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR1_EL1= _ABL_CMPs_SHIFT, 8, 0), + ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR1_EL1= _DPFZS_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR1_EL1_EB= EP_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR1_EL1_IT= E_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR1_EL1= _ABLE_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR1_EL1= _PMICNTR_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR1_EL1_SP= MU_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR1_EL1= _CTX_CMPs_SHIFT, 8, 0), + ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR1_EL1= _WRPs_SHIFT, 8, 0), + ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR1_EL1= _BRPs_SHIFT, 8, 0), + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR1_EL1_SY= SPMUID_SHIFT, 8, 0), + ARM64_FTR_END, +}; + static const struct arm64_ftr_bits ftr_mvfr0[] =3D { ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPRound_= SHIFT, 4, 0), ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPShVec_= SHIFT, 4, 0), @@ -756,10 +771,6 @@ static const struct arm64_ftr_bits ftr_single32[] =3D { ARM64_FTR_END, }; =20 -static const struct arm64_ftr_bits ftr_raz[] =3D { - ARM64_FTR_END, -}; - #define __ARM64_FTR_REG_OVERRIDE(id_str, id, table, ovr) { \ .sys_id =3D id, \ .reg =3D &(struct arm64_ftr_reg){ \ @@ -832,7 +843,7 @@ static const struct __ftr_reg_entry { =20 /* Op1 =3D 0, CRn =3D 0, CRm =3D 5 */ ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0), - ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz), + ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_id_aa64dfr1), =20 /* Op1 =3D 0, CRn =3D 0, CRm =3D 6 */ ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0), --=20 2.53.0 From nobody Sun Jun 21 04:17:37 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A562C175A9D; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="BtTCSSex" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2794CC19424; Tue, 7 Apr 2026 14:30:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1775572217; bh=S2a66R25M2ED9iApd77nQWSljUUEXLR9ndadmbDuSus=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=BtTCSSexqqOVxXwcQ414Ny61PUY9mAcMdzGtvv4DmvWPbKwDzO3QUKIOZawG4NDBb 27cpDSCJqdFlxHkKlEEb0cm4OE+pvfqM2BcaTdmMwHXRkKx8p6x4Qds7OGnitTRCyL c+2q63xzYl2N+RWGeOg8aONVk+gRTVX21H96AF6if+3FyFs1a+/SnK89JNa4DDY+eN rJ6mB/4gyXQcScgfPE+ruhjydng5z5fWep7FOTW/8ffKw6QKM37R01tNh5/nzowm3t /FXODuhHIQ5sS6lu3xtkgOM4HHWlbiwvfOVoF9fAy9nG/u4qJDy5BVjsA6ltQ1ZN79 +FTX5kl9dXb0A== From: "Rob Herring (Arm)" Date: Tue, 07 Apr 2026 09:29:47 -0500 Subject: [PATCH v4 5/6] arm64/boot: Enable EL2 requirements for FEAT_Debugv8p9 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260407-arm-debug-8-9-v4-5-a4864e69b0ea@kernel.org> References: <20260407-arm-debug-8-9-v4-0-a4864e69b0ea@kernel.org> In-Reply-To: <20260407-arm-debug-8-9-v4-0-a4864e69b0ea@kernel.org> To: Will Deacon , Mark Rutland , Catalin Marinas , Jonathan Corbet , Shuah Khan Cc: Anshuman Khandual , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Marc Zyngier , kvmarm@lists.linux.dev, Oliver Upton X-Mailer: b4 0.15-dev From: Anshuman Khandual Fine grained trap control for MDSELR_EL1 register needs to be configured in HDFGRTR2_EL2, and HDFGWTR2_EL2 registers when kernel enters at EL1, but EL2 is also present. MDCR_EL2.EBWE needs to be enabled for additional (beyond 16) breakpoint and watchpoint exceptions when kernel enters at EL1, but EL2 is also present. While here, also update booting.rst with MDCR_EL3 and SCR_EL3 requirements. Cc: Marc Zyngier Cc: Oliver Upton Cc: kvmarm@lists.linux.dev Signed-off-by: Anshuman Khandual Signed-off-by: Rob Herring (Arm) --- v4: - Add that the requirements only apply when there are >16 breakpoints/watchpoints - Adapt to changes in v7.0-rc1 --- Documentation/arch/arm64/booting.rst | 13 +++++++++++++ arch/arm64/include/asm/el2_setup.h | 14 ++++++++++++++ 2 files changed, 27 insertions(+) diff --git a/Documentation/arch/arm64/booting.rst b/Documentation/arch/arm6= 4/booting.rst index 13ef311dace8..00ba91bbd278 100644 --- a/Documentation/arch/arm64/booting.rst +++ b/Documentation/arch/arm64/booting.rst @@ -369,6 +369,19 @@ Before jumping into the kernel, the following conditio= ns must be met: - ZCR_EL2.LEN must be initialised to the same value for all CPUs the kernel will execute on. =20 + For CPUs with FEAT_Debugv8p9 extension present and >16 breakpoints or + watchpoints: + + - If the kernel is entered at EL1 and EL2 is present: + + - HDFGRTR2_EL2.nMDSELR_EL1 (bit 5) must be initialized to 0b1 + - HDFGWTR2_EL2.nMDSELR_EL1 (bit 5) must be initialized to 0b1 + - MDCR_EL2.EBWE (bit 43) must be initialized to 0b1 + + - If EL3 is present: + + - MDCR_EL3.EBWE (bit 43) must be initialized to 0b1 + For CPUs with the Scalable Matrix Extension (FEAT_SME): =20 - If EL3 is present: diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el= 2_setup.h index 85f4c1615472..b51a280c18c0 100644 --- a/arch/arm64/include/asm/el2_setup.h +++ b/arch/arm64/include/asm/el2_setup.h @@ -174,6 +174,13 @@ // to own it. =20 .Lskip_trace_\@: + mrs x1, id_aa64dfr0_el1 + ubfx x1, x1, #ID_AA64DFR0_EL1_DebugVer_SHIFT, #4 + cmp x1, #ID_AA64DFR0_EL1_DebugVer_V8P9 + b.lt .Lskip_dbg_v8p9_\@ + + orr x2, x2, #MDCR_EL2_EBWE +.Lskip_dbg_v8p9_\@: msr mdcr_el2, x2 // Configure debug traps .endm =20 @@ -438,6 +445,13 @@ orr x0, x0, #HDFGRTR2_EL2_nPMSDSFR_EL1 =20 .Lskip_spefds_\@: + mrs x1, id_aa64dfr0_el1 + ubfx x1, x1, #ID_AA64DFR0_EL1_DebugVer_SHIFT, #4 + cmp x1, #ID_AA64DFR0_EL1_DebugVer_V8P9 + b.lt .Lskip_dbg_v8p9_\@ + + mov_q x0, HDFGWTR2_EL2_nMDSELR_EL1 +.Lskip_dbg_v8p9_\@: msr_s SYS_HDFGRTR2_EL2, x0 msr_s SYS_HDFGWTR2_EL2, x0 msr_s SYS_HFGRTR2_EL2, xzr --=20 2.53.0 From nobody Sun Jun 21 04:17:37 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7AB4627EFE9; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ZEBen4WD" Received: by smtp.kernel.org (Postfix) with ESMTPSA id B1A10C2BCB5; Tue, 7 Apr 2026 14:30:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1775572218; bh=SJDQ3b5SsRthX8/7tiLEloyuRg0cJ7pkoH2/b6dPyTw=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=ZEBen4WD5noftUnkL55UHtJD5sfjPzXnWFbmZAjtb3mJX89esSwhus8rJnPftmxe+ FbtJlWTqB1BK1ORUdlnYLkDy2hiQu18chJxTBCnau2CgCoIoF6XqlSjK2uEUYZmmEm w6cqdP+DkrUkK2FfDLCfEjzycA9ZfQtFPEwYVbPLrJH0mT/WwpzLPk8khqfn+vuwWx C161Q+FNw0IfMZ+5dbDKMzUP/d06V8gn4zLsxtRlfJZQtJ+AYCCLS/Kk8So2nUivk0 5iRf9TNvlLxC7M62XO2Iex6CCrh5xA/+aiBzbSO2I1YwVacszwEDUpfBaMqXsL0W0V 8eh6SB2Tq4e2A== From: "Rob Herring (Arm)" Date: Tue, 07 Apr 2026 09:29:48 -0500 Subject: [PATCH v4 6/6] arm64: hw_breakpoint: Enable FEAT_Debugv8p9 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260407-arm-debug-8-9-v4-6-a4864e69b0ea@kernel.org> References: <20260407-arm-debug-8-9-v4-0-a4864e69b0ea@kernel.org> In-Reply-To: <20260407-arm-debug-8-9-v4-0-a4864e69b0ea@kernel.org> To: Will Deacon , Mark Rutland , Catalin Marinas , Jonathan Corbet , Shuah Khan Cc: Anshuman Khandual , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org X-Mailer: b4 0.15-dev From: Anshuman Khandual Currently, there can be maximum 16 breakpoints and 16 watchpoints available on a given platform - as detected from ID_AA64DFR0_EL1.[BRPs|WRPs] register fields. These breakpoints and watchpoints can be extended further up to 64 via a new arch feature FEAT_Debugv8p9. Checking for FEAT_Debugv8p9 alone is not enough to enable the support. It is also necessary to determine if there are more than 16 breakpoints or watchpoints. The behavior with FEAT_Debugv8p9 and <=3D16 breakpoints and watchpoints is IMPDEF. The addition of the MDSELR_EL1 to set the bank index makes the register accesses non-atomic. However, the combination of all the breakpoint code being in the kprobe blacklist and breakpoint install/uninstall being protected by perf locking (IRQs disabled and context lock) will prevent debug exceptions during accesses and serialize the accesses. Signed-off-by: Anshuman Khandual Signed-off-by: Rob Herring (Arm) --- v4: - Update commit message. - Configure MDSCR_EL1_EMBWE on CPU reset/hotplug instead of every time breakpoints are enabled/disabled. - Drop unnecessary IRQ save and restore on register accesses. - Stash checking whether FEAT_Debugv8p9 is used rather than reading feature register on every register access. - Check that we're greater than or equal to Debug_v8p9 not just equal to. - Use is_debug_v8p9_enabled() in get_num_brps/get_num_wrps(). Handle the case when FEAT_Debugv8p9 is present, but the number of BP/WP are <16. It is IMPDEF if ID_AA64DFR1_EL1 is used in this case. It is also IMPDEF if MDSELR_EL1 is accessible. TF-A doesn't enable access to MDSELR_EL1 in this case. - Mark register access functions nokprobe. --- arch/arm64/include/asm/hw_breakpoint.h | 47 ++++++++++++++++++++++++++----= ---- arch/arm64/kernel/debug-monitors.c | 16 ++++++++---- arch/arm64/kernel/hw_breakpoint.c | 41 +++++++++++++++++++++++++++-- 3 files changed, 87 insertions(+), 17 deletions(-) diff --git a/arch/arm64/include/asm/hw_breakpoint.h b/arch/arm64/include/as= m/hw_breakpoint.h index bd81cf17744a..c5624a906f3c 100644 --- a/arch/arm64/include/asm/hw_breakpoint.h +++ b/arch/arm64/include/asm/hw_breakpoint.h @@ -79,8 +79,9 @@ static inline void decode_ctrl_reg(u32 reg, * Limits. * Changing these will require modifications to the register accessors. */ -#define ARM_MAX_BRP 16 -#define ARM_MAX_WRP 16 +#define ARM_MAX_BRP 64 +#define ARM_MAX_WRP 64 +#define MAX_PER_BANK 16 =20 /* Virtual debug register bases. */ #define AARCH64_DBG_REG_BVR 0 @@ -94,6 +95,14 @@ static inline void decode_ctrl_reg(u32 reg, #define AARCH64_DBG_REG_NAME_WVR wvr #define AARCH64_DBG_REG_NAME_WCR wcr =20 +static inline bool is_debug_v8p9_enabled(void) +{ + u64 dfr0 =3D read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1); + int dver =3D cpuid_feature_extract_unsigned_field(dfr0, ID_AA64DFR0_EL1_D= ebugVer_SHIFT); + + return dver >=3D ID_AA64DFR0_EL1_DebugVer_V8P9; +} + /* Accessor macros for the debug registers. */ #define AARCH64_DBG_READ(N, REG, VAL) do {\ VAL =3D read_sysreg(dbg##REG##N##_el1);\ @@ -138,19 +147,37 @@ static inline void ptrace_hw_copy_thread(struct task_= struct *task) /* Determine number of BRP registers available. */ static inline int get_num_brps(void) { - u64 dfr0 =3D read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1); - return 1 + - cpuid_feature_extract_unsigned_field(dfr0, - ID_AA64DFR0_EL1_BRPs_SHIFT); + u64 dfr0, dfr1; + int brps; + + dfr0 =3D read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1); + brps =3D cpuid_feature_extract_unsigned_field(dfr0, ID_AA64DFR0_EL1_BRPs_= SHIFT); + if (is_debug_v8p9_enabled() && brps =3D=3D 15) { + dfr1 =3D read_sanitised_ftr_reg(SYS_ID_AA64DFR1_EL1); + brps =3D cpuid_feature_extract_unsigned_field_width(dfr1, + ID_AA64DFR1_EL1_BRPs_SHIFT, 8); + if (!brps) + return 16; + } + return 1 + brps; } =20 /* Determine number of WRP registers available. */ static inline int get_num_wrps(void) { - u64 dfr0 =3D read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1); - return 1 + - cpuid_feature_extract_unsigned_field(dfr0, - ID_AA64DFR0_EL1_WRPs_SHIFT); + u64 dfr0, dfr1; + int wrps; + + dfr0 =3D read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1); + wrps =3D cpuid_feature_extract_unsigned_field(dfr0, ID_AA64DFR0_EL1_WRPs_= SHIFT); + if (is_debug_v8p9_enabled() && wrps =3D=3D 15) { + dfr1 =3D read_sanitised_ftr_reg(SYS_ID_AA64DFR1_EL1); + wrps =3D cpuid_feature_extract_unsigned_field_width(dfr1, + ID_AA64DFR1_EL1_WRPs_SHIFT, 8); + if (!wrps) + return 16; + } + return 1 + wrps; } =20 #ifdef CONFIG_CPU_PM diff --git a/arch/arm64/kernel/debug-monitors.c b/arch/arm64/kernel/debug-m= onitors.c index 29307642f4c9..8ff74432d0c3 100644 --- a/arch/arm64/kernel/debug-monitors.c +++ b/arch/arm64/kernel/debug-monitors.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include @@ -123,11 +124,16 @@ void disable_debug_monitors(enum dbg_active_el el) } NOKPROBE_SYMBOL(disable_debug_monitors); =20 -/* - * OS lock clearing. - */ -static int clear_os_lock(unsigned int cpu) +static int debug_monitors_reset(unsigned int cpu) { + if (is_debug_v8p9_enabled()) { + u64 mdscr =3D mdscr_read(); + + mdscr |=3D MDSCR_EL1_EMBWE; + mdscr_write(mdscr); + } + + /* Clear OS lock */ write_sysreg(0, osdlr_el1); write_sysreg(0, oslar_el1); isb(); @@ -138,7 +144,7 @@ static int __init debug_monitors_init(void) { return cpuhp_setup_state(CPUHP_AP_ARM64_DEBUG_MONITORS_STARTING, "arm64/debug_monitors:starting", - clear_os_lock, NULL); + debug_monitors_reset, NULL); } postcore_initcall(debug_monitors_init); =20 diff --git a/arch/arm64/kernel/hw_breakpoint.c b/arch/arm64/kernel/hw_break= point.c index a9266dc710b4..ea48c1562bee 100644 --- a/arch/arm64/kernel/hw_breakpoint.c +++ b/arch/arm64/kernel/hw_breakpoint.c @@ -40,6 +40,7 @@ static DEFINE_PER_CPU(int, stepping_kernel_bp); /* Number of BRP/WRP registers on this CPU. */ static int core_num_brps; static int core_num_wrps; +static bool has_debug_v8p9; =20 int hw_breakpoint_slots(int type) { @@ -104,7 +105,7 @@ int hw_breakpoint_slots(int type) WRITE_WB_REG_CASE(OFF, 14, REG, VAL); \ WRITE_WB_REG_CASE(OFF, 15, REG, VAL) =20 -static u64 read_wb_reg(int reg, int n) +static nokprobe_inline u64 __read_wb_reg(int reg, int n) { u64 val =3D 0; =20 @@ -119,9 +120,27 @@ static u64 read_wb_reg(int reg, int n) =20 return val; } + +static u64 read_wb_reg(int reg, int n) +{ + u64 val; + + /* + * Bank selection in MDSELR_EL1, followed by an indexed read from + * breakpoint (or watchpoint) registers cannot be interrupted, as + * that might cause misread from the wrong targets instead. Hence + * this requires mutual exclusion. + */ + if (has_debug_v8p9) { + write_sysreg_s(SYS_FIELD_PREP(MDSELR_EL1, BANK, n / MAX_PER_BANK), SYS_M= DSELR_EL1); + isb(); + } + val =3D __read_wb_reg(reg, n % MAX_PER_BANK); + return val; +} NOKPROBE_SYMBOL(read_wb_reg); =20 -static void write_wb_reg(int reg, int n, u64 val) +static nokprobe_inline void __write_wb_reg(int reg, int n, u64 val) { switch (reg + n) { GEN_WRITE_WB_REG_CASES(AARCH64_DBG_REG_BVR, AARCH64_DBG_REG_NAME_BVR, val= ); @@ -133,6 +152,21 @@ static void write_wb_reg(int reg, int n, u64 val) } isb(); } + +static void write_wb_reg(int reg, int n, u64 val) +{ + /* + * Bank selection in MDSELR_EL1, followed by an indexed read from + * breakpoint (or watchpoint) registers cannot be interrupted, as + * that might cause misread from the wrong targets instead. Hence + * this requires mutual exclusion. + */ + if (has_debug_v8p9) { + write_sysreg_s(SYS_FIELD_PREP(MDSELR_EL1, BANK, n / MAX_PER_BANK), SYS_M= DSELR_EL1); + isb(); + } + __write_wb_reg(reg, n % MAX_PER_BANK, val); +} NOKPROBE_SYMBOL(write_wb_reg); =20 /* @@ -990,6 +1024,7 @@ static int __init arch_hw_breakpoint_init(void) =20 core_num_brps =3D get_num_brps(); core_num_wrps =3D get_num_wrps(); + has_debug_v8p9 =3D (core_num_brps > 16) || (core_num_wrps > 16); =20 pr_info("found %d breakpoint and %d watchpoint registers.\n", core_num_brps, core_num_wrps); @@ -1006,6 +1041,8 @@ static int __init arch_hw_breakpoint_init(void) =20 /* Register cpu_suspend hw breakpoint restore hook */ cpu_suspend_set_dbg_restorer(hw_breakpoint_reset); + BUILD_BUG_ON((ARM_MAX_BRP % MAX_PER_BANK) !=3D 0); + BUILD_BUG_ON((ARM_MAX_WRP % MAX_PER_BANK) !=3D 0); =20 return ret; } --=20 2.53.0