From nobody Sun Jun 21 06:29:08 2026 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2CF9C3921E3; Mon, 6 Apr 2026 18:13:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.21.23.139 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775499196; cv=none; b=BJpfgEzHh7VHnfNvpjxAPRkq3V6iEysF3e/UGB12Oxaw1lcDydzzhCaBf83LHza5Rdvj+Q09XoP0f+z1Y+8t3dZpCRlHfsroHVK2Gz2qC63lg55ArAS7uqtKBGc0D3KUYubOFfPJ1zbAhiCwQL04cOH559IL8kB6pOcUZTVh/sQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775499196; c=relaxed/simple; bh=AsXZHe8dhzo/iV7ai1HnoAnUoNxuSgEq0RdX3yPSBFs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=eTdLm9ERUuqACzvwkgYpjIp1fPixQNrPT0pY14wMx213SSWrobuuY+fYscbfsz86CnVk8iqGMZyOYkEhtgD2wMsHGOfbpjWOUwRwa4oJlK0sNis3LzuIC3KJxq/tbONb84NCW9xBRLEdUJTsGapEe590eZHVdY5rl4UN8CfeEjM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org; spf=pass smtp.mailfrom=disroot.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b=ighzWj/k; arc=none smtp.client-ip=178.21.23.139 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=disroot.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b="ighzWj/k" Received: from [127.0.0.1] (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id C26D7271C5; Mon, 6 Apr 2026 20:13:12 +0200 (CEST) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id FRfC7Y_FFm5T; Mon, 6 Apr 2026 20:13:12 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1775499191; bh=AsXZHe8dhzo/iV7ai1HnoAnUoNxuSgEq0RdX3yPSBFs=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=ighzWj/kRuYvWME5OHu/g4tYQSctPfv0Uq/FHXLOzc3jRZ+lhO9dZdHoEts1RkIdJ tmctHylLf9v9ZA+akMaxMxB7ZO6y/iN15i1w8+ylr8ZA1btq5fM4NucUGu5DwCUG1T VcpG1Zs7PXPeY2cOu67uBRfRsYJ+rYr+1QWEPWssnEmE0hmO6S1m4h2h9BiqMcjO3f q74VPHq1wipCO0wMskOVK+PPqruA0rOBk7z+oaIhwYoX2kROfJVsSQ0K2qxrRBtTQS vfcxJxmkazV4b9Qsz160Pa7gxgWwqScxpxlvVpWgxFvQjK1dIBh3dBL9bJJmeTsPql QjFn3sKHZhHow== From: Rustam Adilov To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Stanley Chang , linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Rustam Adilov , Michael Zavertkin Subject: [PATCH v4 1/6] phy: realtek: usb2: introduce vstatus/new_reg_req variables to driver data Date: Mon, 6 Apr 2026 23:12:23 +0500 Message-ID: <20260406181228.25892-2-adilov@disroot.org> In-Reply-To: <20260406181228.25892-1-adilov@disroot.org> References: <20260406181228.25892-1-adilov@disroot.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In RTL9607C SoC, the vstatus register is located at a certain offset from the base and so introduce the vstatus_offset to handle it. Busy bit of the vstatus and new_reg_req bit are also different and so introduce these variables to the driver data as well. Add these variables to the pre-existing phy cfg structs for RTD SoCs and assign them the default values. Co-developed-by: Michael Zavertkin Signed-off-by: Michael Zavertkin Signed-off-by: Rustam Adilov --- drivers/phy/realtek/phy-rtk-usb2.c | 59 ++++++++++++++++++++++++------ 1 file changed, 48 insertions(+), 11 deletions(-) diff --git a/drivers/phy/realtek/phy-rtk-usb2.c b/drivers/phy/realtek/phy-r= tk-usb2.c index 248550ef98ca..f5d2f0c3376a 100644 --- a/drivers/phy/realtek/phy-rtk-usb2.c +++ b/drivers/phy/realtek/phy-rtk-usb2.c @@ -64,6 +64,9 @@ struct phy_reg { void __iomem *reg_wrap_vstatus; void __iomem *reg_gusb2phyacc0; int vstatus_index; + int vstatus_offset; + int vstatus_busy; + int new_reg_req; }; =20 struct phy_data { @@ -96,6 +99,9 @@ struct phy_cfg { bool do_toggle_driving; bool use_default_parameter; bool is_double_sensitivity_mode; + int vstatus_offset; + int vstatus_busy; + int new_reg_req; }; =20 struct phy_parameter { @@ -162,21 +168,21 @@ static char rtk_phy_read(struct phy_reg *phy_reg, cha= r addr) addr -=3D OFFEST_PHY_READ; =20 /* polling until VBusy =3D=3D 0 */ - ret =3D utmi_wait_register(reg_gusb2phyacc0, PHY_VSTS_BUSY, 0); + ret =3D utmi_wait_register(reg_gusb2phyacc0, phy_reg->vstatus_busy, 0); if (ret) return (char)ret; =20 /* VCtrl =3D low nibble of addr, and set PHY_NEW_REG_REQ */ - val =3D PHY_NEW_REG_REQ | (GET_LOW_NIBBLE(addr) << PHY_VCTRL_SHIFT); + val =3D phy_reg->new_reg_req | (GET_LOW_NIBBLE(addr) << PHY_VCTRL_SHIFT); writel(val, reg_gusb2phyacc0); - ret =3D utmi_wait_register(reg_gusb2phyacc0, PHY_VSTS_BUSY, 0); + ret =3D utmi_wait_register(reg_gusb2phyacc0, phy_reg->vstatus_busy, 0); if (ret) return (char)ret; =20 /* VCtrl =3D high nibble of addr, and set PHY_NEW_REG_REQ */ - val =3D PHY_NEW_REG_REQ | (GET_HIGH_NIBBLE(addr) << PHY_VCTRL_SHIFT); + val =3D phy_reg->new_reg_req | (GET_HIGH_NIBBLE(addr) << PHY_VCTRL_SHIFT); writel(val, reg_gusb2phyacc0); - ret =3D utmi_wait_register(reg_gusb2phyacc0, PHY_VSTS_BUSY, 0); + ret =3D utmi_wait_register(reg_gusb2phyacc0, phy_reg->vstatus_busy, 0); if (ret) return (char)ret; =20 @@ -194,25 +200,25 @@ static int rtk_phy_write(struct phy_reg *phy_reg, cha= r addr, char data) int ret =3D 0; =20 /* write data to VStatusOut2 (data output to phy) */ - writel((u32)data << shift_bits, reg_wrap_vstatus); + writel((u32)data << shift_bits, reg_wrap_vstatus + phy_reg->vstatus_offse= t); =20 - ret =3D utmi_wait_register(reg_gusb2phyacc0, PHY_VSTS_BUSY, 0); + ret =3D utmi_wait_register(reg_gusb2phyacc0, phy_reg->vstatus_busy, 0); if (ret) return ret; =20 /* VCtrl =3D low nibble of addr, set PHY_NEW_REG_REQ */ - val =3D PHY_NEW_REG_REQ | (GET_LOW_NIBBLE(addr) << PHY_VCTRL_SHIFT); + val =3D phy_reg->new_reg_req | (GET_LOW_NIBBLE(addr) << PHY_VCTRL_SHIFT); =20 writel(val, reg_gusb2phyacc0); - ret =3D utmi_wait_register(reg_gusb2phyacc0, PHY_VSTS_BUSY, 0); + ret =3D utmi_wait_register(reg_gusb2phyacc0, phy_reg->vstatus_busy, 0); if (ret) return ret; =20 /* VCtrl =3D high nibble of addr, set PHY_NEW_REG_REQ */ - val =3D PHY_NEW_REG_REQ | (GET_HIGH_NIBBLE(addr) << PHY_VCTRL_SHIFT); + val =3D phy_reg->new_reg_req | (GET_HIGH_NIBBLE(addr) << PHY_VCTRL_SHIFT); =20 writel(val, reg_gusb2phyacc0); - ret =3D utmi_wait_register(reg_gusb2phyacc0, PHY_VSTS_BUSY, 0); + ret =3D utmi_wait_register(reg_gusb2phyacc0, phy_reg->vstatus_busy, 0); if (ret) return ret; =20 @@ -957,6 +963,7 @@ static int get_phy_data_by_efuse(struct rtk_phy *rtk_ph= y, =20 static int parse_phy_data(struct rtk_phy *rtk_phy) { + struct phy_cfg *phy_cfg =3D rtk_phy->phy_cfg; struct device *dev =3D rtk_phy->dev; struct device_node *np =3D dev->of_node; struct phy_parameter *phy_parameter; @@ -974,6 +981,9 @@ static int parse_phy_data(struct rtk_phy *rtk_phy) phy_parameter->phy_reg.reg_wrap_vstatus =3D of_iomap(np, 0); phy_parameter->phy_reg.reg_gusb2phyacc0 =3D of_iomap(np, 1) + index; phy_parameter->phy_reg.vstatus_index =3D index; + phy_parameter->phy_reg.vstatus_offset =3D phy_cfg->vstatus_offset; + phy_parameter->phy_reg.vstatus_busy =3D phy_cfg->vstatus_busy; + phy_parameter->phy_reg.new_reg_req =3D phy_cfg->new_reg_req; =20 if (of_property_read_bool(np, "realtek,inverse-hstx-sync-clock")) phy_parameter->inverse_hstx_sync_clock =3D true; @@ -1085,6 +1095,9 @@ static const struct phy_cfg rtd1295_phy_cfg =3D { .driving_updated_for_dev_dis =3D 0xf, .use_default_parameter =3D false, .is_double_sensitivity_mode =3D false, + .vstatus_offset =3D 0, + .vstatus_busy =3D PHY_VSTS_BUSY, + .new_reg_req =3D PHY_NEW_REG_REQ, }; =20 static const struct phy_cfg rtd1395_phy_cfg =3D { @@ -1109,6 +1122,9 @@ static const struct phy_cfg rtd1395_phy_cfg =3D { .driving_updated_for_dev_dis =3D 0xf, .use_default_parameter =3D false, .is_double_sensitivity_mode =3D false, + .vstatus_offset =3D 0, + .vstatus_busy =3D PHY_VSTS_BUSY, + .new_reg_req =3D PHY_NEW_REG_REQ, }; =20 static const struct phy_cfg rtd1395_phy_cfg_2port =3D { @@ -1133,6 +1149,9 @@ static const struct phy_cfg rtd1395_phy_cfg_2port =3D= { .driving_updated_for_dev_dis =3D 0xf, .use_default_parameter =3D false, .is_double_sensitivity_mode =3D false, + .vstatus_offset =3D 0, + .vstatus_busy =3D PHY_VSTS_BUSY, + .new_reg_req =3D PHY_NEW_REG_REQ, }; =20 static const struct phy_cfg rtd1619_phy_cfg =3D { @@ -1155,6 +1174,9 @@ static const struct phy_cfg rtd1619_phy_cfg =3D { .driving_updated_for_dev_dis =3D 0xf, .use_default_parameter =3D false, .is_double_sensitivity_mode =3D false, + .vstatus_offset =3D 0, + .vstatus_busy =3D PHY_VSTS_BUSY, + .new_reg_req =3D PHY_NEW_REG_REQ, }; =20 static const struct phy_cfg rtd1319_phy_cfg =3D { @@ -1181,6 +1203,9 @@ static const struct phy_cfg rtd1319_phy_cfg =3D { .driving_updated_for_dev_dis =3D 0xf, .use_default_parameter =3D false, .is_double_sensitivity_mode =3D true, + .vstatus_offset =3D 0, + .vstatus_busy =3D PHY_VSTS_BUSY, + .new_reg_req =3D PHY_NEW_REG_REQ, }; =20 static const struct phy_cfg rtd1312c_phy_cfg =3D { @@ -1206,6 +1231,9 @@ static const struct phy_cfg rtd1312c_phy_cfg =3D { .driving_updated_for_dev_dis =3D 0xf, .use_default_parameter =3D false, .is_double_sensitivity_mode =3D true, + .vstatus_offset =3D 0, + .vstatus_busy =3D PHY_VSTS_BUSY, + .new_reg_req =3D PHY_NEW_REG_REQ, }; =20 static const struct phy_cfg rtd1619b_phy_cfg =3D { @@ -1231,6 +1259,9 @@ static const struct phy_cfg rtd1619b_phy_cfg =3D { .driving_updated_for_dev_dis =3D 0x8, .use_default_parameter =3D false, .is_double_sensitivity_mode =3D true, + .vstatus_offset =3D 0, + .vstatus_busy =3D PHY_VSTS_BUSY, + .new_reg_req =3D PHY_NEW_REG_REQ, }; =20 static const struct phy_cfg rtd1319d_phy_cfg =3D { @@ -1256,6 +1287,9 @@ static const struct phy_cfg rtd1319d_phy_cfg =3D { .driving_updated_for_dev_dis =3D 0x8, .use_default_parameter =3D false, .is_double_sensitivity_mode =3D true, + .vstatus_offset =3D 0, + .vstatus_busy =3D PHY_VSTS_BUSY, + .new_reg_req =3D PHY_NEW_REG_REQ, }; =20 static const struct phy_cfg rtd1315e_phy_cfg =3D { @@ -1282,6 +1316,9 @@ static const struct phy_cfg rtd1315e_phy_cfg =3D { .driving_updated_for_dev_dis =3D 0x8, .use_default_parameter =3D false, .is_double_sensitivity_mode =3D true, + .vstatus_offset =3D 0, + .vstatus_busy =3D PHY_VSTS_BUSY, + .new_reg_req =3D PHY_NEW_REG_REQ, }; =20 static const struct of_device_id usbphy_rtk_dt_match[] =3D { --=20 2.53.0 From nobody Sun Jun 21 06:29:08 2026 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7A8783932DF; Mon, 6 Apr 2026 18:13:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.21.23.139 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775499198; cv=none; b=FkWU1kAGvy9x7konuEhY8B2AVJUVB9gB/EtUEgSiEyu3WPDL4x7pyOSGppFwY6/KAv/ZOFUJKXGA5BSpREppDspc5mG4r4phudXCguDPYJvclCFWUb1XgCZcaapuVMSY7A9s/vPzVeCpfrB6d1aDigrG2LtkW2kLasZU+3QBQyg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775499198; c=relaxed/simple; bh=gIZeKQ/pICKwWE/VdqKZ3JQLiyrx2OmNRFtpK70fdEc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=R2of2SOrB59r44LhIakdgFQhBvF9MT2RVvIKoBdujPtSMV8Kyo75Odr4v/TQ/x3dv/Uy4Eb9gvZLYHfq89lKPTN24r6GPDfx0mwd07JJTHHnnzTAUcczQ9i+FpsEuEmfpvGlz1Vo6ltCeXH7B1NAimaFJxQlcFSQFN8s4pmnYaM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org; spf=pass smtp.mailfrom=disroot.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b=GxdQSGAh; arc=none smtp.client-ip=178.21.23.139 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=disroot.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b="GxdQSGAh" Received: from [127.0.0.1] (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id 279FD271E5; Mon, 6 Apr 2026 20:13:15 +0200 (CEST) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with UTF8SMTP id ZVndUVLmG6Zn; Mon, 6 Apr 2026 20:13:14 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1775499194; bh=gIZeKQ/pICKwWE/VdqKZ3JQLiyrx2OmNRFtpK70fdEc=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=GxdQSGAhezM8aD2UjxZlu1rMnBzMqmzBVYZlcCl02luP87wStfgnZ232G5P79prji QUpTfPllcmdofDcU8Kh3kmjn3AvzQN3odqe9Jh17QgGPiqflfSIaOo9eObxxbmnw9y rUTXnMmneRoYQO31LwfcawNHLvktM2taUnsgbj9dBczpZD2gn9k7U5+ldYetokZ2gr z6zNjBeSw2CJQyLm7qj1vAnLH38wNEd1Xa2sryXJ7Qnp6BcVh6nfnPWtsOumqCbVbA JwIS3dbN47kx12ZJZ6yv5FmeE/H3N78kPeAmgW6AAg+jyLFLPpl+VSsioGPrrN1jsS xC3Mk/9oRDypQ== From: Rustam Adilov To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Stanley Chang , linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Rustam Adilov , Michael Zavertkin Subject: [PATCH v4 2/6] phy: realtek: usb2: introduce read and write functions to driver data Date: Mon, 6 Apr 2026 23:12:24 +0500 Message-ID: <20260406181228.25892-3-adilov@disroot.org> In-Reply-To: <20260406181228.25892-1-adilov@disroot.org> References: <20260406181228.25892-1-adilov@disroot.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" RTL9607C is a big endian SoC but has little endian USB host controller and thus, reads and writes to the reg_gusb2phyacc0 should go through le32_to_cpu and cpu_to_le32 functions respectively. This doesn't apply to vstatus register though. The reason is readl/writel functions, despite the supposed little endian byte swap, still operate with native endian. The __raw_{read,write} are also native endianness. And so wrapping them around le32 makes a proper byte swap from big endian to little endian. To handle this situation, introduce read and write functions to the driver data and create a default variation of read and write function for the current RTD SoCs. Adjust all instances of utmi_wait_register function to now include the read function as one of its arguments. Assign the existing phy configuration for RTD SoCs to the default read and write functions. Co-developed-by: Michael Zavertkin Signed-off-by: Michael Zavertkin Signed-off-by: Rustam Adilov --- drivers/phy/realtek/phy-rtk-usb2.c | 63 ++++++++++++++++++++++++------ 1 file changed, 50 insertions(+), 13 deletions(-) diff --git a/drivers/phy/realtek/phy-rtk-usb2.c b/drivers/phy/realtek/phy-r= tk-usb2.c index f5d2f0c3376a..0facd5f02e2d 100644 --- a/drivers/phy/realtek/phy-rtk-usb2.c +++ b/drivers/phy/realtek/phy-rtk-usb2.c @@ -67,6 +67,9 @@ struct phy_reg { int vstatus_offset; int vstatus_busy; int new_reg_req; + + u32 (*read)(void __iomem *reg); + void (*write)(u32 val, void __iomem *reg); }; =20 struct phy_data { @@ -102,6 +105,9 @@ struct phy_cfg { int vstatus_offset; int vstatus_busy; int new_reg_req; + + u32 (*read)(void __iomem *reg); + void (*write)(u32 val, void __iomem *reg); }; =20 struct phy_parameter { @@ -128,6 +134,16 @@ struct rtk_phy { struct dentry *debug_dir; }; =20 +static u32 rtk_usb2phy_read(void __iomem *reg) +{ + return readl(reg); +} + +static void rtk_usb2phy_write(u32 val, void __iomem *reg) +{ + writel(val, reg); +} + /* mapping 0xE0 to 0 ... 0xE7 to 7, 0xF0 to 8 ,,, 0xF7 to 15 */ static inline int page_addr_to_array_index(u8 addr) { @@ -144,12 +160,13 @@ static inline u8 array_index_to_page_addr(int index) #define PHY_IO_TIMEOUT_USEC (50000) #define PHY_IO_DELAY_US (100) =20 -static inline int utmi_wait_register(void __iomem *reg, u32 mask, u32 resu= lt) +static inline int utmi_wait_register(u32 (*read)(void __iomem *reg), void = __iomem *reg, u32 mask, + u32 result) { int ret; unsigned int val; =20 - ret =3D read_poll_timeout(readl, val, ((val & mask) =3D=3D result), + ret =3D read_poll_timeout(read, val, ((val & mask) =3D=3D result), PHY_IO_DELAY_US, PHY_IO_TIMEOUT_USEC, false, reg); if (ret) { pr_err("%s can't program USB phy\n", __func__); @@ -168,25 +185,25 @@ static char rtk_phy_read(struct phy_reg *phy_reg, cha= r addr) addr -=3D OFFEST_PHY_READ; =20 /* polling until VBusy =3D=3D 0 */ - ret =3D utmi_wait_register(reg_gusb2phyacc0, phy_reg->vstatus_busy, 0); + ret =3D utmi_wait_register(phy_reg->read, reg_gusb2phyacc0, phy_reg->vsta= tus_busy, 0); if (ret) return (char)ret; =20 /* VCtrl =3D low nibble of addr, and set PHY_NEW_REG_REQ */ val =3D phy_reg->new_reg_req | (GET_LOW_NIBBLE(addr) << PHY_VCTRL_SHIFT); - writel(val, reg_gusb2phyacc0); - ret =3D utmi_wait_register(reg_gusb2phyacc0, phy_reg->vstatus_busy, 0); + phy_reg->write(val, reg_gusb2phyacc0); + ret =3D utmi_wait_register(phy_reg->read, reg_gusb2phyacc0, phy_reg->vsta= tus_busy, 0); if (ret) return (char)ret; =20 /* VCtrl =3D high nibble of addr, and set PHY_NEW_REG_REQ */ val =3D phy_reg->new_reg_req | (GET_HIGH_NIBBLE(addr) << PHY_VCTRL_SHIFT); - writel(val, reg_gusb2phyacc0); - ret =3D utmi_wait_register(reg_gusb2phyacc0, phy_reg->vstatus_busy, 0); + phy_reg->write(val, reg_gusb2phyacc0); + ret =3D utmi_wait_register(phy_reg->read, reg_gusb2phyacc0, phy_reg->vsta= tus_busy, 0); if (ret) return (char)ret; =20 - val =3D readl(reg_gusb2phyacc0); + val =3D phy_reg->read(reg_gusb2phyacc0); =20 return (char)(val & PHY_REG_DATA_MASK); } @@ -202,23 +219,23 @@ static int rtk_phy_write(struct phy_reg *phy_reg, cha= r addr, char data) /* write data to VStatusOut2 (data output to phy) */ writel((u32)data << shift_bits, reg_wrap_vstatus + phy_reg->vstatus_offse= t); =20 - ret =3D utmi_wait_register(reg_gusb2phyacc0, phy_reg->vstatus_busy, 0); + ret =3D utmi_wait_register(phy_reg->read, reg_gusb2phyacc0, phy_reg->vsta= tus_busy, 0); if (ret) return ret; =20 /* VCtrl =3D low nibble of addr, set PHY_NEW_REG_REQ */ val =3D phy_reg->new_reg_req | (GET_LOW_NIBBLE(addr) << PHY_VCTRL_SHIFT); =20 - writel(val, reg_gusb2phyacc0); - ret =3D utmi_wait_register(reg_gusb2phyacc0, phy_reg->vstatus_busy, 0); + phy_reg->write(val, reg_gusb2phyacc0); + ret =3D utmi_wait_register(phy_reg->read, reg_gusb2phyacc0, phy_reg->vsta= tus_busy, 0); if (ret) return ret; =20 /* VCtrl =3D high nibble of addr, set PHY_NEW_REG_REQ */ val =3D phy_reg->new_reg_req | (GET_HIGH_NIBBLE(addr) << PHY_VCTRL_SHIFT); =20 - writel(val, reg_gusb2phyacc0); - ret =3D utmi_wait_register(reg_gusb2phyacc0, phy_reg->vstatus_busy, 0); + phy_reg->write(val, reg_gusb2phyacc0); + ret =3D utmi_wait_register(phy_reg->read, reg_gusb2phyacc0, phy_reg->vsta= tus_busy, 0); if (ret) return ret; =20 @@ -984,6 +1001,8 @@ static int parse_phy_data(struct rtk_phy *rtk_phy) phy_parameter->phy_reg.vstatus_offset =3D phy_cfg->vstatus_offset; phy_parameter->phy_reg.vstatus_busy =3D phy_cfg->vstatus_busy; phy_parameter->phy_reg.new_reg_req =3D phy_cfg->new_reg_req; + phy_parameter->phy_reg.read =3D phy_cfg->read; + phy_parameter->phy_reg.write =3D phy_cfg->write; =20 if (of_property_read_bool(np, "realtek,inverse-hstx-sync-clock")) phy_parameter->inverse_hstx_sync_clock =3D true; @@ -1098,6 +1117,8 @@ static const struct phy_cfg rtd1295_phy_cfg =3D { .vstatus_offset =3D 0, .vstatus_busy =3D PHY_VSTS_BUSY, .new_reg_req =3D PHY_NEW_REG_REQ, + .read =3D rtk_usb2phy_read, + .write =3D rtk_usb2phy_write, }; =20 static const struct phy_cfg rtd1395_phy_cfg =3D { @@ -1125,6 +1146,8 @@ static const struct phy_cfg rtd1395_phy_cfg =3D { .vstatus_offset =3D 0, .vstatus_busy =3D PHY_VSTS_BUSY, .new_reg_req =3D PHY_NEW_REG_REQ, + .read =3D rtk_usb2phy_read, + .write =3D rtk_usb2phy_write, }; =20 static const struct phy_cfg rtd1395_phy_cfg_2port =3D { @@ -1152,6 +1175,8 @@ static const struct phy_cfg rtd1395_phy_cfg_2port =3D= { .vstatus_offset =3D 0, .vstatus_busy =3D PHY_VSTS_BUSY, .new_reg_req =3D PHY_NEW_REG_REQ, + .read =3D rtk_usb2phy_read, + .write =3D rtk_usb2phy_write, }; =20 static const struct phy_cfg rtd1619_phy_cfg =3D { @@ -1177,6 +1202,8 @@ static const struct phy_cfg rtd1619_phy_cfg =3D { .vstatus_offset =3D 0, .vstatus_busy =3D PHY_VSTS_BUSY, .new_reg_req =3D PHY_NEW_REG_REQ, + .read =3D rtk_usb2phy_read, + .write =3D rtk_usb2phy_write, }; =20 static const struct phy_cfg rtd1319_phy_cfg =3D { @@ -1206,6 +1233,8 @@ static const struct phy_cfg rtd1319_phy_cfg =3D { .vstatus_offset =3D 0, .vstatus_busy =3D PHY_VSTS_BUSY, .new_reg_req =3D PHY_NEW_REG_REQ, + .read =3D rtk_usb2phy_read, + .write =3D rtk_usb2phy_write, }; =20 static const struct phy_cfg rtd1312c_phy_cfg =3D { @@ -1234,6 +1263,8 @@ static const struct phy_cfg rtd1312c_phy_cfg =3D { .vstatus_offset =3D 0, .vstatus_busy =3D PHY_VSTS_BUSY, .new_reg_req =3D PHY_NEW_REG_REQ, + .read =3D rtk_usb2phy_read, + .write =3D rtk_usb2phy_write, }; =20 static const struct phy_cfg rtd1619b_phy_cfg =3D { @@ -1262,6 +1293,8 @@ static const struct phy_cfg rtd1619b_phy_cfg =3D { .vstatus_offset =3D 0, .vstatus_busy =3D PHY_VSTS_BUSY, .new_reg_req =3D PHY_NEW_REG_REQ, + .read =3D rtk_usb2phy_read, + .write =3D rtk_usb2phy_write, }; =20 static const struct phy_cfg rtd1319d_phy_cfg =3D { @@ -1290,6 +1323,8 @@ static const struct phy_cfg rtd1319d_phy_cfg =3D { .vstatus_offset =3D 0, .vstatus_busy =3D PHY_VSTS_BUSY, .new_reg_req =3D PHY_NEW_REG_REQ, + .read =3D rtk_usb2phy_read, + .write =3D rtk_usb2phy_write, }; =20 static const struct phy_cfg rtd1315e_phy_cfg =3D { @@ -1319,6 +1354,8 @@ static const struct phy_cfg rtd1315e_phy_cfg =3D { .vstatus_offset =3D 0, .vstatus_busy =3D PHY_VSTS_BUSY, .new_reg_req =3D PHY_NEW_REG_REQ, + .read =3D rtk_usb2phy_read, + .write =3D rtk_usb2phy_write, }; =20 static const struct of_device_id usbphy_rtk_dt_match[] =3D { --=20 2.53.0 From nobody Sun Jun 21 06:29:08 2026 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E73A53921DC; Mon, 6 Apr 2026 18:13:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.21.23.139 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775499202; cv=none; b=NyimLCch5m8vd+3rSO4lOQGUK2AE48Spw523raBhwNNtPhuCquQ0QK8fv5QQqfxNVVC0oF91Egybm9mecar2S7OJCLHGa5mqEmkqpwhwcLXJ5n7Z7XovoUZLtey8v2sTZVSmBUoTaDW7GhG/aLXj9q0x5NlteMMslDRgWEBAdAU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775499202; c=relaxed/simple; bh=q1+LKLLtR1bAaINu5uVU69ZrC7e0Z0cwmPf7kJz6BLI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Npt8afZIrW/Y3oCPHRppQ0iekHK1w8O6IMFngvKaN2o4FTpJYgR5dDJB6pCUMnZw5JeUw/mtxyGkK1B/K5IfkycdQtmoNWjMXuOK9Hi4AJd7Mf4CDeKIXcbaHg7wtY3r6oaD3NsKz3xK3oIOBUxZLO58OsrwfZ+7KsRU2DQZlSI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org; spf=pass smtp.mailfrom=disroot.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b=ic7pP+af; arc=none smtp.client-ip=178.21.23.139 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=disroot.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b="ic7pP+af" Received: from [127.0.0.1] (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id 89CBE264DC; Mon, 6 Apr 2026 20:13:17 +0200 (CEST) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id mlL4EYys3aXy; Mon, 6 Apr 2026 20:13:17 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1775499197; bh=q1+LKLLtR1bAaINu5uVU69ZrC7e0Z0cwmPf7kJz6BLI=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=ic7pP+afh1y8QoHApbqIB6BbTWGY//wibXP3EAhZB8YLM936S7xlDCYXOjZS1BNU9 yg9m/oZpNMk+Ry1RNdreQ9NgHcjeX3K3ihw3bgUuO4ILlriswPwWLvQnjlV5/d8kuP GIZbAgaiR+UAN7DK26qD9djNj4dckLGH3n938ct60w+aJc+xpmTsoPS6DrsnIVK0ie QpRZxggjDfIwtIcSKT+CP8YXREhSlHTQG0EzBMgrltjeULw5QJK22CHp5ChRxAXVM0 PvR/r3c178dk+KtM1Uf3hYTbYoERS5euMg7yuKOGKtacl8iiYC8koK0Wzma+kpK4vJ sorOXvy9TG37g== From: Rustam Adilov To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Stanley Chang , linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Rustam Adilov , Krzysztof Kozlowski Subject: [PATCH v4 3/6] dt-bindings: phy: realtek,usb2phy.yaml: extend for resets and RTL9607C support Date: Mon, 6 Apr 2026 23:12:25 +0500 Message-ID: <20260406181228.25892-4-adilov@disroot.org> In-Reply-To: <20260406181228.25892-1-adilov@disroot.org> References: <20260406181228.25892-1-adilov@disroot.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the "realtek,rtl9607-usb2phy" compatible for USB2 PHY on the RTL9607C SoC series. Add a resets property to properties to describe the usb2phy reset line. In RTL9607C, USB2 PHY reset line is from "IP Enable controller" which is multipurpose and handle activating various SoC peripherals. It is unclear whether RTD SoCs have something similar to that so set the resets to false for these devices. RTL9607C requires the "resets" to be specified so add the corresponding if check for the "realtek,rtl9607-usb2phy" compatible. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Rustam Adilov --- .../bindings/phy/realtek,usb2phy.yaml | 25 ++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/phy/realtek,usb2phy.yaml b/D= ocumentation/devicetree/bindings/phy/realtek,usb2phy.yaml index 9911ada39ee7..7b50833c8e19 100644 --- a/Documentation/devicetree/bindings/phy/realtek,usb2phy.yaml +++ b/Documentation/devicetree/bindings/phy/realtek,usb2phy.yaml @@ -11,7 +11,8 @@ maintainers: - Stanley Chang =20 description: | - Realtek USB 2.0 PHY support the digital home center (DHC) RTD series SoC= s. + Realtek USB 2.0 PHY support the digital home center (DHC) RTD and + RTL9607C series SoCs. The USB 2.0 PHY driver is designed to support the XHCI controller. The S= oCs support multiple XHCI controllers. One PHY device node maps to one XHCI controller. @@ -57,6 +58,12 @@ description: | XHCI controller#1 -- usb2phy -- phy#0 XHCI controller#2 -- usb2phy -- phy#0 =20 + RTL9607C SoCs USB + The USB architecture includes OHCI and EHCI controllers. + Both of them map to one USB2.0 PHY. + OHCI controller#0 -- usb2phy -- phy#0 + EHCI controller#0 -- usb2phy -- phy#0 + properties: compatible: enum: @@ -69,6 +76,7 @@ properties: - realtek,rtd1395-usb2phy-2port - realtek,rtd1619-usb2phy - realtek,rtd1619b-usb2phy + - realtek,rtl9607-usb2phy =20 reg: items: @@ -130,6 +138,9 @@ properties: minimum: -8 maximum: 8 =20 + resets: + maxItems: 1 + required: - compatible - reg @@ -157,6 +168,18 @@ allOf: then: properties: realtek,driving-level-compensate: false + - if: + properties: + compatible: + contains: + enum: + - realtek,rtl9607-usb2phy + then: + required: + - resets + else: + properties: + resets: false =20 additionalProperties: false =20 --=20 2.53.0 From nobody Sun Jun 21 06:29:08 2026 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4567D3932C9; Mon, 6 Apr 2026 18:13:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.21.23.139 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775499202; cv=none; b=gPIRGaxT/E/HzR1kEQmEhuEIdK1zQHU/sAjCMKDygTjkULnnz3/vwUQ1x6A0K2+7D6EQj1zKd6CdvGZMfHhoDxrx8fAJgaJxtqKFa+ZLlLF2fQOfoeS31qjC/G5DZg+CgJnbwdP6KH6xLtMtMNFQjUgTrnSOcm2pp1LuTQEp0ZQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775499202; c=relaxed/simple; bh=5A2ncLpb8vvjigR8O34mpX5m4sWPYSzbApPsYUi+pRo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Udpn9nQWl7GEIzBRBcKx2tGlqizp/XaqCTsg0ARMNAUUuqtvMAsBQU+kuGvYy9kFvR07zEewznKd4aFnsNrda/1ATFWFH3yKUiNgFgYgorbPI/vKlRU2ARtNsudNleQLkrMVZix4qqMkBwtApTQz8CJZ9qDq20H5jqVi2GGgrR8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org; spf=pass smtp.mailfrom=disroot.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b=Oax7lDBA; arc=none smtp.client-ip=178.21.23.139 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=disroot.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b="Oax7lDBA" Received: from [127.0.0.1] (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id DA91F270DE; Mon, 6 Apr 2026 20:13:19 +0200 (CEST) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id TEbxBC7KUCVY; Mon, 6 Apr 2026 20:13:19 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1775499199; bh=5A2ncLpb8vvjigR8O34mpX5m4sWPYSzbApPsYUi+pRo=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=Oax7lDBA+ECo3XW9O1L1ThTryL4uE7OKAsNQq/u2niuooLqh7kpX8b6q0im2obpti Ih9kLKWbdKsvQJaC1zfGeY8MuCgNszvuu24EPxdgQN+FjcIBefXGQQqayGgIVLJzg5 wIccGaNrlN5qPJYKxl+mb/zoPGTBl/jiQ0cy+UTF7bi5+Miqcuao5Ccyi95xZkL1YX icRgisMzqNUQ2sSgh4lDhkEojKCThcHGaZzaIck1st8xQ5nhqsGRcYCZaomif5WsGY Q8KA2JUlwY5ukci2RNd+RMTjhi9/U7gTllJVmkLJoXeuIUfxXqG/ScDOEG4EgX46I4 iJ7dn7d/jvSXw== From: Rustam Adilov To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Stanley Chang , linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Rustam Adilov , Michael Zavertkin Subject: [PATCH v4 4/6] phy: realtek: usb2: introduce reset controller struct Date: Mon, 6 Apr 2026 23:12:26 +0500 Message-ID: <20260406181228.25892-5-adilov@disroot.org> In-Reply-To: <20260406181228.25892-1-adilov@disroot.org> References: <20260406181228.25892-1-adilov@disroot.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In RTL9607C, there is so called "IP Enable Controller" which resemble reset controller with reset lines and is used for various things like USB, PCIE, GMAC and such. Introduce the reset_control struct to this driver to handle deasserting usb2 phy reset line. Make use of the function devm_reset_control_array_get_optional_exclusive() function to get the reset controller and since existing RTD SoCs don't specify the resets we can have a cleaner code. Co-developed-by: Michael Zavertkin Signed-off-by: Michael Zavertkin Signed-off-by: Rustam Adilov --- drivers/phy/realtek/phy-rtk-usb2.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/phy/realtek/phy-rtk-usb2.c b/drivers/phy/realtek/phy-r= tk-usb2.c index 0facd5f02e2d..64fd42513b86 100644 --- a/drivers/phy/realtek/phy-rtk-usb2.c +++ b/drivers/phy/realtek/phy-rtk-usb2.c @@ -17,6 +17,7 @@ #include #include #include +#include #include =20 /* GUSB2PHYACCn register */ @@ -130,6 +131,7 @@ struct rtk_phy { struct phy_cfg *phy_cfg; int num_phy; struct phy_parameter *phy_parameter; + struct reset_control *phy_rst; =20 struct dentry *debug_dir; }; @@ -592,6 +594,15 @@ static int do_rtk_phy_init(struct rtk_phy *rtk_phy, in= t index) phy_parameter =3D &((struct phy_parameter *)rtk_phy->phy_parameter)[index= ]; phy_reg =3D &phy_parameter->phy_reg; =20 + if (rtk_phy->phy_rst) { + int ret =3D reset_control_deassert(rtk_phy->phy_rst); + + if (ret) + return ret; + + msleep(5); + } + if (phy_cfg->use_default_parameter) { dev_dbg(rtk_phy->dev, "%s phy#%d use default parameter\n", __func__, index); @@ -1059,6 +1070,11 @@ static int rtk_usb2phy_probe(struct platform_device = *pdev) =20 rtk_phy->num_phy =3D phy_cfg->num_phy; =20 + rtk_phy->phy_rst =3D devm_reset_control_array_get_optional_exclusive(dev); + if (IS_ERR(rtk_phy->phy_rst)) + return dev_err_probe(dev, PTR_ERR(rtk_phy->phy_rst), + "usb2 phy resets are not working\n"); + ret =3D parse_phy_data(rtk_phy); if (ret) goto err; --=20 2.53.0 From nobody Sun Jun 21 06:29:08 2026 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A3DAD39479B; Mon, 6 Apr 2026 18:13:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.21.23.139 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775499206; cv=none; b=aQA1Wd2n6ojr25BlPW0WUeOWsU3DufUJS/XA1ZY6whBPXQ5vL2g0T7hcDc4zKVQ71apxGrIduvOwvSRHuUThsblUltdZk7tPDalPysJgJX9LZBZxmUxzV00pmbX+sM41VPPhUz51Ak60n3wyPDnk+qssahdvounUm+kMS/3Oyic= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775499206; c=relaxed/simple; bh=2b582OA9bo8ZO+4nA6VuGo0KsqY+xwfvgTSwFREy4/o=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=kcr9OB+fOV2lnWJ2Go0mS8c+/tMCahMHDZY2EOfo8ehto2Z3mM/z/cwQc+AF/FOvVBt9lUj5k6bD7hvUx2xHJ9yyt72bFBgzWJXjq+aE4ZcRdmbAzIJy5jSjcTiyAXIqMF1GjE5Zif4EYOgBxaLXZoLjWsBgNMnsUCrJhC3ilZQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org; spf=pass smtp.mailfrom=disroot.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b=dxvSqtVn; arc=none smtp.client-ip=178.21.23.139 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=disroot.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b="dxvSqtVn" Received: from [127.0.0.1] (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id 6B5262708A; Mon, 6 Apr 2026 20:13:22 +0200 (CEST) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id JkYX7jfwsH7m; Mon, 6 Apr 2026 20:13:21 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1775499201; bh=2b582OA9bo8ZO+4nA6VuGo0KsqY+xwfvgTSwFREy4/o=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=dxvSqtVnagn1cxHhDJCDbuVm26m5zVu+zstYtFPjDlaj8+a+uTOtKfQNJpGPBYR3m zBQdlmvgA6+f3sitwPEs2ZebyhevJMZcey+96j/0WrhSyUaELdoNeCnjEfNmGvwfCn 2cBIKM1E3muAgxppxn02NoMLH4q5xIcottgtKI8QaG8oHs7MHcy4lbc/kcllK9NWDM w0oRR3hVe5hv7GrQSffiNKzBQ2QGayvMDZoMzz8/Za1SxPaL+8mjfuUJywhB7GPcxb FMQeb37CC4LnTAXtXQx987Y9TwTmBCinvs5mGJDMxipNhJPt0Te+ZHQNk+vk+sPgmN fv8R7t2eBWc+g== From: Rustam Adilov To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Stanley Chang , linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Rustam Adilov , Michael Zavertkin Subject: [PATCH v4 5/6] phy: realtek: usb2: add support for RTL9607C USB2 PHY Date: Mon, 6 Apr 2026 23:12:27 +0500 Message-ID: <20260406181228.25892-6-adilov@disroot.org> In-Reply-To: <20260406181228.25892-1-adilov@disroot.org> References: <20260406181228.25892-1-adilov@disroot.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for the usb2 phy of RTL9607C series based SoCs. Add the macros and phy config struct for rtl9607. RTL9607C requires to clear a "force host disconnect" bit in the specific register (which is at an offset from reg_wrap_vstatus) before proceeding with phy parameter writes. Add the bool variable to the driver data struct and hide this whole procedure under the if statement that checks this new variable. Add the appropriate little endian read and write functions for rtl9607 and assign them to its phy config struct. Co-developed-by: Michael Zavertkin Signed-off-by: Michael Zavertkin Signed-off-by: Rustam Adilov --- drivers/phy/realtek/phy-rtk-usb2.c | 57 ++++++++++++++++++++++++++++++ 1 file changed, 57 insertions(+) diff --git a/drivers/phy/realtek/phy-rtk-usb2.c b/drivers/phy/realtek/phy-r= tk-usb2.c index 64fd42513b86..9311cf09521b 100644 --- a/drivers/phy/realtek/phy-rtk-usb2.c +++ b/drivers/phy/realtek/phy-rtk-usb2.c @@ -26,6 +26,12 @@ #define PHY_VCTRL_SHIFT 8 #define PHY_REG_DATA_MASK 0xff =20 +#define PHY_9607_VSTS_BUSY BIT(17) +#define PHY_9607_NEW_REG_REQ BIT(13) + +#define PHY_9607_FORCE_DISCONNECT_REG 0x10 +#define PHY_9607_FORCE_DISCONNECT_BIT BIT(5) + #define GET_LOW_NIBBLE(addr) ((addr) & 0x0f) #define GET_HIGH_NIBBLE(addr) (((addr) & 0xf0) >> 4) =20 @@ -109,6 +115,7 @@ struct phy_cfg { =20 u32 (*read)(void __iomem *reg); void (*write)(u32 val, void __iomem *reg); + bool force_host_disconnect; }; =20 struct phy_parameter { @@ -146,6 +153,18 @@ static void rtk_usb2phy_write(u32 val, void __iomem *r= eg) writel(val, reg); } =20 +static u32 rtk_usb2phy_read_le(void __iomem *reg) +{ + return le32_to_cpu(readl(reg)); +} + +static void rtk_usb2phy_write_le(u32 val, void __iomem *reg) +{ + u32 tmp =3D cpu_to_le32(val); + + writel(tmp, reg); +} + /* mapping 0xE0 to 0 ... 0xE7 to 7, 0xF0 to 8 ,,, 0xF7 to 15 */ static inline int page_addr_to_array_index(u8 addr) { @@ -609,6 +628,16 @@ static int do_rtk_phy_init(struct rtk_phy *rtk_phy, in= t index) goto do_toggle; } =20 + if (phy_cfg->force_host_disconnect) { + /* disable force-host-disconnect */ + u32 temp =3D readl(phy_reg->reg_wrap_vstatus + PHY_9607_FORCE_DISCONNECT= _REG); + + temp &=3D ~PHY_9607_FORCE_DISCONNECT_BIT; + writel(temp, phy_reg->reg_wrap_vstatus + PHY_9607_FORCE_DISCONNECT_REG); + + msleep(10); + } + /* Set page 0 */ phy_data_page =3D phy_cfg->page0; rtk_phy_set_page(phy_reg, 0); @@ -1374,6 +1403,33 @@ static const struct phy_cfg rtd1315e_phy_cfg =3D { .write =3D rtk_usb2phy_write, }; =20 +static const struct phy_cfg rtl9607_phy_cfg =3D { + .page0_size =3D MAX_USB_PHY_PAGE0_DATA_SIZE, + .page0 =3D { [0] =3D {0xe0, 0x95}, + [4] =3D {0xe4, 0x6a}, + [12] =3D {0xf3, 0x31}, }, + .page1_size =3D MAX_USB_PHY_PAGE1_DATA_SIZE, + .page1 =3D { [0] =3D {0xe0, 0x26}, }, + .page2_size =3D MAX_USB_PHY_PAGE2_DATA_SIZE, + .page2 =3D { [7] =3D {0xe7, 0x33}, }, + .num_phy =3D 1, + .check_efuse_version =3D CHECK_EFUSE_V2, + .efuse_dc_driving_rate =3D EFUS_USB_DC_CAL_RATE, + .dc_driving_mask =3D 0x1f, + .efuse_dc_disconnect_rate =3D EFUS_USB_DC_DIS_RATE, + .dc_disconnect_mask =3D 0xf, + .usb_dc_disconnect_at_page0 =3D true, + .do_toggle =3D true, + .driving_updated_for_dev_dis =3D 0x8, + .is_double_sensitivity_mode =3D true, + .vstatus_offset =3D 0xc, + .vstatus_busy =3D PHY_9607_VSTS_BUSY, + .new_reg_req =3D PHY_9607_NEW_REG_REQ, + .read =3D rtk_usb2phy_read_le, + .write =3D rtk_usb2phy_write_le, + .force_host_disconnect =3D true, +}; + static const struct of_device_id usbphy_rtk_dt_match[] =3D { { .compatible =3D "realtek,rtd1295-usb2phy", .data =3D &rtd1295_phy_cfg }, { .compatible =3D "realtek,rtd1312c-usb2phy", .data =3D &rtd1312c_phy_cfg= }, @@ -1384,6 +1440,7 @@ static const struct of_device_id usbphy_rtk_dt_match[= ] =3D { { .compatible =3D "realtek,rtd1395-usb2phy-2port", .data =3D &rtd1395_phy= _cfg_2port }, { .compatible =3D "realtek,rtd1619-usb2phy", .data =3D &rtd1619_phy_cfg }, { .compatible =3D "realtek,rtd1619b-usb2phy", .data =3D &rtd1619b_phy_cfg= }, + { .compatible =3D "realtek,rtl9607-usb2phy", .data =3D &rtl9607_phy_cfg }, {}, }; MODULE_DEVICE_TABLE(of, usbphy_rtk_dt_match); --=20 2.53.0 From nobody Sun Jun 21 06:29:08 2026 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 539183932C0; Mon, 6 Apr 2026 18:13:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.21.23.139 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775499215; cv=none; b=toJiALXM4hYe3bFfcb15O1tOAi4vFDoDGboVdLz/6LiPl4ZiRSPlpShC/hahApRdXRnbI0Pl/fYhPwEQeedoaBIFKHlW7YS6j+EbltaKMCCXq9qXMPWse9unO4oB3ibS5hEKScx2KTURdBCNlpncEtxBHx90KlMhYxg7ljVyJME= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775499215; c=relaxed/simple; bh=Fsbxr1KoI6nvNJg1iQcsK0ER51AzQq33E2rDDFIUpTE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=bUpTTcI4bxcysgjRqXgTY097PGbi6gSQcWTAypl7+iYi16pI/gkBbCmqSHGiRxrcyqPgKsD9SKYImgnGtXryQg/EcSMw0r9QNoeiZKO+Hu7ekgepAu0TsZzVMtM+6FnGfm1ZgCSFFA9Yn/YBjoOm3VRT52DYTicGFWtJQ3yWPoc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org; spf=pass smtp.mailfrom=disroot.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b=HPtLwA4i; arc=none smtp.client-ip=178.21.23.139 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=disroot.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b="HPtLwA4i" Received: from [127.0.0.1] (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id 6E0A727143; Mon, 6 Apr 2026 20:13:29 +0200 (CEST) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id 6faqmuIb3mDs; Mon, 6 Apr 2026 20:13:24 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1775499204; bh=Fsbxr1KoI6nvNJg1iQcsK0ER51AzQq33E2rDDFIUpTE=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=HPtLwA4i3jzwxFGuYS2km+VjEA3rmAC9POyflymmmEGyyHdy/XlHrZaeVa5YMbG5k Xp2BM1kgOa1giOrjgcj8QFAWU1GBrSKhDxJhaCswrbQQ70loXJn1TOPg8YV7NRXV6o glKkpV+LQS0cr2zl3IIQQSBIhJOJHw3tUIHJm7ZgR3ptAPwRoi5CtTPqwlmeOb/AKH C2qKYWZaVd3o+EI9m+rqStqgyg7kQ9kcAg/inDvrFVulI8Wall6M+/o/IuPps0gkQT R8vETunyScMLbQwP+AepcZoZE6TBXbTNuP3QwUkAzN/rPtx+B5S2nyss5xtnUM8c8L +k2JqtzugFp0g== From: Rustam Adilov To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Stanley Chang , linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Rustam Adilov Subject: [PATCH v4 6/6] phy: realtek: Make configs available for MACH_REALTEK_RTL Date: Mon, 6 Apr 2026 23:12:28 +0500 Message-ID: <20260406181228.25892-7-adilov@disroot.org> In-Reply-To: <20260406181228.25892-1-adilov@disroot.org> References: <20260406181228.25892-1-adilov@disroot.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the MACH_REALTEK_RTL to the if statement to make the config options available for Realtek RTL SoCs as well. Signed-off-by: Rustam Adilov --- drivers/phy/realtek/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/phy/realtek/Kconfig b/drivers/phy/realtek/Kconfig index 75ac7e7c31ae..76f9215d8b94 100644 --- a/drivers/phy/realtek/Kconfig +++ b/drivers/phy/realtek/Kconfig @@ -3,7 +3,7 @@ # Phy drivers for Realtek platforms # =20 -if ARCH_REALTEK || COMPILE_TEST +if ARCH_REALTEK || MACH_REALTEK_RTL || COMPILE_TEST =20 config PHY_RTK_RTD_USB2PHY tristate "Realtek RTD USB2 PHY Transceiver Driver" @@ -29,4 +29,4 @@ config PHY_RTK_RTD_USB3PHY DWC3 USB IP. This driver will do the PHY initialization of the parameters. =20 -endif # ARCH_REALTEK || COMPILE_TEST +endif # ARCH_REALTEK || MACH_REALTEK_RTL || COMPILE_TEST --=20 2.53.0