From nobody Sun Jun 21 06:37:24 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 9536733A9F3 for ; Mon, 6 Apr 2026 16:47:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775494048; cv=none; b=XxcmbODEULMWCGdXChXzwESvHlcCwrnWqF1D9uxw1+SV/6GMEKXY5S0074BpkQjidOMDCKkik3W93gK1lErDnARg+SX6Hy3OC9q15Oogj0SEwMj/g4fFA8ho5iT+m5cvBYkS9bkHcGa15vHb1V8FDL/m6Dnh3l7GUDbFrIAQKMg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775494048; c=relaxed/simple; bh=RjyP2D1fTKruhCbxtZ3oeTYzHGWYyMJK78WSAjXluj0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=FVAEke1nSgQWnDuVKut3ApVeYbT9hvys44jcTg/XxgTeZBCTrxvW0fs06c0SApXpv+b1abFY7HsIO9d8ik+f2JA8GdpZ6qK2HRuhp3NFkvovbcT7Db6W61yxBJRcnqV2ifbaPwe4gCTWJ/EsAp6y6Tig7CCSkrZ6gsPxbiWl8g8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=WxFfwS1w; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="WxFfwS1w" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6264F175A; Mon, 6 Apr 2026 09:47:20 -0700 (PDT) Received: from workstation-e142269.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 8DCF03F7D8; Mon, 6 Apr 2026 09:47:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1775494046; bh=RjyP2D1fTKruhCbxtZ3oeTYzHGWYyMJK78WSAjXluj0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=WxFfwS1w80wr9zICsTMC6J+JNpju8crtP2jCoeyfELyI+XLJzpF9CY1Iu8T12pbkr 06ndLBLhnS3f2xIt/TI6JwRxbfAcAD49mtHEdq3TzA5su0G+QDzKnmUAg/AYr5k0XZ t6TXPDEh0cmLkoTN0yxknXHdBBxX7U8uxM0W8M2k= From: Wei-Lin Chang To: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org Cc: Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon , Wei-Lin Chang Subject: [PATCH 1/2] KVM: arm64: Factor out TG0/1 decoding of VTCR and TCR Date: Mon, 6 Apr 2026 17:46:17 +0100 Message-ID: <20260406164618.3312473-2-weilin.chang@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260406164618.3312473-1-weilin.chang@arm.com> References: <20260406164618.3312473-1-weilin.chang@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The current code decodes TCR.TG0/TG1 and VTCR.TG0 inline at several places. Extract this logic into helpers so the granule size is derived in one place. This enables us to alter the effective granule size in the same place, which we will need in a later patch. Signed-off-by: Wei-Lin Chang --- arch/arm64/kvm/at.c | 73 +++++++++++++++++++++++++---------------- arch/arm64/kvm/nested.c | 70 ++++++++++++++++++++++++--------------- 2 files changed, 89 insertions(+), 54 deletions(-) diff --git a/arch/arm64/kvm/at.c b/arch/arm64/kvm/at.c index c5c5644b1878..ff8ba30e917b 100644 --- a/arch/arm64/kvm/at.c +++ b/arch/arm64/kvm/at.c @@ -135,14 +135,54 @@ static void compute_s1poe(struct kvm_vcpu *vcpu, stru= ct s1_walk_info *wi) wi->e0poe =3D (wi->regime !=3D TR_EL2) && (val & TCR2_EL1_E0POE); } =20 +static unsigned int tg0_to_shift(u64 tg0) +{ + switch (tg0) { + case TCR_EL1_TG0_4K: + return 12; + case TCR_EL1_TG0_16K: + return 14; + case TCR_EL1_TG0_64K: + default: /* IMPDEF: treat any other value as 64k */ + return 16; + } +} + +static unsigned int tg1_to_shift(u64 tg1) +{ + switch (tg1) { + case TCR_EL1_TG1_4K: + return 12; + case TCR_EL1_TG1_16K: + return 14; + case TCR_EL1_TG1_64K: + default: /* IMPDEF: treat any other value as 64k */ + return 16; + } +} + +static u64 tcr_tg_shift(struct kvm *kvm, u64 tcr, bool upper_range) +{ + unsigned int shift; + + /* Someone was silly enough to encode TG0/TG1 differently */ + if (upper_range) + shift =3D tg1_to_shift(FIELD_GET(TCR_EL1_TG1_MASK, tcr)); + else + shift =3D tg0_to_shift(FIELD_GET(TCR_EL1_TG0_MASK, tcr)); + + return shift; +} + static int setup_s1_walk(struct kvm_vcpu *vcpu, struct s1_walk_info *wi, struct s1_walk_result *wr, u64 va) { - u64 hcr, sctlr, tcr, tg, ps, ia_bits, ttbr; + u64 hcr, sctlr, tcr, ps, ia_bits, ttbr; unsigned int stride, x; - bool va55, tbi, lva; + bool va55, tbi, lva, upper_range; =20 va55 =3D va & BIT(55); + upper_range =3D va55 && wi->regime !=3D TR_EL2; =20 if (vcpu_has_nv(vcpu)) { hcr =3D __vcpu_sys_reg(vcpu, HCR_EL2); @@ -173,35 +213,12 @@ static int setup_s1_walk(struct kvm_vcpu *vcpu, struc= t s1_walk_info *wi, BUG(); } =20 - /* Someone was silly enough to encode TG0/TG1 differently */ - if (va55 && wi->regime !=3D TR_EL2) { + if (upper_range) wi->txsz =3D FIELD_GET(TCR_T1SZ_MASK, tcr); - tg =3D FIELD_GET(TCR_TG1_MASK, tcr); - - switch (tg << TCR_TG1_SHIFT) { - case TCR_TG1_4K: - wi->pgshift =3D 12; break; - case TCR_TG1_16K: - wi->pgshift =3D 14; break; - case TCR_TG1_64K: - default: /* IMPDEF: treat any other value as 64k */ - wi->pgshift =3D 16; break; - } - } else { + else wi->txsz =3D FIELD_GET(TCR_T0SZ_MASK, tcr); - tg =3D FIELD_GET(TCR_TG0_MASK, tcr); - - switch (tg << TCR_TG0_SHIFT) { - case TCR_TG0_4K: - wi->pgshift =3D 12; break; - case TCR_TG0_16K: - wi->pgshift =3D 14; break; - case TCR_TG0_64K: - default: /* IMPDEF: treat any other value as 64k */ - wi->pgshift =3D 16; break; - } - } =20 + wi->pgshift =3D tcr_tg_shift(vcpu->kvm, tcr, upper_range); wi->pa52bit =3D has_52bit_pa(vcpu, wi, tcr); =20 ia_bits =3D get_ia_size(wi); diff --git a/arch/arm64/kvm/nested.c b/arch/arm64/kvm/nested.c index 883b6c1008fb..2bfab3007cb3 100644 --- a/arch/arm64/kvm/nested.c +++ b/arch/arm64/kvm/nested.c @@ -378,20 +378,36 @@ static int walk_nested_s2_pgd(struct kvm_vcpu *vcpu, = phys_addr_t ipa, return 0; } =20 -static void vtcr_to_walk_info(u64 vtcr, struct s2_walk_info *wi) +static unsigned int tg0_to_shift(u64 tg0) +{ + switch (tg0) { + case VTCR_EL2_TG0_4K: + return 12; + case VTCR_EL2_TG0_16K: + return 14; + case VTCR_EL2_TG0_64K: + default: /* IMPDEF: treat any other value as 64k */ + return 16; + } +} + +static u64 vtcr_tg0_shift(struct kvm *kvm, u64 vtcr) +{ + u64 tg0 =3D FIELD_GET(VTCR_EL2_TG0_MASK, vtcr); + unsigned int shift =3D tg0_to_shift(tg0); + + return shift; +} + +static size_t vtcr_tg0_size(struct kvm *kvm, u64 vtcr) +{ + return BIT(vtcr_tg0_shift(kvm, vtcr)); +} + +static void vtcr_to_walk_info(struct kvm *kvm, u64 vtcr, struct s2_walk_in= fo *wi) { wi->t0sz =3D vtcr & TCR_EL2_T0SZ_MASK; - - switch (FIELD_GET(VTCR_EL2_TG0_MASK, vtcr)) { - case VTCR_EL2_TG0_4K: - wi->pgshift =3D 12; break; - case VTCR_EL2_TG0_16K: - wi->pgshift =3D 14; break; - case VTCR_EL2_TG0_64K: - default: /* IMPDEF: treat any other value as 64k */ - wi->pgshift =3D 16; break; - } - + wi->pgshift =3D vtcr_tg0_shift(kvm, vtcr); wi->sl =3D FIELD_GET(VTCR_EL2_SL0_MASK, vtcr); /* Global limit for now, should eventually be per-VM */ wi->max_oa_bits =3D min(get_kvm_ipa_limit(), @@ -414,7 +430,7 @@ int kvm_walk_nested_s2(struct kvm_vcpu *vcpu, phys_addr= _t gipa, =20 wi.baddr =3D vcpu_read_sys_reg(vcpu, VTTBR_EL2); =20 - vtcr_to_walk_info(vtcr, &wi); + vtcr_to_walk_info(vcpu->kvm, vtcr, &wi); =20 wi.be =3D vcpu_read_sys_reg(vcpu, SCTLR_EL2) & SCTLR_ELx_EE; =20 @@ -515,17 +531,19 @@ static u8 get_guest_mapping_ttl(struct kvm_s2_mmu *mm= u, u64 addr) u64 tmp, sz =3D 0, vtcr =3D mmu->tlb_vtcr; kvm_pte_t pte; u8 ttl, level; + struct kvm *kvm =3D kvm_s2_mmu_to_kvm(mmu); + size_t tg0_size =3D vtcr_tg0_size(kvm, vtcr); =20 - lockdep_assert_held_write(&kvm_s2_mmu_to_kvm(mmu)->mmu_lock); + lockdep_assert_held_write(&kvm->mmu_lock); =20 - switch (FIELD_GET(VTCR_EL2_TG0_MASK, vtcr)) { - case VTCR_EL2_TG0_4K: + switch (tg0_size) { + case SZ_4K: ttl =3D (TLBI_TTL_TG_4K << 2); break; - case VTCR_EL2_TG0_16K: + case SZ_16K: ttl =3D (TLBI_TTL_TG_16K << 2); break; - case VTCR_EL2_TG0_64K: + case SZ_64K: default: /* IMPDEF: treat any other value as 64k */ ttl =3D (TLBI_TTL_TG_64K << 2); break; @@ -535,19 +553,19 @@ static u8 get_guest_mapping_ttl(struct kvm_s2_mmu *mm= u, u64 addr) =20 again: /* Iteratively compute the block sizes for a particular granule size */ - switch (FIELD_GET(VTCR_EL2_TG0_MASK, vtcr)) { - case VTCR_EL2_TG0_4K: + switch (tg0_size) { + case SZ_4K: if (sz < SZ_4K) sz =3D SZ_4K; else if (sz < SZ_2M) sz =3D SZ_2M; else if (sz < SZ_1G) sz =3D SZ_1G; else sz =3D 0; break; - case VTCR_EL2_TG0_16K: + case SZ_16K: if (sz < SZ_16K) sz =3D SZ_16K; else if (sz < SZ_32M) sz =3D SZ_32M; else sz =3D 0; break; - case VTCR_EL2_TG0_64K: + case SZ_64K: default: /* IMPDEF: treat any other value as 64k */ if (sz < SZ_64K) sz =3D SZ_64K; else if (sz < SZ_512M) sz =3D SZ_512M; @@ -598,14 +616,14 @@ unsigned long compute_tlb_inval_range(struct kvm_s2_m= mu *mmu, u64 val) =20 if (!max_size) { /* Compute the maximum extent of the invalidation */ - switch (FIELD_GET(VTCR_EL2_TG0_MASK, mmu->tlb_vtcr)) { - case VTCR_EL2_TG0_4K: + switch (vtcr_tg0_size(kvm, mmu->tlb_vtcr)) { + case SZ_4K: max_size =3D SZ_1G; break; - case VTCR_EL2_TG0_16K: + case SZ_16K: max_size =3D SZ_32M; break; - case VTCR_EL2_TG0_64K: + case SZ_64K: default: /* IMPDEF: treat any other value as 64k */ /* * No, we do not support 52bit IPA in nested yet. Once --=20 2.43.0 From nobody Sun Jun 21 06:37:24 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 3666D38AC99 for ; Mon, 6 Apr 2026 16:47:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775494057; cv=none; b=uBkYPKQcMjbVdHZL55hHOvzijmFs+gfCtwrnmHCcfQ0iBLja4xnyDaDasGEoeHS1310MFFBdyWdK2P8a3gEtw8C3goqtvZnfdi4T1Naazu/3booxkLzrHtd4mkXs5RTbi1blLSpiCdv5EAwV0JE2oJsLGdec61EjhEIjMQQeJ0c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775494057; c=relaxed/simple; bh=+TkEll1g4GPMoDQnUJ+ojaCZea8pptFIoCXOi3JHR/Q=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=C6/UOASpugALAmcEWxun2bwGS1ip1fFGLuSX06UZ4ztdcAe3JKKzqfuLdeby352OIdCt25W66UCtm5lUuy2dPa/MvNgpnIGSpJYrC0LnW1icae2zwjvYX47T0UGvSQOTuA5VUwt3xHNDW5gaAihCesftCcKzPf74jNt/bUdfyvI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=pazcLLgE; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="pazcLLgE" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id EC47016F3; Mon, 6 Apr 2026 09:47:29 -0700 (PDT) Received: from workstation-e142269.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 258A53F7D8; Mon, 6 Apr 2026 09:47:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1775494055; bh=+TkEll1g4GPMoDQnUJ+ojaCZea8pptFIoCXOi3JHR/Q=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=pazcLLgEY+txpooJQ2Q2dqL696hUl0qWATrOFtJeOxjQX5loFPlBhHscKu08qaw5c Akoxy7d0q1HRQtp0rag04febeM0q9IzTjCQ7O3wM0YjETgEL9M4L8MLiNhk6HnonkS eKRMN2BN1ydiRUqKtNXB1SWesVmL0db5zBFYbqlU= From: Wei-Lin Chang To: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org Cc: Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon , Wei-Lin Chang Subject: [PATCH 2/2] KVM: arm64: Fallback to a supported value for unsupported guest TGx Date: Mon, 6 Apr 2026 17:46:18 +0100 Message-ID: <20260406164618.3312473-3-weilin.chang@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260406164618.3312473-1-weilin.chang@arm.com> References: <20260406164618.3312473-1-weilin.chang@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When KVM derives the translation granule for emulated stage-1 and stage-2 walks, it decodes TCR/VTCR.TGx and treats the granule as-is. This is wrong when the guest programs a granule size that is not advertised in the guest's ID_AA64MMFR0_EL1.TGRAN* fields. Architecturally, such a value must be treated as an implemented granule size. Choose an available one while prioritizing PAGE_SIZE. Signed-off-by: Wei-Lin Chang --- arch/arm64/kvm/at.c | 48 ++++++++++++++++++++++++++ arch/arm64/kvm/nested.c | 75 +++++++++++++++++++++++++++++++---------- 2 files changed, 105 insertions(+), 18 deletions(-) diff --git a/arch/arm64/kvm/at.c b/arch/arm64/kvm/at.c index ff8ba30e917b..6dd883798f83 100644 --- a/arch/arm64/kvm/at.c +++ b/arch/arm64/kvm/at.c @@ -135,6 +135,30 @@ static void compute_s1poe(struct kvm_vcpu *vcpu, struc= t s1_walk_info *wi) wi->e0poe =3D (wi->regime !=3D TR_EL2) && (val & TCR2_EL1_E0POE); } =20 +#define _has_tgran(__r, __sz) \ + ({ \ + u64 _s1, _mmfr0 =3D __r; \ + \ + _s1 =3D SYS_FIELD_GET(ID_AA64MMFR0_EL1, \ + TGRAN##__sz, _mmfr0); \ + \ + _s1 !=3D ID_AA64MMFR0_EL1_TGRAN##__sz##_NI; \ + }) + +static bool has_tgran(u64 mmfr0, unsigned int shift) +{ + switch (shift) { + case 12: + return _has_tgran(mmfr0, 4); + case 14: + return _has_tgran(mmfr0, 16); + case 16: + return _has_tgran(mmfr0, 64); + default: + BUG(); + } +} + static unsigned int tg0_to_shift(u64 tg0) { switch (tg0) { @@ -161,8 +185,23 @@ static unsigned int tg1_to_shift(u64 tg1) } } =20 +static unsigned int fallback_tgran_shift(u64 mmfr0) +{ + if (has_tgran(mmfr0, PAGE_SHIFT)) + return PAGE_SHIFT; + else if (has_tgran(mmfr0, 12)) + return 12; + else if (has_tgran(mmfr0, 14)) + return 14; + else if (has_tgran(mmfr0, 16)) + return 16; + else + return PAGE_SHIFT; +} + static u64 tcr_tg_shift(struct kvm *kvm, u64 tcr, bool upper_range) { + u64 mmfr0 =3D kvm_read_vm_id_reg(kvm, SYS_ID_AA64MMFR0_EL1); unsigned int shift; =20 /* Someone was silly enough to encode TG0/TG1 differently */ @@ -171,6 +210,15 @@ static u64 tcr_tg_shift(struct kvm *kvm, u64 tcr, bool= upper_range) else shift =3D tg0_to_shift(FIELD_GET(TCR_EL1_TG0_MASK, tcr)); =20 + /* + * If TGx is programmed to an unimplemented value (not advertised in + * ID_AA64MMFR0_EL1), we should treat it as if an implemented value is + * written, as per the architecture. Choose an available one while + * prioritizing PAGE_SIZE. + */ + if (!has_tgran(mmfr0, shift)) + return fallback_tgran_shift(mmfr0); + return shift; } =20 diff --git a/arch/arm64/kvm/nested.c b/arch/arm64/kvm/nested.c index 2bfab3007cb3..64794ba4848d 100644 --- a/arch/arm64/kvm/nested.c +++ b/arch/arm64/kvm/nested.c @@ -378,6 +378,36 @@ static int walk_nested_s2_pgd(struct kvm_vcpu *vcpu, p= hys_addr_t ipa, return 0; } =20 +#define _has_tgran_2(__r, __sz) \ + ({ \ + u64 _s1, _s2, _mmfr0 =3D __r; \ + \ + _s2 =3D SYS_FIELD_GET(ID_AA64MMFR0_EL1, \ + TGRAN##__sz##_2, _mmfr0); \ + \ + _s1 =3D SYS_FIELD_GET(ID_AA64MMFR0_EL1, \ + TGRAN##__sz, _mmfr0); \ + \ + ((_s2 !=3D ID_AA64MMFR0_EL1_TGRAN##__sz##_2_NI && \ + _s2 !=3D ID_AA64MMFR0_EL1_TGRAN##__sz##_2_TGRAN##__sz) || \ + (_s2 =3D=3D ID_AA64MMFR0_EL1_TGRAN##__sz##_2_TGRAN##__sz && \ + _s1 !=3D ID_AA64MMFR0_EL1_TGRAN##__sz##_NI)); \ + }) + +static bool has_tgran_2(u64 mmfr0, unsigned int shift) +{ + switch (shift) { + case 12: + return _has_tgran_2(mmfr0, 4); + case 14: + return _has_tgran_2(mmfr0, 16); + case 16: + return _has_tgran_2(mmfr0, 64); + default: + BUG(); + } +} + static unsigned int tg0_to_shift(u64 tg0) { switch (tg0) { @@ -391,11 +421,35 @@ static unsigned int tg0_to_shift(u64 tg0) } } =20 +static unsigned int fallback_tgran2_shift(u64 mmfr0) +{ + if (has_tgran_2(mmfr0, PAGE_SHIFT)) + return PAGE_SHIFT; + else if (has_tgran_2(mmfr0, 12)) + return 12; + else if (has_tgran_2(mmfr0, 14)) + return 14; + else if (has_tgran_2(mmfr0, 16)) + return 16; + else + return PAGE_SHIFT; +} + static u64 vtcr_tg0_shift(struct kvm *kvm, u64 vtcr) { + u64 mmfr0 =3D kvm_read_vm_id_reg(kvm, SYS_ID_AA64MMFR0_EL1); u64 tg0 =3D FIELD_GET(VTCR_EL2_TG0_MASK, vtcr); unsigned int shift =3D tg0_to_shift(tg0); =20 + /* + * If TGx is programmed to an unimplemented value (not advertised in + * ID_AA64MMFR0_EL1), we should treat it as if an implemented value is + * written, as per the architecture. Choose an available one while + * prioritizing PAGE_SIZE. + */ + if (!has_tgran_2(mmfr0, shift)) + return fallback_tgran2_shift(mmfr0); + return shift; } =20 @@ -1516,21 +1570,6 @@ static void kvm_map_l1_vncr(struct kvm_vcpu *vcpu) } } =20 -#define has_tgran_2(__r, __sz) \ - ({ \ - u64 _s1, _s2, _mmfr0 =3D __r; \ - \ - _s2 =3D SYS_FIELD_GET(ID_AA64MMFR0_EL1, \ - TGRAN##__sz##_2, _mmfr0); \ - \ - _s1 =3D SYS_FIELD_GET(ID_AA64MMFR0_EL1, \ - TGRAN##__sz, _mmfr0); \ - \ - ((_s2 !=3D ID_AA64MMFR0_EL1_TGRAN##__sz##_2_NI && \ - _s2 !=3D ID_AA64MMFR0_EL1_TGRAN##__sz##_2_TGRAN##__sz) || \ - (_s2 =3D=3D ID_AA64MMFR0_EL1_TGRAN##__sz##_2_TGRAN##__sz && \ - _s1 !=3D ID_AA64MMFR0_EL1_TGRAN##__sz##_NI)); \ - }) /* * Our emulated CPU doesn't support all the possible features. For the * sake of simplicity (and probably mental sanity), wipe out a number @@ -1617,15 +1656,15 @@ u64 limit_nv_id_reg(struct kvm *kvm, u32 reg, u64 v= al) */ switch (PAGE_SIZE) { case SZ_4K: - if (has_tgran_2(orig_val, 4)) + if (_has_tgran_2(orig_val, 4)) val |=3D SYS_FIELD_PREP_ENUM(ID_AA64MMFR0_EL1, TGRAN4_2, IMP); fallthrough; case SZ_16K: - if (has_tgran_2(orig_val, 16)) + if (_has_tgran_2(orig_val, 16)) val |=3D SYS_FIELD_PREP_ENUM(ID_AA64MMFR0_EL1, TGRAN16_2, IMP); fallthrough; case SZ_64K: - if (has_tgran_2(orig_val, 64)) + if (_has_tgran_2(orig_val, 64)) val |=3D SYS_FIELD_PREP_ENUM(ID_AA64MMFR0_EL1, TGRAN64_2, IMP); break; } --=20 2.43.0