From nobody Wed Apr 8 04:28:49 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A3D5C212542; Mon, 6 Apr 2026 20:25:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775507137; cv=none; b=eadbhgF0ic0J3tMifw6IWfIpKxZwRN7yPE741Gv2jFIRG617LwuLFdVqJQU3NIqkXteBZQLohkm81+NJPf23thsoYwriGARlV6NdYymBVFTTcVaTFsMxCCEHFJaDGfZclblVSGGGmWMS4Jwz/d5uue9K7kbnnHtGPwjV2/n1Vew= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775507137; c=relaxed/simple; bh=OTR3bFhUuHWfHudW/1mDZVYi5w4WUPb0Vet1Eonn6tg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=kyvUAdYHnX78yYNNa0OpxKhUn2MlGblz8qBDtDnALpiZ59pjtBwjtqkoq9W2oz+G/YnIb1+2SKa/n9o/cGZEUe3cIJAIMcNe6STYqEyEBVEJz3V2zQmgL2oLdNAcnO6nNLwu9sHsSIXhXaNS2GhXmu6h/TBh/WA/tYW/pYkUTP8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=sUt6PJfX; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="sUt6PJfX" Received: by smtp.kernel.org (Postfix) with ESMTPS id 62497C2BCB3; Mon, 6 Apr 2026 20:25:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1775507137; bh=OTR3bFhUuHWfHudW/1mDZVYi5w4WUPb0Vet1Eonn6tg=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=sUt6PJfXlsuSMUk9vWmYRP4td9W979suuEmAmMvy/IWKg2F/oZHvKebwXQ/Lh6Puv /+6XBBW66KaBrfF9fMDNVbTT3jjf53eXR/5I9DDhWatuOcckgAhOhUa6i2Ih99pqci FVnLGHBadqz+aXCEn5OX6L0BAxuG19mffbmd4mIbkcs3amIT6MdjH0HVxp/Ozln2sd y+RxCWvXl+8x12yJZ8QampsMUVVTeMHk3ktN7Nn4sdOSYWY7sMsLijIky0ofHtFmh1 QDqlkLTyfx16Mz2Podv/HJ87R9pdBl1jfnEstwaYbLXaKuTZySKk835i/paQFblSxA +WHrIwgWOTU4Q== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 408B0FB5166; Mon, 6 Apr 2026 20:25:37 +0000 (UTC) From: George Moussalem via B4 Relay Date: Mon, 06 Apr 2026 22:24:38 +0200 Subject: [PATCH v21 1/6] dt-bindings: pwm: add IPQ6018 binding Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260406-ipq-pwm-v21-1-6ed1e868e4c2@outlook.com> References: <20260406-ipq-pwm-v21-0-6ed1e868e4c2@outlook.com> In-Reply-To: <20260406-ipq-pwm-v21-0-6ed1e868e4c2@outlook.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, George Moussalem , Devi Priya , Baruch Siach , Bjorn Andersson , Krzysztof Kozlowski X-Mailer: b4 0.15.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1775507135; l=1986; i=george.moussalem@outlook.com; s=20260406; h=from:subject:message-id; bh=nDWws50WaNvgOfPtIO2WBqjwriMPqndXS0BxB4pO04E=; b=vWsu1ylE+520h9fCI92em01kv+7O5LlzpmfD0ib1MZKI3/mGs5vExbXkpgmE7SvoDhDVnj3Mm NIVcIxlzI8kAgmvzaf5m4HsYQrPj2ylqu4GrmhtQOrjKcpNfF6DwfWG X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=uqspem3ahtBvPEBuxVbyyXT/0Vp3JNb/mo1EPbmBzWg= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20260406 with auth_id=722 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: Devi Priya DT binding for the PWM block in Qualcomm IPQ6018 SoC. Reviewed-by: Bjorn Andersson Reviewed-by: Krzysztof Kozlowski Co-developed-by: Baruch Siach Signed-off-by: Baruch Siach Signed-off-by: Devi Priya Signed-off-by: George Moussalem --- .../devicetree/bindings/pwm/qcom,ipq6018-pwm.yaml | 51 ++++++++++++++++++= ++++ 1 file changed, 51 insertions(+) diff --git a/Documentation/devicetree/bindings/pwm/qcom,ipq6018-pwm.yaml b/= Documentation/devicetree/bindings/pwm/qcom,ipq6018-pwm.yaml new file mode 100644 index 000000000000..f9f1f652e752 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/qcom,ipq6018-pwm.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/qcom,ipq6018-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm IPQ6018 PWM controller + +maintainers: + - George Moussalem + +properties: + compatible: + oneOf: + - items: + - enum: + - qcom,ipq5018-pwm + - qcom,ipq5332-pwm + - qcom,ipq9574-pwm + - const: qcom,ipq6018-pwm + - const: qcom,ipq6018-pwm + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + "#pwm-cells": + const: 3 + +required: + - compatible + - reg + - clocks + - "#pwm-cells" + +additionalProperties: false + +examples: + - | + #include + + pwm: pwm@1941010 { + compatible =3D "qcom,ipq6018-pwm"; + reg =3D <0x01941010 0x20>; + clocks =3D <&gcc GCC_ADSS_PWM_CLK>; + assigned-clocks =3D <&gcc GCC_ADSS_PWM_CLK>; + assigned-clock-rates =3D <100000000>; + #pwm-cells =3D <3>; + }; --=20 2.39.5 From nobody Wed Apr 8 04:28:49 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A3DE32ED843; Mon, 6 Apr 2026 20:25:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775507137; cv=none; b=rSg1NjnmsruYmkX3R11W6k4Z8AtS38TZ+TqeYL720Tdv31TMvmKHDhnKxFF3tEIwgHWVheBySdmsHQ+TjnxpU5oSVZHZv22ih+8Aiy54O5TPR5z1YON6AsiVaBCkMkBlJ/jMUaSmVPHvRKFy9ayw1ZRvJkoI6VDG2UJjbwnNxG4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775507137; c=relaxed/simple; bh=//4hFRzRx51KF8dy4TmLZTzuscwSckXo5IqSX/SPqZY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ArKzdfp/X7WMN4QtZSZyRhbAQp45YLQl6I5amOM+CrsyZ9gVl6Ig9XllK6FIsPUocURasHGcptv5FS/XwVHiC3l+roWqJXmNVv/U4DRwsgaL3Kc2MJhyHwPIV0yGbI1K/DDtF0ESVy/9H6z+VJfdpkob1whus00BilrEYX2k+OI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=dKYd77b2; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="dKYd77b2" Received: by smtp.kernel.org (Postfix) with ESMTPS id 5EF39C19425; Mon, 6 Apr 2026 20:25:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1775507137; bh=//4hFRzRx51KF8dy4TmLZTzuscwSckXo5IqSX/SPqZY=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=dKYd77b2EVEbYFEoz8GlRUWt4QG2CKaZJdXDAMG7k2AgpxexfBmH0G8LoDmtRFgtY oVgXAZu50MD7faY9SaQ12xL84uf9+kwbnCDQrkjdvTOkopuA5J25KzYmsaKizbqSfm EEsih8WGBU/42qU+ti1nOOkawPiT7SbJD47IMI7a8YS10y+CBZUKQCqw7GOcEF3fW4 EaX/Fwko1zH0NhYrlUyJaJNw82U4O1cQfa6aXVlbYE658InbuDfjyY4I6HZek9oMxo O5H++QXbopgbyTj8lEvNg+/vzQZRP8Q6jQVx7AfXjEWdzgNw9WdcbP3vtgeEmd18L1 dJ2shBfGt8snQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5343AFB5168; Mon, 6 Apr 2026 20:25:37 +0000 (UTC) From: George Moussalem via B4 Relay Date: Mon, 06 Apr 2026 22:24:39 +0200 Subject: [PATCH v21 2/6] pwm: driver for qualcomm ipq6018 pwm block Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260406-ipq-pwm-v21-2-6ed1e868e4c2@outlook.com> References: <20260406-ipq-pwm-v21-0-6ed1e868e4c2@outlook.com> In-Reply-To: <20260406-ipq-pwm-v21-0-6ed1e868e4c2@outlook.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, George Moussalem , Devi Priya , Baruch Siach X-Mailer: b4 0.15.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1775507135; l=10191; i=george.moussalem@outlook.com; s=20260406; h=from:subject:message-id; bh=hCPxbSZuZ7s50wScexFoYf75FXO3O4WXi/g+V0VERTQ=; b=5g3ijef6uxDRL+31oDDnTpHKv8/sH7xFpw4FOJX8mXgdZCvjdLylG4wYYZQmPv04L5JCHRMUe vMVN6yfhxZ6BtrzjTUWbcFrNh+gAkfafTuwLYgBgS1WNbwObzcTF4Xd X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=uqspem3ahtBvPEBuxVbyyXT/0Vp3JNb/mo1EPbmBzWg= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20260406 with auth_id=722 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: Devi Priya Driver for the PWM block in Qualcomm IPQ6018 line of SoCs. Based on driver from downstream Codeaurora kernel tree. Removed support for older (V1) variants because I have no access to that hardware. Tested on IPQ5018 and IPQ6010 based hardware. Co-developed-by: Baruch Siach Signed-off-by: Baruch Siach Signed-off-by: Devi Priya Reviewed-by: Bjorn Andersson Signed-off-by: George Moussalem --- drivers/pwm/Kconfig | 12 +++ drivers/pwm/Makefile | 1 + drivers/pwm/pwm-ipq.c | 259 ++++++++++++++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 272 insertions(+) diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 6f3147518376..e8886a9b64d9 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -347,6 +347,18 @@ config PWM_INTEL_LGM To compile this driver as a module, choose M here: the module will be called pwm-intel-lgm. =20 +config PWM_IPQ + tristate "IPQ PWM support" + depends on ARCH_QCOM || COMPILE_TEST + depends on HAVE_CLK && HAS_IOMEM + help + Generic PWM framework driver for IPQ PWM block which supports + 4 pwm channels. Each of the these channels can be configured + independent of each other. + + To compile this driver as a module, choose M here: the module + will be called pwm-ipq. + config PWM_IQS620A tristate "Azoteq IQS620A PWM support" depends on MFD_IQS62X || COMPILE_TEST diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index 0dc0d2b69025..5630a521a7cf 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -29,6 +29,7 @@ obj-$(CONFIG_PWM_IMX1) +=3D pwm-imx1.o obj-$(CONFIG_PWM_IMX27) +=3D pwm-imx27.o obj-$(CONFIG_PWM_IMX_TPM) +=3D pwm-imx-tpm.o obj-$(CONFIG_PWM_INTEL_LGM) +=3D pwm-intel-lgm.o +obj-$(CONFIG_PWM_IPQ) +=3D pwm-ipq.o obj-$(CONFIG_PWM_IQS620A) +=3D pwm-iqs620a.o obj-$(CONFIG_PWM_JZ4740) +=3D pwm-jz4740.o obj-$(CONFIG_PWM_KEEMBAY) +=3D pwm-keembay.o diff --git a/drivers/pwm/pwm-ipq.c b/drivers/pwm/pwm-ipq.c new file mode 100644 index 000000000000..b79e5e457d1a --- /dev/null +++ b/drivers/pwm/pwm-ipq.c @@ -0,0 +1,259 @@ +// SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 +/* + * Copyright (c) 2016-2017, 2020 The Linux Foundation. All rights reserved. + * + * Hardware notes / Limitations: + * - The PWM controller has no publicly available datasheet. + * - Each of the four channels is programmed via two 32-bit registers + * (REG0 and REG1 at 8-byte stride). + * - Period and duty-cycle reconfiguration is fully atomic: new divider, + * pre-divider, and high-duration values are latched by setting the + * UPDATE bit (bit 30 in REG1). The hardware applies the new settings + * at the beginning of the next period without disabling the output, + * so the currently running period is always completed. + * - On disable (clearing the ENABLE bit 31 in REG1), the hardware + * finishes the current period before stopping the output. The pin + * is then driven to the inactive (low) level. + * - Upon disabling, the hardware resets the pre-divider (PRE_DIV) and div= ider + * fields (PWM_DIV) in REG0 and REG1 to 0x0000 and 0x0001 respectively. + * - Only normal polarity is supported. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* The frequency range supported is 1 Hz to 100 Mhz (clock rate) */ +#define IPQ_PWM_MAX_PERIOD_NS ((u64)NSEC_PER_SEC) +#define IPQ_PWM_MIN_PERIOD_NS 10 + +/* + * Two 32-bit registers for each PWM: REG0, and REG1. + * Base offset for PWM #i is at 8 * #i. + */ +#define IPQ_PWM_REG0 0 +#define IPQ_PWM_REG0_PWM_DIV GENMASK(15, 0) +#define IPQ_PWM_REG0_HI_DURATION GENMASK(31, 16) + +#define IPQ_PWM_REG1 4 +#define IPQ_PWM_REG1_PRE_DIV GENMASK(15, 0) + +/* + * The max value specified for each field is based on the number of bits + * in the pwm control register for that field (16-bit) + */ +#define IPQ_PWM_MAX_DIV FIELD_MAX(IPQ_PWM_REG0_PWM_DIV) + +/* + * Enable bit is set to enable output toggling in pwm device. + * Update bit is set to trigger the change and is unset automatically + * to reflect the changed divider and high duration values in register. + */ +#define IPQ_PWM_REG1_UPDATE BIT(30) +#define IPQ_PWM_REG1_ENABLE BIT(31) + +struct ipq_pwm_chip { + void __iomem *mem; + unsigned long clk_rate; +}; + +static struct ipq_pwm_chip *ipq_pwm_from_chip(struct pwm_chip *chip) +{ + return pwmchip_get_drvdata(chip); +} + +static unsigned int ipq_pwm_reg_read(struct pwm_device *pwm, unsigned int = reg) +{ + struct ipq_pwm_chip *ipq_chip =3D ipq_pwm_from_chip(pwm->chip); + unsigned int off =3D 8 * pwm->hwpwm + reg; + + return readl(ipq_chip->mem + off); +} + +static void ipq_pwm_reg_write(struct pwm_device *pwm, unsigned int reg, + unsigned int val) +{ + struct ipq_pwm_chip *ipq_chip =3D ipq_pwm_from_chip(pwm->chip); + unsigned int off =3D 8 * pwm->hwpwm + reg; + + writel(val, ipq_chip->mem + off); +} + +static int ipq_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, + const struct pwm_state *state) +{ + struct ipq_pwm_chip *ipq_chip =3D ipq_pwm_from_chip(chip); + unsigned int pre_div, pwm_div; + u64 period_ns, duty_ns; + unsigned long val =3D 0; + unsigned long hi_dur; + + if (state->polarity !=3D PWM_POLARITY_NORMAL) + return -EINVAL; + + /* + * Check the upper and lower bounds for the period as per + * hardware limits + */ + period_ns =3D max(state->period, IPQ_PWM_MIN_PERIOD_NS); + period_ns =3D min(state->period, IPQ_PWM_MAX_PERIOD_NS); + duty_ns =3D min(state->duty_cycle, period_ns); + + /* + * Pick the maximal value for PWM_DIV that still allows a + * 100% relative duty cycle. This allows a fine grained + * selection of duty cycles. + */ + pwm_div =3D IPQ_PWM_MAX_DIV - 1; + + /* + * although mul_u64_u64_div_u64 returns a u64, in practice it + * won't overflow due to above constraints. Take the max period + * of 10^9 (NSEC_PER_SEC) and the pwm_div + 1 (IPQ_PWM_MAX_DIV) + * 10^9 * 10^8 + * ------------- =3D> which fits well into a 32-bit unsigned int. + * 10^9 * 65,535 + */ + pre_div =3D mul_u64_u64_div_u64(period_ns, ipq_chip->clk_rate, + (u64)NSEC_PER_SEC * (pwm_div + 1)); + + if (!pre_div) + return -ERANGE; + + pre_div -=3D 1; + + if (pre_div > IPQ_PWM_MAX_DIV) + pre_div =3D IPQ_PWM_MAX_DIV; + + /* pwm duty =3D HI_DUR * (PRE_DIV + 1) / clk_rate */ + hi_dur =3D mul_u64_u64_div_u64(duty_ns, ipq_chip->clk_rate, + (u64)(pre_div + 1) * NSEC_PER_SEC); + + val =3D FIELD_PREP(IPQ_PWM_REG0_HI_DURATION, hi_dur) | + FIELD_PREP(IPQ_PWM_REG0_PWM_DIV, pwm_div); + ipq_pwm_reg_write(pwm, IPQ_PWM_REG0, val); + + val =3D FIELD_PREP(IPQ_PWM_REG1_PRE_DIV, pre_div); + ipq_pwm_reg_write(pwm, IPQ_PWM_REG1, val); + + /* PWM enable toggle needs a separate write to REG1 */ + val |=3D IPQ_PWM_REG1_UPDATE; + if (state->enabled) + val |=3D IPQ_PWM_REG1_ENABLE; + ipq_pwm_reg_write(pwm, IPQ_PWM_REG1, val); + + return 0; +} + +static int ipq_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, + struct pwm_state *state) +{ + struct ipq_pwm_chip *ipq_chip =3D ipq_pwm_from_chip(chip); + unsigned int pre_div, pwm_div, hi_dur; + u64 effective_div, hi_div; + u32 reg0, reg1; + + reg1 =3D ipq_pwm_reg_read(pwm, IPQ_PWM_REG1); + state->enabled =3D reg1 & IPQ_PWM_REG1_ENABLE; + + if (!state->enabled) + return 0; + + reg0 =3D ipq_pwm_reg_read(pwm, IPQ_PWM_REG0); + + state->polarity =3D PWM_POLARITY_NORMAL; + + pwm_div =3D FIELD_GET(IPQ_PWM_REG0_PWM_DIV, reg0); + hi_dur =3D FIELD_GET(IPQ_PWM_REG0_HI_DURATION, reg0); + pre_div =3D FIELD_GET(IPQ_PWM_REG1_PRE_DIV, reg1); + + effective_div =3D (u64)(pre_div + 1) * (pwm_div + 1); + + /* + * effective_div <=3D 0x100000000, so the multiplication doesn't overflow. + */ + state->period =3D DIV64_U64_ROUND_UP(effective_div * NSEC_PER_SEC, + ipq_chip->clk_rate); + + hi_div =3D hi_dur * (pre_div + 1); + state->duty_cycle =3D DIV64_U64_ROUND_UP(hi_div * NSEC_PER_SEC, + ipq_chip->clk_rate); + + /* + * ensure a valid config is passed back to PWM core in case duty_cycle + * is > period (>100%) + */ + state->duty_cycle =3D min(state->duty_cycle, state->period); + + return 0; +} + +static const struct pwm_ops ipq_pwm_ops =3D { + .apply =3D ipq_pwm_apply, + .get_state =3D ipq_pwm_get_state, +}; + +static int ipq_pwm_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct ipq_pwm_chip *pwm; + struct pwm_chip *chip; + struct clk *clk; + int ret; + + chip =3D devm_pwmchip_alloc(dev, 4, sizeof(*pwm)); + if (IS_ERR(chip)) + return PTR_ERR(chip); + pwm =3D ipq_pwm_from_chip(chip); + + pwm->mem =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(pwm->mem)) + return dev_err_probe(dev, PTR_ERR(pwm->mem), + "Failed to acquire resource\n"); + + clk =3D devm_clk_get_enabled(dev, NULL); + if (IS_ERR(clk)) + return dev_err_probe(dev, PTR_ERR(clk), + "Failed to get clock\n"); + + ret =3D devm_clk_rate_exclusive_get(dev, clk); + if (ret) + return dev_err_probe(dev, ret, "Failed to lock clock rate\n"); + + pwm->clk_rate =3D clk_get_rate(clk); + if (!pwm->clk_rate) + return dev_err_probe(dev, -EINVAL, "Failed due to clock rate being zero\= n"); + + chip->ops =3D &ipq_pwm_ops; + + ret =3D devm_pwmchip_add(dev, chip); + if (ret < 0) + return dev_err_probe(dev, ret, "Failed to add pwm chip\n"); + + return 0; +} + +static const struct of_device_id pwm_ipq_dt_match[] =3D { + { .compatible =3D "qcom,ipq6018-pwm", }, + {} +}; +MODULE_DEVICE_TABLE(of, pwm_ipq_dt_match); + +static struct platform_driver ipq_pwm_driver =3D { + .driver =3D { + .name =3D "ipq-pwm", + .of_match_table =3D pwm_ipq_dt_match, + }, + .probe =3D ipq_pwm_probe, +}; + +module_platform_driver(ipq_pwm_driver); + +MODULE_LICENSE("GPL"); --=20 2.39.5 From nobody Wed Apr 8 04:28:49 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A3E8A2F5A36; Mon, 6 Apr 2026 20:25:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775507137; cv=none; b=tJzi9FgIBWFZbl3/asAGws+tIxIoXawgi4M3ZdWWijJzxRXK/sUC5yac0ZEItx9tWnxIFOyfvJiS+jIAVe7gM61U+Rj0ZEpapRH6vo3hxR7NNHltbGxUG4kPNDqem/jsaUUbuGJoraQNLXp2Ys74WgqAvUQbotTezMG5yF+t//w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775507137; c=relaxed/simple; bh=i/I3n7L/H6hcG6nNaZkHBC8yKfiawIv49U505TQUT5U=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Y7i4h3cH/ainV8R+W6uZ3UOphFtmPKL8Ie0p1AZzRb1RVMM7ssLwLFkDqR9UwtmXBEp5vNBOryx87L9rf6UDSsDgndYiI3vkqJNOvx5RRT5ouoOFAUq2YyCqp1ApkSvvlC8+7yxs/GqFIjWwuysEFW1uRVKgn2vMR/yGUNZNQQA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Bw3rxeWI; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Bw3rxeWI" Received: by smtp.kernel.org (Postfix) with ESMTPS id 7E72DC4AF0F; Mon, 6 Apr 2026 20:25:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1775507137; bh=i/I3n7L/H6hcG6nNaZkHBC8yKfiawIv49U505TQUT5U=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=Bw3rxeWIawanPQ7g7xbjZwa4vlfiwhvgFdnLm2iG5WaDSFM6eEAtMXtyb5SBAQ+dC rKuJ5Bi2f0zBFGvafijlogxkNtGITABtdQ7T2jhHz+KaOnagnc+TSorfwo0T82/hyc S9EVgx1/q6jr/HW6lgauBZDNoe0UqLvxLY6jtIYrAauLh7yRJWuJFv5OY7Ww5rcj8y gpQujtzypeDrd7nYuTNsbQusA7sQnbfIloU6WVNuTAqwur9c67v3IjyMooklKClpIC s1rZxeifTaVNm6Z+lb3v11Nf+yd9UvTBw3Pzyy/oBooXw/sTTVzxHIGZhXuNw91Shp mVDPsx6qQfjFg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 67E6AFB516E; Mon, 6 Apr 2026 20:25:37 +0000 (UTC) From: George Moussalem via B4 Relay Date: Mon, 06 Apr 2026 22:24:40 +0200 Subject: [PATCH v21 3/6] arm64: dts: qcom: ipq6018: add pwm node Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260406-ipq-pwm-v21-3-6ed1e868e4c2@outlook.com> References: <20260406-ipq-pwm-v21-0-6ed1e868e4c2@outlook.com> In-Reply-To: <20260406-ipq-pwm-v21-0-6ed1e868e4c2@outlook.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, George Moussalem , Devi Priya , Baruch Siach , Konrad Dybcio , Krzysztof Kozlowski X-Mailer: b4 0.15.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1775507135; l=1396; i=george.moussalem@outlook.com; s=20260406; h=from:subject:message-id; bh=rU0+JNTTNlPTGkuyuKC6rpbyunJNB1G3olmsX3Lsvj0=; b=UY26W8b27DfZIb9XTOrlGpRmBuUvC+BUePVSm+qZ8Oqk+6NLyq1o1f+k6Odi/mu5rkA7VNa+Z QIViuXMBfwkB9NZtayiiaUJSkcrkdflayDjY8UDwWDp0PPqJhYEzuTm X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=uqspem3ahtBvPEBuxVbyyXT/0Vp3JNb/mo1EPbmBzWg= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20260406 with auth_id=722 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: Devi Priya Describe the PWM block on IPQ6018. Although PWM is in the TCSR area, make pwm its own node as simple-mfd has been removed from the bindings and as such hardware components should have its own node. Reviewed-by: Krzysztof Kozlowski Co-developed-by: Baruch Siach Signed-off-by: Baruch Siach Signed-off-by: Devi Priya Reviewed-by: Konrad Dybcio Signed-off-by: George Moussalem --- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qc= om/ipq6018.dtsi index 40f1c262126e..7866844cc09f 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -413,6 +413,16 @@ tcsr: syscon@1937000 { reg =3D <0x0 0x01937000 0x0 0x21000>; }; =20 + pwm: pwm@1941010 { + compatible =3D "qcom,ipq6018-pwm"; + reg =3D <0x0 0x01941010 0x0 0x20>; + clocks =3D <&gcc GCC_ADSS_PWM_CLK>; + assigned-clocks =3D <&gcc GCC_ADSS_PWM_CLK>; + assigned-clock-rates =3D <100000000>; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + usb2: usb@70f8800 { compatible =3D "qcom,ipq6018-dwc3", "qcom,dwc3"; reg =3D <0x0 0x070f8800 0x0 0x400>; --=20 2.39.5 From nobody Wed Apr 8 04:28:49 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AC9972F9985; Mon, 6 Apr 2026 20:25:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775507137; cv=none; b=ezn6hycoQU4Uy9cylkgpT1cIJSJ+hLkf04Mxmflxop32irRTqACyyjaXBDCRCCJKTENGFLu9JwgDgEp3yv/lO2Tx/2JIetJ9l8/2PgZMkxLn3pYsO3kT7sBOcIjFRG/9aOrPW0XgTF6xD16qvHVdXFTNAMq/aFhEBzttY5HeJHI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775507137; c=relaxed/simple; bh=vY+msfSpuSB0jDw6x5AYAD4LtNsvmSIBHHnDm/9oW0w=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=tU/bIlqHIhrcrvRqw5jZRzb/R/BMNduWnH5jFdYEVzHZRF5cv1vpBcwbYBb5iiLyVfMAL22f8W8hHxw3ycer9eRPnt7Qb8wkBA6BdPQyB3K+udEcyBJgjrqCPdAAhLzcIENHt5CkWDqlkBKrJlMB1REPWI9osUQlAm+QMKoD5K0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=rpWzqBd3; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="rpWzqBd3" Received: by smtp.kernel.org (Postfix) with ESMTPS id 8D3DBC2BCB5; Mon, 6 Apr 2026 20:25:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1775507137; bh=vY+msfSpuSB0jDw6x5AYAD4LtNsvmSIBHHnDm/9oW0w=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=rpWzqBd39rxWR4Sbo+ks6Nqp1m5At37BAHCU7uUkeTcUISZlyGzReQI7Evr4jeL2B MyreQUKG/KHfoWblP+1OwMA9T54HIAEqp2cs6XpUDtKU/r/m3irc4W0zL6YnOYE+C/ yV6kw3L6WBplFIctkbS0nhMpDjhnXWCB9soX+2t+msZJZM9TPwkUPYNjjEu9MZRbYD sEhkm2Q8los78LI/HkR58UmMGxPEYZ866Wb0sqybkywv9fVHjNkgQ32FyCGLYdL2h7 dDrvoXAjtWFRjOg5HCm2D484YYSPiLisjUeTgG9tAhV34JSgcYwjYzkCE5xL6xAezU kAy/P68hUSBxQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 84589FB5168; Mon, 6 Apr 2026 20:25:37 +0000 (UTC) From: George Moussalem via B4 Relay Date: Mon, 06 Apr 2026 22:24:41 +0200 Subject: [PATCH v21 4/6] arm64: dts: qcom: ipq5018: add pwm node Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260406-ipq-pwm-v21-4-6ed1e868e4c2@outlook.com> References: <20260406-ipq-pwm-v21-0-6ed1e868e4c2@outlook.com> In-Reply-To: <20260406-ipq-pwm-v21-0-6ed1e868e4c2@outlook.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, George Moussalem , Dmitry Baryshkov , Konrad Dybcio X-Mailer: b4 0.15.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1775507135; l=1238; i=george.moussalem@outlook.com; s=20260406; h=from:subject:message-id; bh=Q3Kni45lqsYFrwlIKyqfk0z6yh8vt/BwrVScgBSze6s=; b=fBxEPiCugHIQg0LwhaaK7nTTlhEPCk4139ehZNq13093fuLZ05hrjiKW7DJ/E2L8/9e9eCcYu vvqOEKb6aDJAmom01ZPGzhNlB0CkJqLfc6TKlwSwYmmlUoSiKXWCRaP X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=uqspem3ahtBvPEBuxVbyyXT/0Vp3JNb/mo1EPbmBzWg= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20260406 with auth_id=722 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: George Moussalem Describe the PWM block on IPQ5018. Although PWM is in the TCSR area, make pwm its own node as simple-mfd has been removed from the bindings and as such hardware components should have its own node. Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: George Moussalem --- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qc= om/ipq5018.dtsi index 6f8004a22a1f..edff89257468 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi @@ -453,6 +453,16 @@ tcsr: syscon@1937000 { reg =3D <0x01937000 0x21000>; }; =20 + pwm: pwm@1941010 { + compatible =3D "qcom,ipq5018-pwm", "qcom,ipq6018-pwm"; + reg =3D <0x01941010 0x20>; + clocks =3D <&gcc GCC_ADSS_PWM_CLK>; + assigned-clocks =3D <&gcc GCC_ADSS_PWM_CLK>; + assigned-clock-rates =3D <100000000>; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + sdhc_1: mmc@7804000 { compatible =3D "qcom,ipq5018-sdhci", "qcom,sdhci-msm-v5"; reg =3D <0x7804000 0x1000>; --=20 2.39.5 From nobody Wed Apr 8 04:28:49 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CE23C30DEA5; Mon, 6 Apr 2026 20:25:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775507137; cv=none; b=aSLDeAMT/WrunVzAdQ/DYFaCQUfxSFW6MsCffWJAF9JXpzJJfvKwlAXGK7CimfNgLm2YVNqghUZtReWhEbHevVLKO208+efN6LI7sKpCXD+lHjRIcr1aeSKUOR7147asTBN3x4pUnAvaMP3VRxpOKXtGeJLs7b+vquqK1L27dEo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775507137; c=relaxed/simple; bh=/B2IQaLuxVrNEdJu/LPbr3v6eJv9lHIeCnJulAPSQ3o=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=MQcDRfQIBBSMeUzh+Lj239fn9FujG3fsyDohOEShtqgRZ4xDJioBlExVQl7CwSxjh3+RpFjxTAlo0gYrW5ZpbTbSidK/J/Wj9QDzXLSNHp64Y7uun6XLSkGMGp3bGFZSbyrSErESCrJMFlm9L5lLE5XjHKtvhP/H1O+I2tR8hlk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=hwYBDj8D; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="hwYBDj8D" Received: by smtp.kernel.org (Postfix) with ESMTPS id A1FF7C2BCB2; Mon, 6 Apr 2026 20:25:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1775507137; bh=/B2IQaLuxVrNEdJu/LPbr3v6eJv9lHIeCnJulAPSQ3o=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=hwYBDj8DwhZ75ZPw5XhPmZQ6OO0gGZXBDWQCkYxlb1dNzxEuezjOJsAhV3woXNY5w JYfzpAf0OeC6HB6WUAcM2neu7TH1J5RdUs79rTbEG4tziXHkmCOFC9IGIAXqSjTk4A ZMnKCRZbdA6zpaWXqWx8lxUuV0fN/RGgAH0b3OoKrpkRKoe6zIVaqSV/eR9Hu/19B6 owO6dv3D8vY3qu0bZRE6ln3kHhu03T7AQZfrrFAuUX1j2FWzgc8H8LHUCMEDYlv4Kw D2VTrO6E9ymY6Et6vbMLT4alj+RnjUzx05GKOWhPrHBocAx7XtSViuEWIM27TwoaH3 sf18JpvH7Sw4A== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 95C61FB5166; Mon, 6 Apr 2026 20:25:37 +0000 (UTC) From: George Moussalem via B4 Relay Date: Mon, 06 Apr 2026 22:24:42 +0200 Subject: [PATCH v21 5/6] arm64: dts: qcom: ipq5332: add pwm node Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260406-ipq-pwm-v21-5-6ed1e868e4c2@outlook.com> References: <20260406-ipq-pwm-v21-0-6ed1e868e4c2@outlook.com> In-Reply-To: <20260406-ipq-pwm-v21-0-6ed1e868e4c2@outlook.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, George Moussalem , Dmitry Baryshkov , Konrad Dybcio X-Mailer: b4 0.15.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1775507135; l=1258; i=george.moussalem@outlook.com; s=20260406; h=from:subject:message-id; bh=wArkqHV7Q7hOp/b7t2Csz+B/hx/JQeURK4X1hAhc6/s=; b=+btGXL0ph+olveYvqptYbxqv2iABShV57vZ6llT43p64+KvU0n4iSNCOPVrsIJ6knSOyLa9Zo SjDOIbJVvLYD7lvkfHRrfdzgdg1CObeFdfAF3DtvoE+fMV0t6Frpblw X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=uqspem3ahtBvPEBuxVbyyXT/0Vp3JNb/mo1EPbmBzWg= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20260406 with auth_id=722 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: George Moussalem Describe the PWM block on IPQ5332. Although PWM is in the TCSR area, make pwm its own node as simple-mfd has been removed from the bindings and as such hardware components should have its own node. Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: George Moussalem --- arch/arm64/boot/dts/qcom/ipq5332.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qc= om/ipq5332.dtsi index e227730d99a6..27504b7cfe9e 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi @@ -334,6 +334,16 @@ tcsr: syscon@1937000 { reg =3D <0x01937000 0x21000>; }; =20 + pwm: pwm@1941010 { + compatible =3D "qcom,ipq5332-pwm", "qcom,ipq6018-pwm"; + reg =3D <0x01941010 0x20>; + clocks =3D <&gcc GCC_ADSS_PWM_CLK>; + assigned-clocks =3D <&gcc GCC_ADSS_PWM_CLK>; + assigned-clock-rates =3D <100000000>; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + sdhc: mmc@7804000 { compatible =3D "qcom,ipq5332-sdhci", "qcom,sdhci-msm-v5"; reg =3D <0x07804000 0x1000>, <0x07805000 0x1000>; --=20 2.39.5 From nobody Wed Apr 8 04:28:49 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CC708302140; Mon, 6 Apr 2026 20:25:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775507137; cv=none; b=GxARqx0Bvjw06T08VNEE/c4/zSrAdFVO6laoms9j0tG36A1MvX08xJeg690BiXeA8oWvnKRhy8sJEslnwmoiCvu/ukiF1u5Rh5k1AQHux5hlYYuXtNwpqulaFPZrfjkskE3sa7lrr/8xUhOXUf+nVbJpx0rdiXrt2dLTIhdi5mY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775507137; c=relaxed/simple; bh=ribnztIR4jWaiDRYmWtd83mRF1GazSvlgDdIiliQ/NI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=eNWctWMgyZyTBMIhFOPTZavtRU8AhmykZDncshCaGAtRlqd17g4OM2kXK7cm+dJX0QTHHu/rtIzm4sNVZXfyr4g+Hy+DGdSOFQrPi7QQdcPViHvaCx/0ptOj1rFE4jpsObpvTUEhR0TGc5K5zdKk7wAZu4pdGjeAPHRRTACnC/U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=CXN88ZPV; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="CXN88ZPV" Received: by smtp.kernel.org (Postfix) with ESMTPS id AEC07C2BCB0; Mon, 6 Apr 2026 20:25:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1775507137; bh=ribnztIR4jWaiDRYmWtd83mRF1GazSvlgDdIiliQ/NI=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=CXN88ZPVaZbVCe3Oe5FGn+/aTE03Q5FCHQkzYAnD/s21Wr7UxVKf0Dnceh9rtm6Qw HIAutMWdcdmorlFfyT1/29P9V/T3M4ogB5b2Q0WHJ+RDc+LPk85l3nYmvcLJsJnHQv Y2lbw2Liat16pry+XxcKZMCf8abPngsuHxEOJjcQWHCZlo6vpBQigWGLjoGeEPOhRZ k5OxS6MSFqNv9liD2eCGtPZRtSobvgt6+fnoFtE6b9RSbI2D6Lm1ZdtaSs9w8uoGCT 7RVGfUntc3me3cpHM7trYfhN7NSz9siA6gUybWEEp7dcjnO09OxtqhFpu8LO4AMe9B DbD/Wjpnc6JYg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id A65F6FB516F; Mon, 6 Apr 2026 20:25:37 +0000 (UTC) From: George Moussalem via B4 Relay Date: Mon, 06 Apr 2026 22:24:43 +0200 Subject: [PATCH v21 6/6] arm64: dts: qcom: ipq9574: add pwm node Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260406-ipq-pwm-v21-6-6ed1e868e4c2@outlook.com> References: <20260406-ipq-pwm-v21-0-6ed1e868e4c2@outlook.com> In-Reply-To: <20260406-ipq-pwm-v21-0-6ed1e868e4c2@outlook.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, George Moussalem , Dmitry Baryshkov , Konrad Dybcio X-Mailer: b4 0.15.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1775507135; l=1239; i=george.moussalem@outlook.com; s=20260406; h=from:subject:message-id; bh=ZGylQ/mkBST8aMMXzv/c+bz2PK+194wczC4slSURFQY=; b=XvLPQ0OY93o1OdqdxLdxqFja7hrUaeFR/mqYjahxFcHPpWCwUkH9Gj8CSE2ZykcEZGdBrV7jc 7urHSEWvPY0CrtGq6tA4aWFofLpikodtPUD1labvUdn6mbCLPNsKrU/ X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=uqspem3ahtBvPEBuxVbyyXT/0Vp3JNb/mo1EPbmBzWg= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20260406 with auth_id=722 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: George Moussalem Describe the PWM block on IPQ9574. Although PWM is in the TCSR area, make pwm its own node as simple-mfd has been removed from the bindings and as such hardware components should have its own node. Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: George Moussalem --- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qc= om/ipq9574.dtsi index 622cfa96ed2b..3f15c40f7841 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -445,6 +445,16 @@ tcsr: syscon@1937000 { reg =3D <0x01937000 0x21000>; }; =20 + pwm: pwm@1941010 { + compatible =3D "qcom,ipq9574-pwm", "qcom,ipq6018-pwm"; + reg =3D <0x01941010 0x20>; + clocks =3D <&gcc GCC_ADSS_PWM_CLK>; + assigned-clocks =3D <&gcc GCC_ADSS_PWM_CLK>; + assigned-clock-rates =3D <100000000>; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + sdhc_1: mmc@7804000 { compatible =3D "qcom,ipq9574-sdhci", "qcom,sdhci-msm-v5"; reg =3D <0x07804000 0x1000>, --=20 2.39.5