From nobody Sun Jun 14 21:21:51 2026 Received: from smtpbg151.qq.com (smtpbg151.qq.com [18.169.211.239]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5D4BD325701; Mon, 6 Apr 2026 15:56:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=18.169.211.239 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775490975; cv=none; b=Aw89ALjkrqNOrACjtqgC//baBOH4XOcaNPq2mg/3UalycC9tNrmIzpONJgwyqtyOBe/Fn7GUWBRXO8UaJZNdVfEEAZgcJH7iVz6f3yGI9StEd126xl7etv/SjXBk6BubHyFqxMsvATy4IrYOCYjFQiJW+IRRjQYtqJia0FZ7JV4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775490975; c=relaxed/simple; bh=gnkUmVU1LyJnPFJoUBS9r7AF4qmy3GcAKD0eBQeszLA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=bjJVHDMpfMQogJF+BZDy0PEdodo+kkg6+95WuW6QZyCGIKQ+qn/7vhmGlrACtxphOGrSEHrd1iYxY/Huh4H0QRbNXfYgKvmFNCDyL4yfMdWAudoe4zMEgVuW7X1gNUzv1F+pMIA8YskXbVkQQYNmPtFDjlsqXeJ7NzK5MoyTCoU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=radxa.com; spf=pass smtp.mailfrom=radxa.com; arc=none smtp.client-ip=18.169.211.239 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=radxa.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=radxa.com X-QQ-mid: zesmtpgz9t1775490892tfbe0e21d X-QQ-Originating-IP: bR5ZXZfIll1MIptKQxxeV+OfKwfN8IGcIP4TTnaIjIk= Received: from [192.168.30.32] ( [116.234.14.100]) by bizesmtp.qq.com (ESMTP) with id ; Mon, 06 Apr 2026 23:54:50 +0800 (CST) X-QQ-SSF: 0000000000000000000000000000000 X-QQ-GoodBg: 0 X-BIZMAIL-ID: 17703681536824160484 EX-QQ-RecipientCnt: 11 From: Xilin Wu Date: Mon, 06 Apr 2026 23:54:33 +0800 Subject: [PATCH 1/5] clk: qcom: clk-rcg2: fix clk_rcg2_calc_mnd() producing wrong M/N/pre_div Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260406-clk-qcom-gpclk-fixes-v1-1-7a14fe64552d@radxa.com> References: <20260406-clk-qcom-gpclk-fixes-v1-0-7a14fe64552d@radxa.com> In-Reply-To: <20260406-clk-qcom-gpclk-fixes-v1-0-7a14fe64552d@radxa.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Dzmitry Sankouski , Taniya Das , Mike Turquette Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Stephen Boyd , Xilin Wu X-Mailer: b4 0.15.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=3853; i=sophon@radxa.com; h=from:subject:message-id; bh=gnkUmVU1LyJnPFJoUBS9r7AF4qmy3GcAKD0eBQeszLA=; b=owGbwMvMwCVmdFg0fe08Iz/G02pJDJmXr7vPUr621IbHyb5z8aFJf8w3HVn0UrFGrnzTkZsVr Pu4MkIZOkpZGMS4GGTFFFkU4hnmslfmXnsqVqoHM4eVCWQIAxenAExkxnlGho9C2/jbn3JMbkox 29fja/NNV/XLBM8dUSscHq+ZXn9xninD/xqfbRueTfxrscFwxs53Wyv/Gt/aumuBk1fTB3Zr0Yq q7WwA X-Developer-Key: i=sophon@radxa.com; a=openpgp; fpr=205F009D07796DD6E516752E32C31567AD9E324E X-QQ-SENDSIZE: 520 Feedback-ID: zesmtpgz:radxa.com:qybglogicsvrsz:qybglogicsvrsz3b-0 X-QQ-XMAILINFO: NC+WtJebsKNcbqM23I/D6x2h7HydLJXjUrP/3sbtB4cunSXC4buP+d7B AnmrOrKNdYyJfoZ60fUG4mIDB/R+WwHIN+hC4gOuGxmKd25Ri5HPtJeWRoWlUxiDqspSry/ oP8UfVDTQPHr9GfEJucHbmOFuDHV8PRz+4WoEgPCrc2oPziXiPAOO57WuO//7HK2xDGvAiD 2PHuMg0DG02QYnIY5Iz9cywfqRY3bjgKly9WwC2TjLXSBhEGso0bDxg24TknSriMy7wNg5v hqpsAwhFmuEMGOsfwW9JfkrUf05ycrunQNLxtXCLN7amlj5MmSdKD+3cSEkE/ri9iZ2yxZv B59Tp7Fv+PZ8gta2GIXAy0+JYrdupHuRYwkM4cpmfw5Rm3FVohAQOdQEfBafPoy59ugVG4A FlivT9wAMr90hYLHp3pFbw4Wz/dr/6zd1IqOGi5CdK/wOqhSMkrq6VliKBpMaTtCv4/BFGp MmL0cVh3eSpD0ndVAtz2gleZYkHnQ/TIbC0LAp1ubldo4O/cUvccJjDqaeZfsBlF7/bO6kC VIWNjrqGgnt2QfkOLVaTm7EZ8QH3HaFRVAnk82o7N6crA4SvqA43URZMzIYG2FvMJ7cFADS UibKxAi88HUkzcTD2mNcTjQI2C5D3VCGkuKorBngYPj8eFtl5Y2mP64FSG5FsYJt+SUk+D1 WGvDIBlK9irh7l64gmiUL4o9qm7DVcVhoIjNVstYxfQZfPs79JKhjXvVk2mF94widpJf54q xLqQ8iKaVhGAB13Hd2siZQbIvuPd1/bZxozEFkmPeiVXkQlAFVgqwiOT/8GZ+2QA5W5e4OP go4IObIUs11nu6K6AnN/vnfnXmG17BgHyHrrwrUEcrpeJ/CYsD+bdyoYBThE6r/NCEu3ol8 9EHUxUBBBoM9yNqEhac3mQ7y7euxrVKfUZj3dKJ65BrR4leBkyvhOhpcDPuHakZVjpnDuu6 +y3a7gj4asdj6Qr31bLEGuDSsz7+yKoA6reuXH7cuPQpVMQ/LuME+e6rc6BxTCOntGx4wOb kDG4xaWASobe+wf6fPizJNxh/KXiQEW5ISO5OBHJfraKf6Z6mD5vw5y4UAPA3yMFU8bFGC5 kJoNv7RasWE X-QQ-XMRINFO: M/715EihBoGS47X28/vv4NpnfpeBLnr4Qg== X-QQ-RECHKSPAM: 0 Fix three related bugs in clk_rcg2_calc_mnd() that cause the GP clock MND divider to produce incorrect frequencies and duty cycles: 1) n_max and n_candidate are declared as u16 but can hold values exceeding 65535 during computation. When mnd_width is 16 and mnd_max is 65535, even m=3D1 gives n_max=3D65536 which overflows u16 to 0, making "n_candidate < n_max" always false. Similarly n_candidate overflows on intermediate products (e.g., 15360 * 5 =3D 76800 wraps to 11264), causing the wrong value to be accepted as n. Fix by changing both n_max and n_candidate from u16 to u32. 2) n_max is computed as (m + mnd_max), which only accounts for the N register constraint (n - m must fit in mnd_width bits). However, the D register shares the same mnd_width bits but must store values up to 2*n for duty cycle control. When n > mnd_max/2, the D register cannot represent high duty cycles, silently clamping the maximum achievable duty cycle (e.g. to 85% instead of 99%). Fix by computing n_max as (mnd_max + 1) / 2, ensuring 2*n always fits within the D register's bit width. 3) When no pre-division is needed (pre_div stays at its initial value of 1), "pre_div > 1 ? pre_div : 0" sets f->pre_div to 0. The subsequent convert_to_reg_val() computes (0 * 2 - 1) which underflows the u8 pre_div field to 255, programming a 128x pre-divider into hardware. Fix by assigning pre_div unconditionally. Since pre_div is initialized to 1 and only multiplied, it is always >=3D 1. A value of 1 correctly converts to register value 1 via convert_to_reg_val(), which means no pre-division in calc_rate(). Example with parent=3D19.2 MHz XO, requesting 25 kHz: Before: m=3D1, n=3D48, pre_div=3D15 -> 26666 Hz (6.7% error) After: m=3D1, n=3D768, pre_div=3D1 -> 25000 Hz (exact) Fixes: 898b72fa44f5 ("clk: qcom: gcc-sdm845: Add general purpose clock ops") Signed-off-by: Xilin Wu --- drivers/clk/qcom/clk-rcg2.c | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c index 6064a0e17d51..82ee7ca1703a 100644 --- a/drivers/clk/qcom/clk-rcg2.c +++ b/drivers/clk/qcom/clk-rcg2.c @@ -437,27 +437,35 @@ static void clk_rcg2_calc_mnd(u64 parent_rate, u64 ra= te, struct freq_tbl *f, int i =3D 2; unsigned int pre_div =3D 1; unsigned long rates_gcd, scaled_parent_rate; - u16 m, n =3D 1, n_candidate =3D 1, n_max; + u32 n_max, n_candidate =3D 1; + u16 m, n =3D 1; =20 rates_gcd =3D gcd(parent_rate, rate); m =3D div64_u64(rate, rates_gcd); scaled_parent_rate =3D div64_u64(parent_rate, rates_gcd); - while (scaled_parent_rate > (mnd_max + m) * pre_div_max) { + + /* + * Limit n so that the D register can represent the full duty cycle + * range. The D register stores values up to 2*(n-m) using mnd_width + * bits. Since m >=3D 1, n <=3D (mnd_max + 1) / 2 guarantees + * 2*(n-m) <=3D mnd_max - 1. + */ + n_max =3D (mnd_max + 1) / 2; + + while (scaled_parent_rate > (unsigned long)n_max * pre_div_max) { // we're exceeding divisor's range, trying lower scale. if (m > 1) { m--; scaled_parent_rate =3D mult_frac(scaled_parent_rate, m, (m + 1)); } else { // cannot lower scale, just set max divisor values. - f->n =3D mnd_max + m; + f->n =3D n_max; f->pre_div =3D pre_div_max; f->m =3D m; return; } } =20 - n_max =3D m + mnd_max; - while (scaled_parent_rate > 1) { while (scaled_parent_rate % i =3D=3D 0) { n_candidate *=3D i; @@ -475,7 +483,7 @@ static void clk_rcg2_calc_mnd(u64 parent_rate, u64 rate= , struct freq_tbl *f, =20 f->m =3D m; f->n =3D n; - f->pre_div =3D pre_div > 1 ? pre_div : 0; + f->pre_div =3D pre_div; } =20 static int clk_rcg2_determine_gp_rate(struct clk_hw *hw, --=20 2.53.0 From nobody Sun Jun 14 21:21:51 2026 Received: from smtpbg150.qq.com (smtpbg150.qq.com [18.132.163.193]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7EA45329C6D; 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dmarc=pass (p=none dis=none) header.from=radxa.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=radxa.com X-QQ-mid: zesmtpgz9t1775490894t032c96f4 X-QQ-Originating-IP: NwwJw9qpw8W/iHvEWx8Za8lBoUkFMiXVPxCDldnH0xs= Received: from [192.168.30.32] ( [116.234.14.100]) by bizesmtp.qq.com (ESMTP) with id ; Mon, 06 Apr 2026 23:54:53 +0800 (CST) X-QQ-SSF: 0000000000000000000000000000000 X-QQ-GoodBg: 0 X-BIZMAIL-ID: 7787406259801255964 EX-QQ-RecipientCnt: 11 From: Xilin Wu Date: Mon, 06 Apr 2026 23:54:34 +0800 Subject: [PATCH 2/5] clk: qcom: clk-rcg2: use 64-bit arithmetic in set_duty_cycle() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260406-clk-qcom-gpclk-fixes-v1-2-7a14fe64552d@radxa.com> References: <20260406-clk-qcom-gpclk-fixes-v1-0-7a14fe64552d@radxa.com> In-Reply-To: <20260406-clk-qcom-gpclk-fixes-v1-0-7a14fe64552d@radxa.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Dzmitry Sankouski , Taniya Das , Mike Turquette Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Stephen Boyd , Xilin Wu X-Mailer: b4 0.15.1 X-Developer-Signature: v=1; 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When n is large and duty->num is also large, the intermediate result overflows u32. For example, requesting 50% duty on a 1 kHz output derived from a 19.2 MHz parent gives n=3D19200, duty->num=3D500000, duty->den=3D1000000: 19200 * 500000 * 2 =3D 19,200,000,000 > U32_MAX (4,294,967,295) The truncated result produces a completely wrong duty cycle (5.26% instead of the requested 50%). Use DIV_ROUND_CLOSEST_ULL() with an explicit (u64) cast to prevent the overflow. Fixes: 7f891faf596e ("clk: qcom: clk-rcg2: Add support for duty-cycle for R= CG") Signed-off-by: Xilin Wu Reviewed-by: Konrad Dybcio --- drivers/clk/qcom/clk-rcg2.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c index 82ee7ca1703a..0e8f0473897e 100644 --- a/drivers/clk/qcom/clk-rcg2.c +++ b/drivers/clk/qcom/clk-rcg2.c @@ -783,7 +783,7 @@ static int clk_rcg2_set_duty_cycle(struct clk_hw *hw, s= truct clk_duty *duty) n =3D (~(notn_m) + m) & mask; =20 /* Calculate 2d value */ - d =3D DIV_ROUND_CLOSEST(n * duty->num * 2, duty->den); + d =3D DIV_ROUND_CLOSEST_ULL((u64)n * duty->num * 2, duty->den); =20 /* * Check bit widths of 2d. If D is too big reduce duty cycle. --=20 2.53.0 From nobody Sun Jun 14 21:21:51 2026 Received: from smtpbgjp3.qq.com (smtpbgjp3.qq.com [54.92.39.34]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BB840329C6D for ; Mon, 6 Apr 2026 15:55:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=54.92.39.34 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775490909; cv=none; b=H+K7RBKrzPQGPla71Hvl8n1XGGz8yqDYA/rbu0q6s7GzyDOV1Qzc+3WBcEgsEthL3sORoOmcnWy/FUSDgUxah+eaZZWFQEJYzelH/kl/mj+tPmhgO44cbFvOCecAofL9ArKNYCGBjuBnL2/RNnp6hKY4AyVZoKyVqziv7Ko1Du0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775490909; c=relaxed/simple; bh=aOqTALeaaPjEPJvjLbPBj3axhry4HV3f5+Juq9Ed1J4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=CgwFKkt+YfGOHi5J8dnTWGJkQPt6JhjjyNRfos6J3krg9LfCPRy66MzKdEalP4zbBSNjNqBckYQq0UU5CaPUxLTECsX4oGjiRF/IFWLOLbB9i0Vbh4RFB2IfJvYgbtNdknFe20Cq8Mg7yMY0Dy6njXPkFYeknqb78rdSc3Ha6jg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=radxa.com; spf=pass smtp.mailfrom=radxa.com; arc=none smtp.client-ip=54.92.39.34 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=radxa.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=radxa.com X-QQ-mid: zesmtpgz9t1775490897te3757a25 X-QQ-Originating-IP: e43LyfCY0OpxhV6mr2hMhuaKYNHUSn0WtLAmc+LxKLc= Received: from [192.168.30.32] ( [116.234.14.100]) by bizesmtp.qq.com (ESMTP) with id ; Mon, 06 Apr 2026 23:54:55 +0800 (CST) X-QQ-SSF: 0000000000000000000000000000000 X-QQ-GoodBg: 0 X-BIZMAIL-ID: 3139723224806532076 EX-QQ-RecipientCnt: 12 From: Xilin Wu Date: Mon, 06 Apr 2026 23:54:35 +0800 Subject: [PATCH 3/5] clk: qcom: clk-branch: calculate timeout based on clock frequency Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260406-clk-qcom-gpclk-fixes-v1-3-7a14fe64552d@radxa.com> References: <20260406-clk-qcom-gpclk-fixes-v1-0-7a14fe64552d@radxa.com> In-Reply-To: <20260406-clk-qcom-gpclk-fixes-v1-0-7a14fe64552d@radxa.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Dzmitry Sankouski , Taniya Das , Mike Turquette Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Stephen Boyd , Xilin Wu , Mike Tipton X-Mailer: b4 0.15.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=2227; i=sophon@radxa.com; h=from:subject:message-id; bh=aOqTALeaaPjEPJvjLbPBj3axhry4HV3f5+Juq9Ed1J4=; b=owGbwMvMwCVmdFg0fe08Iz/G02pJDJmXr7vHlB+W4fH5q/b8Z0SXhsB+7rc2RUWSp46eyFB7U Cd0e2NYRykLgxgXg6yYIotCPMNc9srca0/FSvVg5rAygQxh4OIUgInsD2Bk2B3OfGa6oLnH4xcP wtf6W9b/2fvZ26Lr9Md6B6PZE9bqdTD8U1we+lN4gZu//93U3yt36Oy7auUz8em9x0eeKcwyqZ/ fwQYA X-Developer-Key: i=sophon@radxa.com; a=openpgp; fpr=205F009D07796DD6E516752E32C31567AD9E324E X-QQ-SENDSIZE: 520 Feedback-ID: zesmtpgz:radxa.com:qybglogicsvrsz:qybglogicsvrsz3b-0 X-QQ-XMAILINFO: NlVgJxuVJf8SMdlxgAde3YDtfF3wvD3jkT61XgSOXhHO/aWc7RduW4jV 0umexWe7yJjcOIn5zin6i4uwV/qmFn6BrakiyaEyXC2liCG7wYiCce2zANwEACLl26jsMoV 3IKOZu4lHs9R5M/h6WCqGp/wyCZVa6e45VQJ4aZsufCDYzIcM83ux97+LC4zdq6gr/e7nr4 B8YbmUZoS7F+q9zYIWU+Na5iwgCvSgfmlFUWLuG1nfQ9yrMjoVhlRUxpGnMo9vr/Jr/DmTY lPDf+HV8o+xwK1/+x/RSd6NZVl9cdJPR6H9anrv/tAVlSS/RBUnQ1efbUwtAM3wXOHlIVwI jW1/mlhv0vsEbOB7FDZzE7oL9sItCkNusiIiJjs9MO5MBhn5x89v9yKH59YM5UwXtIvsrDO EhpORY5CYUJ/AzqXpaXdYR1uT0bbI/HuAS4joxKgHZwShQ6/TfUX0ja0m56jk/hTBwuNC1D jTUA+2qVDuSti49yS/vhiXymhGtMJYX90j5jIfyVTiS5Zqe4S2wDlrqLug7UnFhI7h68L60 GYUnIy37wolkBZjf/EAi2slVBFdyEr3jeXA1awXH1owTV1voCTAWTsDRmTOg04h4TRJ3cBQ Aqll3C4u9T5r1NSYpdALdCenaaS0H66g2lvC9DkCK4lJK2NYDUKCjEbxGA7cyNXEtqgSLad OvOwYYnlxyOz3i7hwNGiVFTLEld3E3L532S9AEwWJA4LQbtqb+MrQMGWRQD70YY4QcVIeKg 7fGbyrP+KC8pniwk2C6uJ73E+o2EE3XxqjSFvgMjampSlbFjQm1IjlhhIy+MvL1g+MptX3a k5joMbJyyyArrsNeqt/mJ9yN7el6JrkxMSsRGSdnQ0n0NJASdU5B8Y5o4mn2B4DLqmDxIDO RUHZAGG8ZrAdVGTO5RFmYzDnCt4E4+kTPMJA8iR8+cL+MSTNp5NnCe4r5jqFLLQELMZMv3J 7aM98wptE+pE47ZLvbm11pDeym7wu/Q4wq76fZHlt7QW4YZYz3h0hing6WoNRWo11GVF0hc xxInBY5ZKyruLtShSKTplekQ9Uqt2+RqauCiKI1ihtDbDS6C29lUVjW0aKtkym1oQD4KOH7 A== X-QQ-XMRINFO: Nq+8W0+stu50tPAe92KXseR0ZZmBTk3gLg== X-QQ-RECHKSPAM: 0 Clock branches with extremely low rates (tens of Hz to low kHz) take much longer to toggle than the fixed 200 us timeout allows. A 1 kHz clock needs at least 3 ms (3 cycles) to toggle. Instead of increasing the timeout to a huge fixed value for all clocks, dynamically compute the required timeout based on the current clock rate, accounting for 3 cycles at the current clock rate. Based on a downstream patch by Mike Tipton: https://git.codelinaro.org/clo/la/kernel/qcom/-/commit/aa899c2d1fa31e247f04= 810f125ac9c60927c901 Fixes: 6e0ad1b6c1c9 ("clk: qcom: Add support for branches/gate clocks") Signed-off-by: Mike Tipton Signed-off-by: Xilin Wu --- drivers/clk/qcom/clk-branch.c | 22 ++++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/drivers/clk/qcom/clk-branch.c b/drivers/clk/qcom/clk-branch.c index 444e7d8648d4..2641dcf93277 100644 --- a/drivers/clk/qcom/clk-branch.c +++ b/drivers/clk/qcom/clk-branch.c @@ -59,9 +59,27 @@ static bool clk_branch2_check_halt(const struct clk_bran= ch *br, bool enabling) return (val & CBCR_CLK_OFF) =3D=3D (invert ? 0 : CBCR_CLK_OFF); } =20 +static int get_branch_timeout(const struct clk_branch *br) +{ + unsigned long rate; + int timeout; + + /* + * The time it takes a clock branch to toggle is roughly 3 clock cycles. + */ + rate =3D clk_hw_get_rate(&br->clkr.hw); + if (!rate) + return 200; + + timeout =3D 3 * (USEC_PER_SEC / rate); + + return max(timeout, 200); +} + static int clk_branch_wait(const struct clk_branch *br, bool enabling, bool (check_halt)(const struct clk_branch *, bool)) { + int timeout, count; bool voted =3D br->halt_check & BRANCH_VOTED; const char *name =3D clk_hw_get_name(&br->clkr.hw); =20 @@ -77,9 +95,9 @@ static int clk_branch_wait(const struct clk_branch *br, b= ool enabling, } else if (br->halt_check =3D=3D BRANCH_HALT_ENABLE || br->halt_check =3D=3D BRANCH_HALT || (enabling && voted)) { - int count =3D 200; + timeout =3D get_branch_timeout(br); =20 - while (count-- > 0) { + for (count =3D timeout; count > 0; count--) { if (check_halt(br, enabling)) return 0; udelay(1); --=20 2.53.0 From nobody Sun Jun 14 21:21:51 2026 Received: from smtpbguseast2.qq.com (smtpbguseast2.qq.com [54.204.34.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 38A21274FDC for ; Mon, 6 Apr 2026 15:55:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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spf=pass smtp.mailfrom=radxa.com X-QQ-mid: zesmtpgz9t1775490899ta4844d97 X-QQ-Originating-IP: kz4tg1extCWtRAZh5P45oqkn990iC9RLqZTRzwmI0eU= Received: from [192.168.30.32] ( [116.234.14.100]) by bizesmtp.qq.com (ESMTP) with id ; Mon, 06 Apr 2026 23:54:58 +0800 (CST) X-QQ-SSF: 0000000000000000000000000000000 X-QQ-GoodBg: 0 X-BIZMAIL-ID: 13727944797770228139 EX-QQ-RecipientCnt: 12 From: Xilin Wu Date: Mon, 06 Apr 2026 23:54:36 +0800 Subject: [PATCH 4/5] clk: qcom: clk-rcg2: calculate timeout based on clock frequency Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260406-clk-qcom-gpclk-fixes-v1-4-7a14fe64552d@radxa.com> References: <20260406-clk-qcom-gpclk-fixes-v1-0-7a14fe64552d@radxa.com> In-Reply-To: <20260406-clk-qcom-gpclk-fixes-v1-0-7a14fe64552d@radxa.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Dzmitry Sankouski , Taniya Das , Mike Turquette Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Stephen Boyd , Xilin Wu , Mike Tipton X-Mailer: b4 0.15.1 X-Developer-Signature: v=1; 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A 1 kHz clock needs at least 3 ms (3 cycles) for the configuration handshake. Instead of increasing the timeout to a huge fixed value for all clocks, dynamically compute the required timeout based on both the old and new clock rates, accounting for 3 cycles at each rate. Based on a downstream patch by Mike Tipton: https://git.codelinaro.org/clo/la/kernel/qcom/-/commit/aa899c2d1fa31e247f04= 810f125ac9c60927c901 Fixes: bcd61c0f535a ("clk: qcom: Add support for root clock generators (RCG= s)") Signed-off-by: Mike Tipton Signed-off-by: Xilin Wu --- drivers/clk/qcom/clk-rcg.h | 2 ++ drivers/clk/qcom/clk-rcg2.c | 27 +++++++++++++++++++++++++-- 2 files changed, 27 insertions(+), 2 deletions(-) diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h index 4fbdf4880d03..12c1ce0f774c 100644 --- a/drivers/clk/qcom/clk-rcg.h +++ b/drivers/clk/qcom/clk-rcg.h @@ -159,6 +159,7 @@ extern const struct clk_ops clk_dyn_rcg_ops; * @clkr: regmap clock handle * @cfg_off: defines the cfg register offset from the CMD_RCGR + CFG_REG * @parked_cfg: cached value of the CFG register for parked RCGs + * @configured_freq: last configured frequency, used for timeout calculati= on * @hw_clk_ctrl: whether to enable hardware clock control */ struct clk_rcg2 { @@ -174,6 +175,7 @@ struct clk_rcg2 { struct clk_regmap clkr; u8 cfg_off; u32 parked_cfg; + unsigned long configured_freq; bool hw_clk_ctrl; }; =20 diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c index 0e8f0473897e..732f34629ea2 100644 --- a/drivers/clk/qcom/clk-rcg2.c +++ b/drivers/clk/qcom/clk-rcg2.c @@ -111,9 +111,27 @@ static u8 clk_rcg2_get_parent(struct clk_hw *hw) return __clk_rcg2_get_parent(hw, cfg); } =20 +static int get_update_timeout(const struct clk_rcg2 *rcg) +{ + int timeout =3D 0; + unsigned long current_freq; + + /* + * The time it takes an RCG to update is roughly 3 clock cycles of the + * old and new clock rates. + */ + current_freq =3D clk_hw_get_rate(&rcg->clkr.hw); + if (current_freq) + timeout +=3D 3 * (USEC_PER_SEC / current_freq); + if (rcg->configured_freq) + timeout +=3D 3 * (USEC_PER_SEC / rcg->configured_freq); + + return max(timeout, 500); +} + static int update_config(struct clk_rcg2 *rcg) { - int count, ret; + int timeout, count, ret; u32 cmd; struct clk_hw *hw =3D &rcg->clkr.hw; const char *name =3D clk_hw_get_name(hw); @@ -123,8 +141,10 @@ static int update_config(struct clk_rcg2 *rcg) if (ret) return ret; =20 + timeout =3D get_update_timeout(rcg); + /* Wait for update to take effect */ - for (count =3D 500; count > 0; count--) { + for (count =3D timeout; count > 0; count--) { ret =3D regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, &cmd); if (ret) return ret; @@ -602,6 +622,8 @@ static int clk_rcg2_configure(struct clk_rcg2 *rcg, con= st struct freq_tbl *f) if (ret) return ret; =20 + rcg->configured_freq =3D f->freq; + return update_config(rcg); } =20 @@ -689,6 +711,7 @@ static int clk_rcg2_set_gp_rate(struct clk_hw *hw, unsi= gned long rate, =20 clk_rcg2_calc_mnd(parent_rate, rate, f, mnd_max, hid_max / 2); convert_to_reg_val(f); + rcg->configured_freq =3D rate; ret =3D clk_rcg2_configure_gp(rcg, f); =20 return ret; --=20 2.53.0 From nobody Sun Jun 14 21:21:51 2026 Received: from smtpbgbr1.qq.com (smtpbgbr1.qq.com [54.207.19.206]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5FE32325701; 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dmarc=pass (p=none dis=none) header.from=radxa.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=radxa.com X-QQ-mid: zesmtpgz9t1775490902t7c4ddd20 X-QQ-Originating-IP: u9LdF/MuUBTYhB/eG4aIcw9LJyIudnoCCsBBbNR3WA0= Received: from [192.168.30.32] ( [116.234.14.100]) by bizesmtp.qq.com (ESMTP) with id ; Mon, 06 Apr 2026 23:55:00 +0800 (CST) X-QQ-SSF: 0000000000000000000000000000000 X-QQ-GoodBg: 0 X-BIZMAIL-ID: 190652990989054796 EX-QQ-RecipientCnt: 11 From: Xilin Wu Date: Mon, 06 Apr 2026 23:54:37 +0800 Subject: [PATCH 5/5] clk: qcom: clk-rcg2: fix set_duty_cycle() integer overflow in boundary checks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260406-clk-qcom-gpclk-fixes-v1-5-7a14fe64552d@radxa.com> References: <20260406-clk-qcom-gpclk-fixes-v1-0-7a14fe64552d@radxa.com> In-Reply-To: <20260406-clk-qcom-gpclk-fixes-v1-0-7a14fe64552d@radxa.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Dzmitry Sankouski , Taniya Das , Mike Turquette Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Stephen Boyd , Xilin Wu X-Mailer: b4 0.15.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=1716; i=sophon@radxa.com; h=from:subject:message-id; bh=/G6qp68CyMYWgMJp25Zpj5M5dAg24l46LVGosbtcH1Q=; b=owGbwMvMwCVmdFg0fe08Iz/G02pJDJmXr3vInVurq5DKfrvxnuJkDpObF482zFHjdHF+ksvu2 33zgkVpRykLgxgXg6yYIotCPMNc9srca0/FSvVg5rAygQxh4OIUgIlwxjH899efY9N1Y8vtE+JM Rov+R7Tdzec7qp58tHzDqaAYgUNvQxkZLq11FQi7/SxU0/0hZ66zwJmJV4qC1+SdlfpWvCjm+rY SJgA= X-Developer-Key: i=sophon@radxa.com; a=openpgp; fpr=205F009D07796DD6E516752E32C31567AD9E324E X-QQ-SENDSIZE: 520 Feedback-ID: zesmtpgz:radxa.com:qybglogicsvrsz:qybglogicsvrsz3b-0 X-QQ-XMAILINFO: NOH1TaCqk/M+slQkMoa7JS71wOtNgBraIBTc1/7ijaxzoXHqkg8NttZg W4lR8azkvfuHBWM+B+hfKoeuT+aORDoxQuo1Fl/veh+4kzy1Plq9CBQGaUKCSv8OQj6hGNf UbKHxk1ZLWgGdHm7CKJ6JKMXk0Q+GtMmmeiK6PaqAWrtyebDKrcmSVbQJV71bhX/3UtHCGN zfkF369C4EnOl+LSOUW6LHskcIR31xCGyTHa/yhtVXY1THrK+b9E3C97jmJbk8ElEbGqSQ6 icVMkwztS1B9giv4jrTbuui5ToVUg0kUPPFWCQ6QnxSf3JAJTZ2G9FSyZERMMbPYDHBUMa5 xUg+KsMIHv0wHoDmHrOI8js8GJ9VDt9dR+oGGhUIlAN5g3U+SuAKZtB+mthJiXxQ0CxKPHs zYXzb8Ajm97Eo/ExH0vSBfuUPnffi4Ihad1DNkBm4Oss13+x4F1IXXn3k0BjJfuv6+8TvEb vn36VZLukQ6QSbJ79rlfTUCvmNKn/dLHzY+VzUha6NmWUwjk4A6dxZIS9M1d8G/MJVJHQID uh+hCaJ8OccrHO0OzE5mTibDsPfMPJMJiEE/quUiMEAdSICZfDCb9YdHXpQBsW4ZOfnv5Ge Izz1Wcs+1RHrIVUbyoaYBG6th6q49JVjgH12tdoqx+BSvqc8Jh6Uc07tLJM4ooKiApZvOw6 3cYfpQ+1Nqm35HgO2Wb41j0ODMmSNJ9+CGUQQQaW0Iew/t6EIuA6gmGp1XOS1EHTymsgsuO F7h308Jj+u4yVCBS56taleWDnjL6Sf8cTkZMNKwokuQqZ9xuXrTavplLY02VbtaQzExK5Nn w/G45UtGqVLAtdF0hs9zQEk8zh48r664hhljO/ks/cD/t1b/CnL2W8F6FZXuHNpTqi6mnMx vcO9NqdEjcDPwcVucvfZI/5Bu4DulkT2UvwRIDYknQ+1q5Sgoq8rIwVRJmqxQGs0RnM1y14 tRf02e6IHbqr3hsm+TIuKYu1WgJG0OPzTza/eDVX/zvQH705Rs4TebJNBCgItg2BVF6dg2G gbI5D2Il6zkhlqk/ph X-QQ-XMRINFO: MPJ6Tf5t3I/ylTmHUqvI8+Wpn+Gzalws3A== X-QQ-RECHKSPAM: 0 The duty cycle boundary checks in clk_rcg2_set_duty_cycle() use integer division to compare the 2d value against hardware limits: if ((d / 2) > (n - m)) d =3D (n - m) * 2; else if ((d / 2) < (m / 2)) d =3D m; When d is odd, d/2 truncates, allowing values one beyond the hardware maximum to pass. For example with n=3D7680, m=3D1, requesting 99.995% duty: d =3D 15359 (raw 2d value) d / 2 =3D 7679 (truncated) n - m =3D 7679 7679 > 7679 =E2=86=92 false, check passes But d=3D15359 exceeds the hardware limit of 2*(n-m)=3D15358. Writing this invalid value causes the RCG to fail its configuration update, the CMD_UPDATE bit never clears, and the clock output stops entirely. The initial D value in __clk_rcg2_configure_mnd() correctly uses direct comparison without division: d_val =3D clamp_t(u32, d_val, f->m, 2 * (f->n - f->m)); Align set_duty_cycle() with the same bounds by comparing directly: if (d > (n - m) * 2) else if (d < m) Fixes: 7f891faf596e ("clk: qcom: clk-rcg2: Add support for duty-cycle for R= CG") Signed-off-by: Xilin Wu Reviewed-by: Konrad Dybcio --- drivers/clk/qcom/clk-rcg2.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c index 732f34629ea2..153d2058c2a9 100644 --- a/drivers/clk/qcom/clk-rcg2.c +++ b/drivers/clk/qcom/clk-rcg2.c @@ -814,9 +814,9 @@ static int clk_rcg2_set_duty_cycle(struct clk_hw *hw, s= truct clk_duty *duty) */ d =3D clamp_val(d, 1, mask); =20 - if ((d / 2) > (n - m)) + if (d > (n - m) * 2) d =3D (n - m) * 2; - else if ((d / 2) < (m / 2)) + else if (d < m) d =3D m; =20 not2d =3D ~d & mask; --=20 2.53.0