From nobody Mon Apr 6 13:30:40 2026 Received: from mail.cjdns.fr (mail.cjdns.fr [5.135.140.105]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 94AB72EA171; Sat, 4 Apr 2026 18:36:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=5.135.140.105 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775327807; cv=none; b=LGwE6qW5IeF7C4xetP49BsR/dqd6gDmNLnn6Ug5z4xKXFIyBeJKaBmahnk1nzhzfOCmy91yonefS4xZy5S9rOQ3deUgXXjq/KEt+r5MSu+oLF2QQU+44kLRG41l5BEeMdTtw0dTGrX7lTJ0Fq/nLvXi7iEGXFOl5j9T7rMsALP8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775327807; c=relaxed/simple; bh=O3z31uVT+Dfd8j0b4hkRpmwYzvLPn03LuNW3yKqjl40=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=onD1a2Ny6C4eicvPlBe8br6BMyB5DZImMyAZVWPSqg+Um4cj7aG1nBINxc0sRy0Xe2JucwqQP0qr0OLxSLf11ICvpfyWGHZU1jFS4l3sh4wO+LJ9JgCoypgKbuBx/2W/4/8pyQfVqXk/ZUH2R6rit6moqmECNqZhPrkQkj6jhOo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=cjdns.fr; spf=none smtp.mailfrom=cjdns.fr; dkim=pass (2048-bit key) header.d=cjdns.fr header.i=@cjdns.fr header.b=Rn6Gb5QX; arc=none smtp.client-ip=5.135.140.105 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=cjdns.fr Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=cjdns.fr Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=cjdns.fr header.i=@cjdns.fr header.b="Rn6Gb5QX" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id B559418DE45; Sat, 4 Apr 2026 20:29:06 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cjdns.fr; s=dkim; t=1775327350; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=GdKZudBiZWRmnj2Q8xLAe5Ktsw/srDvDPRU3HuRREMc=; b=Rn6Gb5QXZSL5zhyytefJst9A+Qdw6SWvJs967M8kEw+/W/uBKhTtX5UFzfWrzsiVI2Cmr5 q2WzVV8YyKZOZnAFnIWRS7krVGWY7bVY5/dFEWlIsVSY5cI2y0T7uJFlqqDKwKOsM0yXXC inkkhr6TECuK3HTDrmQlX+phlU0seQwBtDrY/b7T3FkeGvVGIbWNBxwAYDrmxJ1MmYvLlg w6rswPBuSY3bWcVfAarnsNPKTDRLH9nG0Ws4BMiFPqXj62yLULL/YiOjyy/T2wnbCywJ6f 2cNshIo1YlZ4+0ijHEyEJ8J31CQ8H/VGOiO1rsRRHy79hOmORl/MaLsicsrXRg== From: Caleb James DeLisle To: linux-pci@vger.kernel.org Cc: linux-mips@vger.kernel.org, naseefkm@gmail.com, ryder.lee@mediatek.com, helgaas@kernel.org, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, ansuelsmth@gmail.com, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Caleb James DeLisle Subject: [PATCH v4 2/2] PCI: mediatek: Add support for EcoNet EN7528 SoC Date: Sat, 4 Apr 2026 18:28:54 +0000 Message-Id: <20260404182854.2183651-3-cjd@cjdns.fr> In-Reply-To: <20260404182854.2183651-1-cjd@cjdns.fr> References: <20260404182854.2183651-1-cjd@cjdns.fr> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" Add support for the PCIe present on the EcoNet EN7528 (and EN751221) SoCs. These SoCs have a mix of Gen1 and Gen2 capable ports, but the Gen2 ports require re-training after startup. Co-developed-by: Ahmed Naseef Signed-off-by: Ahmed Naseef Signed-off-by: Caleb James DeLisle --- drivers/pci/controller/Kconfig | 2 +- drivers/pci/controller/pcie-mediatek.c | 133 +++++++++++++++++++++++++ 2 files changed, 134 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig index 686349e09cd3..5808d5e407fd 100644 --- a/drivers/pci/controller/Kconfig +++ b/drivers/pci/controller/Kconfig @@ -209,7 +209,7 @@ config PCI_MVEBU =20 config PCIE_MEDIATEK tristate "MediaTek PCIe controller" - depends on ARCH_AIROHA || ARCH_MEDIATEK || COMPILE_TEST + depends on ARCH_AIROHA || ARCH_MEDIATEK || ECONET || COMPILE_TEST depends on OF depends on PCI_MSI select IRQ_MSI_LIB diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controlle= r/pcie-mediatek.c index 75722524fe74..915a35825ce1 100644 --- a/drivers/pci/controller/pcie-mediatek.c +++ b/drivers/pci/controller/pcie-mediatek.c @@ -7,6 +7,7 @@ * Honghui Zhang */ =20 +#include #include #include #include @@ -14,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -77,6 +79,7 @@ =20 #define PCIE_CONF_VEND_ID 0x100 #define PCIE_CONF_DEVICE_ID 0x102 +#define PCIE_CONF_REV_CLASS 0x104 #define PCIE_CONF_CLASS_ID 0x106 =20 #define PCIE_INT_MASK 0x420 @@ -89,6 +92,11 @@ #define MSI_MASK BIT(23) #define MTK_MSI_IRQS_NUM 32 =20 +#define EN7528_HOST_MODE 0x00804201 +#define EN7528_LINKUP_REG 0x50 +#define EN7528_RC0_LINKUP BIT(1) +#define EN7528_RC1_LINKUP BIT(2) + #define PCIE_AHB_TRANS_BASE0_L 0x438 #define PCIE_AHB_TRANS_BASE0_H 0x43c #define AHB2PCIE_SIZE(x) ((x) & GENMASK(4, 0)) @@ -148,12 +156,15 @@ struct mtk_pcie_port; * @MTK_PCIE_FIX_DEVICE_ID: host's device ID needed to be fixed * @MTK_PCIE_NO_MSI: Bridge has no MSI support, and relies on an external = block * @MTK_PCIE_SKIP_RSTB: Skip calling RSTB bits on PCIe probe + * @MTK_PCIE_RETRAIN: Re-train link to bridge after startup because some + * Gen2-capable devices start as Gen1. */ enum mtk_pcie_quirks { MTK_PCIE_FIX_CLASS_ID =3D BIT(0), MTK_PCIE_FIX_DEVICE_ID =3D BIT(1), MTK_PCIE_NO_MSI =3D BIT(2), MTK_PCIE_SKIP_RSTB =3D BIT(3), + MTK_PCIE_RETRAIN =3D BIT(4), }; =20 /** @@ -753,6 +764,80 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_po= rt *port) return 0; } =20 +static int mtk_pcie_startup_port_en7528(struct mtk_pcie_port *port) +{ + struct mtk_pcie *pcie =3D port->pcie; + struct pci_host_bridge *host =3D pci_host_bridge_from_priv(pcie); + struct resource *mem =3D NULL; + struct resource_entry *entry; + u32 val, link_mask; + int err; + + entry =3D resource_list_first_type(&host->windows, IORESOURCE_MEM); + if (entry) + mem =3D entry->res; + if (!mem) + return -EINVAL; + + if (!pcie->cfg) { + dev_err(pcie->dev, "EN7528: pciecfg syscon not available\n"); + return -EINVAL; + } + + /* Assert all reset signals */ + writel(0, port->base + PCIE_RST_CTRL); + + /* + * Enable PCIe link down reset, if link status changed from link up to + * link down, this will reset MAC control registers and configuration + * space. + */ + writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL); + + msleep(PCIE_T_PVPERL_MS); + + /* De-assert PHY, PE, PIPE, MAC and configuration reset */ + val =3D readl(port->base + PCIE_RST_CTRL); + val |=3D PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB | + PCIE_MAC_SRSTB | PCIE_CRSTB; + writel(val, port->base + PCIE_RST_CTRL); + + writel(PCIE_CLASS_CODE | PCIE_REVISION_ID, + port->base + PCIE_CONF_REV_CLASS); + writel(EN7528_HOST_MODE, port->base); + + link_mask =3D (port->slot =3D=3D 0) ? EN7528_RC0_LINKUP : EN7528_RC1_LINK= UP; + + /* 100ms timeout value should be enough for Gen1/2 training */ + err =3D regmap_read_poll_timeout(pcie->cfg, EN7528_LINKUP_REG, val, + !!(val & link_mask), 20, + PCI_PM_D3COLD_WAIT * USEC_PER_MSEC); + if (err) { + dev_err(pcie->dev, "EN7528: port%d link timeout\n", port->slot); + return -ETIMEDOUT; + } + + /* Activate INTx interrupts */ + val =3D readl(port->base + PCIE_INT_MASK); + val &=3D ~INTX_MASK; + writel(val, port->base + PCIE_INT_MASK); + + if (IS_ENABLED(CONFIG_PCI_MSI)) + mtk_pcie_enable_msi(port); + + /* Set AHB to PCIe translation windows */ + val =3D lower_32_bits(mem->start) | + AHB2PCIE_SIZE(fls(resource_size(mem))); + writel(val, port->base + PCIE_AHB_TRANS_BASE0_L); + + val =3D upper_32_bits(mem->start); + writel(val, port->base + PCIE_AHB_TRANS_BASE0_H); + + writel(WIN_ENABLE, port->base + PCIE_AXI_WINDOW0); + + return 0; +} + static void __iomem *mtk_pcie_map_bus(struct pci_bus *bus, unsigned int devfn, int where) { @@ -1149,6 +1234,46 @@ static int mtk_pcie_probe(struct platform_device *pd= ev) if (err) goto put_resources; =20 + /* EN7528 PCIe initially comes up as Gen1 even if Gen2 is supported. + * The cannonical way to achieve Gen2 is to re-train the link + * immediately after setup. However, to save a lot of duplicated code + * we use pcie_retrain_link() which is usable once we have the pci_dev + * struct for the bridge, i.e. after pci_host_probe(). */ + if (pcie->soc->quirks & MTK_PCIE_RETRAIN) { + int slot =3D of_get_pci_domain_nr(dev->of_node); + struct pci_dev *rc =3D NULL; + int ret =3D -ENOENT; + + if (slot >=3D 0) + rc =3D pci_get_slot(host->bus, PCI_DEVFN(slot, 0)); + + if (rc) { + ret =3D -EOPNOTSUPP; + + /* pcie_retrain_link() is not an exported symbol but + * this driver supports being built as a loadable + * module. Someone using this on an EN7528 should make + * it builtin, or accept Gen1 PCI. */ +#if IS_BUILTIN(CONFIG_PCIE_MEDIATEK) + ret =3D pcie_retrain_link(rc, true); +#endif + } + + if (ret) { + dev_info(dev, "port%d failed to retrain %pe\n", slot, + ERR_PTR(ret)); + } else { + u16 lnksta; + u32 speed; + + pcie_capability_read_word(rc, PCI_EXP_LNKSTA, &lnksta); + speed =3D lnksta & PCI_EXP_LNKSTA_CLS; + + dev_info(dev, "port%d link retrained, speed %s\n", slot, + pci_speed_string(pcie_link_speed[speed])); + } + } + return 0; =20 put_resources: @@ -1264,8 +1389,16 @@ static const struct mtk_pcie_soc mtk_pcie_soc_mt7629= =3D { .quirks =3D MTK_PCIE_FIX_CLASS_ID | MTK_PCIE_FIX_DEVICE_ID, }; =20 +static const struct mtk_pcie_soc mtk_pcie_soc_en7528 =3D { + .ops =3D &mtk_pcie_ops_v2, + .startup =3D mtk_pcie_startup_port_en7528, + .setup_irq =3D mtk_pcie_setup_irq, + .quirks =3D MTK_PCIE_RETRAIN, +}; + static const struct of_device_id mtk_pcie_ids[] =3D { { .compatible =3D "airoha,an7583-pcie", .data =3D &mtk_pcie_soc_an7583 }, + { .compatible =3D "econet,en7528-pcie", .data =3D &mtk_pcie_soc_en7528 }, { .compatible =3D "mediatek,mt2701-pcie", .data =3D &mtk_pcie_soc_v1 }, { .compatible =3D "mediatek,mt7623-pcie", .data =3D &mtk_pcie_soc_v1 }, { .compatible =3D "mediatek,mt2712-pcie", .data =3D &mtk_pcie_soc_mt2712 = }, --=20 2.39.5