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Sat, 04 Apr 2026 01:17:38 -0700 (PDT) Received: from hu-krichai-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-c76c657dfb7sm6786408a12.24.2026.04.04.01.17.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 04 Apr 2026 01:17:38 -0700 (PDT) From: Krishna Chaitanya Chundru Date: Sat, 04 Apr 2026 13:47:20 +0530 Subject: [PATCH v4 3/3] PCI: qcom: Program T_POWER_ON Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260404-t_power_on_fux-v4-3-2891391177f4@oss.qualcomm.com> References: <20260404-t_power_on_fux-v4-0-2891391177f4@oss.qualcomm.com> In-Reply-To: <20260404-t_power_on_fux-v4-0-2891391177f4@oss.qualcomm.com> To: Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Jingoo Han Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, mayank.rana@oss.qualcomm.com, quic_vbadigan@quicinc.com, Krishna Chaitanya Chundru X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1775290642; l=2508; i=krishna.chundru@oss.qualcomm.com; s=20230907; h=from:subject:message-id; bh=eLlhRSUUKQzMD4xw0eb0Pj6hBFVgOdEaGYz5rmdOD0w=; b=FoSqAxwrZC+d2vwgX0vXTnnO4tPPZUWaJ/+SnJjtKhp10P54ksl61uq7Bio4H4ZaPODY184qU uXcFi/zk+gtBjD3aKb7GyEFrr9nbEPEMfcr8roD85aBqaFVuZML5aIg X-Developer-Key: i=krishna.chundru@oss.qualcomm.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-Authority-Analysis: v=2.4 cv=ari/yCZV c=1 sm=1 tr=0 ts=69d0c923 cx=c_pps a=oF/VQ+ItUULfLr/lQ2/icg==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=wXczfBY3881IDOTkNB0A:9 a=QEXdDO2ut3YA:10 a=3WC7DwWrALyhR5TkjVHa:22 X-Proofpoint-ORIG-GUID: h1Fsxyz34l_oeiGm9Gwe-7va6QzsnwUp X-Proofpoint-GUID: h1Fsxyz34l_oeiGm9Gwe-7va6QzsnwUp X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDA0MDA3MiBTYWx0ZWRfX3tifrD5UQwgs h3cM4YnjTrskTXqM0LionI7HR0MKqxvEdX1wrtFLfBoDmCvo8DB5jtPwmLyVrU5AHRQq6qNcN/w iep4/Vf+DKdIMVDGl3UKJY7K9OBiKRCVEs61kl4Dl4q4yWvoJfpumTLreS8WodS0JOhr/NBw4lr bidUOyVggC3scV3UYcWNPw4Igk8/E9LmYK96gQlWyea78oymUXhRK5A0dDOUuHNBRPH5GyDkU+c eLEJgOxkvG3oYJ/Ld063FS64khSOJVLaYRc+Fx/d1QYvl3rFiJYp4sTDk4RsTVdoP50KV4xPRra 4iE4XeZ2bR5Irabv0zsgs7M8ZcOs1cJq+4qvQIJ/pFT6LY4qQjzaT1wVDSqAEypgmXfdDVnpNqf 0K2c4XagwbPk6JhylLQvQfM1jPjOjgciOusojEJrGs6Z+kd1CbXrRTgDJY1dD5el9gF0zBHTkkF q8vw4icidX0J0cWGXbA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-03_07,2026-04-03_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 suspectscore=0 clxscore=1015 malwarescore=0 phishscore=0 lowpriorityscore=0 bulkscore=0 priorityscore=1501 spamscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2604040072 Some platforms have incorrect T_POWER_ON value programmed in hardware. Generally these will be corrected by bootloaders, but not all targets support bootloaders to program correct values due to that LTR_L1.2_THRESHOLD value calculated by aspm driver can be wrong, which can result in improper L1.2 exit behavior and if AER happens to be supported and enabled, the error may be *reported* via AER. Parse "t-power-on-us" property from each root port node and program them as part of host initialization using dw_pcie_program_t_power_on() before link training. This property in added to the dtschema here[1]. Signed-off-by: Krishna Chaitanya Chundru Link[1]: https://lore.kernel.org/all/20260205093346.667898-1-krishna.chundr= u@oss.qualcomm.com/ --- drivers/pci/controller/dwc/pcie-qcom.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controlle= r/dwc/pcie-qcom.c index 67a16af69ddc75fca1b123e70715e692a91a9135..a8f82f860c08fe2eabad2c0eed5= 41b8dd121215e 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -269,6 +269,7 @@ struct qcom_pcie_perst { struct qcom_pcie_port { struct list_head list; struct phy *phy; + u32 l1ss_t_power_on; struct list_head perst; }; =20 @@ -1283,6 +1284,14 @@ static int qcom_pcie_phy_power_on(struct qcom_pcie *= pcie) return 0; } =20 +static void qcom_pcie_configure_ports(struct qcom_pcie *pcie) +{ + struct qcom_pcie_port *port; + + list_for_each_entry(port, &pcie->ports, list) + dw_pcie_program_t_power_on(pcie->pci, port->l1ss_t_power_on); +} + static int qcom_pcie_host_init(struct dw_pcie_rp *pp) { struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); @@ -1317,6 +1326,8 @@ static int qcom_pcie_host_init(struct dw_pcie_rp *pp) dw_pcie_remove_capability(pcie->pci, PCI_CAP_ID_MSIX); dw_pcie_remove_ext_capability(pcie->pci, PCI_EXT_CAP_ID_DPC); =20 + qcom_pcie_configure_ports(pcie); + qcom_pcie_perst_deassert(pcie); =20 if (pcie->cfg->ops->config_sid) { @@ -1759,6 +1770,9 @@ static int qcom_pcie_parse_port(struct qcom_pcie *pci= e, struct device_node *node if (ret) return ret; =20 + /* TODO: Need to move to dwc once multi root port support is added. */ + of_property_read_u32(node, "t-power-on-us", &port->l1ss_t_power_on); + port->phy =3D phy; INIT_LIST_HEAD(&port->list); list_add_tail(&port->list, &pcie->ports); --=20 2.34.1