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Sat, 04 Apr 2026 01:17:34 -0700 (PDT) Received: from hu-krichai-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-c76c657dfb7sm6786408a12.24.2026.04.04.01.17.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 04 Apr 2026 01:17:34 -0700 (PDT) From: Krishna Chaitanya Chundru Date: Sat, 04 Apr 2026 13:47:19 +0530 Subject: [PATCH v4 2/3] PCI: dwc: Add helper to Program T_POWER_ON Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260404-t_power_on_fux-v4-2-2891391177f4@oss.qualcomm.com> References: <20260404-t_power_on_fux-v4-0-2891391177f4@oss.qualcomm.com> In-Reply-To: <20260404-t_power_on_fux-v4-0-2891391177f4@oss.qualcomm.com> To: Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Jingoo Han Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, mayank.rana@oss.qualcomm.com, quic_vbadigan@quicinc.com, Krishna Chaitanya Chundru , Shawn Lin X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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This value is used by the ASPM driver to compute the LTR_L1.2_THRESHOLD. Currently, some controllers exposes T_POWER_ON value of zero in the L1SS capability registers, leading to incorrect LTR_L1.2_THRESHOLD calculations, which can result in improper L1.2 exit behavior and if AER happens to be supported and enabled, the error may be *reported* via AER. Add a helper to override T_POWER_ON value by the DWC controller drivers. Tested-by: Shawn Lin Reviewed-by: Shawn Lin Signed-off-by: Krishna Chaitanya Chundru --- drivers/pci/controller/dwc/pcie-designware.c | 28 ++++++++++++++++++++++++= ++++ drivers/pci/controller/dwc/pcie-designware.h | 1 + 2 files changed, 29 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/con= troller/dwc/pcie-designware.c index 5741c09dde7f40487c6da6dfd66f7c8d96a74259..6289329ef2b2a4ac9264d1c6cb5= ea4e88c261634 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -1249,6 +1249,34 @@ void dw_pcie_hide_unsupported_l1ss(struct dw_pcie *p= ci) dw_pcie_writel_dbi(pci, l1ss + PCI_L1SS_CAP, l1ss_cap); } =20 +/* TODO: Need to handle multi root ports */ +void dw_pcie_program_t_power_on(struct dw_pcie *pci, u16 t_power_on) +{ + u8 scale, value; + u16 offset; + u32 val; + + if (!t_power_on) + return; + + offset =3D dw_pcie_find_ext_capability(pci, PCI_EXT_CAP_ID_L1SS); + if (!offset) + return; + + pcie_encode_t_power_on(t_power_on, &scale, &value); + + dw_pcie_dbi_ro_wr_en(pci); + + val =3D readl(pci->dbi_base + offset + PCI_L1SS_CAP); + val &=3D ~(PCI_L1SS_CAP_P_PWR_ON_SCALE | PCI_L1SS_CAP_P_PWR_ON_VALUE); + FIELD_MODIFY(PCI_L1SS_CAP_P_PWR_ON_SCALE, &val, scale); + FIELD_MODIFY(PCI_L1SS_CAP_P_PWR_ON_VALUE, &val, value); + + writel(val, pci->dbi_base + offset + PCI_L1SS_CAP); + + dw_pcie_dbi_ro_wr_dis(pci); +} + void dw_pcie_setup(struct dw_pcie *pci) { u32 val; diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/con= troller/dwc/pcie-designware.h index ae6389dd9caa5c27690f998d58729130ea863984..da67beece3f11e33d9a1937fa23= d443feea3bbc7 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -602,6 +602,7 @@ int dw_pcie_prog_ep_inbound_atu(struct dw_pcie *pci, u8= func_no, int index, u8 bar, size_t size); void dw_pcie_disable_atu(struct dw_pcie *pci, u32 dir, int index); void dw_pcie_hide_unsupported_l1ss(struct dw_pcie *pci); +void dw_pcie_program_t_power_on(struct dw_pcie *pci, u16 t_power_on); void dw_pcie_setup(struct dw_pcie *pci); void dw_pcie_iatu_detect(struct dw_pcie *pci); int dw_pcie_edma_detect(struct dw_pcie *pci); --=20 2.34.1