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Sat, 04 Apr 2026 01:17:30 -0700 (PDT) Received: from hu-krichai-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-c76c657dfb7sm6786408a12.24.2026.04.04.01.17.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 04 Apr 2026 01:17:30 -0700 (PDT) From: Krishna Chaitanya Chundru Date: Sat, 04 Apr 2026 13:47:18 +0530 Subject: [PATCH v4 1/3] PCI/ASPM: Add helper to encode L1SS T_POWER_ON fields Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260404-t_power_on_fux-v4-1-2891391177f4@oss.qualcomm.com> References: <20260404-t_power_on_fux-v4-0-2891391177f4@oss.qualcomm.com> In-Reply-To: <20260404-t_power_on_fux-v4-0-2891391177f4@oss.qualcomm.com> To: Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Jingoo Han Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, mayank.rana@oss.qualcomm.com, quic_vbadigan@quicinc.com, Krishna Chaitanya Chundru , Shawn Lin X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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This helper can be used by the controller drivers to change the default/wrong value of T_POWER_ON in L1ss capability register to avoid incorrect calculation of LTR_L1.2_THRESHOLD value. The helper converts a T_POWER_ON time specified in microseconds into the appropriate scale/value encoding defined by the PCIe spec r7.0, sec 7.8.3.2. Values that exceed the maximum encodable range are clamped to the largest representable encoding. Tested-by: Shawn Lin Reviewed-by: Shawn Lin Signed-off-by: Krishna Chaitanya Chundru --- drivers/pci/pci.h | 2 ++ drivers/pci/pcie/aspm.c | 40 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 42 insertions(+) diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 13d998fbacce6698514d92500dfea03cc562cdc2..48964602d802e114a6a2481df3f= b75d9e178a31b 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -1105,6 +1105,7 @@ void pcie_aspm_pm_state_change(struct pci_dev *pdev, = bool locked); void pcie_aspm_powersave_config_link(struct pci_dev *pdev); void pci_configure_ltr(struct pci_dev *pdev); void pci_bridge_reconfigure_ltr(struct pci_dev *pdev); +void pcie_encode_t_power_on(u16 t_power_on_us, u8 *scale, u8 *value); #else static inline void pcie_aspm_remove_cap(struct pci_dev *pdev, u32 lnkcap) = { } static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { } @@ -1113,6 +1114,7 @@ static inline void pcie_aspm_pm_state_change(struct p= ci_dev *pdev, bool locked) static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) {= } static inline void pci_configure_ltr(struct pci_dev *pdev) { } static inline void pci_bridge_reconfigure_ltr(struct pci_dev *pdev) { } +static inline void pcie_encode_t_power_on(u16 t_power_on_us, u8 *scale, u8= *value) { } #endif =20 #ifdef CONFIG_PCIE_ECRC diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c index 21f5d23e0b61bd7e1163cc869fe9356d1ab87b34..879d7ecddf8d6430c49f31c88a7= 5d5c6e74015d6 100644 --- a/drivers/pci/pcie/aspm.c +++ b/drivers/pci/pcie/aspm.c @@ -525,6 +525,46 @@ static u32 calc_l12_pwron(struct pci_dev *pdev, u32 sc= ale, u32 val) return 0; } =20 +/** + * pcie_encode_t_power_on - Encode T_POWER_ON into scale and value fields + * @t_power_on_us: T_POWER_ON time in microseconds + * @scale: Encoded T_POWER_ON Scale (0..2) + * @value: Encoded T_POWER_ON Value + * + * T_POWER_ON is encoded as: + * T_POWER_ON(us) =3D scale_unit(us) * value + * + * where scale_unit is selected by @scale: + * 0: 2us + * 1: 10us + * 2: 100us + * + * If @t_power_on_us exceeds the maximum representable value, the result + * is clamped to the largest encodable T_POWER_ON. + * + * See PCIe r7.0, sec 7.8.3.2. + */ +void pcie_encode_t_power_on(u16 t_power_on_us, u8 *scale, u8 *value) +{ + u8 maxv =3D FIELD_MAX(PCI_L1SS_CAP_P_PWR_ON_VALUE); + + /* T_POWER_ON_Value ("value") is a 5-bit field with max value of 31. */ + if (t_power_on_us <=3D 2 * maxv) { + *scale =3D 0; /* Value times 2us */ + *value =3D DIV_ROUND_UP(t_power_on_us, 2); + } else if (t_power_on_us <=3D 10 * maxv) { + *scale =3D 1; /* Value times 10us */ + *value =3D DIV_ROUND_UP(t_power_on_us, 10); + } else if (t_power_on_us <=3D 100 * maxv) { + *scale =3D 2; /* value times 100us */ + *value =3D DIV_ROUND_UP(t_power_on_us, 100); + } else { + *scale =3D 2; + *value =3D maxv; + } +} +EXPORT_SYMBOL(pcie_encode_t_power_on); + /* * Encode an LTR_L1.2_THRESHOLD value for the L1 PM Substates Control 1 * register. Ports enter L1.2 when the most recent LTR value is greater --=20 2.34.1