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Sat, 04 Apr 2026 01:17:30 -0700 (PDT) Received: from hu-krichai-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-c76c657dfb7sm6786408a12.24.2026.04.04.01.17.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 04 Apr 2026 01:17:30 -0700 (PDT) From: Krishna Chaitanya Chundru Date: Sat, 04 Apr 2026 13:47:18 +0530 Subject: [PATCH v4 1/3] PCI/ASPM: Add helper to encode L1SS T_POWER_ON fields Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260404-t_power_on_fux-v4-1-2891391177f4@oss.qualcomm.com> References: <20260404-t_power_on_fux-v4-0-2891391177f4@oss.qualcomm.com> In-Reply-To: <20260404-t_power_on_fux-v4-0-2891391177f4@oss.qualcomm.com> To: Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Jingoo Han Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, mayank.rana@oss.qualcomm.com, quic_vbadigan@quicinc.com, Krishna Chaitanya Chundru , Shawn Lin X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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This helper can be used by the controller drivers to change the default/wrong value of T_POWER_ON in L1ss capability register to avoid incorrect calculation of LTR_L1.2_THRESHOLD value. The helper converts a T_POWER_ON time specified in microseconds into the appropriate scale/value encoding defined by the PCIe spec r7.0, sec 7.8.3.2. Values that exceed the maximum encodable range are clamped to the largest representable encoding. Tested-by: Shawn Lin Reviewed-by: Shawn Lin Signed-off-by: Krishna Chaitanya Chundru --- drivers/pci/pci.h | 2 ++ drivers/pci/pcie/aspm.c | 40 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 42 insertions(+) diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 13d998fbacce6698514d92500dfea03cc562cdc2..48964602d802e114a6a2481df3f= b75d9e178a31b 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -1105,6 +1105,7 @@ void pcie_aspm_pm_state_change(struct pci_dev *pdev, = bool locked); void pcie_aspm_powersave_config_link(struct pci_dev *pdev); void pci_configure_ltr(struct pci_dev *pdev); void pci_bridge_reconfigure_ltr(struct pci_dev *pdev); +void pcie_encode_t_power_on(u16 t_power_on_us, u8 *scale, u8 *value); #else static inline void pcie_aspm_remove_cap(struct pci_dev *pdev, u32 lnkcap) = { } static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { } @@ -1113,6 +1114,7 @@ static inline void pcie_aspm_pm_state_change(struct p= ci_dev *pdev, bool locked) static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) {= } static inline void pci_configure_ltr(struct pci_dev *pdev) { } static inline void pci_bridge_reconfigure_ltr(struct pci_dev *pdev) { } +static inline void pcie_encode_t_power_on(u16 t_power_on_us, u8 *scale, u8= *value) { } #endif =20 #ifdef CONFIG_PCIE_ECRC diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c index 21f5d23e0b61bd7e1163cc869fe9356d1ab87b34..879d7ecddf8d6430c49f31c88a7= 5d5c6e74015d6 100644 --- a/drivers/pci/pcie/aspm.c +++ b/drivers/pci/pcie/aspm.c @@ -525,6 +525,46 @@ static u32 calc_l12_pwron(struct pci_dev *pdev, u32 sc= ale, u32 val) return 0; } =20 +/** + * pcie_encode_t_power_on - Encode T_POWER_ON into scale and value fields + * @t_power_on_us: T_POWER_ON time in microseconds + * @scale: Encoded T_POWER_ON Scale (0..2) + * @value: Encoded T_POWER_ON Value + * + * T_POWER_ON is encoded as: + * T_POWER_ON(us) =3D scale_unit(us) * value + * + * where scale_unit is selected by @scale: + * 0: 2us + * 1: 10us + * 2: 100us + * + * If @t_power_on_us exceeds the maximum representable value, the result + * is clamped to the largest encodable T_POWER_ON. + * + * See PCIe r7.0, sec 7.8.3.2. + */ +void pcie_encode_t_power_on(u16 t_power_on_us, u8 *scale, u8 *value) +{ + u8 maxv =3D FIELD_MAX(PCI_L1SS_CAP_P_PWR_ON_VALUE); + + /* T_POWER_ON_Value ("value") is a 5-bit field with max value of 31. */ + if (t_power_on_us <=3D 2 * maxv) { + *scale =3D 0; /* Value times 2us */ + *value =3D DIV_ROUND_UP(t_power_on_us, 2); + } else if (t_power_on_us <=3D 10 * maxv) { + *scale =3D 1; /* Value times 10us */ + *value =3D DIV_ROUND_UP(t_power_on_us, 10); + } else if (t_power_on_us <=3D 100 * maxv) { + *scale =3D 2; /* value times 100us */ + *value =3D DIV_ROUND_UP(t_power_on_us, 100); + } else { + *scale =3D 2; + *value =3D maxv; + } +} +EXPORT_SYMBOL(pcie_encode_t_power_on); + /* * Encode an LTR_L1.2_THRESHOLD value for the L1 PM Substates Control 1 * register. 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Sat, 04 Apr 2026 01:17:34 -0700 (PDT) Received: from hu-krichai-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-c76c657dfb7sm6786408a12.24.2026.04.04.01.17.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 04 Apr 2026 01:17:34 -0700 (PDT) From: Krishna Chaitanya Chundru Date: Sat, 04 Apr 2026 13:47:19 +0530 Subject: [PATCH v4 2/3] PCI: dwc: Add helper to Program T_POWER_ON Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260404-t_power_on_fux-v4-2-2891391177f4@oss.qualcomm.com> References: <20260404-t_power_on_fux-v4-0-2891391177f4@oss.qualcomm.com> In-Reply-To: <20260404-t_power_on_fux-v4-0-2891391177f4@oss.qualcomm.com> To: Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Jingoo Han Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, mayank.rana@oss.qualcomm.com, quic_vbadigan@quicinc.com, Krishna Chaitanya Chundru , Shawn Lin X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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This value is used by the ASPM driver to compute the LTR_L1.2_THRESHOLD. Currently, some controllers exposes T_POWER_ON value of zero in the L1SS capability registers, leading to incorrect LTR_L1.2_THRESHOLD calculations, which can result in improper L1.2 exit behavior and if AER happens to be supported and enabled, the error may be *reported* via AER. Add a helper to override T_POWER_ON value by the DWC controller drivers. Tested-by: Shawn Lin Reviewed-by: Shawn Lin Signed-off-by: Krishna Chaitanya Chundru --- drivers/pci/controller/dwc/pcie-designware.c | 28 ++++++++++++++++++++++++= ++++ drivers/pci/controller/dwc/pcie-designware.h | 1 + 2 files changed, 29 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/con= troller/dwc/pcie-designware.c index 5741c09dde7f40487c6da6dfd66f7c8d96a74259..6289329ef2b2a4ac9264d1c6cb5= ea4e88c261634 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -1249,6 +1249,34 @@ void dw_pcie_hide_unsupported_l1ss(struct dw_pcie *p= ci) dw_pcie_writel_dbi(pci, l1ss + PCI_L1SS_CAP, l1ss_cap); } =20 +/* TODO: Need to handle multi root ports */ +void dw_pcie_program_t_power_on(struct dw_pcie *pci, u16 t_power_on) +{ + u8 scale, value; + u16 offset; + u32 val; + + if (!t_power_on) + return; + + offset =3D dw_pcie_find_ext_capability(pci, PCI_EXT_CAP_ID_L1SS); + if (!offset) + return; + + pcie_encode_t_power_on(t_power_on, &scale, &value); + + dw_pcie_dbi_ro_wr_en(pci); + + val =3D readl(pci->dbi_base + offset + PCI_L1SS_CAP); + val &=3D ~(PCI_L1SS_CAP_P_PWR_ON_SCALE | PCI_L1SS_CAP_P_PWR_ON_VALUE); + FIELD_MODIFY(PCI_L1SS_CAP_P_PWR_ON_SCALE, &val, scale); + FIELD_MODIFY(PCI_L1SS_CAP_P_PWR_ON_VALUE, &val, value); + + writel(val, pci->dbi_base + offset + PCI_L1SS_CAP); + + dw_pcie_dbi_ro_wr_dis(pci); +} + void dw_pcie_setup(struct dw_pcie *pci) { u32 val; diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/con= troller/dwc/pcie-designware.h index ae6389dd9caa5c27690f998d58729130ea863984..da67beece3f11e33d9a1937fa23= d443feea3bbc7 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -602,6 +602,7 @@ int dw_pcie_prog_ep_inbound_atu(struct dw_pcie *pci, u8= func_no, int index, u8 bar, size_t size); void dw_pcie_disable_atu(struct dw_pcie *pci, u32 dir, int index); void dw_pcie_hide_unsupported_l1ss(struct dw_pcie *pci); +void dw_pcie_program_t_power_on(struct dw_pcie *pci, u16 t_power_on); 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Sat, 04 Apr 2026 01:17:38 -0700 (PDT) Received: from hu-krichai-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-c76c657dfb7sm6786408a12.24.2026.04.04.01.17.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 04 Apr 2026 01:17:38 -0700 (PDT) From: Krishna Chaitanya Chundru Date: Sat, 04 Apr 2026 13:47:20 +0530 Subject: [PATCH v4 3/3] PCI: qcom: Program T_POWER_ON Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260404-t_power_on_fux-v4-3-2891391177f4@oss.qualcomm.com> References: <20260404-t_power_on_fux-v4-0-2891391177f4@oss.qualcomm.com> In-Reply-To: <20260404-t_power_on_fux-v4-0-2891391177f4@oss.qualcomm.com> To: Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Jingoo Han Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, mayank.rana@oss.qualcomm.com, quic_vbadigan@quicinc.com, Krishna Chaitanya Chundru X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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Generally these will be corrected by bootloaders, but not all targets support bootloaders to program correct values due to that LTR_L1.2_THRESHOLD value calculated by aspm driver can be wrong, which can result in improper L1.2 exit behavior and if AER happens to be supported and enabled, the error may be *reported* via AER. Parse "t-power-on-us" property from each root port node and program them as part of host initialization using dw_pcie_program_t_power_on() before link training. This property in added to the dtschema here[1]. Signed-off-by: Krishna Chaitanya Chundru Link[1]: https://lore.kernel.org/all/20260205093346.667898-1-krishna.chundr= u@oss.qualcomm.com/ --- drivers/pci/controller/dwc/pcie-qcom.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controlle= r/dwc/pcie-qcom.c index 67a16af69ddc75fca1b123e70715e692a91a9135..a8f82f860c08fe2eabad2c0eed5= 41b8dd121215e 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -269,6 +269,7 @@ struct qcom_pcie_perst { struct qcom_pcie_port { struct list_head list; struct phy *phy; + u32 l1ss_t_power_on; struct list_head perst; }; =20 @@ -1283,6 +1284,14 @@ static int qcom_pcie_phy_power_on(struct qcom_pcie *= pcie) return 0; } =20 +static void qcom_pcie_configure_ports(struct qcom_pcie *pcie) +{ + struct qcom_pcie_port *port; + + list_for_each_entry(port, &pcie->ports, list) + dw_pcie_program_t_power_on(pcie->pci, port->l1ss_t_power_on); +} + static int qcom_pcie_host_init(struct dw_pcie_rp *pp) { struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); @@ -1317,6 +1326,8 @@ static int qcom_pcie_host_init(struct dw_pcie_rp *pp) dw_pcie_remove_capability(pcie->pci, PCI_CAP_ID_MSIX); dw_pcie_remove_ext_capability(pcie->pci, PCI_EXT_CAP_ID_DPC); =20 + qcom_pcie_configure_ports(pcie); + qcom_pcie_perst_deassert(pcie); =20 if (pcie->cfg->ops->config_sid) { @@ -1759,6 +1770,9 @@ static int qcom_pcie_parse_port(struct qcom_pcie *pci= e, struct device_node *node if (ret) return ret; =20 + /* TODO: Need to move to dwc once multi root port support is added. */ + of_property_read_u32(node, "t-power-on-us", &port->l1ss_t_power_on); + port->phy =3D phy; INIT_LIST_HEAD(&port->list); list_add_tail(&port->list, &pcie->ports); --=20 2.34.1