From nobody Wed Jun 10 05:07:45 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B8CF43A875E; Sat, 4 Apr 2026 09:51:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775296273; cv=none; b=bJjEEAQm3LjVZKaO+OcwODkqc5oqyf9tdYssWMlxq8hbO8uZBDFVnOB/Hulfp7bsroF3Ef2seESu4/ro/fQYM55zmns/LcfOpXGzg9JvlSDfY5evT6olQkoV7WpTH1cC6tbcRRthq5M9phyFZmBs3Ap88t7qB8EDc7O87PKEO4I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775296273; c=relaxed/simple; bh=KQ8lsG+ZU1fa4Zfq1OtQatABJX25qxFvudXC4UWGJ0Y=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ANd6gYm2W3LMd2hAVIyW/xw4AneJ3omvKgoxT9IZcGo+GydaV4lvbVI0yS6QqWedPYYcE2/+OM2hIgMnxNQgJn78RQIQhvN0QayRkAySLHSadvJ8MzXX9QkW1eKwgFATOLWh4QbiGLVhtBnmXteDUo6Pbtxfb9MzXV3CN8pc3+A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=QBoCvbJr; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="QBoCvbJr" Received: by smtp.kernel.org (Postfix) with ESMTPS id 741B4C19425; Sat, 4 Apr 2026 09:51:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1775296273; bh=KQ8lsG+ZU1fa4Zfq1OtQatABJX25qxFvudXC4UWGJ0Y=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=QBoCvbJroDq84+L4VNdb7CpkUkIyHJgzNHsymOpWvKovpSMa2F1kvB29ZlOi/AI/2 TS2iYinqDjtaF6M3YwUPuiK1f9iVhGSGJQiaW2fUtaHtWcAy/2HQf32ekMWsO1ksrA vQ/Llv30ymDWRxQtCv5XJoGJ1FTC8SgXhkTjVpLOta2riLbNBn7ffzMqirBO4VJHaK LJ4dVGS+kUXah+zJtoa6ZVg6Gr09E0mJSY9zbSooRZUV4kuUN46A9tXZOdjOLAeUc1 7SFeY4Ua3md9UokdAL/XgUFsfb325CQXu0UCBqRQnX/JLVtqntIA/eqpssAZ0ipctd kVZK1WaCF7aug== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 64F68E88D94; Sat, 4 Apr 2026 09:51:13 +0000 (UTC) From: Joe Sandom via B4 Relay Date: Sat, 04 Apr 2026 10:50:54 +0100 Subject: [PATCH 1/5] arm64: dts: qcom: sm8550: add PCIe MHI register regions and port labels Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260404-rb5gen2-dts-v1-1-895f8fc494fc@axon.com> References: <20260404-rb5gen2-dts-v1-0-895f8fc494fc@axon.com> In-Reply-To: <20260404-rb5gen2-dts-v1-0-895f8fc494fc@axon.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Joe Sandom X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1775296270; l=2186; i=jsandom@axon.com; s=20260319; h=from:subject:message-id; bh=8wWHbLnW7l5BtOwjusH2UH9x4Bz7+MdlfIopte9jZIc=; b=/HR3+gbkZpZKc2hF6yjfI/Vn8tsYHQumElfWr1CIXbwGseLSsKQNu1500aTd35ZlhuMnb3zzL 6iniPJ0tl19BrvgjnoLC5a10bl9ArqefVJ/j+70NDdPlMM0Tr7wxhmq X-Developer-Key: i=jsandom@axon.com; a=ed25519; pk=Q/yflwj2WhkgBVTskrS9Vl5oScD0Bp3vTzDi+OxskTo= X-Endpoint-Received: by B4 Relay for jsandom@axon.com/20260319 with auth_id=687 X-Original-From: Joe Sandom Reply-To: jsandom@axon.com From: Joe Sandom Add the MHI register regions to the pcie0 and pcie1 controller nodes so that the MHI bus layer can access controller registers directly. Also add labels to the root port nodes (pcie0_port0, pcie1_port0) to allow board DTS files to reference them for adding endpoint devices to each pcie root port. Signed-off-by: Joe Sandom --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qco= m/sm8550.dtsi index 912525e9bca6f5e1cbb8887ee0bf9e39650dc4ff..d4caf4d00832d7f1e8f65bf2bc8= 73cddadc42168 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -1964,8 +1964,9 @@ pcie0: pcie@1c00000 { <0 0x60000000 0 0xf1d>, <0 0x60000f20 0 0xa8>, <0 0x60001000 0 0x1000>, - <0 0x60100000 0 0x100000>; - reg-names =3D "parf", "dbi", "elbi", "atu", "config"; + <0 0x60100000 0 0x100000>, + <0 0x01C03000 0 0x1000>; + reg-names =3D "parf", "dbi", "elbi", "atu", "config", "mhi"; #address-cells =3D <3>; #size-cells =3D <2>; ranges =3D <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, @@ -2092,7 +2093,7 @@ opp-16000000-3 { }; }; =20 - pcieport0: pcie@0 { + pcie0_port0: pcie@0 { device_type =3D "pci"; reg =3D <0x0 0x0 0x0 0x0 0x0>; bus-range =3D <0x01 0xff>; @@ -2138,8 +2139,9 @@ pcie1: pcie@1c08000 { <0x0 0x40000000 0x0 0xf1d>, <0x0 0x40000f20 0x0 0xa8>, <0x0 0x40001000 0x0 0x1000>, - <0x0 0x40100000 0x0 0x100000>; - reg-names =3D "parf", "dbi", "elbi", "atu", "config"; + <0x0 0x40100000 0x0 0x100000>, + <0x0 0x01C0B000 0x0 0x1000>; + reg-names =3D "parf", "dbi", "elbi", "atu", "config", "mhi"; #address-cells =3D <3>; #size-cells =3D <2>; ranges =3D <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, @@ -2288,7 +2290,7 @@ opp-32000000-4 { }; }; =20 - pcie@0 { + pcie1_port0: pcie@0 { device_type =3D "pci"; reg =3D <0x0 0x0 0x0 0x0 0x0>; bus-range =3D <0x01 0xff>; --=20 2.34.1 From nobody Wed Jun 10 05:07:45 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B8BE03A874E; Sat, 4 Apr 2026 09:51:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260404-rb5gen2-dts-v1-2-895f8fc494fc@axon.com> References: <20260404-rb5gen2-dts-v1-0-895f8fc494fc@axon.com> In-Reply-To: <20260404-rb5gen2-dts-v1-0-895f8fc494fc@axon.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Joe Sandom X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1775296270; l=718; i=jsandom@axon.com; s=20260319; h=from:subject:message-id; bh=J5wHGXLHT9ZEeK8mCO8+XsWDq4+eMfiE3/aGssrA40c=; b=8KhRPaMM/0TP0sqFFPcbk9SQSIB6QkEqGo2pUq0EVkwjG7L1cW2ahYbIaFpumWN7ALvoaApmB /hDYcxyfeqdBpSpyPAcPP2OnCB/hfZHBpzC7to3rDPCQldBstrpcEc9 X-Developer-Key: i=jsandom@axon.com; a=ed25519; pk=Q/yflwj2WhkgBVTskrS9Vl5oScD0Bp3vTzDi+OxskTo= X-Endpoint-Received: by B4 Relay for jsandom@axon.com/20260319 with auth_id=687 X-Original-From: Joe Sandom Reply-To: jsandom@axon.com From: Joe Sandom Update the pcieport0 reference to pcie0_port0 to match the label rename in sm8550.dtsi. Signed-off-by: Joe Sandom --- arch/arm64/boot/dts/qcom/sm8550-hdk.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts b/arch/arm64/boot/dts/= qcom/sm8550-hdk.dts index ee13e6136a8259d28540e718851e094f74ead278..e821b731bdc496c872703723df0= 2ae9b9b0233b5 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts @@ -1012,7 +1012,7 @@ &pcie0 { status =3D "okay"; }; =20 -&pcieport0 { +&pcie0_port0 { wifi@0 { compatible =3D "pci17cb,1107"; reg =3D <0x10000 0x0 0x0 0x0 0x0>; --=20 2.34.1 From nobody Wed Jun 10 05:07:45 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C93913A901C; Sat, 4 Apr 2026 09:51:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775296273; cv=none; b=d+2qTFJocuL5SXHOHaG2E2vdYQVvxXfZd+9Rzwnkpe9pdHnizIPHWhA/n9BO0Kfc2dhjtVBnnaSV/yZVS9RZXD6XXGtzByPmazKhVtKT2Mq4hU502SEqf4B77sxdMgY2dLI/78jte3WiOyhOunMpKUqFgM1c3Jde/RTatSmGTa8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775296273; c=relaxed/simple; bh=YhzONHcHnPtcdh0oJCQOSgrpKU4uyFrSXxBNxGXJ9Hg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=BuGNG5rzHmGaSHLTkFBAV0fTKVs9iYLa4MOT1+E0gnmET2ABtG6GCgOpp/wTROJ1igeQqn4c4hPSb+VcxUGcHqLeHrogBHqQLw/01zohwxcCy77NS0OzifKn+rCin/JJRdEAWnaNQLNVAtGghtI/J0zQfm1pOG1KZS6Qp1SEQdg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=NgsqiTau; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="NgsqiTau" Received: by smtp.kernel.org (Postfix) with ESMTPS id 95916C2BCB0; Sat, 4 Apr 2026 09:51:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1775296273; bh=YhzONHcHnPtcdh0oJCQOSgrpKU4uyFrSXxBNxGXJ9Hg=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=NgsqiTaudFNsHsj44QWNue9B35JUIrA5LPJEyQXiLzUbzVYuHy2YujvlPzr0qTKNK 33+uXEz6V/WsFpQH/wViYpi+zdy+O930GjThoOOml8SCuKB5gXsaG3BPeBexzA/Al2 nF2fRzr2hxlMaMg8IYfKWb42O/tLlp6BYOsF79b/e/S+lOXFIR7IqNp2zQKOY6quSx Yx+ELyye0g4DY1I9wN8uFhT5+pVzXDSFQ2cVo7nrn362cHRyfVM2s+BVGuu4dOpl1x 67/U2kl+hTJ5+imbjXRS7mcDPDaUw3bdLwqjSteZWaqGshy/Bc0Njq36mpMzEwQ443 KSse4IDOJwMbQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8AEC4E88D8B; Sat, 4 Apr 2026 09:51:13 +0000 (UTC) From: Joe Sandom via B4 Relay Date: Sat, 04 Apr 2026 10:50:56 +0100 Subject: [PATCH 3/5] arm64: dts: qcom: sm8550-qrd: update PCIe port label reference Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260404-rb5gen2-dts-v1-3-895f8fc494fc@axon.com> References: <20260404-rb5gen2-dts-v1-0-895f8fc494fc@axon.com> In-Reply-To: <20260404-rb5gen2-dts-v1-0-895f8fc494fc@axon.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Joe Sandom X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1775296270; l=716; i=jsandom@axon.com; s=20260319; h=from:subject:message-id; bh=biasXB222hzEaLoXAD4N9CkWdtezEit9QdECECb0yUM=; b=NB1JN8WQ/Bx3FQNESndN4DFVm4b95WoTwn8wy/OjSS+N9jn1Vomh5e6wGWscmfQpmk02Xp6qN /Hf3CMNDwddAoTns434Ee4AHlyMOTdXJV3pTibRfj55BnMFlJUDU2OE X-Developer-Key: i=jsandom@axon.com; a=ed25519; pk=Q/yflwj2WhkgBVTskrS9Vl5oScD0Bp3vTzDi+OxskTo= X-Endpoint-Received: by B4 Relay for jsandom@axon.com/20260319 with auth_id=687 X-Original-From: Joe Sandom Reply-To: jsandom@axon.com From: Joe Sandom Update the pcieport0 reference to pcie0_port0 to match the label rename in sm8550.dtsi. Signed-off-by: Joe Sandom --- arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/= qcom/sm8550-qrd.dts index 2fb2e0be5e4c6b597f20f332cdf063daa2664205..cf63109ff7bf7b6fc827f108e22= e82b8b04273c1 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts @@ -912,7 +912,7 @@ &pcie0 { status =3D "okay"; }; =20 -&pcieport0 { +&pcie0_port0 { wifi@0 { compatible =3D "pci17cb,1107"; reg =3D <0x10000 0x0 0x0 0x0 0x0>; --=20 2.34.1 From nobody Wed Jun 10 05:07:45 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DC3553A9618; Sat, 4 Apr 2026 09:51:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775296273; cv=none; b=UTfldbCNqKp16a6wwGbKirlB+F3ChiR4KIy8jeBGzBkz8Piuo+qNBFXosvxbEjlPhRljGDkPm6HW4o4BRI4BlK8KkF2J1meC6huf9Mnoa3mf/EZ/ABQUatBdvMwBpy3T/oeGnedoe1c7FBHo90V+p/fA/6XBpLO0toGALSpDXl0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775296273; c=relaxed/simple; bh=sPpqH0YvutjO0fz7t+jK+1WmAmWYtzRqbbkvK0SDgzs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=nXwS/LLX+VYtQYSsCSrI5C+PV5FrSbC6eAQ+k8cjpQieGcsclBSrdAK+4friBmPI4Wj7/crdFekT8Sq+RdQKZmW6cD2faIqWUILqqgjUyVpTR765EZWgQPkZxXAFMf4QCEmXYeo+wu2OJaPdFx/n3EsbHtoNSeYCNicY2MTMzXk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=gI/Xj9Aw; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="gI/Xj9Aw" Received: by smtp.kernel.org (Postfix) with ESMTPS id A9050C4AF0E; Sat, 4 Apr 2026 09:51:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1775296273; bh=sPpqH0YvutjO0fz7t+jK+1WmAmWYtzRqbbkvK0SDgzs=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=gI/Xj9AwFU9p13aFB12u7jOznos4citiqpx9dISiHbIjXg0QHUc/T9LOqS5uSuR/l SnF787mL/mbDmEapqVAHht3V2KeE+CGQEksvsVBGI09CXEOfiBCUETwtu/+sNAJscb HrmgHygLLd4+ptOWM1fnmGgRbG2oZzAyjDYuShZQIQpZBB3wAVB14OCM8IlrqJhmyR Q+2OLIrfTwLu+ijT30IoxujVVd9qtTnxqPq2zRU4M1W4AeUbZD0tYlKnWPc/If2OlA Sj1fD9ukbN2cp9TAlXH6cBrNRM9dUEXJczHF67NcaBRe7IoagakRP8NbrZfzJK4n92 u9TiO/G9xCQ7Q== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id A11D5E88D97; Sat, 4 Apr 2026 09:51:13 +0000 (UTC) From: Joe Sandom via B4 Relay Date: Sat, 04 Apr 2026 10:50:57 +0100 Subject: [PATCH 4/5] dt-bindings: arm: qcom: document QCS8550 RB5Gen2 board Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260404-rb5gen2-dts-v1-4-895f8fc494fc@axon.com> References: <20260404-rb5gen2-dts-v1-0-895f8fc494fc@axon.com> In-Reply-To: <20260404-rb5gen2-dts-v1-0-895f8fc494fc@axon.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Joe Sandom X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1775296270; l=980; i=jsandom@axon.com; s=20260319; h=from:subject:message-id; bh=15NO7S2ceOrSNULajYv+uag1jcs9MYHL1sRr8noMBX4=; b=K6NjDmJkvmY+AnawyNi92gkaQT/IaELHxeHmtbHKFODk+XI3XzxGlzo0yqpPp5dt9EWlQuH9Y PQbKVtOji9IBPaNI41GUoDImzepk9t5r+gBeQ5NU8AkuVYafvzYt1X4 X-Developer-Key: i=jsandom@axon.com; a=ed25519; pk=Q/yflwj2WhkgBVTskrS9Vl5oScD0Bp3vTzDi+OxskTo= X-Endpoint-Received: by B4 Relay for jsandom@axon.com/20260319 with auth_id=687 X-Original-From: Joe Sandom Reply-To: jsandom@axon.com From: Joe Sandom Document the Qualcomm RB5gen2 from Thundercomm based on the QCS8550 chipset from Qualcomm. [1] https://www.thundercomm.com/product/qualcomm-rb5-gen-2-development-kit/ Signed-off-by: Joe Sandom Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentatio= n/devicetree/bindings/arm/qcom.yaml index 1335a7bee397c46e8dc62806091531e32b7327d4..f9f8001e3e6b66e3a926255bdb1= 5363f4c7c2b66 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -1093,6 +1093,12 @@ properties: - const: qcom,qcs8550 - const: qcom,sm8550 =20 + - items: + - enum: + - qcom,qcs8550-rb5gen2 + - const: qcom,qcs8550 + - const: qcom,sm8550 + - items: - enum: - ayaneo,pocket-s2 --=20 2.34.1 From nobody Wed Jun 10 05:07:45 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 388D63AA4E6; Sat, 4 Apr 2026 09:51:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775296274; cv=none; b=uZboDSJ4VLTC8cMPUXShxjMdjiPlTdsPfS0F4WjmW4oyauS9Dvo8uApk6WJzmKArOgAaQjiR6N1wF5HCVMqHq+ZOATozvl+xtsDhExFsMF8J+ZivcbJsEdKaaU6dHGOnPRuyi5BnlTfy6gkh/TEs9yplk/PSU/pDRbRrvk7aD24= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775296274; c=relaxed/simple; bh=ibESnDn0XE4OQCFoFGiSSyhvas1zclWNJVaYCDDQvz8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=oDJbKDOCi1x1zVz0saeuFfu/PZpngiLaXaas6MR/IhlKJgwnyI/EV4ptwoRFduwBizpNGPUcrC+wdpVBvCk685qdDIk3/mwZJIlumjomJ7E3T24CUC9g4UXwCodtAB6hqvhPscxghuhitCqAXFAt5B0kPKCpvMoisdU38t0PaPY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=kj5yWBnd; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="kj5yWBnd" Received: by smtp.kernel.org (Postfix) with ESMTPS id D6888C4AF15; Sat, 4 Apr 2026 09:51:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1775296273; bh=ibESnDn0XE4OQCFoFGiSSyhvas1zclWNJVaYCDDQvz8=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=kj5yWBndXyx83P55HW5vY3QkHydWQ3N6p/SYf8IdNpTmrH+zXgZz9uB8ezL4KN1CV CM//cmn9ME92mWIDCoy3wZeiJjwbAFIgjLY66UXX+1fhAWML3mBfREaF2XZWtr4FVN CHe3WmgWtevAM3Re0dyAxWb++oZuFtKWcLvTmJNc7bHhSALlZ4DFjVzvEOH75+mm54 EXMADzOacaPtI7Yy1ykzkLelVkZpMRAM6faYGoCUd0d1opyoyOqtWRyCTDTiON1Bhn QgLEZfP5nptPnHAB/OZ63Yu26+dhW57wJIq2Nc3dfKlNPgOeeVP2sUz0/1AAtOLlut m5qroAOMdTf2Q== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id C6CE4E88D98; Sat, 4 Apr 2026 09:51:13 +0000 (UTC) From: Joe Sandom via B4 Relay Date: Sat, 04 Apr 2026 10:50:58 +0100 Subject: [PATCH 5/5] arm64: dts: qcom: qcs8550: add QCS8550 RB5Gen2 board support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260404-rb5gen2-dts-v1-5-895f8fc494fc@axon.com> References: <20260404-rb5gen2-dts-v1-0-895f8fc494fc@axon.com> In-Reply-To: <20260404-rb5gen2-dts-v1-0-895f8fc494fc@axon.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Joe Sandom X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1775296270; l=41181; i=jsandom@axon.com; s=20260319; h=from:subject:message-id; bh=pJE9/t5Heo7fmCAD5gp88skg6bVp1HRO9lSCKpL/EYE=; b=b1qjaVLdhWoKvtUQ49Bnx3so4RB3sSngpTfD8JOaYxbEDsqgQbS38tPpd4shcSHGw2fCnwELT s/JQo7+j5IsB1p8kIGXsQ9HTVveBzXlTq+qfuJ/EouSwR4XYUfeICbn X-Developer-Key: i=jsandom@axon.com; a=ed25519; pk=Q/yflwj2WhkgBVTskrS9Vl5oScD0Bp3vTzDi+OxskTo= X-Endpoint-Received: by B4 Relay for jsandom@axon.com/20260319 with auth_id=687 X-Original-From: Joe Sandom Reply-To: jsandom@axon.com From: Joe Sandom The RB5gen2 is an embedded development platform for the QCS8550, based on the Snapdragon 8 Gen 2 SoC (SM8550). This change implements the main board, the vision mezzanine will be supported in a follow up patch. The main board has the following features: - Qualcomm Dragonwing QCS8550 SoC - Adreno GPU 740 - Spectra ISP - Adreno VPU 8550 - Adreno DPU 1295 - 1 x 1GbE Ethernet (USB Ethernet) - WIFI 7 + Bluetooth 5.4 - 1 x USB 2.0 Micro B (Debug) - 1 x USB 3.0 Type C (ADB, DP out) - 2 x USB 3.0 Type A - 1 x HDMI 1.4 Type A - 1 x DP 1.4 Type C - 2 x WSA8845 Speaker amplifiers - 2 x Speaker connectors - 1 x On Board PDM MIC - Accelerometer + Gyro Sensor - 96Boards compatible low-speed and high-speed connectors [1] - 7 x LED indicators (4 user, 2 radio, 1 power) - Buttons for power, volume up/down, force USB boot - 3 x Dip switches On-Board PMICs: - PMK8550 2.1 - PM8550 2.0 - PM8550VS 2.0 x4 - PM8550VE 2.0 - PM8550B 2.0 - PMR735D 2.0 - PM8010 1.1 x2 Product Page: [2] [1] https://www.96boards.org/specifications/ [2] https://www.thundercomm.com/product/qualcomm-rb5-gen-2-development-kit Signed-off-by: Joe Sandom --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/qcs8550-rb5gen2.dts | 1610 ++++++++++++++++++++++= ++++ 2 files changed, 1611 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index 4ba8e73064194926096b98b9556a3207e8f24d72..f8c65771f76629d7fafee15ac8d= 7bb62cd24a20f 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -184,6 +184,7 @@ qcs8300-ride-el2-dtbs :=3D qcs8300-ride.dtb monaco-el2.= dtbo =20 dtb-$(CONFIG_ARCH_QCOM) +=3D qcs8300-ride-el2.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D qcs8550-aim300-aiot.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D qcs8550-rb5gen2.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D qcs9100-ride.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D qcs9100-ride-r3.dtb =20 diff --git a/arch/arm64/boot/dts/qcom/qcs8550-rb5gen2.dts b/arch/arm64/boot= /dts/qcom/qcs8550-rb5gen2.dts new file mode 100644 index 0000000000000000000000000000000000000000..280fbd3a09997e3e2613498e25a= c188680484cc4 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qcs8550-rb5gen2.dts @@ -0,0 +1,1610 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2026 Axon Enterprise, Inc. + */ + +/dts-v1/; + +#include +#include +#include +#include "qcs8550.dtsi" +#include "pm8010.dtsi" +#include "pm8550.dtsi" +#include "pm8550b.dtsi" +#define PMK8550VE_SID 5 +#include "pm8550ve.dtsi" +#include "pm8550vs.dtsi" +#include "pmk8550.dtsi" +#include "pmr735d_a.dtsi" +#include "pmr735d_b.dtsi" + +/ { + model =3D "Qualcomm Technologies, Inc. QCS8550 RB5Gen2"; + compatible =3D "qcom,qcs8550-rb5gen2", "qcom,qcs8550", "qcom,sm8550"; + chassis-type =3D "embedded"; + + aliases { + serial0 =3D &uart7; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + clocks { + clk40m: can-clk { + compatible =3D "fixed-clock"; + clock-frequency =3D <40000000>; + #clock-cells =3D <0>; + }; + }; + + gpio-keys { + compatible =3D "gpio-keys"; + + pinctrl-0 =3D <&volume_up_n>; + pinctrl-names =3D "default"; + + key-volume-up { + label =3D "Volume Up"; + linux,code =3D ; + gpios =3D <&pm8550_gpios 6 GPIO_ACTIVE_LOW>; + debounce-interval =3D <15>; + linux,can-disable; + wakeup-source; + }; + }; + + hdmi-connector { + compatible =3D "hdmi-connector"; + type =3D "a"; + + port { + hdmi_con: endpoint { + remote-endpoint =3D <<9611_out>; + }; + }; + }; + + /* Lontium LT9611UXC fails FW upgrade and has timeouts with geni-i2c */ + /* Workaround is to use bit-banged I2C */ + i2c_hub_3_gpio: i2c { + compatible =3D "i2c-gpio"; + + sda-gpios =3D <&tlmm 22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios =3D <&tlmm 23 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + leds { + compatible =3D "gpio-leds"; + + led-0 { + label =3D "green:status-3"; + function =3D LED_FUNCTION_STATUS; + color =3D ; + gpios =3D <&pm8550_gpios 2 GPIO_ACTIVE_HIGH>; + default-state =3D "off"; + }; + + led-1 { + label =3D "blue:bt-power"; + function =3D LED_FUNCTION_BLUETOOTH; + color =3D ; + gpios =3D <&pm8550b_gpios 7 GPIO_ACTIVE_HIGH>; + linux,default-trigger =3D "bluetooth-power"; + default-state =3D "off"; + }; + + led-2 { + label =3D "yellow:wlan"; + function =3D LED_FUNCTION_WLAN; + color =3D ; + gpios =3D <&pm8550b_gpios 9 GPIO_ACTIVE_HIGH>; + linux,default-trigger =3D "phy0tx"; + default-state =3D "off"; + }; + }; + + lt9611_1v2: lt9611-regulator-1v2 { + compatible =3D "regulator-fixed"; + regulator-name =3D "LT9611_1V2"; + + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + + vin-supply =3D <&vreg_l14b_3p2>; + }; + + lt9611_3v3: lt9611-regulator-3v3 { + compatible =3D "regulator-fixed"; + regulator-name =3D "LT9611_3V3"; + + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + vin-supply =3D <&vreg_l14b_3p2>; + }; + + pmic-glink { + compatible =3D "qcom,sm8550-pmic-glink", "qcom,pmic-glink"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + connector@0 { + compatible =3D "usb-c-connector"; + reg =3D <0>; + power-role =3D "dual"; + data-role =3D "dual"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + pmic_glink_hs_in: endpoint { + remote-endpoint =3D <&usb_1_dwc3_hs>; + }; + }; + + port@1 { + reg =3D <1>; + + pmic_glink_ss_in: endpoint { + remote-endpoint =3D <&redriver_usb_con_ss>; + }; + }; + + port@2 { + reg =3D <2>; + + pmic_glink_sbu_in: endpoint { + remote-endpoint =3D <&redriver_usb_con_sbu>; + }; + }; + }; + }; + }; + + pcie_upd_1p05: regulator-pcie-upd-1p05 { + compatible =3D "regulator-fixed"; + regulator-name =3D "PCIE_UPD_1P05"; + gpio =3D <&tlmm 179 GPIO_ACTIVE_HIGH>; + vin-supply =3D <&vdd_ntn_0p9>; + regulator-min-microvolt =3D <1050000>; + regulator-max-microvolt =3D <1050000>; + enable-active-high; + regulator-enable-ramp-delay =3D <5000>; + pinctrl-0 =3D <&upd_1p05_en>; + pinctrl-names =3D "default"; + }; + + pcie_upd_3p3: regulator-pcie-upd-3p3 { + compatible =3D "regulator-fixed"; + regulator-name =3D "PCIE_UPD_3P3"; + gpio =3D <&tlmm 13 GPIO_ACTIVE_HIGH>; + vin-supply =3D <&pcie_upd_1p05>; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + enable-active-high; + regulator-enable-ramp-delay =3D <10000>; + pinctrl-0 =3D <&upd_3p3_en>; + pinctrl-names =3D "default"; + }; + + upd_reset: regulator-upd-reset { + compatible =3D "regulator-fixed"; + regulator-name =3D "UPD_RESET"; + gpio =3D <&tlmm 182 GPIO_ACTIVE_HIGH>; + vin-supply =3D <&pcie_upd_3p3>; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + enable-active-high; + regulator-enable-ramp-delay =3D <10000>; + regulator-boot-on; + regulator-always-on; + pinctrl-0 =3D <&upd_ponrst>; + pinctrl-names =3D "default"; + }; + + usbhub_reset: regulator-usbhub-reset { + compatible =3D "regulator-fixed"; + regulator-name =3D "USBHUB_RESET"; + gpio =3D <&tlmm 41 GPIO_ACTIVE_LOW>; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + regulator-always-on; + startup-delay-us =3D <1500>; + off-on-delay-us =3D <1500>; + pinctrl-0 =3D <&usbhub_rst>; + pinctrl-names =3D "default"; + }; + + vdd_ntn_0p9: regulator-vdd-ntn-0p9 { + compatible =3D "regulator-fixed"; + regulator-name =3D "VDD_NTN_0P9"; + vin-supply =3D <&vdd_ntn_1p8>; + regulator-min-microvolt =3D <899400>; + regulator-max-microvolt =3D <899400>; + regulator-enable-ramp-delay =3D <4300>; + }; + + vdd_ntn_1p8: regulator-vdd-ntn-1p8 { + compatible =3D "regulator-fixed"; + regulator-name =3D "VDD_NTN_1P8"; + gpio =3D <&tlmm 67 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + enable-active-high; + pinctrl-0 =3D <&ntn0_en>; + pinctrl-names =3D "default"; + regulator-enable-ramp-delay =3D <10000>; + }; + + vdd_ntn1_0p9: regulator-vdd-ntn1-0p9 { + compatible =3D "regulator-fixed"; + regulator-name =3D "VDD_NTN1_0P9"; + vin-supply =3D <&vdd_ntn1_1p8>; + regulator-min-microvolt =3D <899400>; + regulator-max-microvolt =3D <899400>; + regulator-enable-ramp-delay =3D <4300>; + }; + + vdd_ntn1_1p8: regulator-vdd-ntn1-1p8 { + compatible =3D "regulator-fixed"; + regulator-name =3D "VDD_NTN1_1P8"; + gpio =3D <&tlmm 42 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + enable-active-high; + pinctrl-0 =3D <&ntn1_en>; + pinctrl-names =3D "default"; + regulator-enable-ramp-delay =3D <10000>; + }; + + vph_pwr: regulator-vph-pwr { + compatible =3D "regulator-fixed"; + regulator-name =3D "vph_pwr"; + regulator-min-microvolt =3D <3700000>; + regulator-max-microvolt =3D <3700000>; + + regulator-always-on; + regulator-boot-on; + }; + + sound { + compatible =3D "qcom,sm8550-sndcard", "qcom,sm8450-sndcard"; + model =3D "QCS8550-RB5Gen2"; + audio-routing =3D "SpkrLeft IN", "WSA_SPK1 OUT", + "SpkrRight IN", "WSA_SPK2 OUT", + "VA DMIC0", "vdd-micb", + "VA DMIC1", "vdd-micb"; + + wsa-dai-link { + link-name =3D "WSA Playback"; + + cpu { + sound-dai =3D <&q6apmbedai WSA_CODEC_DMA_RX_0>; + }; + + codec { + sound-dai =3D <&left_spkr>, <&right_spkr>, + <&swr0 0>, <&lpass_wsamacro 0>; + }; + + platform { + sound-dai =3D <&q6apm>; + }; + }; + + va-dai-link { + link-name =3D "VA Capture"; + + cpu { + sound-dai =3D <&q6apmbedai VA_CODEC_DMA_TX_0>; + }; + + codec { + sound-dai =3D <&lpass_vamacro 0>; + }; + + platform { + sound-dai =3D <&q6apm>; + }; + }; + }; + + wcn7850-pmu { + compatible =3D "qcom,wcn7850-pmu"; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&wlan_en>, <&bt_default>, <&pmk8550_sleep_clk>; + + wlan-enable-gpios =3D <&tlmm 80 GPIO_ACTIVE_HIGH>; + bt-enable-gpios =3D <&tlmm 81 GPIO_ACTIVE_HIGH>; + + vdd-supply =3D <&vreg_s5g_0p85>; + vddio-supply =3D <&vreg_l15b_1p8>; + vddaon-supply =3D <&vreg_s2g_0p852>; + vdddig-supply =3D <&vreg_s4e_0p95>; + vddrfa1p2-supply =3D <&vreg_s4g_1p25>; + vddrfa1p8-supply =3D <&vreg_s6g_1p86>; + + regulators { + vreg_pmu_rfa_cmn: ldo0 { + regulator-name =3D "vreg_pmu_rfa_cmn"; + }; + + vreg_pmu_aon_0p59: ldo1 { + regulator-name =3D "vreg_pmu_aon_0p59"; + }; + + vreg_pmu_wlcx_0p8: ldo2 { + regulator-name =3D "vreg_pmu_wlcx_0p8"; + }; + + vreg_pmu_wlmx_0p85: ldo3 { + regulator-name =3D "vreg_pmu_wlmx_0p85"; + }; + + vreg_pmu_btcmx_0p85: ldo4 { + regulator-name =3D "vreg_pmu_btcmx_0p85"; + }; + + vreg_pmu_rfa_0p8: ldo5 { + regulator-name =3D "vreg_pmu_rfa_0p8"; + }; + + vreg_pmu_rfa_1p2: ldo6 { + regulator-name =3D "vreg_pmu_rfa_1p2"; + }; + + vreg_pmu_rfa_1p8: ldo7 { + regulator-name =3D "vreg_pmu_rfa_1p8"; + }; + + vreg_pmu_pcie_0p9: ldo8 { + regulator-name =3D "vreg_pmu_pcie_0p9"; + }; + + vreg_pmu_pcie_1p8: ldo9 { + regulator-name =3D "vreg_pmu_pcie_1p8"; + }; + }; + }; +}; + +&apps_rsc { + regulators-0 { + compatible =3D "qcom,pm8550-rpmh-regulators"; + qcom,pmic-id =3D "b"; + + vdd-bob1-supply =3D <&vph_pwr>; + vdd-bob2-supply =3D <&vph_pwr>; + vdd-l1-l4-l10-supply =3D <&vreg_s6g_1p86>; + vdd-l2-l13-l14-supply =3D <&vreg_bob1>; + vdd-l3-supply =3D <&vreg_s4g_1p25>; + vdd-l5-l16-supply =3D <&vreg_bob1>; + vdd-l6-l7-supply =3D <&vreg_bob1>; + vdd-l8-l9-supply =3D <&vreg_bob1>; + vdd-l11-supply =3D <&vreg_s4g_1p25>; + vdd-l12-supply =3D <&vreg_s6g_1p86>; + vdd-l15-supply =3D <&vreg_s6g_1p86>; + vdd-l17-supply =3D <&vreg_bob2>; + + vreg_bob1: bob1 { + regulator-name =3D "vreg_bob1"; + regulator-min-microvolt =3D <3296000>; + regulator-max-microvolt =3D <3960000>; + regulator-initial-mode =3D ; + }; + + vreg_bob2: bob2 { + regulator-name =3D "vreg_bob2"; + regulator-min-microvolt =3D <2720000>; + regulator-max-microvolt =3D <3960000>; + regulator-initial-mode =3D ; + }; + + vreg_l1b_1p8: ldo1 { + regulator-name =3D "vreg_l1b_1p8"; + regulator-min-microvolt =3D <1710000>; + regulator-max-microvolt =3D <1950000>; + regulator-initial-mode =3D ; + }; + + vreg_l2b_3p0: ldo2 { + regulator-name =3D "vreg_l2b_3p0"; + regulator-min-microvolt =3D <2900000>; + regulator-max-microvolt =3D <3544000>; + regulator-initial-mode =3D ; + }; + + vreg_l5b_3p1: ldo5 { + regulator-name =3D "vreg_l5b_3p1"; + regulator-min-microvolt =3D <3000000>; + regulator-max-microvolt =3D <3300000>; + regulator-initial-mode =3D ; + }; + + vreg_l6b_1p8: ldo6 { + regulator-name =3D "vreg_l6b_1p8"; + regulator-min-microvolt =3D <1700000>; + regulator-max-microvolt =3D <3300000>; + regulator-initial-mode =3D ; + }; + + vreg_l7b_1p8: ldo7 { + regulator-name =3D "vreg_l7b_1p8"; + regulator-min-microvolt =3D <1700000>; + regulator-max-microvolt =3D <3300000>; + regulator-initial-mode =3D ; + }; + + vreg_l8b_1p8: ldo8 { + regulator-name =3D "vreg_l8b_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3008000>; + regulator-initial-mode =3D ; + }; + + vreg_l9b_2p9: ldo9 { + regulator-name =3D "vreg_l9b_2p9"; + regulator-min-microvolt =3D <2960000>; + regulator-max-microvolt =3D <3008000>; + regulator-initial-mode =3D ; + }; + + vreg_l11b_1p2: ldo11 { + regulator-name =3D "vreg_l11b_1p2"; + regulator-min-microvolt =3D <1100000>; + regulator-max-microvolt =3D <1300000>; + regulator-initial-mode =3D ; + }; + + vreg_l12b_1p8: ldo12 { + regulator-name =3D "vreg_l12b_1p8"; + regulator-min-microvolt =3D <1710000>; + regulator-max-microvolt =3D <1950000>; + regulator-initial-mode =3D ; + }; + + vreg_l13b_3p0: ldo13 { + regulator-name =3D "vreg_l13b_3p0"; + regulator-min-microvolt =3D <2700000>; + regulator-max-microvolt =3D <3300000>; + regulator-initial-mode =3D ; + }; + + vreg_l14b_3p2: ldo14 { + regulator-name =3D "vreg_l14b_3p2"; + regulator-min-microvolt =3D <3200000>; + regulator-max-microvolt =3D <3300000>; + regulator-initial-mode =3D ; + regulator-always-on; + }; + + vreg_l15b_1p8: ldo15 { + regulator-name =3D "vreg_l15b_1p8"; + regulator-min-microvolt =3D <1760000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + + vreg_l16b_2p8: ldo16 { + regulator-name =3D "vreg_l16b_2p8"; + regulator-min-microvolt =3D <2000000>; + regulator-max-microvolt =3D <3400000>; + regulator-initial-mode =3D ; + }; + + vreg_l17b_2p5: ldo17 { + regulator-name =3D "vreg_l17b_2p5"; + regulator-min-microvolt =3D <2400000>; + regulator-max-microvolt =3D <3300000>; + regulator-initial-mode =3D ; + }; + }; + + regulators-1 { + compatible =3D "qcom,pm8550vs-rpmh-regulators"; + qcom,pmic-id =3D "c"; + + vdd-l1-supply =3D <&vreg_s4g_1p25>; + vdd-l2-supply =3D <&vreg_s4e_0p95>; + vdd-l3-supply =3D <&vreg_s4e_0p95>; + vdd-s1-supply =3D <&vph_pwr>; + vdd-s4-supply =3D <&vph_pwr>; + vdd-s6-supply =3D <&vph_pwr>; + + vreg_l3c_0p9: ldo3 { + regulator-name =3D "vreg_l3c_0p9"; + regulator-min-microvolt =3D <835000>; + regulator-max-microvolt =3D <912000>; + regulator-initial-mode =3D ; + }; + }; + + regulators-2 { + compatible =3D "qcom,pm8550vs-rpmh-regulators"; + qcom,pmic-id =3D "d"; + + vdd-l1-supply =3D <&vreg_s4e_0p95>; + vdd-l2-supply =3D <&vreg_s4e_0p95>; + vdd-s4-supply =3D <&vph_pwr>; + vdd-s5-supply =3D <&vph_pwr>; + + vreg_l1d_0p88: ldo1 { + regulator-name =3D "vreg_l1d_0p88"; + regulator-min-microvolt =3D <825000>; + regulator-max-microvolt =3D <958000>; + regulator-initial-mode =3D ; + }; + + vreg_l2d_0p752: ldo2 { + regulator-name =3D "vreg_l2d_0p752"; + regulator-min-microvolt =3D <675000>; + regulator-max-microvolt =3D <808000>; + regulator-initial-mode =3D ; + }; + + vreg_s4d_0p628: smps4 { + regulator-name =3D "vreg_s4d_0p628"; + regulator-min-microvolt =3D <572000>; + regulator-max-microvolt =3D <988000>; + regulator-initial-mode =3D ; + }; + + vreg_s5d_0p728: smps5 { + regulator-name =3D "vreg_s5d_0p728"; + regulator-min-microvolt =3D <572000>; + regulator-max-microvolt =3D <988000>; + regulator-initial-mode =3D ; + }; + }; + + regulators-3 { + compatible =3D "qcom,pm8550vs-rpmh-regulators"; + qcom,pmic-id =3D "e"; + + vdd-l1-supply =3D <&vreg_s4e_0p95>; + vdd-l2-supply =3D <&vreg_s4e_0p95>; + vdd-l3-supply =3D <&vreg_s4g_1p25>; + vdd-s1-supply =3D <&vph_pwr>; + vdd-s3-supply =3D <&vph_pwr>; + vdd-s4-supply =3D <&vph_pwr>; + vdd-s5-supply =3D <&vph_pwr>; + vdd-s6-supply =3D <&vph_pwr>; + + vreg_l1e_0p88: ldo1 { + regulator-name =3D "vreg_l1e_0p88"; + regulator-min-microvolt =3D <831000>; + regulator-max-microvolt =3D <904000>; + regulator-initial-mode =3D ; + }; + + vreg_l2e_0p9: ldo2 { + regulator-name =3D "vreg_l2e_0p9"; + regulator-min-microvolt =3D <870000>; + regulator-max-microvolt =3D <970000>; + regulator-initial-mode =3D ; + }; + + vreg_l3e_1p2: ldo3 { + regulator-name =3D "vreg_l3e_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + }; + + vreg_s1e_0p72: smps1 { + regulator-name =3D "vreg_s1e_0p72"; + regulator-min-microvolt =3D <532000>; + regulator-max-microvolt =3D <852000>; + regulator-initial-mode =3D ; + }; + + vreg_s3e_0p75: smps3 { + regulator-name =3D "vreg_s3e_0p75"; + regulator-min-microvolt =3D <716000>; + regulator-max-microvolt =3D <884000>; + regulator-initial-mode =3D ; + }; + + vreg_s4e_0p95: smps4 { + regulator-name =3D "vreg_s4e_0p95"; + regulator-min-microvolt =3D <870100>; + regulator-max-microvolt =3D <1152000>; + regulator-initial-mode =3D ; + }; + + vreg_s5e_1p08: smps5 { + regulator-name =3D "vreg_s5e_1p08"; + regulator-min-microvolt =3D <1010000>; + regulator-max-microvolt =3D <1120000>; + regulator-initial-mode =3D ; + }; + + vreg_s6e_0p728: smps6 { + regulator-name =3D "vreg_s6e_0p728"; + regulator-min-microvolt =3D <528000>; + regulator-max-microvolt =3D <904000>; + regulator-initial-mode =3D ; + }; + }; + + regulators-4 { + compatible =3D "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id =3D "f"; + + vdd-l1-supply =3D <&vreg_s4e_0p95>; + vdd-l2-supply =3D <&vreg_s4e_0p95>; + vdd-l3-supply =3D <&vreg_s4e_0p95>; + vdd-s1-supply =3D <&vph_pwr>; + vdd-s3-supply =3D <&vph_pwr>; + vdd-s4-supply =3D <&vph_pwr>; + vdd-s5-supply =3D <&vph_pwr>; + vdd-s7-supply =3D <&vph_pwr>; + + vreg_l1f_0p9: ldo1 { + regulator-name =3D "vreg_l1f_0p9"; + regulator-min-microvolt =3D <866000>; + regulator-max-microvolt =3D <958000>; + regulator-initial-mode =3D ; + }; + + vreg_l2f_0p88: ldo2 { + regulator-name =3D "vreg_l2f_0p88"; + regulator-min-microvolt =3D <866000>; + regulator-max-microvolt =3D <880000>; + regulator-initial-mode =3D ; + }; + + vreg_l3f_0p88: ldo3 { + regulator-name =3D "vreg_l3f_0p88"; + regulator-min-microvolt =3D <830000>; + regulator-max-microvolt =3D <920000>; + regulator-initial-mode =3D ; + }; + + vreg_s1f_0p728: smps1 { + regulator-name =3D "vreg_s1f_0p728"; + regulator-min-microvolt =3D <516000>; + regulator-max-microvolt =3D <904000>; + regulator-initial-mode =3D ; + }; + + vreg_s3f_0p852: smps3 { + regulator-name =3D "vreg_s3f_0p852"; + regulator-min-microvolt =3D <688000>; + regulator-max-microvolt =3D <952000>; + regulator-initial-mode =3D ; + }; + + vreg_s4f_0p5: smps4 { + regulator-name =3D "vreg_s4f_0p5"; + regulator-min-microvolt =3D <300000>; + regulator-max-microvolt =3D <500000>; + regulator-initial-mode =3D ; + }; + + vreg_s5f_0p752: smps5 { + regulator-name =3D "vreg_s5f_0p752"; + regulator-min-microvolt =3D <716000>; + regulator-max-microvolt =3D <884000>; + regulator-initial-mode =3D ; + }; + + vreg_s7f_0p628: smps7 { + regulator-name =3D "vreg_s7f_0p628"; + regulator-min-microvolt =3D <516000>; + regulator-max-microvolt =3D <812000>; + regulator-initial-mode =3D ; + }; + }; + + regulators-5 { + compatible =3D "qcom,pm8550vs-rpmh-regulators"; + qcom,pmic-id =3D "g"; + + vdd-l1-supply =3D <&vreg_s4g_1p25>; + vdd-l2-supply =3D <&vreg_s4g_1p25>; + vdd-l3-supply =3D <&vreg_s4g_1p25>; + vdd-s1-supply =3D <&vph_pwr>; + vdd-s2-supply =3D <&vph_pwr>; + vdd-s3-supply =3D <&vph_pwr>; + vdd-s4-supply =3D <&vph_pwr>; + vdd-s5-supply =3D <&vph_pwr>; + vdd-s6-supply =3D <&vph_pwr>; + + vreg_l1g_1p2: ldo1 { + regulator-name =3D "vreg_l1g_1p2"; + regulator-min-microvolt =3D <1140000>; + regulator-max-microvolt =3D <1260000>; + regulator-initial-mode =3D ; + }; + + vreg_l3g_1p2: ldo3 { + regulator-name =3D "vreg_l3g_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + }; + + vreg_s1g_1p256: smps1 { + regulator-name =3D "vreg_s1g_1p256"; + regulator-min-microvolt =3D <1172000>; + regulator-max-microvolt =3D <1388000>; + regulator-initial-mode =3D ; + }; + + vreg_s2g_0p852: smps2 { + regulator-name =3D "vreg_s2g_0p852"; + regulator-min-microvolt =3D <500000>; + regulator-max-microvolt =3D <1053200>; + regulator-initial-mode =3D ; + }; + + vreg_s3g_0p752: smps3 { + regulator-name =3D "vreg_s3g_0p752"; + regulator-min-microvolt =3D <532000>; + regulator-max-microvolt =3D <1148000>; + regulator-initial-mode =3D ; + }; + + vreg_s4g_1p25: smps4 { + regulator-name =3D "vreg_s4g_1p25"; + regulator-min-microvolt =3D <1172000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + + vreg_s5g_0p85: smps5 { + regulator-name =3D "vreg_s5g_0p85"; + regulator-min-microvolt =3D <800000>; + regulator-max-microvolt =3D <1002600>; + regulator-initial-mode =3D ; + }; + + vreg_s6g_1p86: smps6 { + regulator-name =3D "vreg_s6g_1p86"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <2192000>; + regulator-initial-mode =3D ; + }; + }; + + regulators-6 { + compatible =3D "qcom,pm8010-rpmh-regulators"; + + vdd-l1-l2-supply =3D <&vreg_s4g_1p25>; + vdd-l3-l4-supply =3D <&vreg_bob2>; + vdd-l5-supply =3D <&vreg_s6g_1p86>; + vdd-l6-supply =3D <&vreg_s6g_1p86>; + vdd-l7-supply =3D <&vreg_bob1>; + + qcom,pmic-id =3D "m"; + + vreg_l1m_1p056: ldo1 { + regulator-name =3D "vreg_l1m_1p056"; + regulator-min-microvolt =3D <1056000>; + regulator-max-microvolt =3D <1056000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l2m_1p056: ldo2 { + regulator-name =3D "vreg_l2m_1p056"; + regulator-min-microvolt =3D <1056000>; + regulator-max-microvolt =3D <1056000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l3m_2p8: ldo3 { + regulator-name =3D "vreg_l3m_2p8"; + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + regulator-initial-mode =3D ; + }; + + vreg_l4m_2p8: ldo4 { + regulator-name =3D "vreg_l4m_2p8"; + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + regulator-initial-mode =3D ; + }; + + vreg_l5m_1p8: ldo5 { + regulator-name =3D "vreg_l5m_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + + vreg_l6m_1p8: ldo6 { + regulator-name =3D "vreg_l6m_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + + vreg_l7m_2p9: ldo7 { + regulator-name =3D "vreg_l7m_2p9"; + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2904000>; + regulator-initial-mode =3D ; + }; + }; + + regulators-7 { + compatible =3D "qcom,pm8010-rpmh-regulators"; + + vdd-l1-l2-supply =3D <&vreg_s4g_1p25>; + vdd-l3-l4-supply =3D <&vreg_bob2>; + vdd-l5-supply =3D <&vreg_s6g_1p86>; + vdd-l6-supply =3D <&vreg_bob1>; + vdd-l7-supply =3D <&vreg_bob1>; + + qcom,pmic-id =3D "n"; + + vreg_l1n_1p1: ldo1 { + regulator-name =3D "vreg_l1n_1p1"; + regulator-min-microvolt =3D <1104000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l2n_1p1: ldo2 { + regulator-name =3D "vreg_l2n_1p1"; + regulator-min-microvolt =3D <1104000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l3n_2p8: ldo3 { + regulator-name =3D "vreg_l3n_2p8"; + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <3000000>; + regulator-initial-mode =3D ; + }; + + vreg_l4n_2p8: ldo4 { + regulator-name =3D "vreg_l4n_2p8"; + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <3300000>; + regulator-initial-mode =3D ; + }; + + vreg_l5n_1p8: ldo5 { + regulator-name =3D "vreg_l5n_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + + vreg_l6n_3p3: ldo6 { + regulator-name =3D "vreg_l6n_3p3"; + regulator-min-microvolt =3D <3200000>; + regulator-max-microvolt =3D <3200000>; + regulator-initial-mode =3D ; + }; + + vreg_l7n_2p96: ldo7 { + regulator-name =3D "vreg_l7n_2p96"; + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2960000>; + regulator-initial-mode =3D ; + }; + }; +}; + +&gpi_dma1 { + status =3D "okay"; +}; + +&gpi_dma2 { + status =3D "okay"; +}; + +&gpu { + status =3D "okay"; +}; + +&gpu_zap_shader { + firmware-name =3D "qcom/qcs8550/a740_zap.mbn"; +}; + +&i2c_hub_2 { + clock-frequency =3D <100000>; + + status =3D "okay"; + + typec-mux@1c { + compatible =3D "onnn,nb7vpq904m"; + reg =3D <0x1c>; + + vcc-supply =3D <&vreg_l15b_1p8>; + + retimer-switch; + orientation-switch; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + redriver_usb_con_ss: endpoint { + remote-endpoint =3D <&pmic_glink_ss_in>; + }; + }; + + port@1 { + reg =3D <1>; + + redriver_phy_con_ss: endpoint { + remote-endpoint =3D <&usb_dp_qmpphy_out>; + data-lanes =3D <0 1 2 3>; + }; + }; + + port@2 { + reg =3D <2>; + + redriver_usb_con_sbu: endpoint { + remote-endpoint =3D <&pmic_glink_sbu_in>; + }; + }; + }; + }; +}; + +&i2c_hub_3_gpio { + clock-frequency =3D <400000>; + + status =3D "okay"; + + lt9611_codec: hdmi-bridge@2b { + compatible =3D "lontium,lt9611uxc"; + reg =3D <0x2b>; + + interrupts-extended =3D <&tlmm 40 IRQ_TYPE_EDGE_FALLING>; + reset-gpios =3D <&tlmm 7 GPIO_ACTIVE_HIGH>; + + vdd-supply =3D <<9611_1v2>; + vcc-supply =3D <<9611_3v3>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <<9611_irq_pin <9611_rst_pin>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + lt9611_a: endpoint { + remote-endpoint =3D <&mdss_dsi0_out>; + }; + }; + + port@2 { + reg =3D <2>; + + lt9611_out: endpoint { + remote-endpoint =3D <&hdmi_con>; + }; + }; + }; + }; +}; + +&i2c_hub_4 { + status =3D "okay"; +}; + +&i2c_master_hub_0 { + status =3D "okay"; +}; + +&ipa { + qcom,gsi-loader =3D "self"; + memory-region =3D <&ipa_fw_mem>; + firmware-name =3D "qcom/qcs8550/ipa_fws.mbn"; + + status =3D "okay"; +}; + +&iris { + status =3D "okay"; +}; + +&lpass_vamacro { + pinctrl-0 =3D <&dmic01_default>; + pinctrl-names =3D "default"; + + qcom,dmic-sample-rate =3D <4800000>; + + vdd-micb-supply =3D <&vreg_l15b_1p8>; +}; + +&mdss { + status =3D "okay"; +}; + +&mdss_dsi0 { + vdda-supply =3D <&vreg_l3e_1p2>; + + status =3D "okay"; +}; + +&mdss_dsi0_out { + remote-endpoint =3D <<9611_a>; + data-lanes =3D <0 1 2 3>; +}; + +&mdss_dsi0_phy { + vdds-supply =3D <&vreg_l1e_0p88>; + + status =3D "okay"; +}; + +&mdss_dp0 { + status =3D "okay"; +}; + +&pcie0 { + wake-gpios =3D <&tlmm 96 GPIO_ACTIVE_HIGH>; + perst-gpios =3D <&tlmm 94 GPIO_ACTIVE_LOW>; + + pinctrl-0 =3D <&pcie0_default_state>; + pinctrl-names =3D "default"; + + iommu-map =3D <0x0 &apps_smmu 0x1400 0x1>, + <0x100 &apps_smmu 0x1401 0x1>, + <0x208 &apps_smmu 0x1402 0x1>, + <0x210 &apps_smmu 0x1403 0x1>, + <0x218 &apps_smmu 0x1404 0x1>, + <0x300 &apps_smmu 0x1407 0x1>, + <0x400 &apps_smmu 0x1408 0x1>, + <0x500 &apps_smmu 0x140c 0x1>, + <0x501 &apps_smmu 0x140e 0x1>; + + /delete-property/ msi-map; + + status =3D "okay"; +}; + +&pcie0_phy { + vdda-phy-supply =3D <&vreg_l1e_0p88>; + vdda-pll-supply =3D <&vreg_l3e_1p2>; + + status =3D "okay"; +}; + +&pcie0_port0 { + pcie@0,0 { + compatible =3D "pci1179,0623"; + reg =3D <0x10000 0x0 0x0 0x0 0x0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + + device_type =3D "pci"; + ranges; + bus-range =3D <0x2 0xff>; + + vddc-supply =3D <&vdd_ntn_0p9>; + vdd18-supply =3D <&vdd_ntn_1p8>; + vdd09-supply =3D <&vdd_ntn_0p9>; + vddio1-supply =3D <&vdd_ntn_1p8>; + vddio2-supply =3D <&vdd_ntn_1p8>; + vddio18-supply =3D <&vdd_ntn_1p8>; + + i2c-parent =3D <&i2c_hub_4 0x77>; + + resx-gpios =3D <&tlmm 64 GPIO_ACTIVE_LOW>; + + pinctrl-0 =3D <&tc9563_0_rst>; + pinctrl-names =3D "default"; + + pcie@1,0 { + reg =3D <0x20800 0x0 0x0 0x0 0x0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + + device_type =3D "pci"; + ranges; + bus-range =3D <0x3 0xff>; + }; + + pcie@2,0 { + reg =3D <0x21000 0x0 0x0 0x0 0x0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + + device_type =3D "pci"; + ranges; + bus-range =3D <0x4 0xff>; + }; + + pcie@3,0 { + reg =3D <0x21800 0x0 0x0 0x0 0x0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + device_type =3D "pci"; + ranges; + bus-range =3D <0x5 0xff>; + + pci@0,0 { + reg =3D <0x50000 0x0 0x0 0x0 0x0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + device_type =3D "pci"; + ranges; + }; + + pci@0,1 { + reg =3D <0x50100 0x0 0x0 0x0 0x0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + device_type =3D "pci"; + ranges; + }; + }; + }; +}; + +&pcie1 { + wake-gpios =3D <&tlmm 99 GPIO_ACTIVE_HIGH>; + perst-gpios =3D <&tlmm 97 GPIO_ACTIVE_LOW>; + + pinctrl-0 =3D <&pcie1_default_state>; + pinctrl-names =3D "default"; + + iommu-map =3D <0x0 &apps_smmu 0x1480 0x1>, + <0x100 &apps_smmu 0x1481 0x1>, + <0x208 &apps_smmu 0x1482 0x1>, + <0x210 &apps_smmu 0x1483 0x1>, + <0x218 &apps_smmu 0x1484 0x1>, + <0x300 &apps_smmu 0x1487 0x1>, + <0x400 &apps_smmu 0x1488 0x1>, + <0x500 &apps_smmu 0x148c 0x1>, + <0x501 &apps_smmu 0x148e 0x1>; + + /delete-property/ msi-map; + + status =3D "okay"; +}; + +&pcie1_phy { + vdda-phy-supply =3D <&vreg_l3c_0p9>; + vdda-pll-supply =3D <&vreg_l3e_1p2>; + vdda-qref-supply =3D <&vreg_l1e_0p88>; + + status =3D "okay"; +}; + +&pcie1_port0 { + pcie@0,0 { + compatible =3D "pci1179,0623"; + reg =3D <0x10000 0x0 0x0 0x0 0x0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + + device_type =3D "pci"; + ranges; + bus-range =3D <0x2 0xff>; + + vddc-supply =3D <&vdd_ntn1_0p9>; + vdd18-supply =3D <&vdd_ntn1_1p8>; + vdd09-supply =3D <&vdd_ntn1_0p9>; + vddio1-supply =3D <&vdd_ntn1_1p8>; + vddio2-supply =3D <&vdd_ntn1_1p8>; + vddio18-supply =3D <&vdd_ntn1_1p8>; + + i2c-parent =3D <&i2c_hub_3_gpio 0x77>; + + resx-gpios =3D <&tlmm 65 GPIO_ACTIVE_LOW>; + + pinctrl-0 =3D <&tc9563_1_rst>; + pinctrl-names =3D "default"; + + pcie@1,0 { + reg =3D <0x20800 0x0 0x0 0x0 0x0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + + device_type =3D "pci"; + ranges; + bus-range =3D <0x3 0xff>; + }; + + pcie@2,0 { + reg =3D <0x21000 0x0 0x0 0x0 0x0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + + device_type =3D "pci"; + ranges; + bus-range =3D <0x4 0xff>; + + wifi@0 { + compatible =3D "pci17cb,1107"; + reg =3D <0x40000 0x0 0x0 0x0 0x0>; + + vddrfacmn-supply =3D <&vreg_pmu_rfa_cmn>; + vddaon-supply =3D <&vreg_pmu_aon_0p59>; + vddwlcx-supply =3D <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply =3D <&vreg_pmu_wlmx_0p85>; + vddrfa0p8-supply =3D <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply =3D <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply =3D <&vreg_pmu_rfa_1p8>; + vddpcie0p9-supply =3D <&vreg_pmu_pcie_0p9>; + vddpcie1p8-supply =3D <&vreg_pmu_pcie_1p8>; + }; + }; + + pcie@3,0 { + reg =3D <0x21800 0x0 0x0 0x0 0x0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + device_type =3D "pci"; + ranges; + bus-range =3D <0x5 0xff>; + }; + }; +}; + +&pm8550_gpios { + volume_up_n: volume-up-n-state { + pins =3D "gpio6"; + function =3D "normal"; + power-source =3D <1>; + bias-pull-up; + input-enable; + }; + + sdc2_card_det_n: sdc2-card-det-state { + pins =3D "gpio12"; + function =3D "normal"; + power-source =3D <1>; + bias-pull-up; + input-enable; + }; +}; + +&pm8550_pwm { + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "okay"; + + led@1 { + reg =3D <1>; + color =3D ; + function =3D LED_FUNCTION_STATUS; + function-enumerator =3D <0>; + linux,default-trigger =3D "none"; + default-state =3D "off"; + }; + + led@2 { + reg =3D <2>; + color =3D ; + function =3D LED_FUNCTION_STATUS; + function-enumerator =3D <1>; + linux,default-trigger =3D "none"; + default-state =3D "off"; + }; + + led@3 { + reg =3D <3>; + color =3D ; + function =3D LED_FUNCTION_STATUS; + function-enumerator =3D <2>; + linux,default-trigger =3D "none"; + default-state =3D "off"; + }; +}; + +&pm8550b_eusb2_repeater { + vdd18-supply =3D <&vreg_l15b_1p8>; + vdd3-supply =3D <&vreg_l5b_3p1>; +}; + +&pmk8550_gpios { + pmk8550_sleep_clk: sleep-clk-state { + pins =3D "gpio3"; + function =3D "func1"; + input-disable; + output-enable; + bias-disable; + power-source =3D <0>; + }; +}; + +&pon_pwrkey { + status =3D "okay"; +}; + +&pon_resin { + linux,code =3D ; + + status =3D "okay"; +}; + +&qupv3_id_0 { + status =3D "okay"; +}; + +&qupv3_id_1 { + status =3D "okay"; +}; + +&remoteproc_adsp { + firmware-name =3D "qcom/qcs8550/adsp.mdt", + "qcom/qcs8550/adsp_dtb.mdt"; + status =3D "okay"; +}; + +&remoteproc_cdsp { + firmware-name =3D "qcom/qcs8550/cdsp.mdt", + "qcom/qcs8550/cdsp_dtb.mdt"; + status =3D "okay"; +}; + +&remoteproc_mpss { + firmware-name =3D "qcom/qcs8550/modem.mdt", + "qcom/qcs8550/modem_dtb.mdt"; + status =3D "okay"; +}; + +&sdhc_2 { + cd-gpios =3D <&pm8550_gpios 12 GPIO_ACTIVE_LOW>; + + pinctrl-0 =3D <&sdc2_default>, <&sdc2_card_det_n>; + pinctrl-1 =3D <&sdc2_sleep>, <&sdc2_card_det_n>; + pinctrl-names =3D "default", "sleep"; + + vmmc-supply =3D <&vreg_l9b_2p9>; + vqmmc-supply =3D <&vreg_l8b_1p8>; + + max-sd-hs-hz =3D <37000000>; + + no-sdio; + no-mmc; + + status =3D "okay"; +}; + +&sleep_clk { + clock-frequency =3D <32764>; +}; + +&spi11 { + status =3D "okay"; + + can@0 { + compatible =3D "microchip,mcp2518fd"; + reg =3D <0>; + interrupts-extended =3D <&tlmm 55 IRQ_TYPE_LEVEL_LOW>; + clocks =3D <&clk40m>; + spi-max-frequency =3D <10000000>; + vdd-supply =3D <&vreg_l14b_3p2>; + xceiver-supply =3D <&vreg_l14b_3p2>; + }; +}; + +&swr0 { + status =3D "okay"; + + left_spkr: speaker@0,0 { + compatible =3D "sdw20217020400"; + reg =3D <0 0>; + + reset-gpios =3D <&tlmm 133 GPIO_ACTIVE_LOW>; + + vdd-1p8-supply =3D <&vreg_l15b_1p8>; + vdd-io-supply =3D <&vreg_l15b_1p8>; + + #sound-dai-cells =3D <0>; + sound-name-prefix =3D "SpkrLeft"; + qcom,port-mapping =3D <1 2 3 7 10 13>; + }; + + right_spkr: speaker@0,1 { + compatible =3D "sdw20217020400"; + reg =3D <0 1>; + + reset-gpios =3D <&tlmm 133 GPIO_ACTIVE_LOW>; + + vdd-1p8-supply =3D <&vreg_l15b_1p8>; + vdd-io-supply =3D <&vreg_l15b_1p8>; + + #sound-dai-cells =3D <0>; + sound-name-prefix =3D "SpkrRight"; + qcom,port-mapping =3D <4 5 6 7 11 13>; + }; +}; + +&tlmm { + gpio-reserved-ranges =3D <32 8>; + + bt_default: bt-default-state { + bt-en-pins { + pins =3D "gpio81"; + function =3D "gpio"; + drive-strength =3D <16>; + bias-disable; + }; + + sw-ctrl-pins { + pins =3D "gpio82"; + function =3D "gpio"; + bias-pull-down; + }; + }; + + lt9611_irq_pin: lt9611-irq-state { + pins =3D "gpio40"; + function =3D "gpio"; + bias-disable; + }; + + lt9611_rst_pin: lt9611-rst-state { + pins =3D "gpio7"; + function =3D "gpio"; + output-high; + }; + + ntn0_en: ntn0-en-state { + pins =3D "gpio67"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + ntn1_en: ntn1-en-state { + pins =3D "gpio42"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + upd_1p05_en: upd-1p05-en-state { + pins =3D "gpio179"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + + upd_3p3_en: upd-3p3-en-state { + pins =3D "gpio13"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + + upd_ponrst: upd-ponrst-state { + pins =3D "gpio182"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + + usbhub_rst: usbhub-rst-state { + pins =3D "gpio41"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + }; + + tc9563_0_rst: tc9563-0-rst-state { + pins =3D "gpio64"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + tc9563_1_rst: tc9563-1-rst-state { + pins =3D "gpio65"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + wlan_en: wlan-en-state { + pins =3D "gpio80"; + function =3D "gpio"; + drive-strength =3D <8>; + bias-pull-down; + }; +}; + +&uart7 { + status =3D "okay"; +}; + +&uart14 { + status =3D "okay"; + + bluetooth { + compatible =3D "qcom,wcn7850-bt"; + + vddrfacmn-supply =3D <&vreg_pmu_rfa_cmn>; + vddaon-supply =3D <&vreg_pmu_aon_0p59>; + vddwlcx-supply =3D <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply =3D <&vreg_pmu_wlmx_0p85>; + vddrfa0p8-supply =3D <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply =3D <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply =3D <&vreg_pmu_rfa_1p8>; + }; +}; + +&ufs_mem_hc { + reset-gpios =3D <&tlmm 210 GPIO_ACTIVE_LOW>; + vcc-supply =3D <&vreg_l17b_2p5>; + vcc-max-microamp =3D <1300000>; + vccq-supply =3D <&vreg_l1g_1p2>; + vccq-max-microamp =3D <1200000>; + vdd-hba-supply =3D <&vreg_l3g_1p2>; + + status =3D "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply =3D <&vreg_l1d_0p88>; + vdda-pll-supply =3D <&vreg_l3e_1p2>; + + status =3D "okay"; +}; + +&usb_1 { + status =3D "okay"; +}; + +&usb_1_dwc3_hs { + remote-endpoint =3D <&pmic_glink_hs_in>; +}; + +&usb_1_hsphy { + vdd-supply =3D <&vreg_l1e_0p88>; + vdda12-supply =3D <&vreg_l3e_1p2>; + + phys =3D <&pm8550b_eusb2_repeater>; + + status =3D "okay"; +}; + +&usb_dp_qmpphy { + vdda-phy-supply =3D <&vreg_l3e_1p2>; + vdda-pll-supply =3D <&vreg_l3f_0p88>; + + status =3D "okay"; +}; + +&usb_dp_qmpphy_out { + remote-endpoint =3D <&redriver_phy_con_ss>; +}; + +&xo_board { + clock-frequency =3D <76800000>; +}; --=20 2.34.1