From nobody Tue Apr 7 12:20:08 2026 Received: from mail-yw1-f172.google.com (mail-yw1-f172.google.com [209.85.128.172]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E9F3820D4FF for ; Fri, 3 Apr 2026 15:04:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775228642; cv=none; b=UaubGciioi4avp8XaMYgmj0VC3Fw+rG3JYkNHUyEjyeZb5lXynPB0XA8Xc3lgpMP6Bq+u3SEylhOnwhutLF7vvT1nVI//32YSNnfutk1/InDB1oVMGLMtm2Iqm3hz26h0yxiD2rXMZ+WAIGrmHypK5BSC+ZQJhWWW4rJLgVEmN4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775228642; c=relaxed/simple; bh=6kxY+JG5TxkzQqjFSkDAuoKyhVGSdH/dv9kjFVeZatc=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=lZsrIg+8qldZOW4ohpFMsj3zRK4JrymYH7pgcSs8LW6qLh+rQ3iRbfXTVRbpx9F2Yk5fQcBv2HwDd5L+mPmdNOD5amrce70u1Riukplspfk8Rgg1ArXH5uCBUlxbmLe61PqvuGJQxqEMnFwXjys9DIv9rAIOdeoktT8cQp8yLxM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=Z/b75FH7; arc=none smtp.client-ip=209.85.128.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Z/b75FH7" Received: by mail-yw1-f172.google.com with SMTP id 00721157ae682-79853c0f5b9so32777677b3.0 for ; Fri, 03 Apr 2026 08:04:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1775228640; x=1775833440; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=2fvoeZziZfh1mXsRZ8yiOQc1WiJLbCbPxji8m7HtyAA=; b=Z/b75FH73ZOqv8Ea7YPM4SQhieSBuZAOA/z5rOA9p3qLw62aPs5IH9V1wRezdRYWTy 6Oa2SIevDCNBeQ1nHjryai8HwmmpJU32vByScdb4FmUf2ACdtflea3Uen3AMh/HWTpyP PSEqPUHTWsvznQazxTOe7cvwvx6J96lpoRUgvlOgLJZPkspAUYl76Bbmzk5r5Nn/dm8L 3OEl6uW9CiOu6HvJ0A3xB0HtpM3NBhUtrAEI6sH3F7O00ogAQIyDZbvrzRitICtHQj+p voRkxCEz08abxovrEy70sM3Vzw/H+edMwvCM1OBLz4YOfeiz3gRpI+AsK7zVUlG9ZsYm VZ/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1775228640; x=1775833440; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-gg:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=2fvoeZziZfh1mXsRZ8yiOQc1WiJLbCbPxji8m7HtyAA=; b=CSG9X2rcpZYJvvcNGCYQ5rDZME6GRdNZDmU40fhN8JMrVcy8uITCPkOOx6UaPb3G+J cp9dUXfwuCCVw3fbwZFs+xmXFYuujrdX/ZJEH9BGQXnIUbPOSopGxTOkWCuO/r8U5VuN gO0T2A7r+7454jl6mhHBaX5Gayr1fhu5XEbQIrQqaOXrMAheg+02DgfPB7imQO4UJSFT nu7kdB70j2QEfAvJQTw+T7UKGn6PRu2yEb+hn1ZqbPAYcp3Urz53XD8EpjLCiy6h2JWa Ldl5904ojleKGVBvvOtJ8U8f3U+Flcm0fCQGlYI0fRcPJGh/pP5D6ydspihC6+d8HyTG +v7g== X-Forwarded-Encrypted: i=1; AJvYcCXvG2KkQQ4liBqfML9wlhKlE8R2XWTKtgeboyWDspgiwknsIUxa/65BN+A/CJWQKASfsQT5ZdPmnF/MYyg=@vger.kernel.org X-Gm-Message-State: AOJu0YzgdSQKO9pZVPvVrOLGgr3i4cumc38K+D/x8QHfC8MT9BJIarrS 9thbDk/CDcSJBmqhC8VnYI1yrGP2ilbNd4TGqI6H2rE0v3sJUs22MNsr/KiFGA== X-Gm-Gg: AeBDietNhGb4qX9skiSp7lg6sEPcJafE+iYKAj7K+K5CoETd1hVdwgy8PfyYZNV5+3Q P8djahnT2IsEDH8Tv1kyujR6JSvLpzDaQAlHNdULRGdB6V46qmQjvmtsivDoIF2inrLeSnuKBOL Q7lz9fUSR4LC+gdN0Z0fiJlvQKx2zzccL4kyMMmR/2t7qHlat0qCAM2hSONxDdEoiuFvu8q5hgo L86A9IWm03fEE1oatFUIATRnVQ5n1i1n4kWNoni2EVKJk8Vb5GpeImshngs+tri4amXtDLmSNp4 DpUfJdaVteuRJ37vQeMLPECpIQ6jxl5mpGkcAZmNLdb5KO64C1Dqp6fPUVT70qr9+tz/tk+A6Ds DYT6z909d9Qv+pn20sXNEa6DiC3GtW6nqvMOsyvLwiQBOORxksNavZQ7eFy6TGL67UA+oZE1dru JbN3Z5DzEvKvUYBoD9NQk= X-Received: by 2002:a05:690c:660e:b0:7a4:80ce:8275 with SMTP id 00721157ae682-7a4d566b496mr34629777b3.35.1775228639761; Fri, 03 Apr 2026 08:03:59 -0700 (PDT) Received: from localhost ([76.195.202.134]) by smtp.gmail.com with UTF8SMTPSA id 00721157ae682-7a36ea2c42dsm22723137b3.17.2026.04.03.08.03.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Apr 2026 08:03:59 -0700 (PDT) From: Matt Turner To: Magnus Lindholm Cc: linux-alpha@vger.kernel.org, linux-kernel@vger.kernel.org, Matt Turner Subject: [PATCH] alpha: marvel: Fix lock ordering in init_io7_irqs() Date: Fri, 3 Apr 2026 11:03:56 -0400 Message-ID: <20260403150357.489571-1-mattst88@gmail.com> X-Mailer: git-send-email 2.52.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Move irq_set_chip_and_handler() and irq_set_status_flags() calls outside the io7->irq_lock raw spinlock. These functions take sparse_irq_lock, which is a mutex, and taking a sleeping lock while holding a raw spinlock is invalid. The raw spinlock only needs to protect the hardware CSR accesses. This fixes the following lockdep splat during boot: [ BUG: Invalid wait context ] swapper/0/0 is trying to lock: sparse_irq_lock{....}-{4:4}, at: irq_mark_irq other info that might help us debug this: context-{5:5} 1 lock held by swapper/0/0: #0: &io7->irq_lock{....}-{2:2}, at: init_io7_irqs.constprop.0 Assisted-by: Claude:claude-opus-4-6 Signed-off-by: Matt Turner --- arch/alpha/kernel/sys_marvel.c | 27 +++++++++++++-------------- 1 file changed, 13 insertions(+), 14 deletions(-) diff --git ./arch/alpha/kernel/sys_marvel.c ./arch/alpha/kernel/sys_marvel.c index 1f99b03effc2..d0bdd5e6cfd7 100644 --- ./arch/alpha/kernel/sys_marvel.c +++ ./arch/alpha/kernel/sys_marvel.c @@ -263,6 +263,18 @@ init_io7_irqs(struct io7 *io7, */ printk(" Interrupts reported to CPU at PE %u\n", boot_cpuid); =20 + /* Set up the lsi irqs. */ + for (i =3D 0; i < 128; ++i) { + irq_set_chip_and_handler(base + i, lsi_ops, handle_level_irq); + irq_set_status_flags(i, IRQ_LEVEL); + } + + /* Set up the msi irqs. */ + for (i =3D 128; i < (128 + 512); ++i) { + irq_set_chip_and_handler(base + i, msi_ops, handle_level_irq); + irq_set_status_flags(i, IRQ_LEVEL); + } + raw_spin_lock(&io7->irq_lock); =20 /* set up the error irqs */ @@ -272,26 +284,13 @@ init_io7_irqs(struct io7 *io7, io7_redirect_irq(io7, &io7->csrs->STV_CTL.csr, boot_cpuid); io7_redirect_irq(io7, &io7->csrs->HEI_CTL.csr, boot_cpuid); =20 - /* Set up the lsi irqs. */ - for (i =3D 0; i < 128; ++i) { - irq_set_chip_and_handler(base + i, lsi_ops, handle_level_irq); - irq_set_status_flags(i, IRQ_LEVEL); - } - /* Disable the implemented irqs in hardware. */ - for (i =3D 0; i < 0x60; ++i)=20 + for (i =3D 0; i < 0x60; ++i) init_one_io7_lsi(io7, i, boot_cpuid); =20 init_one_io7_lsi(io7, 0x74, boot_cpuid); init_one_io7_lsi(io7, 0x75, boot_cpuid); =20 - - /* Set up the msi irqs. */ - for (i =3D 128; i < (128 + 512); ++i) { - irq_set_chip_and_handler(base + i, msi_ops, handle_level_irq); - irq_set_status_flags(i, IRQ_LEVEL); - } - for (i =3D 0; i < 16; ++i) init_one_io7_msi(io7, i, boot_cpuid); =20 --=20 2.52.0