From nobody Sun Jun 14 14:34:19 2026 Received: from dggsgout12.his.huawei.com (dggsgout12.his.huawei.com [45.249.212.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 31ED73947A3; Fri, 3 Apr 2026 09:48:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775209737; cv=none; b=P5qurhQaRT2tyGySaZxXpE5G4KcAEaAuUZ7ODv3R98KWSUGhIBhBmKsS6ph4g0xxibmK7g2X+EuUTSgicyDwLHhU7bmqY/sOzfmlyDyn9ZlKykmBNkvW451Zd14Nw1rSqbZPILXeKFF0ZJlON3FpTA2I1g2UFh5JAN1438Z722w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775209737; c=relaxed/simple; bh=qydWQLkPkS95NbWSLGfg3tq8oFn8ZwP/dQ9wzc11y/A=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=SISlXHf38L0fuiH0eI1ZpsPfJS9M6b7ALi2czjTXkjDmH0bz2DpA4lP8EYjpw1Osg0Dyer7uFR8DuxDFMkMkJzxtWkxmp7UWW5Y6xovk6KU8FeiSdZLGOI4FWIzVeWvbvZHv8sgcleYdE5r+BiTB85bRxRfZHiSIbRvy2p/ZbEw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=huaweicloud.com; spf=pass smtp.mailfrom=huaweicloud.com; arc=none smtp.client-ip=45.249.212.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=huaweicloud.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huaweicloud.com Received: from mail.maildlp.com (unknown [172.19.163.177]) by dggsgout12.his.huawei.com (SkyGuard) with ESMTPS id 4fnDRc3sKlzKHMVF; Fri, 3 Apr 2026 17:47:56 +0800 (CST) Received: from mail02.huawei.com (unknown [10.116.40.252]) by mail.maildlp.com (Postfix) with ESMTP id 26E1940593; Fri, 3 Apr 2026 17:48:49 +0800 (CST) Received: from huawei.com (unknown [10.67.174.45]) by APP3 (Coremail) with SMTP id _Ch0CgAnB1TwjM9p8K_UDA--.49742S3; Fri, 03 Apr 2026 17:48:48 +0800 (CST) From: Tengda Wu To: Peter Zijlstra , Namhyung Kim , leo.yan@linux.dev, Li Huafei , Ian Rogers , Kim Phillips , Mark Rutland , Arnaldo Carvalho de Melo , Ingo Molnar Cc: Bill Wendling , Nick Desaulniers , Alexander Shishkin , Adrian Hunter , Zecheng Li , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, llvm@lists.linux.dev, Tengda Wu Subject: [PATCH v2 01/16] perf llvm: Fix arm64 adrp instruction disassembly mismatch with objdump Date: Fri, 3 Apr 2026 09:47:45 +0000 Message-Id: <20260403094800.1418825-2-wutengda@huaweicloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260403094800.1418825-1-wutengda@huaweicloud.com> References: <20260403094800.1418825-1-wutengda@huaweicloud.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _Ch0CgAnB1TwjM9p8K_UDA--.49742S3 X-Coremail-Antispam: 1UD129KBjvJXoWxWryxGr4xuw48Zr1UXFW3Awb_yoW5uw43pr WDKayrJw4UAr1fXwsIkr47ury5CrWvqFW5Kr43ArsYkr43AFyfC34xGr429a47Xryqvw45 Ars09FWUWF48JrJanT9S1TB71UUUUUDqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUQEb4IE77IF4wAFF20E14v26rWj6s0DM7CY07I20VC2zVCF04k2 6cxKx2IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28IrcIa0xkI8VA2jI8067AKxVWUGw A2048vs2IY020Ec7CjxVAFwI0_Gr0_Xr1l8cAvFVAK0II2c7xJM28CjxkF64kEwVA0rcxS w2x7M28EF7xvwVC0I7IYx2IY67AKxVWDJVCq3wA2z4x0Y4vE2Ix0cI8IcVCY1x0267AKxV W8Jr0_Cr1UM28EF7xvwVC2z280aVAFwI0_GcCE3s1l84ACjcxK6I8E87Iv6xkF7I0E14v2 6rxl6s0DM2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64kE6c02F40Ex7xfMc Ij6xIIjxv20xvE14v26r106r15McIj6I8E87Iv67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_ Jr0_Gr1lF7xvr2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20VAGYxC7M4IIrI8v6xkF7I 0E8cxan2IY04v7MxkF7I0En4kS14v26r4a6rW5MxkF7I0Ew4C26cxK6c8Ij28IcwCF04k2 0xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18MI 8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_GFv_WrylIxkGc2Ij64vIr41l IxAIcVC0I7IYx2IY67AKxVW8JVW5JwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Gr1j6F4UJw CI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Gr0_Cr1lIxAIcVC2 z280aVCY1x0267AKxVW8Jr0_Cr1UYxBIdaVFxhVjvjDU0xZFpf9x0pE9mRrUUUUU= X-CM-SenderInfo: pzxwv0hjgdqx5xdzvxpfor3voofrz/ Content-Type: text/plain; charset="utf-8" The operands of 'adrp' instructions parsed by libllvm are currently represented as raw immediates rather than the "address " format used by objdump. This inconsistency causes arm64_mov__parse() to fail when parsing these instructions during post-processing. Example of the mismatch: Current: adrp x18, 8014 Fix: adrp x18, ffff800081f5f000 Fix this by manually extracting the target address from the raw adrp instruction via symbol_lookup_callback(). The address is then converted to a specific symbol during symbol__disassemble_llvm() and formatted to match objdump's output, ensuring compatibility with existing parsers. Signed-off-by: Tengda Wu --- tools/perf/util/llvm.c | 50 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/tools/perf/util/llvm.c b/tools/perf/util/llvm.c index a0deb742a733..533d47e8084d 100644 --- a/tools/perf/util/llvm.c +++ b/tools/perf/util/llvm.c @@ -94,6 +94,7 @@ static void init_llvm(void) struct symbol_lookup_storage { u64 branch_addr; u64 pcrel_load_addr; + u64 pcrel_adrp_addr; }; =20 static const char * @@ -108,6 +109,18 @@ symbol_lookup_callback(void *disinfo, uint64_t value, storage->branch_addr =3D value; else if (*ref_type =3D=3D LLVMDisassembler_ReferenceType_In_PCrel_Load) storage->pcrel_load_addr =3D value; + else if (*ref_type =3D=3D LLVMDisassembler_ReferenceType_In_ARM64_ADRP) { + uint64_t adrp_imm; + + /* immhi (bits 23:5) and immlo (bits 30:29) */ + adrp_imm =3D ((value & 0x00ffffe0) >> 3) | ((value >> 29) & 0x3); + /* Sign-extend the 21-bit immediate to 64-bit */ + if (adrp_imm & (1ULL << 20)) + adrp_imm |=3D ~((1ULL << 21) - 1); + + /* Calculate the target page address */ + storage->pcrel_adrp_addr =3D (address & ~0xFFFLL) + (adrp_imm << 12); + } *ref_type =3D LLVMDisassembler_ReferenceType_InOut_None; return NULL; } @@ -204,6 +217,7 @@ int symbol__disassemble_llvm(const char *filename, stru= ct symbol *sym, =20 storage.branch_addr =3D 0; storage.pcrel_load_addr =3D 0; + storage.pcrel_adrp_addr =3D 0; =20 /* * LLVM's API has the code be disassembled as non-const, cast @@ -227,6 +241,42 @@ int symbol__disassemble_llvm(const char *filename, str= uct symbol *sym, free(name); } } + if (storage.pcrel_adrp_addr !=3D 0) { + /* + * ADRP (Address Page) instructions encode a 21-bit signed + * immediate offset relative to the current PC's page. + * + * To maintain consistency with standard objdump output, + * we truncate the raw encoded immediate at the comma + * and replace it with the resolved absolute page address. + * + * Example conversion: + * From: adrp x18, 8014 + * To: adrp x18, ffff800081f5f000 + */ + char *name; + char *s =3D strchr(disasm_buf, ','); + + if (s =3D=3D NULL) + goto err; + + s++; + *s =3D '\0'; + disasm_len =3D strlen(disasm_buf); + disasm_len +=3D scnprintf(disasm_buf + disasm_len, + sizeof(disasm_buf) - disasm_len, + " %"PRIx64, + storage.pcrel_adrp_addr); + name =3D llvm_name_for_data(dso, filename, + storage.pcrel_adrp_addr); + if (name) { + disasm_len +=3D scnprintf(disasm_buf + disasm_len, + sizeof(disasm_buf) - + disasm_len, + " <%s>", name); + free(name); + } + } if (storage.pcrel_load_addr !=3D 0) { char *name =3D llvm_name_for_data(dso, filename, storage.pcrel_load_addr); --=20 2.34.1 From nobody Sun Jun 14 14:34:19 2026 Received: from dggsgout11.his.huawei.com (dggsgout11.his.huawei.com [45.249.212.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DA9292EBDFA; Fri, 3 Apr 2026 09:48:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.51 ARC-Seal: i=1; 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spf=pass smtp.mailfrom=huaweicloud.com Received: from mail.maildlp.com (unknown [172.19.163.170]) by dggsgout11.his.huawei.com (SkyGuard) with ESMTPS id 4fnDS75hpBzYQtsd; Fri, 3 Apr 2026 17:48:23 +0800 (CST) Received: from mail02.huawei.com (unknown [10.116.40.252]) by mail.maildlp.com (Postfix) with ESMTP id 3ABF540570; Fri, 3 Apr 2026 17:48:49 +0800 (CST) Received: from huawei.com (unknown [10.67.174.45]) by APP3 (Coremail) with SMTP id _Ch0CgAnB1TwjM9p8K_UDA--.49742S4; Fri, 03 Apr 2026 17:48:48 +0800 (CST) From: Tengda Wu To: Peter Zijlstra , Namhyung Kim , leo.yan@linux.dev, Li Huafei , Ian Rogers , Kim Phillips , Mark Rutland , Arnaldo Carvalho de Melo , Ingo Molnar Cc: Bill Wendling , Nick Desaulniers , Alexander Shishkin , Adrian Hunter , Zecheng Li , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, llvm@lists.linux.dev, Tengda Wu Subject: [PATCH v2 02/16] perf capstone: Fix arm64 jump/adrp disassembly mismatch with objdump Date: Fri, 3 Apr 2026 09:47:46 +0000 Message-Id: <20260403094800.1418825-3-wutengda@huaweicloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260403094800.1418825-1-wutengda@huaweicloud.com> References: <20260403094800.1418825-1-wutengda@huaweicloud.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _Ch0CgAnB1TwjM9p8K_UDA--.49742S4 X-Coremail-Antispam: 1UD129KBjvJXoWxtF4rKFyrWF1xJF15Cw1UAwb_yoW7ZFy8pw 4DCw15Jws5Xr1fWws3Ga1kXw1Y9rWfXF1Yk3yxK39akrnayrn3XFWxKFya9Fn8Gry8Gw42 yFs0vF15Wrn5JrJanT9S1TB71UUUUUDqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUQS14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_Jryl82xGYIkIc2 x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2z4x0 Y4vE2Ix0cI8IcVAFwI0_tr0E3s1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Gr1j6F4UJw A2z4x0Y4vEx4A2jsIE14v26rxl6s0DM28EF7xvwVC2z280aVCY1x0267AKxVW0oVCq3wAS 0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7IYx2 IY67AKxVWUGVWUXwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r4UM4x0 Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwACI402YVCY1x02628vn2kIc2 xKxwCY1x0262kKe7AKxVW8ZVWrXwCY1x0264kExVAvwVAq07x20xyl42xK82IYc2Ij64vI r41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s026x8Gjc xK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r4a6rW5MIIYrxkI7VAKI48JMIIF0xvE2Ix0 cI8IcVAFwI0_Gr0_Xr1lIxAIcVC0I7IYx2IY6xkF7I0E14v26r4UJVWxJr1lIxAIcVCF04 k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r4j6F4UMIIF0xvEx4A2jsIEc7Cj xVAFwI0_Gr1j6F4UJbIYCTnIWIevJa73UjIFyTuYvjTRXwIDUUUUU X-CM-SenderInfo: pzxwv0hjgdqx5xdzvxpfor3voofrz/ Content-Type: text/plain; charset="utf-8" The jump and adrp instructions parsed by libcapstone currently lack symbolic representation and use a '#' prefix for addresses. This format is inconsistent with objdump's output, which causes subsequent parsing in jump__parse() and arm64_mov__parse() to fail. Example mismatch: Current: b #0xffff8000800114c8 Fix: b ffff8000800114c8 Current: adrp x18, #0xffff800081f5f000 Fix: adrp x18, ffff800081f5f000 Fix this by implementing extended formatting for these arm64 instructions during symbol__disassemble_capstone(). This ensures the output matches objdump's expected style, including the raw address and the associated suffix. Signed-off-by: Tengda Wu --- tools/perf/util/capstone.c | 107 ++++++++++++++++++++++++++++++++----- tools/perf/util/disasm.c | 5 ++ tools/perf/util/disasm.h | 1 + 3 files changed, 101 insertions(+), 12 deletions(-) diff --git a/tools/perf/util/capstone.c b/tools/perf/util/capstone.c index 25cf6e15ec27..1d8421d2d98c 100644 --- a/tools/perf/util/capstone.c +++ b/tools/perf/util/capstone.c @@ -255,10 +255,6 @@ static void print_capstone_detail(struct cs_insn *insn= , char *buf, size_t len, struct map *map =3D args->ms->map; struct symbol *sym; =20 - /* TODO: support more architectures */ - if (!arch__is_x86(args->arch)) - return; - if (insn->detail =3D=3D NULL) return; =20 @@ -305,6 +301,98 @@ static void print_capstone_detail(struct cs_insn *insn= , char *buf, size_t len, } } =20 +static void format_capstone_insn_x86(struct cs_insn *insn, char *buf, + size_t len, struct annotate_args *args, + u64 addr) +{ + int printed; + + printed =3D scnprintf(buf, len, " %-7s %s", + insn->mnemonic, insn->op_str); + buf +=3D printed; + len -=3D printed; + + print_capstone_detail(insn, buf, len, args, addr); +} + +static void format_capstone_insn_arm64(struct cs_insn *insn, char *buf, + size_t len, struct annotate_args *args, + u64 addr) +{ + struct map *map =3D args->ms->map; + struct symbol *sym; + char *last_imm, *endptr; + u64 orig_addr; + + scnprintf(buf, len, " %-7s %s", + insn->mnemonic, insn->op_str); + /* + * Adjust instructions to keep the existing behavior with objdump. + * + * Example conversion: + * From: b #0xffff8000800114c8 + * To: b ffff8000800114c8 + */ + switch (insn->id) { + case ARM64_INS_B: + case ARM64_INS_BL: + case ARM64_INS_CBNZ: + case ARM64_INS_CBZ: + case ARM64_INS_TBNZ: + case ARM64_INS_TBZ: + case ARM64_INS_ADRP: + /* Extract last immediate value as address */ + last_imm =3D strrchr(buf, '#'); + if (!last_imm) + return; + + orig_addr =3D strtoull(last_imm + 1, &endptr, 16); + if (endptr =3D=3D last_imm + 1) + return; + + /* Relocate map that contains the address */ + if (dso__kernel(map__dso(map))) { + map =3D maps__find(map__kmaps(map), orig_addr); + if (map =3D=3D NULL) + return; + } + + /* Convert it to map-relative address for search */ + addr =3D map__map_ip(map, orig_addr); + + sym =3D map__find_symbol(map, addr); + if (sym =3D=3D NULL) + return; + + /* Symbolize the resolved address */ + len =3D len - (last_imm - buf); + if (addr =3D=3D sym->start) { + scnprintf(last_imm, len, "%"PRIx64" <%s>", + orig_addr, sym->name); + } else { + scnprintf(last_imm, len, "%"PRIx64" <%s+%#"PRIx64">", + orig_addr, sym->name, addr - sym->start); + } + break; + default: + break; + } +} + +static void format_capstone_insn(struct cs_insn *insn, char *buf, size_t l= en, + struct annotate_args *args, u64 addr) +{ + /* TODO: support more architectures */ + if (arch__is_x86(args->arch)) + format_capstone_insn_x86(insn, buf, len, args, addr); + else if (arch__is_arm64(args->arch)) + format_capstone_insn_arm64(insn, buf, len, args, addr); + else { + scnprintf(buf, len, " %-7s %s", + insn->mnemonic, insn->op_str); + } +} + struct find_file_offset_data { u64 ip; u64 offset; @@ -381,14 +469,9 @@ int symbol__disassemble_capstone(const char *filename = __maybe_unused, =20 free_count =3D count =3D perf_cs_disasm(handle, buf, buf_len, start, buf_= len, &insn); for (i =3D 0, offset =3D 0; i < count; i++) { - int printed; - - printed =3D scnprintf(disasm_buf, sizeof(disasm_buf), - " %-7s %s", - insn[i].mnemonic, insn[i].op_str); - print_capstone_detail(&insn[i], disasm_buf + printed, - sizeof(disasm_buf) - printed, args, - start + offset); + format_capstone_insn(&insn[i], disasm_buf, + sizeof(disasm_buf), args, + start + offset); =20 args->offset =3D offset; args->line =3D disasm_buf; diff --git a/tools/perf/util/disasm.c b/tools/perf/util/disasm.c index 40fcaed5d0b1..988b2b748e11 100644 --- a/tools/perf/util/disasm.c +++ b/tools/perf/util/disasm.c @@ -202,6 +202,11 @@ bool arch__is_powerpc(const struct arch *arch) return arch->id.e_machine =3D=3D EM_PPC || arch->id.e_machine =3D=3D EM_P= PC64; } =20 +bool arch__is_arm64(const struct arch *arch) +{ + return arch->id.e_machine =3D=3D EM_AARCH64; +} + static void ins_ops__delete(struct ins_operands *ops) { if (ops =3D=3D NULL) diff --git a/tools/perf/util/disasm.h b/tools/perf/util/disasm.h index a6e478caf61a..d3730ed86dba 100644 --- a/tools/perf/util/disasm.h +++ b/tools/perf/util/disasm.h @@ -111,6 +111,7 @@ struct annotate_args { const struct arch *arch__find(uint16_t e_machine, uint32_t e_flags, const = char *cpuid); bool arch__is_x86(const struct arch *arch); bool arch__is_powerpc(const struct arch *arch); +bool arch__is_arm64(const struct arch *arch); =20 extern const struct ins_ops call_ops; extern const struct ins_ops dec_ops; --=20 2.34.1 From nobody Sun Jun 14 14:34:19 2026 Received: from dggsgout11.his.huawei.com (dggsgout11.his.huawei.com [45.249.212.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1AF5E379EF2; Fri, 3 Apr 2026 09:48:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.51 ARC-Seal: i=1; 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spf=pass smtp.mailfrom=huaweicloud.com Received: from mail.maildlp.com (unknown [172.19.163.198]) by dggsgout11.his.huawei.com (SkyGuard) with ESMTPS id 4fnDS76nTDzYQttc; Fri, 3 Apr 2026 17:48:23 +0800 (CST) Received: from mail02.huawei.com (unknown [10.116.40.252]) by mail.maildlp.com (Postfix) with ESMTP id 5CCD040575; Fri, 3 Apr 2026 17:48:49 +0800 (CST) Received: from huawei.com (unknown [10.67.174.45]) by APP3 (Coremail) with SMTP id _Ch0CgAnB1TwjM9p8K_UDA--.49742S5; Fri, 03 Apr 2026 17:48:49 +0800 (CST) From: Tengda Wu To: Peter Zijlstra , Namhyung Kim , leo.yan@linux.dev, Li Huafei , Ian Rogers , Kim Phillips , Mark Rutland , Arnaldo Carvalho de Melo , Ingo Molnar Cc: Bill Wendling , Nick Desaulniers , Alexander Shishkin , Adrian Hunter , Zecheng Li , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, llvm@lists.linux.dev, Tengda Wu Subject: [PATCH v2 03/16] perf annotate-arm64: Generalize arm64_mov__parse to support standard operands Date: Fri, 3 Apr 2026 09:47:47 +0000 Message-Id: <20260403094800.1418825-4-wutengda@huaweicloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260403094800.1418825-1-wutengda@huaweicloud.com> References: <20260403094800.1418825-1-wutengda@huaweicloud.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _Ch0CgAnB1TwjM9p8K_UDA--.49742S5 X-Coremail-Antispam: 1UD129KBjvJXoWxCr48ArWDJr4UKFyDAF1xAFb_yoWrJryrpw 4qk34DKr48KrZ5Kw43JanYqryfWwsag3yfWFyxtwn5Aw4fKryrJ3Z3KF12kFs5GFy8CrWU JFnYyr15CF4UGaDanT9S1TB71UUUUUDqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUQS14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_JrWl82xGYIkIc2 x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2z4x0 Y4vE2Ix0cI8IcVAFwI0_tr0E3s1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Gr1j6F4UJw A2z4x0Y4vEx4A2jsIE14v26rxl6s0DM28EF7xvwVC2z280aVCY1x0267AKxVW0oVCq3wAS 0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7IYx2 IY67AKxVWUGVWUXwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r4UM4x0 Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwACI402YVCY1x02628vn2kIc2 xKxwCY1x0262kKe7AKxVW8ZVWrXwCY1x0264kExVAvwVAq07x20xyl42xK82IYc2Ij64vI r41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s026x8Gjc xK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r4a6rW5MIIYrxkI7VAKI48JMIIF0xvE2Ix0 cI8IcVAFwI0_Xr0_Ar1lIxAIcVC0I7IYx2IY6xkF7I0E14v26r4UJVWxJr1lIxAIcVCF04 k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r4j6F4UMIIF0xvEx4A2jsIEc7Cj xVAFwI0_Gr1j6F4UJbIYCTnIWIevJa73UjIFyTuYvjTRXpnmUUUUU X-CM-SenderInfo: pzxwv0hjgdqx5xdzvxpfor3voofrz/ Content-Type: text/plain; charset="utf-8" The current arm64_mov__parse() implementation strictly requires the operand to contain a symbol suffix in the "" format. This causes the parser to fail for standard instructions that only contain raw immediates or registers without symbolic annotations. Refactor the function to make symbol matching optional. The parser now correctly extracts the target operand and only attempts to parse the "" suffix if it exists. This change also introduces better handling for whitespace and comments, and adds support for multi-register check via arm64__check_multi_regs(), ensuring compatibility with a wider range of arm64 instruction formats. Signed-off-by: Tengda Wu --- .../perf/util/annotate-arch/annotate-arm64.c | 85 ++++++++++++++----- 1 file changed, 65 insertions(+), 20 deletions(-) diff --git a/tools/perf/util/annotate-arch/annotate-arm64.c b/tools/perf/ut= il/annotate-arch/annotate-arm64.c index 33080fdca125..4c42323b0c18 100644 --- a/tools/perf/util/annotate-arch/annotate-arm64.c +++ b/tools/perf/util/annotate-arch/annotate-arm64.c @@ -14,12 +14,38 @@ struct arch_arm64 { regex_t jump_insn; }; =20 +static bool arm64__check_multi_regs(const char *op) +{ + char *comma =3D strchr(op, ','); + + while (comma) { + char *next =3D comma + 1; + + next =3D skip_spaces(next); + + /* + * Check the first valid character after the comma: + * - If it is '#', it indicates an immediate offset (e.g., [x1, #16]). + * - If it is an alphabetic character, it is highly likely a + * register name (e.g., x, w, s, d, q, v, p, z). + * - Special cases: Alias and control registers like sp, xzr, + * and wzr all start with an alphabetic character. + */ + if (*next && *next !=3D '#' && isalpha(*next)) + return true; + + comma =3D strchr(next, ','); + } + + return false; +} + static int arm64_mov__parse(const struct arch *arch __maybe_unused, struct ins_operands *ops, struct map_symbol *ms __maybe_unused, struct disasm_line *dl __maybe_unused) { - char *s =3D strchr(ops->raw, ','), *target, *endptr; + char *s =3D strchr(ops->raw, ','), *target, *endptr, *comment, prev; =20 if (s =3D=3D NULL) return -1; @@ -31,29 +57,48 @@ static int arm64_mov__parse(const struct arch *arch __m= aybe_unused, if (ops->source.raw =3D=3D NULL) return -1; =20 - target =3D ++s; + target =3D skip_spaces(++s); + comment =3D strchr(s, arch->objdump.comment_char); + + if (comment !=3D NULL) + s =3D comment - 1; + else + s =3D strchr(s, '\0') - 1; + + while (s > target && isspace(s[0])) + --s; + s++; + prev =3D *s; + *s =3D '\0'; ops->target.raw =3D strdup(target); + *s =3D prev; + if (ops->target.raw =3D=3D NULL) goto out_free_source; =20 - ops->target.addr =3D strtoull(target, &endptr, 16); - if (endptr =3D=3D target) - goto out_free_target; - - s =3D strchr(endptr, '<'); - if (s =3D=3D NULL) - goto out_free_target; - endptr =3D strchr(s + 1, '>'); - if (endptr =3D=3D NULL) - goto out_free_target; - - *endptr =3D '\0'; - *s =3D ' '; - ops->target.name =3D strdup(s); - *s =3D '<'; - *endptr =3D '>'; - if (ops->target.name =3D=3D NULL) - goto out_free_target; + ops->target.multi_regs =3D arm64__check_multi_regs(ops->target.raw); + + /* Parse address followed by symbol name, e.g. "addr " */ + if (strchr(target, '<') !=3D NULL) { + ops->target.addr =3D strtoull(target, &endptr, 16); + if (endptr =3D=3D target) + goto out_free_target; + + s =3D strchr(endptr, '<'); + if (s =3D=3D NULL) + goto out_free_target; + endptr =3D strchr(s + 1, '>'); + if (endptr =3D=3D NULL) + goto out_free_target; + + *endptr =3D '\0'; + *s =3D ' '; + ops->target.name =3D strdup(s); + *s =3D '<'; + *endptr =3D '>'; + if (ops->target.name =3D=3D NULL) + goto out_free_target; + } =20 return 0; =20 --=20 2.34.1 From nobody Sun Jun 14 14:34:19 2026 Received: from dggsgout11.his.huawei.com (dggsgout11.his.huawei.com [45.249.212.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 59BDF396B7F; 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dmarc=none (p=none dis=none) header.from=huaweicloud.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huaweicloud.com Received: from mail.maildlp.com (unknown [172.19.163.170]) by dggsgout11.his.huawei.com (SkyGuard) with ESMTPS id 4fnDS806GgzYQttW; Fri, 3 Apr 2026 17:48:24 +0800 (CST) Received: from mail02.huawei.com (unknown [10.116.40.252]) by mail.maildlp.com (Postfix) with ESMTP id 6DE2740573; Fri, 3 Apr 2026 17:48:49 +0800 (CST) Received: from huawei.com (unknown [10.67.174.45]) by APP3 (Coremail) with SMTP id _Ch0CgAnB1TwjM9p8K_UDA--.49742S6; Fri, 03 Apr 2026 17:48:49 +0800 (CST) From: Tengda Wu To: Peter Zijlstra , Namhyung Kim , leo.yan@linux.dev, Li Huafei , Ian Rogers , Kim Phillips , Mark Rutland , Arnaldo Carvalho de Melo , Ingo Molnar Cc: Bill Wendling , Nick Desaulniers , Alexander Shishkin , Adrian Hunter , Zecheng Li , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, llvm@lists.linux.dev, Tengda Wu Subject: [PATCH v2 04/16] perf annotate-arm64: Handle load and store instructions Date: Fri, 3 Apr 2026 09:47:48 +0000 Message-Id: <20260403094800.1418825-5-wutengda@huaweicloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260403094800.1418825-1-wutengda@huaweicloud.com> References: <20260403094800.1418825-1-wutengda@huaweicloud.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _Ch0CgAnB1TwjM9p8K_UDA--.49742S6 X-Coremail-Antispam: 1UD129KBjvJXoWxXw4ftrWUGr4ruFWfZr1xGrg_yoWrZr1kpa nFk345Jr4UWr4Fg3WfXFsru34fKw4UJw1a9ry8J3s3Ca4Ivr97tF4kKr1akF4rGrWkCw4U XFn0vry8Wry5ArJanT9S1TB71UUUUUDqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUQm14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_JF0E3s1l82xGYI kIc2x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2 z4x0Y4vE2Ix0cI8IcVAFwI0_tr0E3s1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Gr1j6F 4UJwA2z4x0Y4vEx4A2jsIE14v26rxl6s0DM28EF7xvwVC2z280aVCY1x0267AKxVW0oVCq 3wAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7 IYx2IY67AKxVWUGVWUXwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r4U M4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwACI402YVCY1x02628vn2 kIc2xKxwCY1x0262kKe7AKxVW8ZVWrXwCY1x0264kExVAvwVAq07x20xyl42xK82IYc2Ij 64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s026x 8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r4a6rW5MIIYrxkI7VAKI48JMIIF0xvE 2Ix0cI8IcVAFwI0_Xr0_Ar1lIxAIcVC0I7IYx2IY6xkF7I0E14v26r4UJVWxJr1lIxAIcV CF04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r4j6F4UMIIF0xvEx4A2jsIE c7CjxVAFwI0_Gr1j6F4UJbIYCTnIWIevJa73UjIFyTuYvjTRGMKuUUUUU X-CM-SenderInfo: pzxwv0hjgdqx5xdzvxpfor3voofrz/ Content-Type: text/plain; charset="utf-8" Add ldst_ops to handle load and store instructions in order to parse the data types and offsets associated with PMU events for memory access instructions. There are many variants of load and store instructions in ARM64, making it difficult to match all of these instruction names completely. Therefore, only the instruction prefixes are matched. The prefix 'ld|st' covers most of the memory access instructions, 'cas|swp' matches atomic instructions, and 'prf' matches memory prefetch instructions. Signed-off-by: Li Huafei Signed-off-by: Tengda Wu --- .../perf/util/annotate-arch/annotate-arm64.c | 72 +++++++++++++++++++ 1 file changed, 72 insertions(+) diff --git a/tools/perf/util/annotate-arch/annotate-arm64.c b/tools/perf/ut= il/annotate-arch/annotate-arm64.c index 4c42323b0c18..8209faaa6086 100644 --- a/tools/perf/util/annotate-arch/annotate-arm64.c +++ b/tools/perf/util/annotate-arch/annotate-arm64.c @@ -3,7 +3,9 @@ #include #include #include +#include #include +#include #include #include "../annotate.h" #include "../disasm.h" @@ -12,6 +14,7 @@ struct arch_arm64 { struct arch arch; regex_t call_insn; regex_t jump_insn; + regex_t ldst_insn; /* load and store instruction */ }; =20 static bool arm64__check_multi_regs(const char *op) @@ -114,6 +117,59 @@ static const struct ins_ops arm64_mov_ops =3D { .scnprintf =3D mov__scnprintf, }; =20 +static int arm64_ldst__parse(const struct arch *arch __maybe_unused, + struct ins_operands *ops, + struct map_symbol *ms __maybe_unused, + struct disasm_line *dl __maybe_unused) +{ + char *s, *target; + + /* + * The part starting from the memory access annotation '[' is parsed + * as 'target', while the part before it is parsed as 'source'. + */ + target =3D s =3D strchr(ops->raw, arch->objdump.memory_ref_char); + if (!s) + return -1; + + while (s > ops->raw && *s !=3D ',') + --s; + + if (s =3D=3D ops->raw) + return -1; + + *s =3D '\0'; + ops->source.raw =3D strdup(ops->raw); + + *s =3D ','; + if (!ops->source.raw) + return -1; + + ops->source.multi_regs =3D arm64__check_multi_regs(ops->source.raw); + + ops->target.raw =3D strdup(target); + if (!ops->target.raw) { + zfree(&ops->source.raw); + return -1; + } + ops->target.mem_ref =3D true; + ops->target.multi_regs =3D arm64__check_multi_regs(ops->target.raw); + + return 0; +} + +static int arm64_ldst__scnprintf(const struct ins *ins, char *bf, size_t s= ize, + struct ins_operands *ops, int max_ins_name) +{ + return scnprintf(bf, size, "%-*s %s,%s", max_ins_name, ins->name, + ops->source.raw, ops->target.raw); +} + +static struct ins_ops arm64_ldst_ops =3D { + .parse =3D arm64_ldst__parse, + .scnprintf =3D arm64_ldst__scnprintf, +}; + static const struct ins_ops *arm64__associate_instruction_ops(struct arch = *arch, const char *name) { struct arch_arm64 *arm =3D container_of(arch, struct arch_arm64, arch); @@ -124,6 +180,8 @@ static const struct ins_ops *arm64__associate_instructi= on_ops(struct arch *arch, ops =3D &jump_ops; else if (!regexec(&arm->call_insn, name, 2, match, 0)) ops =3D &call_ops; + else if (!regexec(&arm->ldst_insn, name, 2, match, 0)) + ops =3D &arm64_ldst_ops; else if (!strcmp(name, "ret")) ops =3D &ret_ops; else @@ -148,6 +206,8 @@ const struct arch *arch__new_arm64(const struct e_machi= ne_and_e_flags *id, arch->id =3D *id; arch->objdump.comment_char =3D '/'; arch->objdump.skip_functions_char =3D '+'; + arch->objdump.memory_ref_char =3D '['; + arch->objdump.imm_char =3D '#'; arch->associate_instruction_ops =3D arm64__associate_instruction_ops; =20 /* bl, blr */ @@ -161,8 +221,20 @@ const struct arch *arch__new_arm64(const struct e_mach= ine_and_e_flags *id, if (err) goto out_free_call; =20 + /* + * The ARM64 architecture has many variants of load/store instructions. + * It is quite challenging to match all of them completely. Here, we + * only match the prefixes of these instructions. + */ + err =3D regcomp(&arm->ldst_insn, "^(ld|st|cas|prf|swp)", + REG_EXTENDED); + if (err) + goto out_free_jump; + return arch; =20 +out_free_jump: + regfree(&arm->jump_insn); out_free_call: regfree(&arm->call_insn); out_free_arm: --=20 2.34.1 From nobody Sun Jun 14 14:34:19 2026 Received: from dggsgout11.his.huawei.com (dggsgout11.his.huawei.com [45.249.212.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8A2A539769B; Fri, 3 Apr 2026 09:48:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775209741; cv=none; b=Nar+wqCen+VsgR4pLkaX3emEamTallezswk6u5iFtWWOhwvTC3Vj0TF0kBBOIa6UQ2F6tY0UQLtyagPEHg9d9GIhS75GO0K3jQ4/6gA6rw4aqarlyeu9o38WlDqpmSLeoGE+CKkw+ZWFSh+/ARQ9lEFEJ4Gt/1vueM0axbHKEDc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775209741; c=relaxed/simple; bh=l+GBruTgRRKT9WRInpqaaEMpoWeOzWVnxd7MPQTPdqE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=u4Mdwd28WmgZZqkXY6x4rnZ+eFznl93Qc9DTXlXs1z/zntlErsQdXaKk/dQOdhT6tpAlIZsu2olWR7XEEZLdU9Ph7zrfxUHLGYAtQ8b7yNcEiCU7V56YfkwCNAXWZJKMeXE8sdClvaAblEBVGkWm0WnR3R29XqHs/zNLx/e3cQQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=huaweicloud.com; spf=pass smtp.mailfrom=huaweicloud.com; arc=none smtp.client-ip=45.249.212.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=huaweicloud.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huaweicloud.com Received: from mail.maildlp.com (unknown [172.19.163.170]) by dggsgout11.his.huawei.com (SkyGuard) with ESMTPS id 4fnDS80pRwzYQtv2; Fri, 3 Apr 2026 17:48:24 +0800 (CST) Received: from mail02.huawei.com (unknown [10.116.40.252]) by mail.maildlp.com (Postfix) with ESMTP id 8636C4056F; Fri, 3 Apr 2026 17:48:49 +0800 (CST) Received: from huawei.com (unknown [10.67.174.45]) by APP3 (Coremail) with SMTP id _Ch0CgAnB1TwjM9p8K_UDA--.49742S7; Fri, 03 Apr 2026 17:48:49 +0800 (CST) From: Tengda Wu To: Peter Zijlstra , Namhyung Kim , leo.yan@linux.dev, Li Huafei , Ian Rogers , Kim Phillips , Mark Rutland , Arnaldo Carvalho de Melo , Ingo Molnar Cc: Bill Wendling , Nick Desaulniers , Alexander Shishkin , Adrian Hunter , Zecheng Li , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, llvm@lists.linux.dev, Tengda Wu Subject: [PATCH v2 05/16] perf annotate: Introduce extract_op_location callback for arch-specific parsing Date: Fri, 3 Apr 2026 09:47:49 +0000 Message-Id: <20260403094800.1418825-6-wutengda@huaweicloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260403094800.1418825-1-wutengda@huaweicloud.com> References: <20260403094800.1418825-1-wutengda@huaweicloud.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _Ch0CgAnB1TwjM9p8K_UDA--.49742S7 X-Coremail-Antispam: 1UD129KBjvJXoWxtr13tF4kJw4kuF18Kw4UArb_yoWDGF4fpw 4Du34Yyr1rKr4YqwsrXFs5W3Wakw4rWF1Y9r47K39rAFn2yrn5Jan2gF1avF1rtrZxur1j vF4qvrW8XryrGaDanT9S1TB71UUUUUDqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUQm14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_JF0E3s1l82xGYI kIc2x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2 z4x0Y4vE2Ix0cI8IcVAFwI0_tr0E3s1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Gr1j6F 4UJwA2z4x0Y4vEx4A2jsIE14v26rxl6s0DM28EF7xvwVC2z280aVCY1x0267AKxVW0oVCq 3wAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7 IYx2IY67AKxVWUGVWUXwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r4U M4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwACI402YVCY1x02628vn2 kIc2xKxwCY1x0262kKe7AKxVW8ZVWrXwCY1x0264kExVAvwVAq07x20xyl42xK82IYc2Ij 64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s026x 8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r4a6rW5MIIYrxkI7VAKI48JMIIF0xvE 2Ix0cI8IcVAFwI0_Xr0_Ar1lIxAIcVC0I7IYx2IY6xkF7I0E14v26r4UJVWxJr1lIxAIcV CF04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r4j6F4UMIIF0xvEx4A2jsIE c7CjxVAFwI0_Gr1j6F4UJbIYCTnIWIevJa73UjIFyTuYvjTRGMKuUUUUU X-CM-SenderInfo: pzxwv0hjgdqx5xdzvxpfor3voofrz/ Content-Type: text/plain; charset="utf-8" Assembly syntax for operands varies significantly across different architectures, which prevents the operand location (op_loc) parsing logic in annotate_get_insn_location() from being directly reused. To simplify the core logic and improve maintainability, move the operand parsing inside the for_each_insn_op_loc loop into arch-specific extract_op_location callbacks. This refactoring is intended to be a cleanup with no functional changes. Signed-off-by: Li Huafei Signed-off-by: Tengda Wu --- .../util/annotate-arch/annotate-powerpc.c | 10 ++ tools/perf/util/annotate-arch/annotate-x86.c | 82 ++++++++++++++++ tools/perf/util/annotate.c | 96 ++----------------- tools/perf/util/annotate.h | 2 + tools/perf/util/disasm.h | 4 + 5 files changed, 105 insertions(+), 89 deletions(-) diff --git a/tools/perf/util/annotate-arch/annotate-powerpc.c b/tools/perf/= util/annotate-arch/annotate-powerpc.c index 218207b52581..8d0b8def5955 100644 --- a/tools/perf/util/annotate-arch/annotate-powerpc.c +++ b/tools/perf/util/annotate-arch/annotate-powerpc.c @@ -390,6 +390,15 @@ static void update_insn_state_powerpc(struct type_stat= e *state, } #endif /* HAVE_LIBDW_SUPPORT */ =20 +static int extract_op_location_powerpc(const struct arch *arch __maybe_unu= sed, + struct disasm_line *dl, + const char *op_str __maybe_unused, int op_idx, + struct annotated_op_loc *op_loc) +{ + get_powerpc_regs(dl->raw.raw_insn, !op_idx, op_loc); + return 0; +} + const struct arch *arch__new_powerpc(const struct e_machine_and_e_flags *i= d, const char *cpuid __maybe_unused) { @@ -406,5 +415,6 @@ const struct arch *arch__new_powerpc(const struct e_mac= hine_and_e_flags *id, #ifdef HAVE_LIBDW_SUPPORT arch->update_insn_state =3D update_insn_state_powerpc; #endif + arch->extract_op_location =3D extract_op_location_powerpc; return arch; } diff --git a/tools/perf/util/annotate-arch/annotate-x86.c b/tools/perf/util= /annotate-arch/annotate-x86.c index c77aabd48eba..c63ca3250b95 100644 --- a/tools/perf/util/annotate-arch/annotate-x86.c +++ b/tools/perf/util/annotate-arch/annotate-x86.c @@ -3,6 +3,7 @@ #include #include #include +#include #include "../annotate-data.h" #include "../debug.h" #include "../disasm.h" @@ -808,6 +809,86 @@ static void update_insn_state_x86(struct type_state *s= tate, } #endif =20 +/* + * Get register number and access offset from the given instruction. + * It assumes AT&T x86 asm format like OFFSET(REG). Maybe it needs + * to revisit the format when it handles different architecture. + * Fills @reg and @offset when return 0. + */ +static int extract_reg_offset(const struct arch *arch, const char *str, + struct annotated_op_loc *op_loc) +{ + char *p; + + if (arch->objdump.register_char =3D=3D 0) + return -1; + + /* + * It should start from offset, but it's possible to skip 0 + * in the asm. So 0(%rax) should be same as (%rax). + * + * However, it also start with a segment select register like + * %gs:0x18(%rbx). In that case it should skip the part. + */ + if (*str =3D=3D arch->objdump.register_char) { + /* FIXME: Handle other segment registers */ + if (!strncmp(str, "%gs:", 4)) + op_loc->segment =3D INSN_SEG_X86_GS; + + while (*str && !isdigit(*str) && + *str !=3D arch->objdump.memory_ref_char) + str++; + } + + op_loc->offset =3D strtol(str, &p, 0); + op_loc->reg1 =3D arch__dwarf_regnum(arch, p); + if (op_loc->reg1 =3D=3D -1) + return -1; + + /* Get the second register */ + if (op_loc->multi_regs) + op_loc->reg2 =3D arch__dwarf_regnum(arch, p + 1); + + return 0; +} + +static int extract_op_location_x86(const struct arch *arch, + struct disasm_line *dl __maybe_unused, + const char *op_str, int op_idx __maybe_unused, + struct annotated_op_loc *op_loc) +{ + const char *s =3D op_str; + char *p =3D NULL; + + if (op_str =3D=3D NULL) + return 0; + + if (strchr(op_str, arch->objdump.memory_ref_char)) { + op_loc->mem_ref =3D true; + return extract_reg_offset(arch, op_str, op_loc); + } + + /* FIXME: Handle other segment registers */ + if (!strncmp(op_str, "%gs:", 4)) { + op_loc->segment =3D INSN_SEG_X86_GS; + op_loc->offset =3D strtol(op_str + 4, + &p, 0); + if (p && p !=3D op_str + 4) + op_loc->imm =3D true; + return 0; + } + + if (*s =3D=3D arch->objdump.register_char) { + op_loc->reg1 =3D arch__dwarf_regnum(arch, s); + } else if (*s =3D=3D arch->objdump.imm_char) { + op_loc->offset =3D strtol(s + 1, &p, 0); + if (p && p !=3D s + 1) + op_loc->imm =3D true; + } + + return 0; +} + const struct arch *arch__new_x86(const struct e_machine_and_e_flags *id, c= onst char *cpuid) { struct arch *arch =3D zalloc(sizeof(*arch)); @@ -847,5 +928,6 @@ const struct arch *arch__new_x86(const struct e_machine= _and_e_flags *id, const c #ifdef HAVE_LIBDW_SUPPORT arch->update_insn_state =3D update_insn_state_x86; #endif + arch->extract_op_location =3D extract_op_location_x86; return arch; } diff --git a/tools/perf/util/annotate.c b/tools/perf/util/annotate.c index 63f0ee9d4c03..1bf69e00d76d 100644 --- a/tools/perf/util/annotate.c +++ b/tools/perf/util/annotate.c @@ -2450,7 +2450,7 @@ int annotate_check_args(void) return 0; } =20 -static int arch__dwarf_regnum(const struct arch *arch, const char *str) +int arch__dwarf_regnum(const struct arch *arch, const char *str) { const char *p; char *regname, *q; @@ -2473,51 +2473,6 @@ static int arch__dwarf_regnum(const struct arch *arc= h, const char *str) return reg; } =20 -/* - * Get register number and access offset from the given instruction. - * It assumes AT&T x86 asm format like OFFSET(REG). Maybe it needs - * to revisit the format when it handles different architecture. - * Fills @reg and @offset when return 0. - */ -static int extract_reg_offset(const struct arch *arch, const char *str, - struct annotated_op_loc *op_loc) -{ - char *p; - - if (arch->objdump.register_char =3D=3D 0) - return -1; - - /* - * It should start from offset, but it's possible to skip 0 - * in the asm. So 0(%rax) should be same as (%rax). - * - * However, it also start with a segment select register like - * %gs:0x18(%rbx). In that case it should skip the part. - */ - if (*str =3D=3D arch->objdump.register_char) { - if (arch__is_x86(arch)) { - /* FIXME: Handle other segment registers */ - if (!strncmp(str, "%gs:", 4)) - op_loc->segment =3D INSN_SEG_X86_GS; - } - - while (*str && !isdigit(*str) && - *str !=3D arch->objdump.memory_ref_char) - str++; - } - - op_loc->offset =3D strtol(str, &p, 0); - op_loc->reg1 =3D arch__dwarf_regnum(arch, p); - if (op_loc->reg1 =3D=3D -1) - return -1; - - /* Get the second register */ - if (op_loc->multi_regs) - op_loc->reg2 =3D arch__dwarf_regnum(arch, p + 1); - - return 0; -} - /** * annotate_get_insn_location - Get location of instruction * @arch: the architecture info @@ -2548,6 +2503,7 @@ int annotate_get_insn_location(const struct arch *arc= h, struct disasm_line *dl, struct ins_operands *ops; struct annotated_op_loc *op_loc; int i; + int ret; =20 if (ins__is_lock(&dl->ins)) ops =3D dl->ops.locked.ops; @@ -2573,50 +2529,12 @@ int annotate_get_insn_location(const struct arch *a= rch, struct disasm_line *dl, /* Invalidate the register by default */ op_loc->reg1 =3D -1; op_loc->reg2 =3D -1; + op_loc->mem_ref =3D mem_ref; + op_loc->multi_regs =3D multi_regs; =20 - if (insn_str =3D=3D NULL) { - if (!arch__is_powerpc(arch)) - continue; - } - - /* - * For powerpc, call get_powerpc_regs function which extracts the - * required fields for op_loc, ie reg1, reg2, offset from the - * raw instruction. - */ - if (arch__is_powerpc(arch)) { - op_loc->mem_ref =3D mem_ref; - op_loc->multi_regs =3D multi_regs; - get_powerpc_regs(dl->raw.raw_insn, !i, op_loc); - } else if (strchr(insn_str, arch->objdump.memory_ref_char)) { - op_loc->mem_ref =3D true; - op_loc->multi_regs =3D multi_regs; - extract_reg_offset(arch, insn_str, op_loc); - } else { - const char *s =3D insn_str; - char *p =3D NULL; - - if (arch__is_x86(arch)) { - /* FIXME: Handle other segment registers */ - if (!strncmp(insn_str, "%gs:", 4)) { - op_loc->segment =3D INSN_SEG_X86_GS; - op_loc->offset =3D strtol(insn_str + 4, - &p, 0); - if (p && p !=3D insn_str + 4) - op_loc->imm =3D true; - continue; - } - } - - if (*s =3D=3D arch->objdump.register_char) { - op_loc->reg1 =3D arch__dwarf_regnum(arch, s); - } - else if (*s =3D=3D arch->objdump.imm_char) { - op_loc->offset =3D strtol(s + 1, &p, 0); - if (p && p !=3D s + 1) - op_loc->imm =3D true; - } - } + ret =3D arch->extract_op_location(arch, dl, insn_str, i, op_loc); + if (ret) + return ret; } =20 return 0; diff --git a/tools/perf/util/annotate.h b/tools/perf/util/annotate.h index 696e36dbf013..71195a27d38f 100644 --- a/tools/perf/util/annotate.h +++ b/tools/perf/util/annotate.h @@ -494,6 +494,8 @@ int annotate_parse_percent_type(const struct option *op= t, const char *_str, =20 int annotate_check_args(void); =20 +int arch__dwarf_regnum(const struct arch *arch, const char *str); + /** * struct annotated_op_loc - Location info of instruction operand * @reg1: First register in the operand diff --git a/tools/perf/util/disasm.h b/tools/perf/util/disasm.h index d3730ed86dba..94ee67bcbce7 100644 --- a/tools/perf/util/disasm.h +++ b/tools/perf/util/disasm.h @@ -16,6 +16,7 @@ struct symbol; struct data_loc_info; struct type_state; struct disasm_line; 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Fri, 3 Apr 2026 17:48:49 +0800 (CST) Received: from huawei.com (unknown [10.67.174.45]) by APP3 (Coremail) with SMTP id _Ch0CgAnB1TwjM9p8K_UDA--.49742S8; Fri, 03 Apr 2026 17:48:49 +0800 (CST) From: Tengda Wu To: Peter Zijlstra , Namhyung Kim , leo.yan@linux.dev, Li Huafei , Ian Rogers , Kim Phillips , Mark Rutland , Arnaldo Carvalho de Melo , Ingo Molnar Cc: Bill Wendling , Nick Desaulniers , Alexander Shishkin , Adrian Hunter , Zecheng Li , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, llvm@lists.linux.dev, Tengda Wu Subject: [PATCH v2 06/16] perf dwarf-regs: Adapt get_dwarf_regnum() for arm64 Date: Fri, 3 Apr 2026 09:47:50 +0000 Message-Id: <20260403094800.1418825-7-wutengda@huaweicloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260403094800.1418825-1-wutengda@huaweicloud.com> References: <20260403094800.1418825-1-wutengda@huaweicloud.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _Ch0CgAnB1TwjM9p8K_UDA--.49742S8 X-Coremail-Antispam: 1UD129KBjvJXoWxAFyxGrW7trWDGw1fGF4kJFb_yoW5Cw4xpF sxC347Jw4UW3WakwnxAF18WF1rJw48Zr4FyrW0vwsrCrsruFyUZw1fKr1j9F45X3yDJw10 kayqgr18Gr4rJF7anT9S1TB71UUUUUDqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUQm14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_JF0E3s1l82xGYI kIc2x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2 z4x0Y4vE2Ix0cI8IcVAFwI0_tr0E3s1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Gr1j6F 4UJwA2z4x0Y4vEx4A2jsIE14v26rxl6s0DM28EF7xvwVC2z280aVCY1x0267AKxVW0oVCq 3wAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7 IYx2IY67AKxVWUGVWUXwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r4U M4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwACI402YVCY1x02628vn2 kIc2xKxwCY1x0262kKe7AKxVW8ZVWrXwCY1x0264kExVAvwVAq07x20xyl42xK82IYc2Ij 64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s026x 8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r4a6rW5MIIYrxkI7VAKI48JMIIF0xvE 2Ix0cI8IcVAFwI0_Xr0_Ar1lIxAIcVC0I7IYx2IY6xkF7I0E14v26r4UJVWxJr1lIxAIcV CF04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r4j6F4UMIIF0xvEx4A2jsIE c7CjxVAFwI0_Gr1j6F4UJbIYCTnIWIevJa73UjIFyTuYvjTRGMKuUUUUU X-CM-SenderInfo: pzxwv0hjgdqx5xdzvxpfor3voofrz/ Content-Type: text/plain; charset="utf-8" The current arm64 DWARF register lookup relies on 'aarch64_regstr_tbl', a static string table. While this works for kprobe-tracer where register names start with '%', it is insufficient for parsing register numbers directly from raw instructions (e.g., extracting '6' from 'x6' or 'w6') during annotation. Since get_dwarf_regnum() is currently used only by 'perf annotate' and does not affect kprobe-tracer, replace the limited table-based lookup with a programmatic implementation in __get_dwarf_regnum_arm64(). This allows resolving arm64 register names (x0-x30, w0-w30, sp, etc.) directly into their corresponding DWARF register numbers. Signed-off-by: Tengda Wu --- .../util/dwarf-regs-arch/dwarf-regs-arm64.c | 20 +++++++++++++++++++ tools/perf/util/dwarf-regs.c | 2 +- tools/perf/util/include/dwarf-regs.h | 1 + 3 files changed, 22 insertions(+), 1 deletion(-) diff --git a/tools/perf/util/dwarf-regs-arch/dwarf-regs-arm64.c b/tools/per= f/util/dwarf-regs-arch/dwarf-regs-arm64.c index 593ca7d4fccc..be55fc2a4f38 100644 --- a/tools/perf/util/dwarf-regs-arch/dwarf-regs-arm64.c +++ b/tools/perf/util/dwarf-regs-arch/dwarf-regs-arm64.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 #include +#include #include #include "../../../arch/arm64/include/uapi/asm/perf_regs.h" =20 @@ -10,3 +11,22 @@ int __get_dwarf_regnum_for_perf_regnum_arm64(int perf_re= gnum) =20 return perf_regnum; } + +int __get_dwarf_regnum_arm64(const char *name) +{ + int reg; + + if (!strcmp(name, "sp") || !strcmp(name, "wzr") || !strcmp(name, "xzr")) + return 31; + + if (*name !=3D 'x' && *name !=3D 'w') + return -ENOENT; + + name++; + if (!isdigit(*name)) + return -ENOENT; + + reg =3D strtol(name, NULL, 10); + + return reg >=3D 0 && reg <=3D 30 ? reg : -ENOENT; +} diff --git a/tools/perf/util/dwarf-regs.c b/tools/perf/util/dwarf-regs.c index 797f455eba0d..bacf5c13c3bc 100644 --- a/tools/perf/util/dwarf-regs.c +++ b/tools/perf/util/dwarf-regs.c @@ -114,7 +114,7 @@ int get_dwarf_regnum(const char *name, unsigned int mac= hine, unsigned int flags) reg =3D _get_dwarf_regnum(arm_regstr_tbl, name); break; case EM_AARCH64: - reg =3D _get_dwarf_regnum(aarch64_regstr_tbl, name); + reg =3D __get_dwarf_regnum_arm64(name); break; case EM_CSKY: reg =3D __get_csky_regnum(name, flags); diff --git a/tools/perf/util/include/dwarf-regs.h b/tools/perf/util/include= /dwarf-regs.h index 46a764cf322f..a25f038bbff2 100644 --- a/tools/perf/util/include/dwarf-regs.h +++ b/tools/perf/util/include/dwarf-regs.h @@ -105,6 +105,7 @@ int __get_dwarf_regnum_x86_64(const char *name); int __get_dwarf_regnum_for_perf_regnum_i386(int perf_regnum); int __get_dwarf_regnum_for_perf_regnum_x86_64(int perf_regnum); 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Fri, 03 Apr 2026 17:48:49 +0800 (CST) From: Tengda Wu To: Peter Zijlstra , Namhyung Kim , leo.yan@linux.dev, Li Huafei , Ian Rogers , Kim Phillips , Mark Rutland , Arnaldo Carvalho de Melo , Ingo Molnar Cc: Bill Wendling , Nick Desaulniers , Alexander Shishkin , Adrian Hunter , Zecheng Li , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, llvm@lists.linux.dev, Tengda Wu Subject: [PATCH v2 07/16] perf annotate-arm64: Implement extract_op_location() callback Date: Fri, 3 Apr 2026 09:47:51 +0000 Message-Id: <20260403094800.1418825-8-wutengda@huaweicloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260403094800.1418825-1-wutengda@huaweicloud.com> References: <20260403094800.1418825-1-wutengda@huaweicloud.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _Ch0CgAnB1TwjM9p8K_UDA--.49742S9 X-Coremail-Antispam: 1UD129KBjvJXoWxKrykZrWkXF1rAryUKr4UJwb_yoW7Gw48pw 4j9343tr1Utr4Yqw1fZFs3WFy3Cw1fG3Wa9rWxCwsrZFs3Zr18Ja1xKF1a9a45JrZxu34j yF4DtrW8Zr15CaDanT9S1TB71UUUUUDqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUQm14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_JF0E3s1l82xGYI kIc2x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2 z4x0Y4vE2Ix0cI8IcVAFwI0_tr0E3s1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Gr1j6F 4UJwA2z4x0Y4vEx4A2jsIE14v26rxl6s0DM28EF7xvwVC2z280aVCY1x0267AKxVW0oVCq 3wAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7 IYx2IY67AKxVWUGVWUXwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r4U M4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwACI402YVCY1x02628vn2 kIc2xKxwCY1x0262kKe7AKxVW8ZVWrXwCY1x0264kExVAvwVAq07x20xyl42xK82IYc2Ij 64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s026x 8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r4a6rW5MIIYrxkI7VAKI48JMIIF0xvE 2Ix0cI8IcVAFwI0_Xr0_Ar1lIxAIcVC0I7IYx2IY6xkF7I0E14v26r4UJVWxJr1lIxAIcV CF04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r4j6F4UMIIF0xvEx4A2jsIE c7CjxVAFwI0_Gr1j6F4UJbIYCTnIWIevJa73UjIFyTuYvjTRGMKuUUUUU X-CM-SenderInfo: pzxwv0hjgdqx5xdzvxpfor3voofrz/ Content-Type: text/plain; charset="utf-8" Implement the extract_op_location() callback for the arm64 architecture to handle its specific assembly syntax and addressing modes. The extractor handles: 1. Standalone immediate operands (e.g., #0x10). 2. Memory references with diverse addressing modes: - Signed offset: [base, #imm] - Pre-index: [base, #imm]! - Post-index: [base], #imm 3. Multi-register operands and primary/secondary register extraction. This enables 'perf annotate' to resolve memory locations and registers required for data type profiling on arm64. Signed-off-by: Tengda Wu --- .../perf/util/annotate-arch/annotate-arm64.c | 64 +++++++++++++++++++ tools/perf/util/annotate.c | 12 ++-- tools/perf/util/annotate.h | 10 +++ 3 files changed, 81 insertions(+), 5 deletions(-) diff --git a/tools/perf/util/annotate-arch/annotate-arm64.c b/tools/perf/ut= il/annotate-arch/annotate-arm64.c index 8209faaa6086..1fe4c503431b 100644 --- a/tools/perf/util/annotate-arch/annotate-arm64.c +++ b/tools/perf/util/annotate-arch/annotate-arm64.c @@ -191,6 +191,69 @@ static const struct ins_ops *arm64__associate_instruct= ion_ops(struct arch *arch, return ops; } =20 +static int extract_op_location_arm64(const struct arch *arch, + struct disasm_line *dl __maybe_unused, + const char *op_str, int op_idx __maybe_unused, + struct annotated_op_loc *op_loc) +{ + const char *s =3D op_str; + char *p =3D NULL; + + if (op_str =3D=3D NULL) + return 0; + + /* Handle standalone immediate operands (e.g., #0x10) */ + if (*s =3D=3D arch->objdump.imm_char) { + op_loc->offset =3D strtol(s + 1, &p, 0); + if (p && p !=3D s + 1) + op_loc->imm =3D true; + return 0; + } + + /* + * Handle memory references (e.g., [x0, #8]), identify + * arm64 specific addressing modes + */ + if (*s =3D=3D arch->objdump.memory_ref_char) { + op_loc->mem_ref =3D true; + + p =3D strchr(s, ']'); + if (p =3D=3D NULL) + return -1; + + /* Pre-index: [base, #imm]! */ + if (p[1] =3D=3D '!') + op_loc->addr_mode =3D INSN_ADDR_PRE_INDEX; + /* Post-index: [base], #imm */ + else if (p[1] =3D=3D ',' && strchr(p + 1, arch->objdump.imm_char)) + op_loc->addr_mode =3D INSN_ADDR_POST_INDEX; + /* Signed offset: [base{, #imm}] */ + else + op_loc->addr_mode =3D INSN_ADDR_SIGNED_OFFSET; + + s++; + } + + /* Extract the primary register */ + op_loc->reg1 =3D arch__dwarf_regnum(arch, s); + if (op_loc->reg1 =3D=3D -1) + return -1; + + /* Move to the next symbol of the operand, if any */ + s =3D strchr(s, ','); + if (s =3D=3D NULL) + return 0; + s =3D skip_spaces(s + 1); + + /* Parse secondary register or immediate offset */ + if (op_loc->multi_regs) + op_loc->reg2 =3D arch__dwarf_regnum(arch, s); + else if (*s =3D=3D arch->objdump.imm_char) + op_loc->offset =3D strtol(s + 1, &p, 0); + + return 0; +} + const struct arch *arch__new_arm64(const struct e_machine_and_e_flags *id, const char *cpuid __maybe_unused) { @@ -209,6 +272,7 @@ const struct arch *arch__new_arm64(const struct e_machi= ne_and_e_flags *id, arch->objdump.memory_ref_char =3D '['; arch->objdump.imm_char =3D '#'; arch->associate_instruction_ops =3D arm64__associate_instruction_ops; + arch->extract_op_location =3D extract_op_location_arm64; =20 /* bl, blr */ err =3D regcomp(&arm->call_insn, "^blr?$", REG_EXTENDED); diff --git a/tools/perf/util/annotate.c b/tools/perf/util/annotate.c index 1bf69e00d76d..c4d1cb3a7ae4 100644 --- a/tools/perf/util/annotate.c +++ b/tools/perf/util/annotate.c @@ -2452,19 +2452,21 @@ int annotate_check_args(void) =20 int arch__dwarf_regnum(const struct arch *arch, const char *str) { - const char *p; + const char *p =3D str; char *regname, *q; int reg; =20 - p =3D strchr(str, arch->objdump.register_char); - if (p =3D=3D NULL) - return -1; + if (arch->objdump.register_char) { + p =3D strchr(str, arch->objdump.register_char); + if (p =3D=3D NULL) + return -1; + } =20 regname =3D strdup(p); if (regname =3D=3D NULL) return -1; =20 - q =3D strpbrk(regname, ",) "); + q =3D strpbrk(regname, ",)] "); if (q) *q =3D '\0'; =20 diff --git a/tools/perf/util/annotate.h b/tools/perf/util/annotate.h index 71195a27d38f..0391c6a9f011 100644 --- a/tools/perf/util/annotate.h +++ b/tools/perf/util/annotate.h @@ -496,12 +496,21 @@ int annotate_check_args(void); =20 int arch__dwarf_regnum(const struct arch *arch, const char *str); =20 +enum annotated_addr_mode { + INSN_ADDR_NONE =3D 0, + + INSN_ADDR_SIGNED_OFFSET, + INSN_ADDR_PRE_INDEX, + INSN_ADDR_POST_INDEX, +}; + /** * struct annotated_op_loc - Location info of instruction operand * @reg1: First register in the operand * @reg2: Second register in the operand * @offset: Memory access offset in the operand * @segment: Segment selector register + * @addr_mode: Addressing mode, only valid if @mem_ref is true * @mem_ref: Whether the operand accesses memory * @multi_regs: Whether the second register is used * @imm: Whether the operand is an immediate value (in offset) @@ -511,6 +520,7 @@ struct annotated_op_loc { int reg2; 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Fri, 03 Apr 2026 17:48:49 +0800 (CST) From: Tengda Wu To: Peter Zijlstra , Namhyung Kim , leo.yan@linux.dev, Li Huafei , Ian Rogers , Kim Phillips , Mark Rutland , Arnaldo Carvalho de Melo , Ingo Molnar Cc: Bill Wendling , Nick Desaulniers , Alexander Shishkin , Adrian Hunter , Zecheng Li , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, llvm@lists.linux.dev, Tengda Wu Subject: [PATCH v2 08/16] perf annotate-arm64: Enable instruction tracking support Date: Fri, 3 Apr 2026 09:47:52 +0000 Message-Id: <20260403094800.1418825-9-wutengda@huaweicloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260403094800.1418825-1-wutengda@huaweicloud.com> References: <20260403094800.1418825-1-wutengda@huaweicloud.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _Ch0CgAnB1TwjM9p8K_UDA--.49742S10 X-Coremail-Antispam: 1UD129KBjvJXoW7tFWrAr4UZF18Kw4ruFW8Crg_yoW8Ary7pr WDCw1rGF15JFs7KwnxJFW3XryfKw43X3yF9rZ0qw4IyF17tF95tFn7KFWY9F18trWkJw4a yr1qyF1UXay7CaUanT9S1TB71UUUUUDqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUQm14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_JF0E3s1l82xGYI kIc2x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2 z4x0Y4vE2Ix0cI8IcVAFwI0_tr0E3s1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Gr1j6F 4UJwA2z4x0Y4vEx4A2jsIE14v26rxl6s0DM28EF7xvwVC2z280aVCY1x0267AKxVW0oVCq 3wAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7 IYx2IY67AKxVWUGVWUXwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r4U M4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwACI402YVCY1x02628vn2 kIc2xKxwCY1x0262kKe7AKxVW8ZVWrXwCY1x0264kExVAvwVAq07x20xyl42xK82IYc2Ij 64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s026x 8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r4a6rW5MIIYrxkI7VAKI48JMIIF0xvE 2Ix0cI8IcVAFwI0_Xr0_Ar1lIxAIcVC0I7IYx2IY6xkF7I0E14v26r4UJVWxJr1lIxAIcV CF04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r4j6F4UMIIF0xvEx4A2jsIE c7CjxVAFwI0_Gr1j6F4UJbIYCTnIWIevJa73UjIFyTuYvjTRGMKuUUUUU X-CM-SenderInfo: pzxwv0hjgdqx5xdzvxpfor3voofrz/ Content-Type: text/plain; charset="utf-8" Enable instruction tracking for the arm64 architecture in 'perf annotate' to support data type profiling. Define ARM64_REG_SP as 31 to correctly identify the stack pointer register during type state initialization. Update arch_supports_insn_tracking() to include arm64, which allows find_data_type_block() to process the instruction scope for arm64. Signed-off-by: Li Huafei Signed-off-by: Tengda Wu --- tools/perf/util/annotate-data.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/tools/perf/util/annotate-data.c b/tools/perf/util/annotate-dat= a.c index 1eff0a27237d..fd6416d43a2e 100644 --- a/tools/perf/util/annotate-data.c +++ b/tools/perf/util/annotate-data.c @@ -28,6 +28,7 @@ =20 /* register number of the stack pointer */ #define X86_REG_SP 7 +#define ARM64_REG_SP 31 =20 static void delete_var_types(struct die_var_type *var_types); =20 @@ -177,7 +178,8 @@ static void init_type_state(struct type_state *state, c= onst struct arch *arch) state->regs[11].caller_saved =3D true; state->ret_reg =3D 0; state->stack_reg =3D X86_REG_SP; - } + } else if (arch__is_arm64(arch)) + state->stack_reg =3D ARM64_REG_SP; } =20 static void exit_type_state(struct type_state *state) @@ -1421,7 +1423,8 @@ static enum type_match_result find_data_type_insn(str= uct data_loc_info *dloc, =20 static int arch_supports_insn_tracking(struct data_loc_info *dloc) { - if ((arch__is_x86(dloc->arch)) || (arch__is_powerpc(dloc->arch))) + if ((arch__is_x86(dloc->arch)) || (arch__is_powerpc(dloc->arch)) || + (arch__is_arm64(dloc->arch))) return 1; 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charset="utf-8" Implement update_insn_state() for arm64 to track register state changes during load (LDR) instructions. This is essential for maintaining accurate type information when data is moved from memory to registers. The implementation handles the three primary arm64 addressing modes: 1. Signed offset: [base, #imm] 2. Pre-index: [base, #imm]! 3. Post-index: [base], #imm Introduce adjust_reg_index_state() to handle the side effects of pre-index and post-index addressing, where the base register is updated with the offset after or before the memory access. This ensures that the register's offset within a structure is correctly tracked across sequential instructions. A real-world example is shown below: ffff80008011f5b0 : ffff80008011f5b8: ldr x0, [x0, #2712] // x0: struct rq* -> task_struct* ffff80008011f5c0: ldr w1, [x0, #104] // PMU sample at offset 0x68 Before this commit, the type of x0 was incorrectly inferred as 'struct rq': find data type for 0x68(reg0) at pick_task_stop+0x10 var [8] reg0 offset 0 type=3D'struct rq*' chk [10] reg0 offset=3D0x68 ok=3D1 kind=3D1 (struct rq*) : Good! final result: type=3D'struct rq' After this commit, the type of x0 is correctly inferred as 'struct task_str= uct': find data type for 0x68(reg0) at pick_task_stop+0x10 var [8] reg0 offset 0 type=3D'struct rq*' ldr [8] 0xa98(reg0) -> reg0 type=3D'struct task_struct*' chk [10] reg0 offset=3D0x68 ok=3D1 kind=3D1 (struct task_struct*) : Good! final result: type=3D'struct task_struct' Signed-off-by: Li Huafei Signed-off-by: Tengda Wu --- .../perf/util/annotate-arch/annotate-arm64.c | 87 +++++++++++++++++++ 1 file changed, 87 insertions(+) diff --git a/tools/perf/util/annotate-arch/annotate-arm64.c b/tools/perf/ut= il/annotate-arch/annotate-arm64.c index 1fe4c503431b..cac2bf0021c9 100644 --- a/tools/perf/util/annotate-arch/annotate-arm64.c +++ b/tools/perf/util/annotate-arch/annotate-arm64.c @@ -9,6 +9,8 @@ #include #include "../annotate.h" #include "../disasm.h" +#include "../annotate-data.h" +#include "../debug.h" =20 struct arch_arm64 { struct arch arch; @@ -254,6 +256,88 @@ static int extract_op_location_arm64(const struct arch= *arch, return 0; } =20 +#ifdef HAVE_LIBDW_SUPPORT +static int get_mem_offset(struct annotated_op_loc *op_loc, int type_offset) +{ + if (op_loc->addr_mode =3D=3D INSN_ADDR_POST_INDEX) + return type_offset; + + return op_loc->offset + type_offset; +} + +static void adjust_reg_index_state(struct type_state *state, int reg, + struct annotated_op_loc *op_loc, + const char *insn_name, u32 insn_offset) +{ + struct type_state_reg *tsr; + + if (!has_reg_type(state, reg) || + (op_loc->addr_mode !=3D INSN_ADDR_PRE_INDEX && + op_loc->addr_mode !=3D INSN_ADDR_POST_INDEX)) + return; + + tsr =3D &state->regs[reg]; + tsr->offset =3D op_loc->offset + tsr->offset; + tsr->ok =3D true; + + pr_debug_dtp("%s [%x] %s-index %#x(reg%d) -> reg%d", insn_name, + insn_offset, op_loc->addr_mode =3D=3D INSN_ADDR_PRE_INDEX ? + "pre" : "post", op_loc->offset, reg, reg); + pr_debug_type_name(&tsr->type, tsr->kind); +} + +static void update_insn_state_arm64(struct type_state *state, + struct data_loc_info *dloc, Dwarf_Die * cu_die __maybe_unused, + struct disasm_line *dl) +{ + struct annotated_insn_loc loc; + struct annotated_op_loc *src =3D &loc.ops[INSN_OP_SOURCE]; + struct annotated_op_loc *dst =3D &loc.ops[INSN_OP_TARGET]; + struct type_state_reg *tsr; + Dwarf_Die type_die; + u32 insn_offset =3D dl->al.offset; + int sreg, dreg; + + if (annotate_get_insn_location(dloc->arch, dl, &loc) < 0) + return; + + sreg =3D src->reg1; + dreg =3D dst->reg1; + + /* Memory to register transfers */ + if (!strncmp(dl->ins.name, "ld", 2)) { + struct type_state_reg dst_tsr; + + if (!has_reg_type(state, sreg) || + !has_reg_type(state, dreg) || + !state->regs[dreg].ok) + return; + + tsr =3D &state->regs[sreg]; + tsr->copied_from =3D -1; + dst_tsr =3D state->regs[dreg]; + + /* Dereference the pointer if it has one */ + if (dst_tsr.kind =3D=3D TSR_KIND_TYPE && + die_deref_ptr_type(&dst_tsr.type, + get_mem_offset(dst, dst_tsr.offset), + &type_die)) { + tsr->type =3D type_die; + tsr->kind =3D TSR_KIND_TYPE; + tsr->offset =3D 0; + tsr->ok =3D true; + + pr_debug_dtp("ldr [%x] %#x(reg%d) -> reg%d", + insn_offset, dst->offset, dreg, sreg); + pr_debug_type_name(&tsr->type, tsr->kind); + + adjust_reg_index_state(state, dreg, dst, "ldr", insn_offset); + } + return; + } +} +#endif + const struct arch *arch__new_arm64(const struct e_machine_and_e_flags *id, const char *cpuid __maybe_unused) { @@ -273,6 +357,9 @@ const struct arch *arch__new_arm64(const struct e_machi= ne_and_e_flags *id, arch->objdump.imm_char =3D '#'; arch->associate_instruction_ops =3D arm64__associate_instruction_ops; arch->extract_op_location =3D extract_op_location_arm64; +#ifdef HAVE_LIBDW_SUPPORT + arch->update_insn_state =3D update_insn_state_arm64; +#endif =20 /* bl, blr */ err =3D regcomp(&arm->call_insn, "^blr?$", REG_EXTENDED); --=20 2.34.1 From nobody Sun Jun 14 14:34:19 2026 Received: from dggsgout12.his.huawei.com (dggsgout12.his.huawei.com [45.249.212.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 88A73396D28; Fri, 3 Apr 2026 09:48:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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spf=pass smtp.mailfrom=huaweicloud.com Received: from mail.maildlp.com (unknown [172.19.163.170]) by dggsgout12.his.huawei.com (SkyGuard) with ESMTPS id 4fnDRd2YbbzKHMXS; Fri, 3 Apr 2026 17:47:57 +0800 (CST) Received: from mail02.huawei.com (unknown [10.116.40.252]) by mail.maildlp.com (Postfix) with ESMTP id ECB4B40570; Fri, 3 Apr 2026 17:48:49 +0800 (CST) Received: from huawei.com (unknown [10.67.174.45]) by APP3 (Coremail) with SMTP id _Ch0CgAnB1TwjM9p8K_UDA--.49742S12; Fri, 03 Apr 2026 17:48:49 +0800 (CST) From: Tengda Wu To: Peter Zijlstra , Namhyung Kim , leo.yan@linux.dev, Li Huafei , Ian Rogers , Kim Phillips , Mark Rutland , Arnaldo Carvalho de Melo , Ingo Molnar Cc: Bill Wendling , Nick Desaulniers , Alexander Shishkin , Adrian Hunter , Zecheng Li , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, llvm@lists.linux.dev, Tengda Wu Subject: [PATCH v2 10/16] perf annotate-arm64: Support store instruction tracking Date: Fri, 3 Apr 2026 09:47:54 +0000 Message-Id: <20260403094800.1418825-11-wutengda@huaweicloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260403094800.1418825-1-wutengda@huaweicloud.com> References: <20260403094800.1418825-1-wutengda@huaweicloud.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _Ch0CgAnB1TwjM9p8K_UDA--.49742S12 X-Coremail-Antispam: 1UD129KBjvJXoW7CFy7Jr45Zw1ruF48KF1rZwb_yoW8XF4xpF 4DC345tr4jgrsYqwnxZF4IgFyfC3WfJ3WYkr4aywnxZF42yrn3tFWkKF1YkFW5JrZxCw1U Zwn8Kr4DZ3yxCaUanT9S1TB71UUUUUDqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUQm14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_JF0E3s1l82xGYI kIc2x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2 z4x0Y4vE2Ix0cI8IcVAFwI0_tr0E3s1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Gr1j6F 4UJwA2z4x0Y4vEx4A2jsIE14v26rxl6s0DM28EF7xvwVC2z280aVCY1x0267AKxVW0oVCq 3wAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7 IYx2IY67AKxVWUGVWUXwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r4U M4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwACI402YVCY1x02628vn2 kIc2xKxwCY1x0262kKe7AKxVW8ZVWrXwCY1x0264kExVAvwVAq07x20xyl42xK82IYc2Ij 64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s026x 8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r4a6rW5MIIYrxkI7VAKI48JMIIF0xvE 2Ix0cI8IcVAFwI0_Xr0_Ar1lIxAIcVC0I7IYx2IY6xkF7I0E14v26r4UJVWxJr1lIxAIcV CF04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r4j6F4UMIIF0xvEx4A2jsIE c7CjxVAFwI0_Gr1j6F4UJbIYCTnIWIevJa73UjIFyTuYvjTRGMKuUUUUU X-CM-SenderInfo: pzxwv0hjgdqx5xdzvxpfor3voofrz/ Content-Type: text/plain; charset="utf-8" Extend update_insn_state() for arm64 to handle store (STR) instructions. Unlike load instructions, store operations do not change the data type of the registers involved. However, arm64 store instructions sometimes use pre-index or post-index addressing modes (e.g., str x1, [x0, #8]!), which modify the base register as a side effect of the memory access. Call adjust_reg_index_state() for store instructions to ensure the base register's offset is correctly updated in the type state. This maintains synchronization between the hardware register state and the instruction tracker's model during sequential memory operations. Signed-off-by: Tengda Wu --- tools/perf/util/annotate-arch/annotate-arm64.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/tools/perf/util/annotate-arch/annotate-arm64.c b/tools/perf/ut= il/annotate-arch/annotate-arm64.c index cac2bf0021c9..28647a778802 100644 --- a/tools/perf/util/annotate-arch/annotate-arm64.c +++ b/tools/perf/util/annotate-arch/annotate-arm64.c @@ -335,6 +335,16 @@ static void update_insn_state_arm64(struct type_state = *state, } return; } + + /* Register to memory transfers */ + if (!strncmp(dl->ins.name, "st", 2)) { + /* + * Store instructions do not change the register type, + * but the base register must be updated for pre/post-index + * modes. + */ + adjust_reg_index_state(state, dreg, dst, "str", insn_offset); + } } #endif =20 --=20 2.34.1 From nobody Sun Jun 14 14:34:19 2026 Received: from dggsgout12.his.huawei.com (dggsgout12.his.huawei.com [45.249.212.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B8D7B396D38; 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dmarc=none (p=none dis=none) header.from=huaweicloud.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huaweicloud.com Received: from mail.maildlp.com (unknown [172.19.163.170]) by dggsgout12.his.huawei.com (SkyGuard) with ESMTPS id 4fnDRd3D9vzKHMXS; Fri, 3 Apr 2026 17:47:57 +0800 (CST) Received: from mail02.huawei.com (unknown [10.116.40.252]) by mail.maildlp.com (Postfix) with ESMTP id 0FE4C4056F; Fri, 3 Apr 2026 17:48:50 +0800 (CST) Received: from huawei.com (unknown [10.67.174.45]) by APP3 (Coremail) with SMTP id _Ch0CgAnB1TwjM9p8K_UDA--.49742S13; Fri, 03 Apr 2026 17:48:49 +0800 (CST) From: Tengda Wu To: Peter Zijlstra , Namhyung Kim , leo.yan@linux.dev, Li Huafei , Ian Rogers , Kim Phillips , Mark Rutland , Arnaldo Carvalho de Melo , Ingo Molnar Cc: Bill Wendling , Nick Desaulniers , Alexander Shishkin , Adrian Hunter , Zecheng Li , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, llvm@lists.linux.dev, Tengda Wu Subject: [PATCH v2 11/16] perf annotate-arm64: Support stack variable tracking Date: Fri, 3 Apr 2026 09:47:55 +0000 Message-Id: <20260403094800.1418825-12-wutengda@huaweicloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260403094800.1418825-1-wutengda@huaweicloud.com> References: <20260403094800.1418825-1-wutengda@huaweicloud.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _Ch0CgAnB1TwjM9p8K_UDA--.49742S13 X-Coremail-Antispam: 1UD129KBjvJXoWxGFyfArW5tw1DJrW3ur1xXwb_yoWrCrWxpa 1DCFy3Kr47Kr47KFs3JFs3Xr93Wws7Kw17C3s0qwn2yFySkr1rKas5tFW2vFW5Jr97Z34U Gw1DKrs5Xw42gaDanT9S1TB71UUUUUDqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUQm14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_JF0E3s1l82xGYI kIc2x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2 z4x0Y4vE2Ix0cI8IcVAFwI0_tr0E3s1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Gr1j6F 4UJwA2z4x0Y4vEx4A2jsIE14v26rxl6s0DM28EF7xvwVC2z280aVCY1x0267AKxVW0oVCq 3wAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7 IYx2IY67AKxVWUGVWUXwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r4U M4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwACI402YVCY1x02628vn2 kIc2xKxwCY1x0262kKe7AKxVW8ZVWrXwCY1x0264kExVAvwVAq07x20xyl42xK82IYc2Ij 64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s026x 8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r4a6rW5MIIYrxkI7VAKI48JMIIF0xvE 2Ix0cI8IcVAFwI0_Xr0_Ar1lIxAIcVC0I7IYx2IY6xkF7I0E14v26r4UJVWxJr1lIxAIcV CF04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r4j6F4UMIIF0xvEx4A2jsIE c7CjxVAFwI0_Gr1j6F4UJbIYCTnIWIevJa73UjIFyTuYvjTRGMKuUUUUU X-CM-SenderInfo: pzxwv0hjgdqx5xdzvxpfor3voofrz/ Content-Type: text/plain; charset="utf-8" Extend update_insn_state() for arm64 to track data types stored on the stack. This allows 'perf annotate' to maintain type information for local variables that are spilled to or loaded from stack slots. The implementation handles: 1. Stack Loads (LDR): Identify when a register is loaded from a stack slot and update the register's type state based on the tracked stack content or compound member types. 2. Stack Stores (STR): Update or create new stack state entries when a tracked register type is stored to the stack. This enables the instruction tracker to follow data types as they move between registers and memory, specifically for function local variables and compiler-spilled values on arm64. Signed-off-by: Tengda Wu --- .../perf/util/annotate-arch/annotate-arm64.c | 83 ++++++++++++++++++- 1 file changed, 80 insertions(+), 3 deletions(-) diff --git a/tools/perf/util/annotate-arch/annotate-arm64.c b/tools/perf/ut= il/annotate-arch/annotate-arm64.c index 28647a778802..f9100230c2f6 100644 --- a/tools/perf/util/annotate-arch/annotate-arm64.c +++ b/tools/perf/util/annotate-arch/annotate-arm64.c @@ -11,6 +11,8 @@ #include "../disasm.h" #include "../annotate-data.h" #include "../debug.h" +#include "../map.h" +#include "../symbol.h" =20 struct arch_arm64 { struct arch arch; @@ -297,6 +299,8 @@ static void update_insn_state_arm64(struct type_state *= state, Dwarf_Die type_die; u32 insn_offset =3D dl->al.offset; int sreg, dreg; + int fbreg =3D dloc->fbreg; + int fboff =3D 0; =20 if (annotate_get_insn_location(dloc->arch, dl, &loc) < 0) return; @@ -304,17 +308,59 @@ static void update_insn_state_arm64(struct type_state= *state, sreg =3D src->reg1; dreg =3D dst->reg1; =20 + if (dloc->fb_cfa) { + u64 ip =3D dloc->ms->sym->start + dl->al.offset; + u64 pc =3D map__rip_2objdump(dloc->ms->map, ip); + + if (die_get_cfa(dloc->di->dbg, pc, &fbreg, &fboff) < 0) + fbreg =3D -1; + } + /* Memory to register transfers */ if (!strncmp(dl->ins.name, "ld", 2)) { struct type_state_reg dst_tsr; =20 - if (!has_reg_type(state, sreg) || - !has_reg_type(state, dreg) || - !state->regs[dreg].ok) + if (!has_reg_type(state, sreg)) return; =20 tsr =3D &state->regs[sreg]; tsr->copied_from =3D -1; + + /* Check stack variables with offset */ + if (sreg =3D=3D fbreg || sreg =3D=3D state->stack_reg) { + struct type_state_stack *stack; + int offset =3D src->offset - fboff; + + stack =3D find_stack_state(state, offset); + if (stack =3D=3D NULL) { + tsr->ok =3D false; + return; + } else if (!stack->compound) { + tsr->type =3D stack->type; + tsr->kind =3D stack->kind; + tsr->offset =3D stack->ptr_offset; + tsr->ok =3D true; + } else if (die_get_member_type(&stack->type, + offset - stack->offset, + &type_die)) { + tsr->type =3D type_die; + tsr->kind =3D TSR_KIND_TYPE; + tsr->offset =3D 0; + tsr->ok =3D true; + } else { + tsr->ok =3D false; + return; + } + + pr_debug_dtp("ldr [%x] -%#x(stack) -> reg%d", + insn_offset, -offset, sreg); + pr_debug_type_name(&tsr->type, tsr->kind); + return; + } + + if (!has_reg_type(state, dreg) || !state->regs[dreg].ok) + return; + dst_tsr =3D state->regs[dreg]; =20 /* Dereference the pointer if it has one */ @@ -338,6 +384,37 @@ static void update_insn_state_arm64(struct type_state = *state, =20 /* Register to memory transfers */ if (!strncmp(dl->ins.name, "st", 2)) { + /* Check stack variables with offset */ + if (dreg =3D=3D fbreg || dreg =3D=3D state->stack_reg) { + struct type_state_stack *stack; + int offset =3D dst->offset - fboff; + + if (!has_reg_type(state, sreg) || + !state->regs[sreg].ok) + return; + + tsr =3D &state->regs[sreg]; + + stack =3D find_stack_state(state, offset); + if (stack) { + if (!stack->compound) + set_stack_state(stack, offset, tsr->kind, + &tsr->type, tsr->offset); + } else { + findnew_stack_state(state, offset, tsr->kind, + &tsr->type, tsr->offset); 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Fri, 3 Apr 2026 17:48:50 +0800 (CST) Received: from huawei.com (unknown [10.67.174.45]) by APP3 (Coremail) with SMTP id _Ch0CgAnB1TwjM9p8K_UDA--.49742S14; Fri, 03 Apr 2026 17:48:49 +0800 (CST) From: Tengda Wu To: Peter Zijlstra , Namhyung Kim , leo.yan@linux.dev, Li Huafei , Ian Rogers , Kim Phillips , Mark Rutland , Arnaldo Carvalho de Melo , Ingo Molnar Cc: Bill Wendling , Nick Desaulniers , Alexander Shishkin , Adrian Hunter , Zecheng Li , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, llvm@lists.linux.dev, Tengda Wu Subject: [PATCH v2 12/16] perf annotate-arm64: Support 'mov' instruction tracking Date: Fri, 3 Apr 2026 09:47:56 +0000 Message-Id: <20260403094800.1418825-13-wutengda@huaweicloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260403094800.1418825-1-wutengda@huaweicloud.com> References: <20260403094800.1418825-1-wutengda@huaweicloud.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _Ch0CgAnB1TwjM9p8K_UDA--.49742S14 X-Coremail-Antispam: 1UD129KBjvJXoWxXw1rAw1xJFWUCw4DKF45KFg_yoW5Wr1xpa 1DG345t39Igr12grs3XFWrXa4fKwnagasI934Yqw1avrWakr4rtF97KFWaka15XryxCr43 Jw1DtrW3Ww1UCaUanT9S1TB71UUUUUDqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUQm14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_JF0E3s1l82xGYI kIc2x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2 z4x0Y4vE2Ix0cI8IcVAFwI0_tr0E3s1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Gr1j6F 4UJwA2z4x0Y4vEx4A2jsIE14v26rxl6s0DM28EF7xvwVC2z280aVCY1x0267AKxVW0oVCq 3wAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7 IYx2IY67AKxVWUGVWUXwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r4U M4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwACI402YVCY1x02628vn2 kIc2xKxwCY1x0262kKe7AKxVW8ZVWrXwCY1x0264kExVAvwVAq07x20xyl42xK82IYc2Ij 64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s026x 8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r4a6rW5MIIYrxkI7VAKI48JMIIF0xvE 2Ix0cI8IcVAFwI0_Xr0_Ar1lIxAIcVC0I7IYx2IY6xkF7I0E14v26r4UJVWxJr1lIxAIcV CF04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r4j6F4UMIIF0xvEx4A2jsIE c7CjxVAFwI0_Gr1j6F4UJbIYCTnIWIevJa73UjIFyTuYvjTRGMKuUUUUU X-CM-SenderInfo: pzxwv0hjgdqx5xdzvxpfor3voofrz/ Content-Type: text/plain; charset="utf-8" Extend update_insn_state() for arm64 to handle register-to-register 'mov' instructions. When a 'mov' instruction occurs between two registers, the data type information (DWARF type, kind, and offset) needs to be propagated from the source register to the destination register. This ensures that if a pointer or a structure was previously identified in one register, the tracker continues to recognize it after it is moved. A real-world example is shown below: ffff8000803eebf8 : ffff8000803eec20: mov x21, x0 // x0 (struct vm_area_struct*) -> x21 ffff8000803eec28: ldr x2, [x0, #112] ffff8000803eec2c: cbz x2, ffff8000803eec94 ffff8000803eec94: ldr x0, [x21, #152] // PMU sample Before this commit, the type of x21 was unknown, causing the subsequent inference to fail: var [0] reg0 offset 0 type=3D'struct vm_area_struct*' size=3D0x8 chk [9c] reg21 offset=3D0x98 ok=3D0 kind=3D0 cfa : no type information final result: no type information After this commit, the type of x21 is correctly inferred as 'vm_area_struct= ': var [0] reg0 offset 0 type=3D'struct vm_area_struct*' size=3D0x8 mov [28] reg0 -> reg21 type=3D'struct vm_area_struct*' size=3D0x8 chk [9c] reg21 offset=3D0x98 ok=3D1 kind=3D1 (struct vm_area_struct*) : G= ood! found by insn track: 0x98(reg21) type-offset=3D0x98 final result: type=3D'struct vm_area_struct' size=3D0xb0 Signed-off-by: Tengda Wu --- .../perf/util/annotate-arch/annotate-arm64.c | 28 +++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/tools/perf/util/annotate-arch/annotate-arm64.c b/tools/perf/ut= il/annotate-arch/annotate-arm64.c index f9100230c2f6..013b673f4861 100644 --- a/tools/perf/util/annotate-arch/annotate-arm64.c +++ b/tools/perf/util/annotate-arch/annotate-arm64.c @@ -308,6 +308,34 @@ static void update_insn_state_arm64(struct type_state = *state, sreg =3D src->reg1; dreg =3D dst->reg1; =20 + /* Register to register transfers */ + if (!strcmp(dl->ins.name, "mov")) { + if (!has_reg_type(state, sreg)) + return; + + tsr =3D &state->regs[sreg]; + tsr->copied_from =3D -1; + + if (!has_reg_type(state, dreg) || + !state->regs[dreg].ok) { + tsr->ok =3D false; + return; + } + + tsr->type =3D state->regs[dreg].type; + tsr->kind =3D state->regs[dreg].kind; + tsr->offset =3D state->regs[dreg].offset; + tsr->ok =3D true; + + if (tsr->kind =3D=3D TSR_KIND_TYPE || tsr->kind =3D=3D TSR_KIND_POINTER) + tsr->copied_from =3D dreg; + + pr_debug_dtp("mov [%x] reg%d -> reg%d", + insn_offset, dreg, sreg); + pr_debug_type_name(&tsr->type, tsr->kind); + return; + } + if (dloc->fb_cfa) { u64 ip =3D dloc->ms->sym->start + dl->al.offset; u64 pc =3D map__rip_2objdump(dloc->ms->map, ip); --=20 2.34.1 From nobody Sun Jun 14 14:34:19 2026 Received: from dggsgout11.his.huawei.com (dggsgout11.his.huawei.com [45.249.212.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 26F6339C009; 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dmarc=none (p=none dis=none) header.from=huaweicloud.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huaweicloud.com Received: from mail.maildlp.com (unknown [172.19.163.198]) by dggsgout11.his.huawei.com (SkyGuard) with ESMTPS id 4fnDS85pYqzYQtwD; Fri, 3 Apr 2026 17:48:24 +0800 (CST) Received: from mail02.huawei.com (unknown [10.116.40.252]) by mail.maildlp.com (Postfix) with ESMTP id 3C1E540576; Fri, 3 Apr 2026 17:48:50 +0800 (CST) Received: from huawei.com (unknown [10.67.174.45]) by APP3 (Coremail) with SMTP id _Ch0CgAnB1TwjM9p8K_UDA--.49742S15; Fri, 03 Apr 2026 17:48:49 +0800 (CST) From: Tengda Wu To: Peter Zijlstra , Namhyung Kim , leo.yan@linux.dev, Li Huafei , Ian Rogers , Kim Phillips , Mark Rutland , Arnaldo Carvalho de Melo , Ingo Molnar Cc: Bill Wendling , Nick Desaulniers , Alexander Shishkin , Adrian Hunter , Zecheng Li , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, llvm@lists.linux.dev, Tengda Wu Subject: [PATCH v2 13/16] perf annotate-arm64: Support 'add' instruction tracking Date: Fri, 3 Apr 2026 09:47:57 +0000 Message-Id: <20260403094800.1418825-14-wutengda@huaweicloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260403094800.1418825-1-wutengda@huaweicloud.com> References: <20260403094800.1418825-1-wutengda@huaweicloud.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _Ch0CgAnB1TwjM9p8K_UDA--.49742S15 X-Coremail-Antispam: 1UD129KBjvJXoWxZrW5tF4fJF4DKw4fuF1kuFg_yoW5KF43pa 90kryUGw4Igr12grs3ZFW3XryfKan3W3W5Cryqgw1ayrWayr18ta4vkrW3uayrJrZxAw47 Jr15Kr4ruw1qkaUanT9S1TB71UUUUUDqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUQm14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_JF0E3s1l82xGYI kIc2x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2 z4x0Y4vE2Ix0cI8IcVAFwI0_tr0E3s1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Gr1j6F 4UJwA2z4x0Y4vEx4A2jsIE14v26rxl6s0DM28EF7xvwVC2z280aVCY1x0267AKxVW0oVCq 3wAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7 IYx2IY67AKxVWUGVWUXwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r4U M4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwACI402YVCY1x02628vn2 kIc2xKxwCY1x0262kKe7AKxVW8ZVWrXwCY1x0264kExVAvwVAq07x20xyl42xK82IYc2Ij 64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s026x 8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r4a6rW5MIIYrxkI7VAKI48JMIIF0xvE 2Ix0cI8IcVAFwI0_Xr0_Ar1lIxAIcVC0I7IYx2IY6xkF7I0E14v26r4UJVWxJr1lIxAIcV CF04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r4j6F4UMIIF0xvEx4A2jsIE c7CjxVAFwI0_Gr1j6F4UJbIYCTnIWIevJa73UjIFyTuYvjTRGMKuUUUUU X-CM-SenderInfo: pzxwv0hjgdqx5xdzvxpfor3voofrz/ Content-Type: text/plain; charset="utf-8" Extend update_insn_state() for arm64 to track pointer arithmetic and member address calculations. The arm64 'add' instruction frequently calculates structure member addresses, such as 'add x0, x1, #offset'. Tracking this is essential to maintain the connection between a base pointer and its derived member addresses. The implementation checks if the base register contains a pointer or a structure type. When an immediate offset is added, use die_get_member_type() to verify that the resulting offset points to a valid member within the data type. If valid, update the target register's type state with the new offset while preserving the base type information. A real-world example is shown below: ffff80008001c9a8 : ffff80008001c9c4: add x19, x0, #0xeb8 // x0 (task_struct*) + 0xeb8 -> x= 19 ffff80008001c9d0: ldr x0, [x19] // PMU sample Before this commit, the type flow broke at the 'add' instruction, leaving the subsequent load with no type information: chk [28] reg19 offset=3D0 ok=3D0 kind=3D0 cfa : no type information final result: no type information After this commit, the tracker correctly follows the member address calculation: var [0] reg0 offset 0 type=3D'struct task_struct*' add [1c] address of 0xeb8(reg0) -> reg19 type=3D'struct task_struct*' chk [28] reg19 offset=3D0 ok=3D1 kind=3D1 (struct task_struct*) : Good! found by insn track: 0(reg19) type-offset=3D0xeb8 final result: type=3D'struct task_struct' Signed-off-by: Tengda Wu --- .../perf/util/annotate-arch/annotate-arm64.c | 45 +++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/tools/perf/util/annotate-arch/annotate-arm64.c b/tools/perf/ut= il/annotate-arch/annotate-arm64.c index 013b673f4861..d2557b9d6909 100644 --- a/tools/perf/util/annotate-arch/annotate-arm64.c +++ b/tools/perf/util/annotate-arch/annotate-arm64.c @@ -7,6 +7,7 @@ #include #include #include +#include #include "../annotate.h" #include "../disasm.h" #include "../annotate-data.h" @@ -308,6 +309,50 @@ static void update_insn_state_arm64(struct type_state = *state, sreg =3D src->reg1; dreg =3D dst->reg1; =20 + if (!strcmp(dl->ins.name, "add")) { + struct type_state_reg dst_tsr; + + if (!has_reg_type(state, sreg) || + !has_reg_type(state, dreg) || + !state->regs[dreg].ok) + return; + + tsr =3D &state->regs[sreg]; + tsr->copied_from =3D -1; + dst_tsr =3D state->regs[dreg]; + + /* Handle calculation of a register holding a typed pointer */ + if (dst_tsr.kind =3D=3D TSR_KIND_POINTER || + (dst_tsr.kind =3D=3D TSR_KIND_TYPE && + dwarf_tag(&dst_tsr.type) =3D=3D DW_TAG_pointer_type)) { + s32 offset; + + if (dst_tsr.kind =3D=3D TSR_KIND_TYPE && + __die_get_real_type(&dst_tsr.type, &type_die) =3D=3D NULL) + return; + + if (dst_tsr.kind =3D=3D TSR_KIND_POINTER) + type_die =3D dst_tsr.type; + + /* Check if the target type has a member at the new offset */ + offset =3D dst->offset + dst_tsr.offset; + if (die_get_member_type(&type_die, offset, &type_die) =3D=3D NULL) + return; + + tsr->type =3D dst_tsr.type; + tsr->kind =3D dst_tsr.kind; + tsr->offset =3D offset; + tsr->ok =3D true; + + pr_debug_dtp("add [%x] address of %s%#x(reg%d) -> reg%d", + insn_offset, dst->offset < 0 ? "-" : "", + abs(dst->offset), dreg, sreg); + + pr_debug_type_name(&tsr->type, tsr->kind); + } + return; + } + /* Register to register transfers */ if (!strcmp(dl->ins.name, "mov")) { if (!has_reg_type(state, sreg)) --=20 2.34.1 From nobody Sun Jun 14 14:34:19 2026 Received: from dggsgout12.his.huawei.com (dggsgout12.his.huawei.com [45.249.212.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 280B139C013; Fri, 3 Apr 2026 09:48:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775209744; cv=none; b=dAbx+0ZfE0k20b80GIDOaGA1eyCJ+nME8E4da/b2/uHx4MkX9TITxA+HMFlFALuOy1sKxsVjpGCvOfa8tig5aygHfY9pVL2bVn7X6AhihtfGFMEClpJmNzW1omFxPPOEpvjYrrh8KxzcIT8u2951iZyekALOV3UOzDWqYNUpclQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775209744; c=relaxed/simple; bh=HwH4B5poXc31LIeDu685sY3ZXGe2zc0035ou0YyOWAE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=RpsND9Jb3EwJEFLcfE5AwqvbomRSuJCCH32IxS9V3P8vPofv2zrL/L+XIXRYAspOppkvT7ftF5G9Z4RCU7e10rni7xvo7giltzUZ8C8Hos7FR9CIYVP2YXdESi4bxU+Lo7D5CY3jc146NvPrI4drKUghXcNjiApAVfQedTBX1EQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=huaweicloud.com; spf=pass smtp.mailfrom=huaweicloud.com; arc=none smtp.client-ip=45.249.212.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=huaweicloud.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huaweicloud.com Received: from mail.maildlp.com (unknown [172.19.163.177]) by dggsgout12.his.huawei.com (SkyGuard) with ESMTPS id 4fnDRd55qwzKHMYF; Fri, 3 Apr 2026 17:47:57 +0800 (CST) Received: from mail02.huawei.com (unknown [10.116.40.252]) by mail.maildlp.com (Postfix) with ESMTP id 4E2FB40592; Fri, 3 Apr 2026 17:48:50 +0800 (CST) Received: from huawei.com (unknown [10.67.174.45]) by APP3 (Coremail) with SMTP id _Ch0CgAnB1TwjM9p8K_UDA--.49742S16; Fri, 03 Apr 2026 17:48:50 +0800 (CST) From: Tengda Wu To: Peter Zijlstra , Namhyung Kim , leo.yan@linux.dev, Li Huafei , Ian Rogers , Kim Phillips , Mark Rutland , Arnaldo Carvalho de Melo , Ingo Molnar Cc: Bill Wendling , Nick Desaulniers , Alexander Shishkin , Adrian Hunter , Zecheng Li , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, llvm@lists.linux.dev, Tengda Wu Subject: [PATCH v2 14/16] perf annotate-arm64: Support 'adrp' instruction to track global variables Date: Fri, 3 Apr 2026 09:47:58 +0000 Message-Id: <20260403094800.1418825-15-wutengda@huaweicloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260403094800.1418825-1-wutengda@huaweicloud.com> References: <20260403094800.1418825-1-wutengda@huaweicloud.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _Ch0CgAnB1TwjM9p8K_UDA--.49742S16 X-Coremail-Antispam: 1UD129KBjvJXoW3CrW5KF15KF4xCr4fAF1xGrg_yoWDuw1Up3 4DGFy7Wa17Wr4Igrs3XFWUXryfWwsagFyjkryqvr1SyFyxtr1fGa4vyFWaqa18JrykAw17 Jw1DKr4DXw47KaDanT9S1TB71UUUUUDqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUQm14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_JF0E3s1l82xGYI kIc2x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2 z4x0Y4vE2Ix0cI8IcVAFwI0_tr0E3s1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Gr1j6F 4UJwA2z4x0Y4vEx4A2jsIE14v26rxl6s0DM28EF7xvwVC2z280aVCY1x0267AKxVW0oVCq 3wAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7 IYx2IY67AKxVWUGVWUXwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r4U M4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwACI402YVCY1x02628vn2 kIc2xKxwCY1x0262kKe7AKxVW8ZVWrXwCY1x0264kExVAvwVAq07x20xyl42xK82IYc2Ij 64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s026x 8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r4a6rW5MIIYrxkI7VAKI48JMIIF0xvE 2Ix0cI8IcVAFwI0_Xr0_Ar1lIxAIcVC0I7IYx2IY6xkF7I0E14v26r4UJVWxJr1lIxAIcV CF04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r4j6F4UMIIF0xvEx4A2jsIE c7CjxVAFwI0_Gr1j6F4UJbIYCTnIWIevJa73UjIFyTuYvjTRGMKuUUUUU X-CM-SenderInfo: pzxwv0hjgdqx5xdzvxpfor3voofrz/ Content-Type: text/plain; charset="utf-8" Extend update_insn_state() for arm64 to track global variable types calculated via PC-relative addressing. On arm64, global variables are typically accessed by first calculating the page address using 'adrp', followed by an 'add' or 'ldr' to get the specific symbol address. Without tracking 'adrp', the instruction tracker loses the base address, making it impossible to resolve global symbols and their associated DWARF types. Introduce TSR_KIND_GLOBAL_ADDR to represent a partial global address state. When encountering 'adrp', store the page-aligned target address in the register's type state. Upon a subsequent 'add' or 'ldr' instruction that references a TSR_KIND_GLOBAL_ADDR register, combine the page address with the immediate offset. A real-world example is shown below: ffff80008032e008 : ffff80008032e048: adrp x24, ffff80008202f000 ffff80008032e050: add x24, x24, #0xd40 ffff80008032e078: ldr x0, [x24] // PMU sample Before this commit, x24 was unknown, leading to no type information: chk [70] reg24 offset=3D0 ok=3D0 kind=3D0 cfa : no type information final result: no type information After this commit, the tracker correctly follows the adrp/add flow: adrp [40] global addr=3Dffff80008202f000 -> reg24 add [48] global addr=3Dffff80008202fd40 -> reg24 chk [70] reg24 offset=3D0 ok=3D1 kind=3D7 global addr : Good! final result: type=3D'struct folio*' Signed-off-by: Li Huafei Signed-off-by: Tengda Wu --- .../perf/util/annotate-arch/annotate-arm64.c | 64 ++++++++++++++++++- tools/perf/util/annotate-arch/annotate-x86.c | 6 +- tools/perf/util/annotate-data.c | 32 ++++++++-- tools/perf/util/annotate-data.h | 7 +- 4 files changed, 97 insertions(+), 12 deletions(-) diff --git a/tools/perf/util/annotate-arch/annotate-arm64.c b/tools/perf/ut= il/annotate-arch/annotate-arm64.c index d2557b9d6909..6b954bbfaf8d 100644 --- a/tools/perf/util/annotate-arch/annotate-arm64.c +++ b/tools/perf/util/annotate-arch/annotate-arm64.c @@ -290,7 +290,7 @@ static void adjust_reg_index_state(struct type_state *s= tate, int reg, } =20 static void update_insn_state_arm64(struct type_state *state, - struct data_loc_info *dloc, Dwarf_Die * cu_die __maybe_unused, + struct data_loc_info *dloc, Dwarf_Die *cu_die, struct disasm_line *dl) { struct annotated_insn_loc loc; @@ -309,6 +309,23 @@ static void update_insn_state_arm64(struct type_state = *state, sreg =3D src->reg1; dreg =3D dst->reg1; =20 + if (!strcmp(dl->ins.name, "adrp")) { + if (!has_reg_type(state, sreg) || !dl->ops.target.addr) + return; + + tsr =3D &state->regs[sreg]; + tsr->copied_from =3D -1; + tsr->kind =3D TSR_KIND_GLOBAL_ADDR; + /* Partial page-relative address, finalized in next 'add/ldr' */ + tsr->addr =3D dl->ops.target.addr; + tsr->offset =3D 0; + tsr->ok =3D true; + + pr_debug_dtp("adrp [%x] global addr=3D%"PRIx64" -> reg%d\n", + insn_offset, tsr->addr, sreg); + return; + } + if (!strcmp(dl->ins.name, "add")) { struct type_state_reg dst_tsr; =20 @@ -342,6 +359,7 @@ static void update_insn_state_arm64(struct type_state *= state, tsr->type =3D dst_tsr.type; tsr->kind =3D dst_tsr.kind; tsr->offset =3D offset; + tsr->addr =3D 0; tsr->ok =3D true; =20 pr_debug_dtp("add [%x] address of %s%#x(reg%d) -> reg%d", @@ -350,6 +368,18 @@ static void update_insn_state_arm64(struct type_state = *state, =20 pr_debug_type_name(&tsr->type, tsr->kind); } + + /* Handle PC-relative global address calculation (adrp/add pair) */ + if (dst_tsr.kind =3D=3D TSR_KIND_GLOBAL_ADDR) { + tsr->kind =3D dst_tsr.kind; + tsr->addr =3D dst_tsr.addr + dst->offset; + tsr->offset =3D 0; + tsr->ok =3D true; + + pr_debug_dtp("add [%x] global addr=3D%"PRIx64" -> reg%d\n", + insn_offset, tsr->addr, sreg); + } + return; } =20 @@ -370,6 +400,7 @@ static void update_insn_state_arm64(struct type_state *= state, tsr->type =3D state->regs[dreg].type; tsr->kind =3D state->regs[dreg].kind; tsr->offset =3D state->regs[dreg].offset; + tsr->addr =3D state->regs[dreg].addr; tsr->ok =3D true; =20 if (tsr->kind =3D=3D TSR_KIND_TYPE || tsr->kind =3D=3D TSR_KIND_POINTER) @@ -444,6 +475,7 @@ static void update_insn_state_arm64(struct type_state *= state, tsr->type =3D type_die; tsr->kind =3D TSR_KIND_TYPE; tsr->offset =3D 0; + tsr->addr =3D 0; tsr->ok =3D true; =20 pr_debug_dtp("ldr [%x] %#x(reg%d) -> reg%d", @@ -451,6 +483,30 @@ static void update_insn_state_arm64(struct type_state = *state, pr_debug_type_name(&tsr->type, tsr->kind); =20 adjust_reg_index_state(state, dreg, dst, "ldr", insn_offset); + return; + } + + /* Or check if it's a global variable */ + if (dst_tsr.kind =3D=3D TSR_KIND_GLOBAL_ADDR) { + u64 ip =3D dloc->ms->sym->start + dl->al.offset; + u64 addr =3D dst_tsr.addr + dst->offset; + int offset; + + if (!get_global_var_type(cu_die, dloc, ip, addr, &offset, + &type_die) || + !die_get_member_type(&type_die, offset, &type_die)) { + tsr->ok =3D false; + return; + } + + tsr->type =3D type_die; + tsr->kind =3D TSR_KIND_TYPE; + tsr->offset =3D offset; + tsr->addr =3D addr; + tsr->ok =3D true; + pr_debug_dtp("ldr [%x] global (%"PRIx64") -> reg%d", + insn_offset, addr, sreg); + pr_debug_type_name(&tsr->type, tsr->kind); } return; } @@ -472,10 +528,12 @@ static void update_insn_state_arm64(struct type_state= *state, if (stack) { if (!stack->compound) set_stack_state(stack, offset, tsr->kind, - &tsr->type, tsr->offset); + &tsr->type, tsr->offset, + tsr->addr); } else { findnew_stack_state(state, offset, tsr->kind, - &tsr->type, tsr->offset); + &tsr->type, tsr->offset, + tsr->addr); } =20 pr_debug_dtp("str [%x] reg%d -> -%#x(stack)", diff --git a/tools/perf/util/annotate-arch/annotate-x86.c b/tools/perf/util= /annotate-arch/annotate-x86.c index c63ca3250b95..24adfbef8b76 100644 --- a/tools/perf/util/annotate-arch/annotate-x86.c +++ b/tools/perf/util/annotate-arch/annotate-x86.c @@ -780,10 +780,12 @@ static void update_insn_state_x86(struct type_state *= state, */ if (!stack->compound) set_stack_state(stack, offset, tsr->kind, - &tsr->type, tsr->offset); + &tsr->type, tsr->offset, + tsr->addr); } else { findnew_stack_state(state, offset, tsr->kind, - &tsr->type, tsr->offset); + &tsr->type, tsr->offset, + tsr->addr); } =20 if (dst->reg1 =3D=3D fbreg) { diff --git a/tools/perf/util/annotate-data.c b/tools/perf/util/annotate-dat= a.c index fd6416d43a2e..b75d50b2c46f 100644 --- a/tools/perf/util/annotate-data.c +++ b/tools/perf/util/annotate-data.c @@ -70,6 +70,9 @@ void pr_debug_type_name(Dwarf_Die *die, enum type_state_k= ind kind) case TSR_KIND_CANARY: pr_info(" stack canary\n"); return; + case TSR_KIND_GLOBAL_ADDR: + pr_info(" global address\n"); + return; case TSR_KIND_TYPE: default: break; @@ -577,7 +580,7 @@ struct type_state_stack *find_stack_state(struct type_s= tate *state, } =20 void set_stack_state(struct type_state_stack *stack, int offset, u8 kind, - Dwarf_Die *type_die, int ptr_offset) + Dwarf_Die *type_die, int ptr_offset, u64 addr) { int tag; Dwarf_Word size; @@ -594,6 +597,7 @@ void set_stack_state(struct type_state_stack *stack, in= t offset, u8 kind, stack->offset =3D offset; stack->ptr_offset =3D ptr_offset; stack->kind =3D kind; + stack->addr =3D addr; =20 if (kind =3D=3D TSR_KIND_POINTER) { stack->compound =3D false; @@ -616,18 +620,18 @@ void set_stack_state(struct type_state_stack *stack, = int offset, u8 kind, struct type_state_stack *findnew_stack_state(struct type_state *state, int offset, u8 kind, Dwarf_Die *type_die, - int ptr_offset) + int ptr_offset, u64 addr) { struct type_state_stack *stack =3D find_stack_state(state, offset); =20 if (stack) { - set_stack_state(stack, offset, kind, type_die, ptr_offset); + set_stack_state(stack, offset, kind, type_die, ptr_offset, addr); return stack; } =20 stack =3D malloc(sizeof(*stack)); if (stack) { - set_stack_state(stack, offset, kind, type_die, ptr_offset); + set_stack_state(stack, offset, kind, type_die, ptr_offset, addr); list_add(&stack->list, &state->stack_vars); } return stack; @@ -913,7 +917,7 @@ static void update_var_state(struct type_state *state, = struct data_loc_info *dlo continue; =20 findnew_stack_state(state, offset, TSR_KIND_TYPE, - &mem_die, /*ptr_offset=3D*/0); + &mem_die, /*ptr_offset=3D*/0, /*addr=3D*/0); =20 if (var->reg =3D=3D state->stack_reg) { pr_debug_dtp("var [%"PRIx64"] %#x(reg%d)", @@ -1256,6 +1260,24 @@ static enum type_match_result check_matching_type(st= ruct type_state *state, if (dloc->op->offset < 0 && reg !=3D state->stack_reg && reg !=3D dloc->= fbreg) goto check_kernel; } + + if (state->regs[reg].kind =3D=3D TSR_KIND_GLOBAL_ADDR) { + int var_offset; + + pr_debug_dtp("global addr"); + + /* + * The register holds the address of a global variable. Try to + * find the variable by the address and get its type. + */ + if (get_global_var_type(cu_die, dloc, dloc->ip, state->regs[reg].addr, + &var_offset, type_die)) { + dloc->type_offset =3D var_offset; + return PERF_TMR_OK; + } + /* No need to retry global variables */ + return PERF_TMR_BAIL_OUT; + } check_non_register: if (reg =3D=3D dloc->fbreg || reg =3D=3D state->stack_reg) { struct type_state_stack *stack; diff --git a/tools/perf/util/annotate-data.h b/tools/perf/util/annotate-dat= a.h index c26130744260..bae15e1d6db8 100644 --- a/tools/perf/util/annotate-data.h +++ b/tools/perf/util/annotate-data.h @@ -37,6 +37,7 @@ enum type_state_kind { TSR_KIND_PERCPU_POINTER, TSR_KIND_POINTER, TSR_KIND_CANARY, + TSR_KIND_GLOBAL_ADDR, }; =20 /** @@ -187,6 +188,7 @@ struct type_state_reg { u64 lifetime_end; u8 kind; u8 copied_from; + u64 addr; }; =20 /* Type information in a stack location, dynamically allocated */ @@ -199,6 +201,7 @@ struct type_state_stack { int size; bool compound; u8 kind; + u64 addr; }; =20 /* @@ -253,9 +256,9 @@ bool has_reg_type(struct type_state *state, int reg); struct type_state_stack *findnew_stack_state(struct type_state *state, int offset, u8 kind, Dwarf_Die *type_die, - int ptr_offset); + int ptr_offset, u64 addr); void set_stack_state(struct type_state_stack *stack, int offset, u8 kind, - Dwarf_Die *type_die, int ptr_offset); + Dwarf_Die *type_die, int ptr_offset, u64 addr); struct type_state_stack *find_stack_state(struct type_state *state, int offset); bool get_global_var_type(Dwarf_Die *cu_die, struct data_loc_info *dloc, --=20 2.34.1 From nobody Sun Jun 14 14:34:19 2026 Received: from dggsgout12.his.huawei.com (dggsgout12.his.huawei.com [45.249.212.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3A0E23976A3; Fri, 3 Apr 2026 09:48:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.56 ARC-Seal: i=1; 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spf=none smtp.mailfrom=huaweicloud.com Received: from mail.maildlp.com (unknown [172.19.163.177]) by dggsgout12.his.huawei.com (SkyGuard) with ESMTPS id 4fnDRd5jzHzKHMYF; Fri, 3 Apr 2026 17:47:57 +0800 (CST) Received: from mail02.huawei.com (unknown [10.116.40.252]) by mail.maildlp.com (Postfix) with ESMTP id 662BC4058C; Fri, 3 Apr 2026 17:48:50 +0800 (CST) Received: from huawei.com (unknown [10.67.174.45]) by APP3 (Coremail) with SMTP id _Ch0CgAnB1TwjM9p8K_UDA--.49742S17; Fri, 03 Apr 2026 17:48:50 +0800 (CST) From: Tengda Wu To: Peter Zijlstra , Namhyung Kim , leo.yan@linux.dev, Li Huafei , Ian Rogers , Kim Phillips , Mark Rutland , Arnaldo Carvalho de Melo , Ingo Molnar Cc: Bill Wendling , Nick Desaulniers , Alexander Shishkin , Adrian Hunter , Zecheng Li , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, llvm@lists.linux.dev, Tengda Wu Subject: [PATCH v2 15/16] perf annotate-arm64: Support per-cpu variable access tracking Date: Fri, 3 Apr 2026 09:47:59 +0000 Message-Id: <20260403094800.1418825-16-wutengda@huaweicloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260403094800.1418825-1-wutengda@huaweicloud.com> References: <20260403094800.1418825-1-wutengda@huaweicloud.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _Ch0CgAnB1TwjM9p8K_UDA--.49742S17 X-Coremail-Antispam: 1UD129KBjvJXoW3Xr1rWr45Wr1fJr4kWrWxZwb_yoWxKF4kp3 95KFyUGrZ8trs3GwsaqFW3XryF9393Kas2krWY9w1akrW29r1UGa97KrWYgF4UGrykAw4x trn8tr43Xw4DKaUanT9S1TB71UUUUUDqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUQv14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_JF0E3s1l82xGYI kIc2x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2 z4x0Y4vE2Ix0cI8IcVAFwI0_tr0E3s1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Cr1j6r xdM28EF7xvwVC2z280aVAFwI0_GcCE3s1l84ACjcxK6I8E87Iv6xkF7I0E14v26rxl6s0D M2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xIIjx v20xvE14v26r106r15McIj6I8E87Iv67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr0_Gr1l F7xvr2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20VAGYxC7M4IIrI8v6xkF7I0E8cxan2 IY04v7MxkF7I0En4kS14v26r4a6rW5MxkF7I0Ew4C26cxK6c8Ij28IcwCF04k20xvY0x0E wIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18MI8I3I0E74 80Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_GFv_WrylIxkGc2Ij64vIr41lIxAIcVC0 I7IYx2IY67AKxVW5JVW7JwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Gr1j6F4UJwCI42IY6x AIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Gr0_Cr1lIxAIcVC2z280aVCY 1x0267AKxVW8Jr0_Cr1UYxBIdaVFxhVjvjDU0xZFpf9x0pRepBfUUUUU= X-CM-SenderInfo: pzxwv0hjgdqx5xdzvxpfor3voofrz/ Content-Type: text/plain; charset="utf-8" Extend update_insn_state() for arm64 to handle per-cpu variable addressing. On arm64, per-cpu variables are accessed by adding a per-cpu offset (typically from the '__per_cpu_offset' array) to the global variable's address. This logic often results in the following instruction pattern: adrp x4, add x4, x4, #offset // x4 =3D &__per_cpu_offset ldr x6, [x4, w0, sxtw #3] // x6 =3D __per_cpu_offset[cpu] ... adrp x5, add x5, x5, #offset // x5 =3D &global_var ldr x0, [x6, x5] // Pattern A: direct load per-cpu instance OR add x0, x6, x5 // Pattern B: compute per-cpu addr To handle such cases: 1. Identify per-cpu base initialization: Detect 'adrp/add' pairs that resolve to the '__per_cpu_offset' symbol and mark the destination register as TSR_KIND_PERCPU_BASE. 2. Propagate type information: During subsequent 'ldr' or 'add' steps, if one operand is a PERCPU_BASE and the other is a global variable, inherit the type from the global variable to correctly identify the per-cpu instance. A real-world example is shown below: ffff8000808f2d28 : ffff8000808f2d38: adrp x2, ffff800082033000 ffff8000808f2d3c: add x5, x2, #0x3f8 // x5 =3D &__per_cpu_offs= et ffff8000808f2d44: adrp x2, ffff800081f73000 ffff8000808f2d48: add x2, x2, #0x6b8 // x2 =3D &cpu_pcc_subspa= ce_idx ffff8000808f2d6c: ldr x5, [x5, w0, sxtw #3] // x5 =3D __per_cpu_offse= t[cpu] ffff8000808f2d80: ldr w23, [x5, x2] // PMU sample, per_cpu(cp= u_pcc_subspace_idx, cpu) Before this commit, the tracker could not link x5 back to a per-cpu context, resulting in an incorrect data type resolution: adrp [10] global addr=3Dffff800082033000 -> reg2 add [14] global addr=3Dffff8000820333f8 -> reg5 adrp [1c] global addr=3Dffff800081f73000 -> reg2 add [20] global addr=3Dffff800081f736b8 -> reg2 ldr [44] global (ffff8000820333f8) -> reg5 type=3D'long unsigned int[]' s= ize=3D0x1000 chk [58] reg5 offset=3D0 ok=3D1 kind=3D1 (long unsigned int[]) : Good! found by insn track: 0(reg5, reg2) type-offset=3D0 final result: type=3D'long unsigned int' size=3D0x8 After this commit, the tracker correctly identifies the per-cpu flow and resolves the actual variable type: ldr [44] global (ffff8000820333f8) -> reg5 percpu base chk [58] reg5 offset=3D0 ok=3D1 kind=3D2 percpu var : Good! found by insn track: 0(reg5, reg2) type-offset=3D0 final result: type=3D'int' size=3D0x4 Signed-off-by: Tengda Wu --- .../perf/util/annotate-arch/annotate-arm64.c | 69 ++++++++++++++++++- tools/perf/util/annotate-data.c | 33 ++++++--- 2 files changed, 92 insertions(+), 10 deletions(-) diff --git a/tools/perf/util/annotate-arch/annotate-arm64.c b/tools/perf/ut= il/annotate-arch/annotate-arm64.c index 6b954bbfaf8d..89b6b596f984 100644 --- a/tools/perf/util/annotate-arch/annotate-arm64.c +++ b/tools/perf/util/annotate-arch/annotate-arm64.c @@ -378,6 +378,26 @@ static void update_insn_state_arm64(struct type_state = *state, =20 pr_debug_dtp("add [%x] global addr=3D%"PRIx64" -> reg%d\n", insn_offset, tsr->addr, sreg); + return; + } + + /* Handle per-cpu base addresses */ + if (dst_tsr.kind =3D=3D TSR_KIND_PERCPU_BASE) { + if (!dst->multi_regs || !has_reg_type(state, dst->reg2) || + state->regs[dst->reg2].kind !=3D TSR_KIND_GLOBAL_ADDR || + !state->regs[dst->reg2].ok) + return; + + /* Inherit type from the global variable */ + tsr->type =3D state->regs[dst->reg2].type; + tsr->kind =3D state->regs[dst->reg2].kind; + tsr->offset =3D state->regs[dst->reg2].offset; + tsr->addr =3D state->regs[dst->reg2].addr; + tsr->ok =3D true; + + pr_debug_dtp("add [%x] percpu %#"PRIx64" -> reg%d", + insn_offset, tsr->addr, sreg); + pr_debug_type_name(&tsr->type, tsr->kind); } =20 return; @@ -491,6 +511,15 @@ static void update_insn_state_arm64(struct type_state = *state, u64 ip =3D dloc->ms->sym->start + dl->al.offset; u64 addr =3D dst_tsr.addr + dst->offset; int offset; + u8 kind; + const char *var_name =3D NULL; + + /* it might be per-cpu offset */ + if (get_global_var_info(dloc, addr, &var_name, &offset) && + !strcmp(var_name, "__per_cpu_offset")) + kind =3D TSR_KIND_PERCPU_BASE; + else + kind =3D TSR_KIND_TYPE; =20 if (!get_global_var_type(cu_die, dloc, ip, addr, &offset, &type_die) || @@ -500,13 +529,49 @@ static void update_insn_state_arm64(struct type_state= *state, } =20 tsr->type =3D type_die; - tsr->kind =3D TSR_KIND_TYPE; + tsr->kind =3D kind; tsr->offset =3D offset; - tsr->addr =3D addr; + tsr->addr =3D 0; tsr->ok =3D true; + pr_debug_dtp("ldr [%x] global (%"PRIx64") -> reg%d", insn_offset, addr, sreg); pr_debug_type_name(&tsr->type, tsr->kind); + return; + } + + /* Or check if it's a per-cpu base address */ + if (dst_tsr.kind =3D=3D TSR_KIND_PERCPU_BASE) { + u64 ip =3D dloc->ms->sym->start + dl->al.offset; + u64 addr; + int offset; + /* + * If reg2 is a global variable, this means reg1 is + * an index into the variable's per-cpu array, so + * dereference type from reg2. + */ + if (!dst->multi_regs || !has_reg_type(state, dst->reg2) || + state->regs[dst->reg2].kind !=3D TSR_KIND_GLOBAL_ADDR || + !state->regs[dst->reg2].ok) + return; + + addr =3D state->regs[dst->reg2].addr; + if (!get_global_var_type(cu_die, dloc, ip, addr, &offset, + &type_die) || + !die_get_member_type(&type_die, offset, &type_die)) { + tsr->ok =3D false; + return; + } + + tsr->type =3D type_die; + tsr->kind =3D TSR_KIND_TYPE; + tsr->offset =3D offset; + tsr->addr =3D 0; + tsr->ok =3D true; + + pr_debug_dtp("ldr [%x] percpu (reg%d, reg%d) -> reg%d", + insn_offset, dreg, dst->reg2, sreg); + pr_debug_type_name(&tsr->type, tsr->kind); } return; } diff --git a/tools/perf/util/annotate-data.c b/tools/perf/util/annotate-dat= a.c index b75d50b2c46f..7161417d1c76 100644 --- a/tools/perf/util/annotate-data.c +++ b/tools/perf/util/annotate-data.c @@ -1230,20 +1230,37 @@ static enum type_match_result check_matching_type(s= truct type_state *state, } =20 if (state->regs[reg].kind =3D=3D TSR_KIND_PERCPU_BASE) { - u64 var_addr =3D dloc->op->offset; + u64 var_addr; int var_offset; =20 pr_debug_dtp("percpu var"); =20 - if (dloc->op->multi_regs) { - int reg2 =3D dloc->op->reg2; + if (arch__is_arm64(dloc->arch)) { + int reg2; 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dmarc=none (p=none dis=none) header.from=huaweicloud.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=huaweicloud.com Received: from mail.maildlp.com (unknown [172.19.163.170]) by dggsgout12.his.huawei.com (SkyGuard) with ESMTPS id 4fnDRd6Qw5zKHMYS; Fri, 3 Apr 2026 17:47:57 +0800 (CST) Received: from mail02.huawei.com (unknown [10.116.40.252]) by mail.maildlp.com (Postfix) with ESMTP id 7D4F84056D; Fri, 3 Apr 2026 17:48:50 +0800 (CST) Received: from huawei.com (unknown [10.67.174.45]) by APP3 (Coremail) with SMTP id _Ch0CgAnB1TwjM9p8K_UDA--.49742S18; Fri, 03 Apr 2026 17:48:50 +0800 (CST) From: Tengda Wu To: Peter Zijlstra , Namhyung Kim , leo.yan@linux.dev, Li Huafei , Ian Rogers , Kim Phillips , Mark Rutland , Arnaldo Carvalho de Melo , Ingo Molnar Cc: Bill Wendling , Nick Desaulniers , Alexander Shishkin , Adrian Hunter , Zecheng Li , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, llvm@lists.linux.dev, Tengda Wu Subject: [PATCH v2 16/16] perf annotate-arm64: Support 'mrs' instruction to track 'current' pointer Date: Fri, 3 Apr 2026 09:48:00 +0000 Message-Id: <20260403094800.1418825-17-wutengda@huaweicloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260403094800.1418825-1-wutengda@huaweicloud.com> References: <20260403094800.1418825-1-wutengda@huaweicloud.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _Ch0CgAnB1TwjM9p8K_UDA--.49742S18 X-Coremail-Antispam: 1UD129KBjvJXoWxAw4kWryrGr43AFyUJr43ZFb_yoWrZFyfpa yqk345Gr4kGw42gwsxJFZ7ZryfK393Wa45Cr90y34SyF4xKr18t3Z5t3y7Cay5Gr1v9347 Jr4DKrW5GanrCaUanT9S1TB71UUUUUDqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUQv14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_JF0E3s1l82xGYI kIc2x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2 z4x0Y4vE2Ix0cI8IcVAFwI0_tr0E3s1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Cr1j6r xdM28EF7xvwVC2z280aVAFwI0_GcCE3s1l84ACjcxK6I8E87Iv6xkF7I0E14v26rxl6s0D M2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xIIjx v20xvE14v26r106r15McIj6I8E87Iv67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr0_Gr1l F7xvr2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20VAGYxC7M4IIrI8v6xkF7I0E8cxan2 IY04v7MxkF7I0En4kS14v26r4a6rW5MxkF7I0Ew4C26cxK6c8Ij28IcwCF04k20xvY0x0E wIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18MI8I3I0E74 80Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_GFv_WrylIxkGc2Ij64vIr41lIxAIcVC0 I7IYx2IY67AKxVW5JVW7JwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Gr1j6F4UJwCI42IY6x AIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Gr0_Cr1lIxAIcVC2z280aVCY 1x0267AKxVW8Jr0_Cr1UYxBIdaVFxhVjvjDU0xZFpf9x0pRepBfUUUUU= X-CM-SenderInfo: pzxwv0hjgdqx5xdzvxpfor3voofrz/ Content-Type: text/plain; charset="utf-8" Extend update_insn_state() for arm64 to handle the 'mrs' instruction, enabling the tracking of the 'current' task pointer in the kernel. On arm64, the kernel uses the 'sp_el0' system register to store the address of the currently executing 'struct task_struct'. This is typically accessed via the 'get_current()' inline function, resulting in the instruction 'mrs xN, sp_el0'. To resolve the data type of the target register, first verify the access is to 'sp_el0' within a kernel DSO. Then, locate the 'get_current()' inline function's DWARF Die at the current PC and extract its return type (which is 'struct task_struct *'). Introduce a global 'task_struct_off' cache to store the DWARF offset of this type. This is particularly important because the compiler-generated stack canary check code (which loads from 'current') often exists in code sections or leaf functions where the local Compilation Unit (CU) lacks a full 'struct task_struct' definition. Caching the offset allows 'perf annotate' to consistently resolve task-related fields across the entire kernel binary. A real-world example is shown below: ffff8000800deee8 : ffff8000800deef0: mrs x0, sp_el0 // x0 =3D current ffff8000800deef4: ldr w1, [x0, #44] // Access task_struct member Before this commit, the type flow starts with no information: chk [c] reg0 offset=3D0x2c ok=3D0 kind=3D0 cfa : no type information final result: no type information After this commit, the tracker identifies the 'current' pointer from the system register: mrs [8] sp_el0 -> reg0 type=3D'struct task_struct*' chk [c] reg0 offset=3D0x2c ok=3D1 kind=3D1 (struct task_struct*) : Good! found by insn track: 0x2c(reg0) type-offset=3D0x2c final result: type=3D'struct task_struct' Signed-off-by: Li Huafei Signed-off-by: Tengda Wu --- .../perf/util/annotate-arch/annotate-arm64.c | 53 +++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/tools/perf/util/annotate-arch/annotate-arm64.c b/tools/perf/ut= il/annotate-arch/annotate-arm64.c index 89b6b596f984..b03b12594260 100644 --- a/tools/perf/util/annotate-arch/annotate-arm64.c +++ b/tools/perf/util/annotate-arch/annotate-arm64.c @@ -14,6 +14,7 @@ #include "../debug.h" #include "../map.h" #include "../symbol.h" +#include "../dso.h" =20 struct arch_arm64 { struct arch arch; @@ -289,6 +290,8 @@ static void adjust_reg_index_state(struct type_state *s= tate, int reg, pr_debug_type_name(&tsr->type, tsr->kind); } =20 +static Dwarf_Off task_struct_off; + static void update_insn_state_arm64(struct type_state *state, struct data_loc_info *dloc, Dwarf_Die *cu_die, struct disasm_line *dl) @@ -309,6 +312,56 @@ static void update_insn_state_arm64(struct type_state = *state, sreg =3D src->reg1; dreg =3D dst->reg1; =20 + if (!strcmp(dl->ins.name, "mrs")) { + Dwarf_Die func_die; + Dwarf_Attribute attr; + u64 ip, pc; + + if (!has_reg_type(state, sreg)) + return; + + /* Handle case difference: LLVM (SP_EL0) vs objdump (sp_el0) */ + if (!dso__kernel(map__dso(dloc->ms->map)) || + strcasecmp(dl->ops.target.raw, "sp_el0")) + return; + + ip =3D dloc->ms->sym->start + dl->al.offset; + pc =3D map__rip_2objdump(dloc->ms->map, ip); + + if (!task_struct_off || + !dwarf_offdie(dloc->di->dbg, task_struct_off, &type_die)) { + /* + * Find the inline function 'get_current()' Dwarf_Die + * and obtain its return value data type, which should + * be 'struct task_struct *'. + */ + if (!die_find_inlinefunc(cu_die, pc, &func_die) || + !dwarf_attr_integrate(&func_die, DW_AT_type, &attr) || + !dwarf_formref_die(&attr, &type_die)) + return; + + /* + * Cache the 'struct task_struct *' die offset globally. + * This allows us to resolve stack canary accesses even + * in CUs that lack a full task_struct definition (e.g., + * compiler-generated entry/exit code). + */ + task_struct_off =3D dwarf_dieoffset(&type_die); + } + + tsr =3D &state->regs[sreg]; + tsr->copied_from =3D -1; + tsr->type =3D type_die; + tsr->kind =3D TSR_KIND_TYPE; + tsr->offset =3D 0; + tsr->addr =3D 0; + tsr->ok =3D true; + + pr_debug_dtp("mrs [%x] sp_el0 -> reg%d", insn_offset, sreg); + pr_debug_type_name(&type_die, tsr->kind); + return; + } + if (!strcmp(dl->ins.name, "adrp")) { if (!has_reg_type(state, sreg) || !dl->ops.target.addr) return; --=20 2.34.1