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Fri, 3 Apr 2026 02:10:04 -0700 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , "Alexei Starovoitov" , Daniel Borkmann , "Jesper Dangaard Brouer" , John Fastabend , Stanislav Fomichev , Dragos Tatulea , Cosmin Ratiu , Simon Horman , "Jacob Keller" , Lama Kayal , "Michal Swiatkowski" , Carolina Jubran , Nathan Chancellor , Daniel Zahka , Rahul Rameshbabu , "Raed Salem" , , , , , Gal Pressman Subject: [PATCH net-next V2 1/5] net/mlx5e: XSK, Increase size for chunk_size param Date: Fri, 3 Apr 2026 12:09:23 +0300 Message-ID: <20260403090927.139042-2-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260403090927.139042-1-tariqt@nvidia.com> References: <20260403090927.139042-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000C618E:EE_|CY8PR12MB7289:EE_ X-MS-Office365-Filtering-Correlation-Id: 64182260-9c0b-4c74-21ec-08de9160db75 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|1800799024|36860700016|7416014|22082099003|18002099003|56012099003; X-Microsoft-Antispam-Message-Info: Y4nIDdKr3/nWt5mHih48DNnR3bag66lq/F+lozt4MTtPkCTS7hM3c+EutAfzkCLtuOy14Pt73dXMzgiIcGJB7MLxoEEziB1HEQ3R4shgMzKAg+YMMN7TJsm4WCPQ5WFF9e3L4fw1Ch4K3kO4bOUYvO+7cWubQXLWmPDkxp+3XySbxC1h2lr8QuSlrAtfyphHUdx+2xaK06KtyPuMOOQ8BdtYpcabWTNRuoBZLQtBb635jK3+6wH1PcvGz0YjovOg3PiNf4+gu9XuGruBw5uwNMEpX4b+HzXWw1CLIh6JySnhbI9EY//89OFCbbzDVw0GfmiAXW0jTwqanqpcoM4ToEKzSwTw/wGoNeKSyTVg0MKNEF7uzMFlYMgBxx514FIcPOBQI9C3vRBfeqbWjvmjx13fbKAlpF8YwImnRjA2dkLN5Xh55TdcFxSF3S75akL7TJlDWhWXY/3jYJsxA0syTrzmvMlfvfQZ5VEdbJ3ggygqN7BfBAubjDTSU0cHDDw9Le/KGE8CJG/4wpx0AsT37CWn5Oa0uPAj4MZ9Dv9edf8B19IOeOUDbtLL0qvopccQMIMMj9EqwGQgdZD9eUSeyZBRAIHjzIdxGtO8Ld3Kyv2G+RVQYlGIDmSNoQyc9R73mtL56kNQj0ludDYVnHDub48D+y7xaDc0sbaQdWi1NHa98sFCnGrpdFlucwS/RlNrmxWajPlMyMPKEKwmThpCc6/zBqdlbV/KXarurvJVkZwKtgeS3zmO0Txk9Byp1GXjG5chrTAaCTNespyru3XDDQ== X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(82310400026)(1800799024)(36860700016)(7416014)(22082099003)(18002099003)(56012099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: miOaw0hsV1kWHcjxzz6MRjRfuA8n0e6+SKaQ1Ib0cDQ80s6TXXGIZCcD5jgis8kc4X3jvgvk/p/qALVQsjGfcSYCzXXeP20zgA88u488dmvUK0yD+ThWQXO2JOVTO4Ww8gT1fdP+7x2EqWmAvg3giloKzOfHTJI+DtkdJG8g6eFoopzFuzMo3DcBVVnGZjT635dhrmSnS/gL6rmlBLVVcJ/ldRX5VmGDP4HQGvmp4FIncR4/9BIKDU8PxKhef95pCpolSxghjluBvzpcVn/GJdy3N86YLvtki+6hdBuCHPBf0hfOpItwnoqSuvnIvDqNCTlxAOyjcdVs7FNAMa08HUKO41f8TwuQ3munLo3hp6I7MUvrRj37qgVXTdhdbdjnxFgA7tPdRQfqsSniVeWhi+VY5dNOPPX98ABBFfhDRP3E19zevQTbw3kQKfGYfwTG X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Apr 2026 09:10:31.6432 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 64182260-9c0b-4c74-21ec-08de9160db75 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000C618E.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7289 Content-Type: text/plain; charset="utf-8" From: Dragos Tatulea When 64K pages are used, chunk_size can take the 64K value which doesn't fit in u16. This results in overflows that are detected in mlx5e_mpwrq_log_wqe_sz(). Increase the type to u32 to fix this. Signed-off-by: Dragos Tatulea Reviewed-by: Carolina Jubran Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/en/params.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/params.h b/drivers/= net/ethernet/mellanox/mlx5/core/en/params.h index 9b1a2aed17c3..275f9be53a34 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/params.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/params.h @@ -8,7 +8,7 @@ =20 struct mlx5e_xsk_param { u16 headroom; - u16 chunk_size; + u32 chunk_size; bool unaligned; }; =20 --=20 2.44.0 From nobody Mon Apr 6 16:23:50 2026 Received: from BL2PR02CU003.outbound.protection.outlook.com (mail-eastusazon11011015.outbound.protection.outlook.com [52.101.52.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B24EE351C21; Fri, 3 Apr 2026 09:10:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , "Alexei Starovoitov" , Daniel Borkmann , "Jesper Dangaard Brouer" , John Fastabend , Stanislav Fomichev , Dragos Tatulea , Cosmin Ratiu , Simon Horman , "Jacob Keller" , Lama Kayal , "Michal Swiatkowski" , Carolina Jubran , Nathan Chancellor , Daniel Zahka , Rahul Rameshbabu , "Raed Salem" , , , , , Gal Pressman Subject: [PATCH net-next V2 2/5] net/mlx5e: XDP, Improve dma address calculation of linear part for XDP_TX Date: Fri, 3 Apr 2026 12:09:24 +0300 Message-ID: <20260403090927.139042-3-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260403090927.139042-1-tariqt@nvidia.com> References: <20260403090927.139042-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000C6193:EE_|LV5PR12MB9827:EE_ X-MS-Office365-Filtering-Correlation-Id: e54f1a06-4f6c-4702-7f8f-08de9160ddbe X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|82310400026|36860700016|7416014|22082099003|18002099003|56012099003; X-Microsoft-Antispam-Message-Info: YMNwlsnT848i/ZXCFsW4OfMTwWEwp5hZPuohrGS0r70O1A1n/KvvXiQGzPZoRZ12X5xU8m2Qv5fouCc3IpOx7Tat9+l1AQMA/QUAhshNiqOnP8vhpxo3vMpyVG7XBZ84Ki426NzuSmw5asXw9MXsQ7Qc5kdkj0qiAbqqDNY56cN+XATzC6pLQFd4s7oadQs/FVsQGiE3UeLtdB/wmm7HSQb6siFZFw+HY9oQEsStEQPFRZUxgmtnEbjVEXumYEPvHffYQZs8+P+3Wn1JbB9cCPB2S4tDTq03Cj9CzHlkK0GjEngKF6tx5EhgUypS3XxIRWT9lWTbzvrYEXpS+yCbCNRyh+Y0y1DIFZ6YLVknHVgBQ7MGA8Mr0p4Ox9+1Eea5R980JbaS5DvRLF4sglaEYJfbB3etk0X2ah7r9rDEMzbbYn63jrZZdVYNqw9CfZisbSWRP70fzqKty3KJeW/ab7K6DBzqRVfg7JEsQ1KsUtNZpxdw2x4AqiBczG94c4DY15UnY3mnGKUHWoH+C0RhfsYXX2cVuUujEoIL4Ylco5D75dJTd7KAIfCuKHg4AIAd0Qp6y0nW0Opf4IDOQXKbSO9TgvhUevl/irx1PbRvoCrBumpQ9L2Fw6YlJVwJ/+ivhgtRjqxvaDZO482sXbb87b1wOyE7vC4zZVgXXJEAN/xXGkPvIZJoUc5lJGJIIMrO+KpMjratnv2VXjs6q1kOlkORkzgrSQaGWhwBqgNVhmlIXRzNcfEmEd36rKujK6B/jYlRRErTEbHh/PbORJOG4w== X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(376014)(82310400026)(36860700016)(7416014)(22082099003)(18002099003)(56012099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: zf2iqqAzP8meeaBVOAbTz2ZNdIijRdxikqHzYtTVAJW4ES/QCD6eqdSCUgedQo9JBYMEjBISQz1RYQC0Z//lfAvMIPt62QZfBlSvQKm55WbdIHnLqU9GyzbqiIVrUsN0Qjb7l8pNSxgm3Zg1Yt1iQhczgU9lZxgiXxOra0Grvpu68ukCe4IkUJxJY8LIVRJAPnfywqEZkYgZERN1uzcSpeyoEr8Kouax1FFcRmsYYH9uHHuHm9tcfqqHQIOTEXHsg+iG3AR3Clj0OuIqp/Jlji78sr5Lb1tc1ZXXETCu9s2oIHhVTVggF5phofvtOkp0tmmcnA8E7GFKGmstLie/1pGbhvY3IY3/y6Kxz8HLQhZj4Q05JRv47etTev/ujtsRLHggb/3BVeeoOFK/9+57RkjDEJ+X5H/k6ixf5cCRjsUtB86a5n/mbq92dedj3OsD X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Apr 2026 09:10:35.4754 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e54f1a06-4f6c-4702-7f8f-08de9160ddbe X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000C6193.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV5PR12MB9827 Content-Type: text/plain; charset="utf-8" From: Dragos Tatulea When calculating the dma address of the linear part of an XDP frame, the formula assumes that there is a single XDP buffer per page. Extend the formula to allow multiple XDP buffers per page by calculating the data offset in the page. This is a preparation for the upcoming removal of a single XDP buffer per page limitation when the formula will no longer be correct. Signed-off-by: Dragos Tatulea Reviewed-by: Carolina Jubran Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/en/xdp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/xdp.c b/drivers/net= /ethernet/mellanox/mlx5/core/en/xdp.c index 04e1b5fa4825..d3bab198c99c 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/xdp.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/xdp.c @@ -123,7 +123,7 @@ mlx5e_xmit_xdp_buff(struct mlx5e_xdpsq *sq, struct mlx5= e_rq *rq, * mode. */ =20 - dma_addr =3D page_pool_get_dma_addr(page) + (xdpf->data - (void *)xdpf); + dma_addr =3D page_pool_get_dma_addr(page) + offset_in_page(xdpf->data); dma_sync_single_for_device(sq->pdev, dma_addr, xdptxd->len, DMA_BIDIRECTI= ONAL); =20 if (xdptxd->has_frags) { --=20 2.44.0 From nobody Mon Apr 6 16:23:50 2026 Received: from BL0PR03CU003.outbound.protection.outlook.com (mail-eastusazon11012056.outbound.protection.outlook.com [52.101.53.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BE857351C21; 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Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , "Alexei Starovoitov" , Daniel Borkmann , "Jesper Dangaard Brouer" , John Fastabend , Stanislav Fomichev , Dragos Tatulea , Cosmin Ratiu , Simon Horman , "Jacob Keller" , Lama Kayal , "Michal Swiatkowski" , Carolina Jubran , Nathan Chancellor , Daniel Zahka , Rahul Rameshbabu , "Raed Salem" , , , , , Gal Pressman Subject: [PATCH net-next V2 3/5] net/mlx5e: XDP, Remove stride size limitation Date: Fri, 3 Apr 2026 12:09:25 +0300 Message-ID: <20260403090927.139042-4-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260403090927.139042-1-tariqt@nvidia.com> References: <20260403090927.139042-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000C6193:EE_|SJ2PR12MB7848:EE_ X-MS-Office365-Filtering-Correlation-Id: 5ad12e53-1087-4ed2-74d9-08de9160e1bf X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|376014|82310400026|7416014|1800799024|56012099003|18002099003|22082099003; X-Microsoft-Antispam-Message-Info: qLDjDfKlrRDKlxPK3KJceVA1ABpwIgypy4n3kR3nGbuRAoKA311C11TcgRDWLA1v6z2oa4GcnWSG0eZ0o1WsLNDJM2fjMkjItKz7C65f/kiC24efk8GHbG2+kHOReYHGOtk7pPamHsEwD4NU1+D8lcfwRoj57f+SeBkugfekZ2VEEVLNk7G3CBWNfl9MKijPHKSl6gmkDNn1vQuBH45DIkrXd/CQ9aZ3pduOtoino+QkEAqFaRGBSpOyyyTXmMNRpvzksJWectTdcuzr1CHpXifddqlmMmRm9dimUV7Ou+/rrPEptYkU3etqLAK7kg0W0LWWxW1i6XY+SNss7Ik0rPmpf7frMOf2xj9u28qKo2549rfIcnScL4Ttgn3JkxusalKCtayBGapm37WDTKzbDLcFEv9Xi4d2IbROu4HSS0Lp7yZmVeGVfcLZRolaAaKqYdZNNJlwgdUzPSMDMoB3LClQSIOiiTTFtiSqavlhK3zkW1xjCVGSIPAimxaVjnZO4As4nc6YJsZ1SZc5WGthwC2nVnZBACvDpRKDYjVkXWG2ATWozRDbQKYrZM2s28cPJf7taKd4f399U+onY/EmVzUtDlXSf0kMisyRs6zMFSBaj1Z9Cp5rXUWc/yl9DQWIn4fVgeE4R5txewTu51rFdXqr3OttjjNjF/5bbPPrTgffaECfuWIdo9GMmuP61ois2JG6n26dkQyAbCPqGKArxwKVfHaCrgFdqwRBLXhuo5YrjKqRYYR+l05j8YYFnJfM6+ijXA3WQI8jAAvdPweRjg== X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700016)(376014)(82310400026)(7416014)(1800799024)(56012099003)(18002099003)(22082099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: pN8fdz8XztV0geeSMdtIesTuXrQdRVyJVwA/WLAuvLJO7Ai7ET9EU1Bo/AEEhKIBA4ZFgyJg0vn278SFvLoNR9YNljrwKrc0gS7JHOHna9qPCmp/wWRTltu0UwkmM22+UfM8W3wqYMQqjIw5PGcnFDA701pvMBuXwVHzySKzCPUKCRX0ayMt0K3zWzX0SyZUnIo3sfBVY5jSxamO5S4F3NU2JrQnaPEFvQ2tddLivzNkd/7Vz1W1/BV69WxB285dEq3vuqe4N+exQDaVmf48ZkGJCjtSNSrdPOd0CBOZCeANfNdsrfJvBDa4rjW8jVAhYzs05lr4S+fL3OepQ9tHGWyAwVQxHVsWg5aD/cA5si7dnL6ddG3QMBmVOeSzi1uJQIJZcCcmHffOLhCzM5+hP5tEFdmP3sChe15F9icyzQ/JiVvGw8v7ii2+hXjKScmB X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Apr 2026 09:10:42.1939 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5ad12e53-1087-4ed2-74d9-08de9160e1bf X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000C6193.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB7848 Content-Type: text/plain; charset="utf-8" From: Dragos Tatulea Currently XDP mode always uses PAGE_SIZE strides. This limitation existed because page fragment counting was not implemented when XDP was added. Furthermore, due to this limitation there were other issues as well on system with larger pages (e.g. 64K): - XDP for Striding RQ was effectively disabled on such systems. - Legacy RQ allows the configuration but uses a fixed scheme of one XDP buffer per page which is inefficient. As fragment counting was added during the driver conversion to page_pool and the support for XDP multi-buffer, it is now possible to remove this stride size limitation. This patch does just that. Now it is possible to use XDP on systems with higher page sizes (e.g. 64K): - For Striding RQ, loading the program is no longer blocked. Although a 64K page can fit any packet, MTUs that result in stride > 8K will still make the RQ in non-linear mode. That's because the HW doesn't support a higher than 8K stride. - For Legacy RQ, the stride size was PAGE_SIZE which was very inefficient. Now the stride size will be calculated relative to MTU. Legacy RQ will always be in linear mode for larger system pages. This can be observed with an XDP_DROP test [1] when running in Legacy RQ mode on a ARM Neoverse-N1 system with a 64K page size: +-----------------------------------------------+ | MTU | baseline | this change | improvement | |------+------------+-------------+-------------| | 1500 | 15.55 Mpps | 18.99 Mpps | 22.0 % | | 9000 | 15.53 Mpps | 18.24 Mpps | 17.5 % | +-----------------------------------------------+ There are performance benefits for Striding RQ mode as well: - Striding RQ non-linear mode now uses 256B strides, just like non-XDP mode. - Striding RQ linear mode can now fit a number of XDP buffers per page that is relative to the MTU size. That means that on 4K page systems and a small enough MTU, 2 XDP buffers can fit in one page. The above benefits for Striding RQ can be observed with an XDP_DROP test [1] when running on a 4K page x86_64 system (Intel Xeon Platinum 8580): +-----------------------------------------------+ | MTU | baseline | this change | improvement | |------+------------+-------------+-------------| | 1000 | 28.36 Mpps | 33.98 Mpps | 19.82 % | | 9000 | 20.76 Mpps | 26.30 Mpps | 26.70 % | +-----------------------------------------------+ [1] Test description: - xdp-bench with XDP_DROP - RX: single queue - TX: sends 64B packets to saturate CPU on RX side Signed-off-by: Dragos Tatulea Reviewed-by: Carolina Jubran Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/en/params.c | 11 ++--------- 1 file changed, 2 insertions(+), 9 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/params.c b/drivers/= net/ethernet/mellanox/mlx5/core/en/params.c index 26bb31c56e45..1f4a547917ba 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/params.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/params.c @@ -298,12 +298,9 @@ static u32 mlx5e_rx_get_linear_stride_sz(struct mlx5_c= ore_dev *mdev, * no_head_tail_room should be set in the case of XDP with Striding RQ * when SKB is not linear. This is because another page is allocated for = the linear part. */ - sz =3D roundup_pow_of_two(mlx5e_rx_get_linear_sz_skb(params, no_head_tail= _room)); + sz =3D mlx5e_rx_get_linear_sz_skb(params, no_head_tail_room); =20 - /* XDP in mlx5e doesn't support multiple packets per page. - * Do not assume sz <=3D PAGE_SIZE if params->xdp_prog is set. - */ - return params->xdp_prog && sz < PAGE_SIZE ? PAGE_SIZE : sz; + return roundup_pow_of_two(sz); } =20 static u8 mlx5e_mpwqe_log_pkts_per_wqe(struct mlx5_core_dev *mdev, @@ -453,10 +450,6 @@ u8 mlx5e_mpwqe_get_log_stride_size(struct mlx5_core_de= v *mdev, return order_base_2(mlx5e_rx_get_linear_stride_sz(mdev, params, rqo, true)); =20 - /* XDP in mlx5e doesn't support multiple packets per page. */ - if (params->xdp_prog) - return PAGE_SHIFT; - return MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev); } =20 --=20 2.44.0 From nobody Mon Apr 6 16:23:50 2026 Received: from DM5PR21CU001.outbound.protection.outlook.com (mail-centralusazon11011047.outbound.protection.outlook.com [52.101.62.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E20BF38A72F; Fri, 3 Apr 2026 09:11:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.62.47 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775207464; 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Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , "Alexei Starovoitov" , Daniel Borkmann , "Jesper Dangaard Brouer" , John Fastabend , Stanislav Fomichev , Dragos Tatulea , Cosmin Ratiu , Simon Horman , "Jacob Keller" , Lama Kayal , "Michal Swiatkowski" , Carolina Jubran , Nathan Chancellor , Daniel Zahka , Rahul Rameshbabu , "Raed Salem" , , , , , Gal Pressman Subject: [PATCH net-next V2 4/5] net/mlx5e: XDP, Use a single linear page per rq Date: Fri, 3 Apr 2026 12:09:26 +0300 Message-ID: <20260403090927.139042-5-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260403090927.139042-1-tariqt@nvidia.com> References: <20260403090927.139042-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE31:EE_|DS0PR12MB7701:EE_ X-MS-Office365-Filtering-Correlation-Id: 3b07f924-517e-4593-50b5-08de9160e63d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|7416014|36860700016|376014|18002099003|56012099003|22082099003; X-Microsoft-Antispam-Message-Info: uhFfsVlc3Pzs04uss7/KD+E8+wHPBQ9SgiMP58MCZ6HIeLRO0sZAZVcdRfSOIadIR+KBJPvDbVpsx7vsfp1h8aij6bgAzP/R1FQombD7LQZ23o5WX0v6JfJX/NmliY1ClC8ZY5pWqFBgxXRJUxA0fXQ/U6Mzy5E//jbFdtIVi62BIIBy2KgWvI2XZvi7a+kPDQuLZ43Qs2ct+G714GIQ4AheV6KZRTBbaZzSD7pc3nqLZuBD34bf/XFErrPPuZ7q2Tm/6eXGV2rHUWWIi7b08aZgYG/f8NxbLjfexQx8ev98wzR5a7OBI1FXlFDFNSC0oJ09Iy6J43vicjm0TnsHm2bH3kj0dII3hi2Ipdq9U/GGsBN2BB5nMMxeEc+KXpQlh00jY683eJuKu4oLdrFWxVOveLUM8A3p3VxsPIxrnu9udnlcgP9ZtE9wQI/29s12aoipJDXjB9/QZiJFQy7FfAcCwyGOF1LD83gOjv1YaMFRG1EYn4BojuR/gUpMBHELuoRSChduPWLOh1Pecg/Zwid/8y/mNOZuf3X9QrzGzzR6Rzpcz7eBmSzHi0465wYLWFIGibDJeiJA4vizhAj4cTz42hcg8OXsJ9x6pFRhC+dTsLbPNzwnpnnlPiMMQE+d+H2ZFV8i3eCvGzLZq2nCYn730m4c83Ag8kmU7mjHy0TVh2A2Oh74yv6Te/nm5YShT/kVdKfzynp2rpxKGOnMJ0Q4Wa0fCFzxFkZPoMv2moMfTo4lf7dsaiIqAULoUJTCYGYFZcW4mmvliVnSeeLDYw== X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(7416014)(36860700016)(376014)(18002099003)(56012099003)(22082099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: qAt6y/2uVZtKRL/vEujYRmYQt4ijb9WNh+NhomIhI2yEDldBZFa9Ja/zVv4Ins8sAt37VbqhzVuwA3JiClVamIWOdKAaW8ITiJuPSwxMm9Ttqrm5G0WSX3QvzC94ZkNJF2zlOIXoNmX/iM/D+OGqtb2MVLUBeetU9o4dQN8GX21w3SK40qFxoSxHvwm9yvPVOHGl2eb6w2G5S5lDWpSzGr97Ha5zE17N3GFuSk29wp6aTtt5KVCVsM3nNw50BzqWdsxPoN23fP59r4g/wpdPS9uFwzQz89awc1iOZFPWodo2vUxgcOHNZPpCpeoHg75yY/S7BX1JbVy4b4M1PJIkWVxuUYT3PgciwQ6mg18xoJfHBSHXpGeZyN41K2KVHcyimoXPjygdjz8TPfm3XXOQPTbgGiODBwxesKLEjzPkR+xQHT0plW0NYbAdXF0/bML8 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Apr 2026 09:10:49.7527 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3b07f924-517e-4593-50b5-08de9160e63d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE31.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7701 Content-Type: text/plain; charset="utf-8" From: Dragos Tatulea Currently in striding rq there is one mlx5e_frag_page member per WQE for the linear page. This linear page is used only in XDP multi-buffer mode. This is wasteful because only one linear page is needed per rq: the page gets refreshed on every packet, regardless of WQE. Furthermore, it is not needed in other modes (non-XDP, XDP single-buffer). This change moves the linear page into its own structure (struct mlx5_mpw_linear_info) and allocates it only when necessary. A special structure is created because an upcoming patch will extend this structure to support fragmentation of the linear page. This patch has no functional changes. Signed-off-by: Dragos Tatulea Reviewed-by: Carolina Jubran Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/en.h | 6 ++- .../net/ethernet/mellanox/mlx5/core/en_main.c | 37 ++++++++++++++++--- .../net/ethernet/mellanox/mlx5/core/en_rx.c | 17 +++++---- 3 files changed, 47 insertions(+), 13 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en.h b/drivers/net/eth= ernet/mellanox/mlx5/core/en.h index c7ac6ebe8290..592234780f2b 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en.h @@ -591,10 +591,13 @@ union mlx5e_alloc_units { struct mlx5e_mpw_info { u16 consumed_strides; DECLARE_BITMAP(skip_release_bitmap, MLX5_MPWRQ_MAX_PAGES_PER_WQE); - struct mlx5e_frag_page linear_page; union mlx5e_alloc_units alloc_units; }; =20 +struct mlx5e_mpw_linear_info { + struct mlx5e_frag_page frag_page; +}; + #define MLX5E_MAX_RX_FRAGS 4 =20 struct mlx5e_rq; @@ -689,6 +692,7 @@ struct mlx5e_rq { u8 umr_wqebbs; u8 mtts_per_wqe; u8 umr_mode; + struct mlx5e_mpw_linear_info *linear_info; struct mlx5e_shampo_hd *shampo; } mpwqe; }; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/en_main.c index 1238e5356012..aa8359a48b12 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c @@ -369,6 +369,29 @@ static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *= rq, int node) return 0; } =20 +static int mlx5e_rq_alloc_mpwqe_linear_info(struct mlx5e_rq *rq, int node, + struct mlx5e_params *params, + struct mlx5e_rq_opt_param *rqo, + u32 *pool_size) +{ + struct mlx5_core_dev *mdev =3D rq->mdev; + struct mlx5e_mpw_linear_info *li; + + if (mlx5e_rx_mpwqe_is_linear_skb(mdev, params, rqo) || + !params->xdp_prog) + return 0; + + li =3D kvzalloc_node(sizeof(*li), GFP_KERNEL, node); + if (!li) + return -ENOMEM; + + rq->mpwqe.linear_info =3D li; + + /* additional page per packet for the linear part */ + *pool_size *=3D 2; + + return 0; +} =20 static u8 mlx5e_mpwrq_access_mode(enum mlx5e_mpwrq_umr_mode umr_mode) { @@ -915,10 +938,6 @@ static int mlx5e_alloc_rq(struct mlx5e_params *params, mlx5e_mpwqe_get_log_rq_size(mdev, params, rqo); pool_order =3D rq->mpwqe.page_shift - PAGE_SHIFT; =20 - if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params, rqo) && - params->xdp_prog) - pool_size *=3D 2; /* additional page per packet for the linear part */ - rq->mpwqe.log_stride_sz =3D mlx5e_mpwqe_get_log_stride_size(mdev, params, rqo); @@ -936,10 +955,15 @@ static int mlx5e_alloc_rq(struct mlx5e_params *params, if (err) goto err_rq_mkey; =20 - err =3D mlx5_rq_shampo_alloc(mdev, params, rq_param, rq, node); + err =3D mlx5e_rq_alloc_mpwqe_linear_info(rq, node, params, rqo, + &pool_size); if (err) goto err_free_mpwqe_info; =20 + err =3D mlx5_rq_shampo_alloc(mdev, params, rq_param, rq, node); + if (err) + goto err_free_mpwqe_linear_info; + break; default: /* MLX5_WQ_TYPE_CYCLIC */ err =3D mlx5_wq_cyc_create(mdev, &rq_param->wq, rqc_wq, @@ -1054,6 +1078,8 @@ static int mlx5e_alloc_rq(struct mlx5e_params *params, switch (rq->wq_type) { case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: mlx5e_rq_free_shampo(rq); +err_free_mpwqe_linear_info: + kvfree(rq->mpwqe.linear_info); err_free_mpwqe_info: kvfree(rq->mpwqe.info); err_rq_mkey: @@ -1081,6 +1107,7 @@ static void mlx5e_free_rq(struct mlx5e_rq *rq) switch (rq->wq_type) { case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: mlx5e_rq_free_shampo(rq); + kvfree(rq->mpwqe.linear_info); kvfree(rq->mpwqe.info); mlx5_core_destroy_mkey(rq->mdev, be32_to_cpu(rq->mpwqe.umr_mkey_be)); mlx5e_free_mpwqe_rq_drop_page(rq); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c b/drivers/net/= ethernet/mellanox/mlx5/core/en_rx.c index f5c0e2a0ada9..feb042d84b8e 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c @@ -1869,6 +1869,7 @@ mlx5e_skb_from_cqe_mpwrq_nonlinear(struct mlx5e_rq *r= q, struct mlx5e_mpw_info *w struct mlx5e_frag_page *frag_page =3D &wi->alloc_units.frag_pages[page_id= x]; u16 headlen =3D min_t(u16, MLX5E_RX_MAX_HEAD, cqe_bcnt); struct mlx5e_frag_page *head_page =3D frag_page; + struct mlx5e_frag_page *linear_page =3D NULL; struct mlx5e_xdp_buff *mxbuf =3D &rq->mxbuf; u32 page_size =3D BIT(rq->mpwqe.page_shift); u32 frag_offset =3D head_offset; @@ -1897,13 +1898,15 @@ mlx5e_skb_from_cqe_mpwrq_nonlinear(struct mlx5e_rq = *rq, struct mlx5e_mpw_info *w if (prog) { /* area for bpf_xdp_[store|load]_bytes */ net_prefetchw(netmem_address(frag_page->netmem) + frag_offset); + + linear_page =3D &rq->mpwqe.linear_info->frag_page; if (unlikely(mlx5e_page_alloc_fragmented(rq->page_pool, - &wi->linear_page))) { + linear_page))) { rq->stats->buff_alloc_err++; return NULL; } =20 - va =3D netmem_address(wi->linear_page.netmem); + va =3D netmem_address(linear_page->netmem); net_prefetchw(va); /* xdp_frame data area */ linear_hr =3D XDP_PACKET_HEADROOM; linear_data_len =3D 0; @@ -1966,10 +1969,10 @@ mlx5e_skb_from_cqe_mpwrq_nonlinear(struct mlx5e_rq = *rq, struct mlx5e_mpw_info *w for (pfp =3D head_page; pfp < frag_page; pfp++) pfp->frags++; =20 - wi->linear_page.frags++; + linear_page->frags++; } mlx5e_page_release_fragmented(rq->page_pool, - &wi->linear_page); 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Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , "Alexei Starovoitov" , Daniel Borkmann , "Jesper Dangaard Brouer" , John Fastabend , Stanislav Fomichev , Dragos Tatulea , Cosmin Ratiu , Simon Horman , "Jacob Keller" , Lama Kayal , "Michal Swiatkowski" , Carolina Jubran , Nathan Chancellor , Daniel Zahka , Rahul Rameshbabu , "Raed Salem" , , , , , Gal Pressman Subject: [PATCH net-next V2 5/5] net/mlx5e: XDP, Use page fragments for linear data in multibuf-mode Date: Fri, 3 Apr 2026 12:09:27 +0300 Message-ID: <20260403090927.139042-6-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260403090927.139042-1-tariqt@nvidia.com> References: <20260403090927.139042-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000C618F:EE_|PH7PR12MB5656:EE_ X-MS-Office365-Filtering-Correlation-Id: 4b14c3e9-bbef-4fb9-7b07-08de9160eb87 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|7416014|36860700016|82310400026|56012099003|18002099003|22082099003; X-Microsoft-Antispam-Message-Info: b2o57Isp+Kwm6S9W8TXLWkXPEGKOqt3L7Fpqc0cQwg4C6QWOwD0FZ+biH9Vz2cXjN3ZiZLp0mXTSPGndMrYJ6/xsRzNyaQhRrM9JlPBVrJxnVY3+9PAO1rQoH2wIQFGe64PzY9a0NKW3vTgHw0CW/IJ/DP4JIwG8HfS01+exmpIe5QB+KKJGcxx2+UvdCA1kHVVUjFn3sBjY5/3QKlPvT1wmtMfYVc3DYLYk9+pSb+hgR/tvQ4Ou7H+bLb2kZSkKNZ1kpUX9aS67E+8wHWpQMbCffmyuHedqWpUmgZ7eRVMhDio7E28owKc91Y3UTcK4ACp7HTPyFwspGULdotgLjV0q560h/BUWPU2k1X6h57AmeUvJeslQZ/phrM+oUvcm3YzHJtJnqch5siWw48gjlaQ1T0nE4888/Qy/lwROHcWtKsMBB0aAE9pGEMdrlK3Ixkke1QwvVy6sBpTVoH0sTHWr4Lq+c7A6JQc83XhaJlPyCm4J44vpstjEb67lv7A6hIDn7VJNk4wmmJdBxlsr7xrY5FE071ePqd+oqfmaF92byMkiNy/5Xv1YEmmgboAWGCK8jlFaLfa64OMgau/tvrzfYrWuGO3NluvH8QnbPym+sCEHEG/awFK9XTfiBoyRHM0ZHHoys0oEgclWLOqwzH6jenjj9YQmeHi+AW6Ck2T9e9pZxRKb0AyOGRKvshjUdhhsWmzf3ukggiSgQN5eyAtSg6yTGbKXHy1T/mllywFx/6VnLkhvmA+C0nDcxCP//U3B8h3Wz/r9lyNVzDdHJg== X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(376014)(7416014)(36860700016)(82310400026)(56012099003)(18002099003)(22082099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: ugQjkdb1KIlpp+LeXBUosL8oaRufyBYSjmEgawx99UqSvf6rOvKXGV+9GN4+KWPi7wzDraaWKWy4sMgRPBWGbLPhNtvT6s9xcB+SACoYPqu3uUaVKHUnJu5GW3DLm7yuKGb929+SMmAFfmDd8Nt9SMnBO+pnOwgJb6hsuwLX/94HvpawyOYcHl5Cw3N0oJWLMTxpB7BGl0tmK+46f30Id21vEyqvPn4vhMk6oiWo7z/RATKMg0FlsF+L/jz3SvYEQUlDk3wsuaHfI0liAiDatBwiHph/kTF2N/uwMzyy/TzChYOpvWrc9zWZJA4yyjwqN78l+M9SznFlwpnAWZE3sTCvw5sTEKpMQkLmtvHuQEXzx+sI0Ujun1qd1YvOs7ZEaRDv+oDaw7JWIdXdqV+IibkA37oBcgAXbLPLPYqgfNYxuhwQV5qQX/CrZLiY5eUL X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Apr 2026 09:10:58.6049 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4b14c3e9-bbef-4fb9-7b07-08de9160eb87 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000C618F.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB5656 Content-Type: text/plain; charset="utf-8" From: Dragos Tatulea Currently in XDP multi-buffer mode for striding rq a whole page is allocated for the linear part of the XDP buffer. This is wasteful, especially on systems with larger page sizes. This change splits the page into fixed sized fragments. The page is replenished when the maximum number of allowed fragments is reached. When a fragment is not used, it will be simply recycled on next packet. This is great for XDP_DROP as the fragment can be recycled for the next packet. In the most extreme case (XDP_DROP everything), there will be 0 fragments used =3D> only one linear page allocation for the lifetime of the XDP program. The previous page_pool size increase was too conservative (doubling the size) and now there are much fewer allocations (1/8 for a 4K page). So drop the page_pool size extension altogether when the linear side page is used. This small improvement is at most visible for XDP_DROP tests with small 64B packets and a large enough MTU for Striding RQ to be in non-linear mode: +----------------------------------------------------------------------+ | System | MTU | baseline | this change | improvement | |----------------------+------+------------+-------------+-------------| | 4K page x86_64 [1] | 9000 | 26.30 Mpps | 30.45 Mpps | 15.80 % | | 64K page aarch64 [2] | 9000 | 15.27 Mpps | 20.10 Mpps | 31.62 % | +----------------------------------------------------------------------+ [1] Intel Xeon Platinum 8580 [2] ARM Neoverse-N1 Signed-off-by: Dragos Tatulea Reviewed-by: Carolina Jubran Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/en.h | 6 ++ .../net/ethernet/mellanox/mlx5/core/en_main.c | 25 ++++++-- .../net/ethernet/mellanox/mlx5/core/en_rx.c | 60 +++++++++++++++---- 3 files changed, 74 insertions(+), 17 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en.h b/drivers/net/eth= ernet/mellanox/mlx5/core/en.h index 592234780f2b..2270e2e550dd 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en.h @@ -82,6 +82,9 @@ struct page_pool; =20 #define MLX5E_PAGECNT_BIAS_MAX U16_MAX #define MLX5E_RX_MAX_HEAD (256) +#define MLX5E_XDP_LOG_MAX_LINEAR_SZ \ + order_base_2(MLX5_SKB_FRAG_SZ(XDP_PACKET_HEADROOM + MLX5E_RX_MAX_HEAD)) + #define MLX5E_SHAMPO_LOG_HEADER_ENTRY_SIZE (8) #define MLX5E_SHAMPO_WQ_HEADER_PER_PAGE \ (PAGE_SIZE >> MLX5E_SHAMPO_LOG_HEADER_ENTRY_SIZE) @@ -596,6 +599,7 @@ struct mlx5e_mpw_info { =20 struct mlx5e_mpw_linear_info { struct mlx5e_frag_page frag_page; + u16 max_frags; }; =20 #define MLX5E_MAX_RX_FRAGS 4 @@ -1081,6 +1085,8 @@ bool mlx5e_reset_rx_moderation(struct dim_cq_moder *c= q_moder, u8 cq_period_mode, bool mlx5e_reset_rx_channels_moderation(struct mlx5e_channels *chs, u8 cq_= period_mode, bool dim_enabled, bool keep_dim_state); =20 +void mlx5e_mpwqe_dealloc_linear_page(struct mlx5e_rq *rq); + struct mlx5e_sq_param; int mlx5e_open_xdpsq(struct mlx5e_channel *c, struct mlx5e_params *params, struct mlx5e_sq_param *param, struct xsk_buff_pool *xsk_pool, diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/en_main.c index aa8359a48b12..4ba198fb9d6c 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c @@ -371,11 +371,11 @@ static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq = *rq, int node) =20 static int mlx5e_rq_alloc_mpwqe_linear_info(struct mlx5e_rq *rq, int node, struct mlx5e_params *params, - struct mlx5e_rq_opt_param *rqo, - u32 *pool_size) + struct mlx5e_rq_opt_param *rqo) { struct mlx5_core_dev *mdev =3D rq->mdev; struct mlx5e_mpw_linear_info *li; + u32 linear_frag_count; =20 if (mlx5e_rx_mpwqe_is_linear_skb(mdev, params, rqo) || !params->xdp_prog) @@ -385,10 +385,22 @@ static int mlx5e_rq_alloc_mpwqe_linear_info(struct ml= x5e_rq *rq, int node, if (!li) return -ENOMEM; =20 + linear_frag_count =3D + BIT(rq->mpwqe.page_shift - MLX5E_XDP_LOG_MAX_LINEAR_SZ); + if (linear_frag_count > U16_MAX) { + netdev_warn(rq->netdev, + "rq %d: linear_frag_count (%u) larger than expected (%u), page_shif= t: %u, log_max_linear_sz: %u\n", + rq->ix, linear_frag_count, U16_MAX, + rq->mpwqe.page_shift, MLX5E_XDP_LOG_MAX_LINEAR_SZ); + kvfree(li); + return -EINVAL; + } + + li->max_frags =3D linear_frag_count; rq->mpwqe.linear_info =3D li; =20 - /* additional page per packet for the linear part */ - *pool_size *=3D 2; + /* Set to max to force allocation on first run. */ + li->frag_page.frags =3D li->max_frags; =20 return 0; } @@ -955,8 +967,7 @@ static int mlx5e_alloc_rq(struct mlx5e_params *params, if (err) goto err_rq_mkey; =20 - err =3D mlx5e_rq_alloc_mpwqe_linear_info(rq, node, params, rqo, - &pool_size); + err =3D mlx5e_rq_alloc_mpwqe_linear_info(rq, node, params, rqo); if (err) goto err_free_mpwqe_info; =20 @@ -1347,6 +1358,8 @@ void mlx5e_free_rx_descs(struct mlx5e_rq *rq) mlx5_wq_ll_pop(wq, wqe_ix_be, &wqe->next.next_wqe_index); } + + mlx5e_mpwqe_dealloc_linear_page(rq); } else { struct mlx5_wq_cyc *wq =3D &rq->wqe.wq; u16 missing =3D mlx5_wq_cyc_missing(wq); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c b/drivers/net/= ethernet/mellanox/mlx5/core/en_rx.c index feb042d84b8e..5b60aa47c75b 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c @@ -300,6 +300,35 @@ static void mlx5e_page_release_fragmented(struct page_= pool *pp, page_pool_put_unrefed_netmem(pp, netmem, -1, true); } =20 +static int mlx5e_mpwqe_linear_page_refill(struct mlx5e_rq *rq) +{ + struct mlx5e_mpw_linear_info *li =3D rq->mpwqe.linear_info; + + if (likely(li->frag_page.frags < li->max_frags)) + return 0; + + if (likely(li->frag_page.netmem)) { + mlx5e_page_release_fragmented(rq->page_pool, &li->frag_page); + li->frag_page.netmem =3D 0; + } + + return mlx5e_page_alloc_fragmented(rq->page_pool, &li->frag_page); +} + +static void *mlx5e_mpwqe_get_linear_page_frag(struct mlx5e_rq *rq) +{ + struct mlx5e_mpw_linear_info *li =3D rq->mpwqe.linear_info; + u32 frag_offset; + + if (unlikely(mlx5e_mpwqe_linear_page_refill(rq))) + return NULL; + + frag_offset =3D li->frag_page.frags << MLX5E_XDP_LOG_MAX_LINEAR_SZ; + WARN_ON(frag_offset >=3D BIT(rq->mpwqe.page_shift)); + + return netmem_address(li->frag_page.netmem) + frag_offset; +} + static inline int mlx5e_get_rx_frag(struct mlx5e_rq *rq, struct mlx5e_wqe_frag_info *frag) { @@ -702,6 +731,22 @@ static void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq= , u16 ix) bitmap_fill(wi->skip_release_bitmap, rq->mpwqe.pages_per_wqe); } =20 +void mlx5e_mpwqe_dealloc_linear_page(struct mlx5e_rq *rq) +{ + struct mlx5e_mpw_linear_info *li =3D rq->mpwqe.linear_info; + + if (!li || !li->frag_page.netmem) + return; + + mlx5e_page_release_fragmented(rq->page_pool, &li->frag_page); + + /* Recovery flow can call this function and then alloc again, so leave + * things in a good state for re-allocation. + */ + li->frag_page.netmem =3D 0; + li->frag_page.frags =3D li->max_frags; +} + INDIRECT_CALLABLE_SCOPE bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq) { struct mlx5_wq_cyc *wq =3D &rq->wqe.wq; @@ -1899,18 +1944,17 @@ mlx5e_skb_from_cqe_mpwrq_nonlinear(struct mlx5e_rq = *rq, struct mlx5e_mpw_info *w /* area for bpf_xdp_[store|load]_bytes */ net_prefetchw(netmem_address(frag_page->netmem) + frag_offset); =20 - linear_page =3D &rq->mpwqe.linear_info->frag_page; - if (unlikely(mlx5e_page_alloc_fragmented(rq->page_pool, - linear_page))) { + va =3D mlx5e_mpwqe_get_linear_page_frag(rq); + if (!va) { rq->stats->buff_alloc_err++; return NULL; } =20 - va =3D netmem_address(linear_page->netmem); net_prefetchw(va); /* xdp_frame data area */ linear_hr =3D XDP_PACKET_HEADROOM; linear_data_len =3D 0; linear_frame_sz =3D MLX5_SKB_FRAG_SZ(linear_hr + MLX5E_RX_MAX_HEAD); + linear_page =3D &rq->mpwqe.linear_info->frag_page; } else { skb =3D napi_alloc_skb(rq->cq.napi, ALIGN(MLX5E_RX_MAX_HEAD, sizeof(long))); @@ -1971,8 +2015,6 @@ mlx5e_skb_from_cqe_mpwrq_nonlinear(struct mlx5e_rq *r= q, struct mlx5e_mpw_info *w =20 linear_page->frags++; } - mlx5e_page_release_fragmented(rq->page_pool, - linear_page); return NULL; /* page/packet was consumed by XDP */ } =20 @@ -1989,15 +2031,11 @@ mlx5e_skb_from_cqe_mpwrq_nonlinear(struct mlx5e_rq = *rq, struct mlx5e_mpw_info *w rq, mxbuf->xdp.data_hard_start, linear_frame_sz, mxbuf->xdp.data - mxbuf->xdp.data_hard_start, len, mxbuf->xdp.data - mxbuf->xdp.data_meta); - if (unlikely(!skb)) { - mlx5e_page_release_fragmented(rq->page_pool, - linear_page); + if (unlikely(!skb)) return NULL; - } =20 skb_mark_for_recycle(skb); linear_page->frags++; - mlx5e_page_release_fragmented(rq->page_pool, linear_page); =20 if (xdp_buff_has_frags(&mxbuf->xdp)) { struct mlx5e_frag_page *pagep; --=20 2.44.0