From nobody Sun Apr 5 13:05:43 2026 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 55DD3372B31; Fri, 3 Apr 2026 06:49:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.244.123.138 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775198999; cv=none; b=jSuuz9rq3PgxXbAOaZ2Q1MO48sf6AQLNMan+dDLR80qs+NNYoeZNeysJ/JdVo9oXXKh+AfBxO9eFc2x5ik7irUQZbmUJFfSuEr9y6nsFpQdXAwsdabF6tJafTS7drFerRykoj0k7aY3SkMa6KPng+JsDmKXrlwWBgqiqFEqPGu4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775198999; c=relaxed/simple; bh=RB83I2nH48G2R5UVVKvA0Wx1mlrNr4P968tNH9JcDDA=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=NKBKCW+RQ88MozHfuBaXz8faMGo3tS6GCet/B17Np/cdILZ+wFRzGL7vvuWwaVYcFUG+IYSuOjZQcmZrwZebWA2VPolIte1IStTjqunEk6bGcvRK+7DlJlVrTHTBX0GIKHsw2Zduv8fX8dztfjHopbgZY9NuN7vBaqaDVo9Oap8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=FHMJCZ1j; arc=none smtp.client-ip=60.244.123.138 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="FHMJCZ1j" X-UUID: 4cfb559e2f2911f1ae70033691e9ac7d-20260403 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=Lvbv8ytIdTwjGat5iq09ZVK5234WoS7drLcT9eltSXI=; b=FHMJCZ1jXdJb6yChLAATfRRXklLdpgux44U4GxPLLzm6j+4dLX3pyyMqZlBL95SEFczUXkrDRHFbNnt/MrxVRoge1QoB941ZDO6Oek0u+HO/pyngArJXTa5WoX6vA4nCbcHVP2wN7vUHqeLcKDJxfai3sMcGI9q+kGtK9m9l7Qk=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.3.12,REQID:5e50e509-4224-4597-9c3c-c25c95ee9d63,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:e7bac3a,CLOUDID:40e8048f-6df4-4a3d-a7a4-fbdc42d669ce,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102|836|865|888|898,TC:-5,Cont ent:0|15|50,EDM:-3,IP:nil,URL:0,File:130,RT:0,Bulk:nil,QS:nil,BEC:-1,COL:0 ,OSI:0,OSA:0,AV:0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 2,SSN|SDN X-CID-BAS: 2,SSN|SDN,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-CID-RHF: D41D8CD98F00B204E9800998ECF8427E X-UUID: 4cfb559e2f2911f1ae70033691e9ac7d-20260403 Received: from mtkmbs11n2.mediatek.inc [(172.21.101.187)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1440060470; Fri, 03 Apr 2026 14:49:45 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs13n2.mediatek.inc (172.21.101.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.29; Fri, 3 Apr 2026 14:49:44 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.2562.29 via Frontend Transport; Fri, 3 Apr 2026 14:49:43 +0800 From: Jianhua Lin To: , , , , , , CC: , , , , , , , , , Jianhua Lin Subject: [PATCH v6 3/3] media: mediatek: jpeg: add compatible for MT8189 SoC Date: Fri, 3 Apr 2026 14:49:12 +0800 Message-ID: <20260403064912.17259-4-jianhua.lin@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20260403064912.17259-1-jianhua.lin@mediatek.com> References: <20260403064912.17259-1-jianhua.lin@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Compared to the previous generation ICs, the MT8189 uses a 34-bit IOVA address space (16GB) and requires a single clock configuration. Therefore, add new compatible strings ("mediatek,mt8189-jpgenc" and "mediatek,mt8189-jpgdec") along with their specific driver data to support the JPEG encoder and decoder of the MT8189 SoC. Signed-off-by: Jianhua Lin --- .../platform/mediatek/jpeg/mtk_jpeg_core.c | 44 +++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c b/drivers= /media/platform/mediatek/jpeg/mtk_jpeg_core.c index 8c684756d5fc..786cc2942c3a 100644 --- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c +++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c @@ -1867,6 +1867,10 @@ static struct clk_bulk_data mt8173_jpeg_dec_clocks[]= =3D { { .id =3D "jpgdec" }, }; =20 +static struct clk_bulk_data mtk_jpeg_dec_clocks[] =3D { + { .id =3D "jpgdec" }, +}; + static const struct mtk_jpeg_variant mt8173_jpeg_drvdata =3D { .clks =3D mt8173_jpeg_dec_clocks, .num_clks =3D ARRAY_SIZE(mt8173_jpeg_dec_clocks), @@ -1898,6 +1902,38 @@ static const struct mtk_jpeg_variant mtk_jpeg_drvdat= a =3D { .multi_core =3D false, }; =20 +static const struct mtk_jpeg_variant mtk8189_jpegenc_drvdata =3D { + .clks =3D mtk_jpeg_clocks, + .num_clks =3D ARRAY_SIZE(mtk_jpeg_clocks), + .formats =3D mtk_jpeg_enc_formats, + .num_formats =3D MTK_JPEG_ENC_NUM_FORMATS, + .qops =3D &mtk_jpeg_enc_qops, + .irq_handler =3D mtk_jpeg_enc_irq, + .hw_reset =3D mtk_jpeg_enc_reset, + .m2m_ops =3D &mtk_jpeg_enc_m2m_ops, + .dev_name =3D "mtk-jpeg-enc", + .ioctl_ops =3D &mtk_jpeg_enc_ioctl_ops, + .out_q_default_fourcc =3D V4L2_PIX_FMT_YUYV, + .cap_q_default_fourcc =3D V4L2_PIX_FMT_JPEG, + .support_34bit =3D true, +}; + +static const struct mtk_jpeg_variant mtk8189_jpegdec_drvdata =3D { + .clks =3D mtk_jpeg_dec_clocks, + .num_clks =3D ARRAY_SIZE(mtk_jpeg_dec_clocks), + .formats =3D mtk_jpeg_dec_formats, + .num_formats =3D MTK_JPEG_DEC_NUM_FORMATS, + .qops =3D &mtk_jpeg_dec_qops, + .irq_handler =3D mtk_jpeg_dec_irq, + .hw_reset =3D mtk_jpeg_dec_reset, + .m2m_ops =3D &mtk_jpeg_dec_m2m_ops, + .dev_name =3D "mtk-jpeg-dec", + .ioctl_ops =3D &mtk_jpeg_dec_ioctl_ops, + .out_q_default_fourcc =3D V4L2_PIX_FMT_JPEG, + .cap_q_default_fourcc =3D V4L2_PIX_FMT_YUV420M, + .support_34bit =3D true, +}; + static struct mtk_jpeg_variant mtk8195_jpegenc_drvdata =3D { .formats =3D mtk_jpeg_enc_formats, .num_formats =3D MTK_JPEG_ENC_NUM_FORMATS, @@ -1937,6 +1973,14 @@ static const struct of_device_id mtk_jpeg_match[] = =3D { .compatible =3D "mediatek,mtk-jpgenc", .data =3D &mtk_jpeg_drvdata, }, + { + .compatible =3D "mediatek,mt8189-jpgenc", + .data =3D &mtk8189_jpegenc_drvdata, + }, + { + .compatible =3D "mediatek,mt8189-jpgdec", + .data =3D &mtk8189_jpegdec_drvdata, + }, { .compatible =3D "mediatek,mt8195-jpgenc", .data =3D &mtk8195_jpegenc_drvdata, --=20 2.45.2