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(unknown [10.28.36.165]) by maili.marvell.com (Postfix) with ESMTP id A05FC3F7051; Thu, 2 Apr 2026 19:55:46 -0700 (PDT) From: Ratheesh Kannoth To: , , CC: , , , , , , , , , , , , , , , , , Ratheesh Kannoth Subject: [PATCH v10 net-next 1/6] octeontx2-af: npc: cn20k: debugfs enhancements Date: Fri, 3 Apr 2026 08:25:28 +0530 Message-ID: <20260403025533.6250-2-rkannoth@marvell.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260403025533.6250-1-rkannoth@marvell.com> References: <20260403025533.6250-1-rkannoth@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=KeffcAYD c=1 sm=1 tr=0 ts=69cf2c39 cx=c_pps a=rEv8fa4AjpPjGxpoe8rlIQ==:117 a=rEv8fa4AjpPjGxpoe8rlIQ==:17 a=A5OVakUREuEA:10 a=VkNPw1HP01LnGYTKEx00:22 a=l0iWHRpgs5sLHlkKQ1IR:22 a=QXcCYyLzdtTjyudCfB6f:22 a=M5GUcnROAAAA:8 a=Ci00bJMBAOu-zhm_1uQA:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDAzMDAyNCBTYWx0ZWRfX3NSE7FVi7o0N wk0zuhQ3HZG7nOH/dbnSOLuz0yzS41AfI16/pq/sjrBWXE7IDPRC0HPCPPtOwPUqIQ+pXcZsDjC nEAoOIp868PU5Sc54fP+ckE1j8bH70Vq0OkTPiK9t4FTC3BpAbogWOB87RfOg8cusg4VekC8/pS QWxuXPDdcgP8LZfQw8YDdG7xIXnnNkuorIMuukloR1MNelMLMtpx6WMgdVuD1WTYnNO0etA5WI3 6TjzN3l4RP8kW9E0PbO50dJpXIy9lPZsXyH4B2U+mf8TMjtUn8szsqWs2uVTGLPA04SlAd51zQv tUyn7ARgYQVp+F8sQSnvYD7TnqlrpStDgCNoXzKqvN7zij5T767z+Q+g1tbtTGS6Ex0SeWjcYO+ 6Ezsq8ad/hS10n+d+5kKlwObi8smbVLsN4QTfcboi5WCMhhZgygjP4AD31biCmdBqjNxiWFXEy6 Ip1DQd+WThK/6Y3nR2w== X-Proofpoint-GUID: 3Ycb3nYoYTK17pWI3jAeQUeMHx_DVWIj X-Proofpoint-ORIG-GUID: 3Ycb3nYoYTK17pWI3jAeQUeMHx_DVWIj X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-03_01,2026-04-02_05,2025-10-01_01 Content-Type: text/plain; charset="utf-8" Improve MCAM visibility and field debugging for CN20K NPC. - Extend "mcam_layout" to show enabled (+) or disabled state per entry so status can be verified without parsing the full "mcam_entry" dump. - Add "dstats" debugfs entry: reports recently hit MCAM indices with packet counts; stats are cleared on read so each read shows deltas. - Add "mismatch" debugfs entry: lists MCAM entries that are enabled but not explicitly allocated, helping diagnose allocation/field issues. Signed-off-by: Ratheesh Kannoth --- .../marvell/octeontx2/af/cn20k/debugfs.c | 126 +++++++++++++++++- .../ethernet/marvell/octeontx2/af/cn20k/npc.c | 16 ++- .../ethernet/marvell/octeontx2/af/cn20k/npc.h | 7 + 3 files changed, 135 insertions(+), 14 deletions(-) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/cn20k/debugfs.c b/dr= ivers/net/ethernet/marvell/octeontx2/af/cn20k/debugfs.c index 3debf2fae1a4..e8f85ed5ead7 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/cn20k/debugfs.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/cn20k/debugfs.c @@ -13,6 +13,7 @@ #include "struct.h" #include "rvu.h" #include "debugfs.h" +#include "cn20k/reg.h" #include "cn20k/npc.h" =20 static int npc_mcam_layout_show(struct seq_file *s, void *unused) @@ -58,7 +59,8 @@ static int npc_mcam_layout_show(struct seq_file *s, void = *unused) "v:%u", vidx0); } =20 - seq_printf(s, "\t%u(%#x) %s\n", idx0, pf1, + seq_printf(s, "\t%u(%#x)%c %s\n", idx0, pf1, + test_bit(idx0, npc_priv->en_map) ? '+' : ' ', map ? buf0 : " "); } goto next; @@ -101,9 +103,13 @@ static int npc_mcam_layout_show(struct seq_file *s, vo= id *unused) vidx1); } =20 - seq_printf(s, "%05u(%#x) %s\t\t%05u(%#x) %s\n", - idx1, pf2, v1 ? buf1 : " ", - idx0, pf1, v0 ? buf0 : " "); + seq_printf(s, "%05u(%#x)%c %s\t\t%05u(%#x)%c %s\n", + idx1, pf2, + test_bit(idx1, npc_priv->en_map) ? '+' : ' ', + v1 ? buf1 : " ", + idx0, pf1, + test_bit(idx0, npc_priv->en_map) ? '+' : ' ', + v0 ? buf0 : " "); =20 continue; } @@ -120,8 +126,9 @@ static int npc_mcam_layout_show(struct seq_file *s, voi= d *unused) vidx0); } =20 - seq_printf(s, "\t\t \t\t%05u(%#x) %s\n", idx0, - pf1, map ? buf0 : " "); + seq_printf(s, "\t\t \t\t%05u(%#x)%c %s\n", idx0, pf1, + test_bit(idx0, npc_priv->en_map) ? '+' : ' ', + map ? buf0 : " "); continue; } =20 @@ -134,7 +141,8 @@ static int npc_mcam_layout_show(struct seq_file *s, voi= d *unused) snprintf(buf1, sizeof(buf1), "v:%05u", vidx1); } =20 - seq_printf(s, "%05u(%#x) %s\n", idx1, pf1, + seq_printf(s, "%05u(%#x)%c %s\n", idx1, pf1, + test_bit(idx1, npc_priv->en_map) ? '+' : ' ', map ? buf1 : " "); } next: @@ -145,6 +153,100 @@ static int npc_mcam_layout_show(struct seq_file *s, v= oid *unused) =20 DEFINE_SHOW_ATTRIBUTE(npc_mcam_layout); =20 +static u64 dstats[MAX_NUM_BANKS][MAX_SUBBANK_DEPTH * MAX_NUM_SUB_BANKS] = =3D {}; +static int npc_mcam_dstats_show(struct seq_file *s, void *unused) +{ + struct npc_priv_t *npc_priv; + int blkaddr, pf, mcam_idx; + u64 stats, delta; + struct rvu *rvu; + u8 key_type; + void *map; + + npc_priv =3D npc_priv_get(); + rvu =3D s->private; + blkaddr =3D rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); + if (blkaddr < 0) + return 0; + + seq_puts(s, "idx\tpfunc\tstats\n"); + for (int bank =3D npc_priv->num_banks - 1; bank >=3D 0; bank--) { + for (int idx =3D npc_priv->bank_depth - 1; idx >=3D 0; idx--) { + mcam_idx =3D bank * npc_priv->bank_depth + idx; + + npc_mcam_idx_2_key_type(rvu, mcam_idx, &key_type); + if (key_type =3D=3D NPC_MCAM_KEY_X4 && bank !=3D 0) + continue; + + if (!test_bit(mcam_idx, npc_priv->en_map)) + continue; + + stats =3D rvu_read64(rvu, blkaddr, + NPC_AF_CN20K_MCAMEX_BANKX_STAT_EXT(idx, bank)); + if (!stats) + continue; + if (stats =3D=3D dstats[bank][idx]) + continue; + + if (stats < dstats[bank][idx]) + dstats[bank][idx] =3D 0; + + pf =3D 0xFFFF; + map =3D xa_load(&npc_priv->xa_idx2pf_map, mcam_idx); + if (map) + pf =3D xa_to_value(map); + + if (stats > dstats[bank][idx]) + delta =3D stats - dstats[bank][idx]; + else + delta =3D stats; + + seq_printf(s, "%u\t%#04x\t%llu\n", + mcam_idx, pf, delta); + dstats[bank][idx] =3D stats; + } + } + return 0; +} +DEFINE_SHOW_ATTRIBUTE(npc_mcam_dstats); + +static int npc_mcam_mismatch_show(struct seq_file *s, void *unused) +{ + struct npc_priv_t *npc_priv; + struct npc_subbank *sb; + int mcam_idx, sb_off; + struct rvu *rvu; + void *map; + int rc; + + npc_priv =3D npc_priv_get(); + rvu =3D s->private; + + seq_puts(s, "index\tsb idx\tkw type\n"); + for (int bank =3D npc_priv->num_banks - 1; bank >=3D 0; bank--) { + for (int idx =3D npc_priv->bank_depth - 1; idx >=3D 0; idx--) { + mcam_idx =3D bank * npc_priv->bank_depth + idx; + + if (!test_bit(mcam_idx, npc_priv->en_map)) + continue; + + map =3D xa_load(&npc_priv->xa_idx2pf_map, mcam_idx); + if (map) + continue; + + rc =3D npc_mcam_idx_2_subbank_idx(rvu, mcam_idx, + &sb, &sb_off); + if (rc) + continue; + + seq_printf(s, "%u\t%d\t%u\n", mcam_idx, sb->idx, + sb->key_type); + } + } + return 0; +} +DEFINE_SHOW_ATTRIBUTE(npc_mcam_mismatch); + static int npc_mcam_default_show(struct seq_file *s, void *unused) { struct npc_priv_t *npc_priv; @@ -257,6 +359,16 @@ int npc_cn20k_debugfs_init(struct rvu *rvu) if (!npc_dentry) return -EFAULT; =20 + npc_dentry =3D debugfs_create_file("dstats", 0444, rvu->rvu_dbg.npc, rvu, + &npc_mcam_dstats_fops); + if (!npc_dentry) + return -EFAULT; + + npc_dentry =3D debugfs_create_file("mismatch", 0444, rvu->rvu_dbg.npc, rv= u, + &npc_mcam_mismatch_fops); + if (!npc_dentry) + return -EFAULT; + npc_dentry =3D debugfs_create_file("mcam_default", 0444, rvu->rvu_dbg.npc, rvu, &npc_mcam_default_fops); =20 diff --git a/drivers/net/ethernet/marvell/octeontx2/af/cn20k/npc.c b/driver= s/net/ethernet/marvell/octeontx2/af/cn20k/npc.c index 7291fdb89b03..e854b85ced9e 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/cn20k/npc.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/cn20k/npc.c @@ -808,6 +808,9 @@ npc_cn20k_enable_mcam_entry(struct rvu *rvu, int blkadd= r, u64 cfg, hw_prio; u8 kw_type; =20 + enable ? set_bit(index, npc_priv.en_map) : + clear_bit(index, npc_priv.en_map); + npc_mcam_idx_2_key_type(rvu, index, &kw_type); if (kw_type =3D=3D NPC_MCAM_KEY_X2) { cfg =3D rvu_read64(rvu, blkaddr, @@ -1016,14 +1019,12 @@ static void npc_cn20k_config_kw_x4(struct rvu *rvu,= struct npc_mcam *mcam, =20 static void npc_cn20k_set_mcam_bank_cfg(struct rvu *rvu, int blkaddr, int mcam_idx, - int bank, u8 kw_type, bool enable, u8 hw_prio) + int bank, u8 kw_type, u8 hw_prio) { struct npc_mcam *mcam =3D &rvu->hw->mcam; u64 bank_cfg; =20 bank_cfg =3D (u64)hw_prio << 24; - if (enable) - bank_cfg |=3D 0x1; =20 if (kw_type =3D=3D NPC_MCAM_KEY_X2) { rvu_write64(rvu, blkaddr, @@ -1119,7 +1120,8 @@ void npc_cn20k_config_mcam_entry(struct rvu *rvu, int= blkaddr, int index, /* TODO: */ /* PF installing VF rule */ npc_cn20k_set_mcam_bank_cfg(rvu, blkaddr, mcam_idx, bank, - kw_type, enable, hw_prio); + kw_type, hw_prio); + npc_cn20k_enable_mcam_entry(rvu, blkaddr, index, enable); } =20 void npc_cn20k_copy_mcam_entry(struct rvu *rvu, int blkaddr, u16 src, u16 = dest) @@ -1735,9 +1737,9 @@ static int npc_subbank_idx_2_mcam_idx(struct rvu *rvu= , struct npc_subbank *sb, return 0; } =20 -static int npc_mcam_idx_2_subbank_idx(struct rvu *rvu, u16 mcam_idx, - struct npc_subbank **sb, - int *sb_off) +int npc_mcam_idx_2_subbank_idx(struct rvu *rvu, u16 mcam_idx, + struct npc_subbank **sb, + int *sb_off) { int bank_off, sb_id; =20 diff --git a/drivers/net/ethernet/marvell/octeontx2/af/cn20k/npc.h b/driver= s/net/ethernet/marvell/octeontx2/af/cn20k/npc.h index 815d0b257a7e..004a556c7b90 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/cn20k/npc.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/cn20k/npc.h @@ -170,6 +170,7 @@ struct npc_defrag_show_node { * @num_banks: Number of banks. * @num_subbanks: Number of subbanks. * @subbank_depth: Depth of subbank. + * @en_map: Enable/disable status. * @kw: Kex configured key type. * @sb: Subbank array. * @xa_sb_used: Array of used subbanks. @@ -193,6 +194,9 @@ struct npc_priv_t { const int num_banks; int num_subbanks; int subbank_depth; + DECLARE_BITMAP(en_map, MAX_NUM_BANKS * + MAX_NUM_SUB_BANKS * + MAX_SUBBANK_DEPTH); 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(unknown [10.28.36.165]) by maili.marvell.com (Postfix) with ESMTP id 680643F7051; Thu, 2 Apr 2026 19:55:53 -0700 (PDT) From: Ratheesh Kannoth To: , , CC: , , , , , , , , , , , , , , , , , Ratheesh Kannoth Subject: [PATCH v10 net-next 2/6] net/mlx5e: heap-allocate devlink param values Date: Fri, 3 Apr 2026 08:25:29 +0530 Message-ID: <20260403025533.6250-3-rkannoth@marvell.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260403025533.6250-1-rkannoth@marvell.com> References: <20260403025533.6250-1-rkannoth@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: 8GYJ5CZcgLtSrfe5CBAFCQgaG33_lLIh X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDAzMDAyNCBTYWx0ZWRfXzSCoIrZqeeCm 7e+ZEXwyn2JAM1YFU07pbQXhfnLVnrJj4QmIqLG5b/aKA45mUUFSgEORVzBPrfpPAzsKjPjts9j bAZ7iCNlnrms0nCyWEwrP3Byn4Qj/iI62YxbqfFHvODvMelFAkc6UuuSz4DEPRjEwjyowQgWYEP XMoP+7PAw1AOiUR28p+B2tJorngxjSq487Dz55BVw/5CiyD9nhNNHpu+0N47cxT4u55iJ/JyTnH l4BkD2ECLa20xY/XlMnIkcNZdeFYnCva443s3UGnMH7+5Qh8Eie0dyMEyc0FscASoVEVkcLGYkH 8agCO2CIfWBdEzezNEGdUJk/igkKhdaGu/YwQZ3SLIEWc3BPRSKQqVNHvLBNymkq/gE7W392TR5 oGzx1jpR3izDR7IEI3DHH8UuGslhoiAYyF9iEed4VJyQA1omptOV+DuQm1n29Rmjvqx17Ubo1Jf ZDMDh7xP9Ur3IJCJWMw== X-Proofpoint-GUID: 8GYJ5CZcgLtSrfe5CBAFCQgaG33_lLIh X-Authority-Analysis: v=2.4 cv=fLs0HJae c=1 sm=1 tr=0 ts=69cf2c42 cx=c_pps a=rEv8fa4AjpPjGxpoe8rlIQ==:117 a=rEv8fa4AjpPjGxpoe8rlIQ==:17 a=A5OVakUREuEA:10 a=VkNPw1HP01LnGYTKEx00:22 a=l0iWHRpgs5sLHlkKQ1IR:22 a=EAYMVhzMl8SCOHhVQcBL:22 a=M5GUcnROAAAA:8 a=aWKQy79EXxaKdZR1qOkA:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-03_01,2026-04-02_05,2025-10-01_01 Content-Type: text/plain; charset="utf-8" union devlink_param_value grows when U64 array params are added to devlink. Keeping a four-element array of that union on the stack in mlx5e_pcie_cong_get_thresh_config() then trips -Wframe-larger-than=3D1280. Allocate the temporary values with kcalloc() and free them on success and error paths. Signed-off-by: Ratheesh Kannoth --- .../ethernet/mellanox/mlx5/core/en/pcie_cong_event.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/pcie_cong_event.c b= /drivers/net/ethernet/mellanox/mlx5/core/en/pcie_cong_event.c index 2eb666a46f39..f02995552129 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/pcie_cong_event.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/pcie_cong_event.c @@ -259,15 +259,21 @@ mlx5e_pcie_cong_get_thresh_config(struct mlx5_core_de= v *dev, MLX5_DEVLINK_PARAM_ID_PCIE_CONG_OUT_HIGH, }; struct devlink *devlink =3D priv_to_devlink(dev); - union devlink_param_value val[4]; + union devlink_param_value *val; + + val =3D kcalloc(4, sizeof(*val), GFP_KERNEL); + if (!val) + return -ENOMEM; =20 for (int i =3D 0; i < 4; i++) { u32 id =3D ids[i]; int err; =20 err =3D devl_param_driverinit_value_get(devlink, id, &val[i]); - if (err) + if (err) { + kfree(val); return err; + } } =20 config->inbound_low =3D val[0].vu16; @@ -275,6 +281,7 @@ mlx5e_pcie_cong_get_thresh_config(struct mlx5_core_dev = *dev, config->outbound_low =3D val[2].vu16; config->outbound_high =3D val[3].vu16; =20 + kfree(val); return 0; } =20 --=20 2.43.0 From nobody Fri Apr 3 06:03:33 2026 Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7FE8B346E56; Fri, 3 Apr 2026 02:56:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=67.231.156.173 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775184980; cv=none; b=FFUitkuB/7Sf11TJkyu4GCZVZHjemeNDD/5ExsqJokUyE14shLpvBY4xTSa0Z2NH6hfRz76HWSml7qfu0wjMcVb8xE+Lkv/eYCS2cGIPwJ77GmV+8LPLTSohVI1Q4BchWyGoh0UblJCym8OFI8mrq5WTNSamjl5qDl0x/FYvXwo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775184980; c=relaxed/simple; bh=HTB5LVyzGaqyGqFg0pLwaSJxY8IvAljyIPE/uW+PIKA=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=iGn1aJ4R6OYl5F3ZgnvfRC/JvbNn33Dyew+rNN4AiRHLRnhx+GopNLbx9ndAw7jtH6l4N3+G/5/4SH+wmcn02fj9a3WcsVHuqlMjNS3ptgSUx6lI+IQ3juLR8B7vbM7GEiSVUVguaJr8BCi7fXkp/jbqLkXuihadJuNyt5muDjM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com; spf=pass smtp.mailfrom=marvell.com; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b=GEuGqSOF; arc=none smtp.client-ip=67.231.156.173 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=marvell.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b="GEuGqSOF" Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 632MB9pW909204; Thu, 2 Apr 2026 19:56:08 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=pfpt0220; bh=f VJaLfVIxjcVE+aNUmi4U4zxQXneXTzyEPQSYqxf0NM=; b=GEuGqSOFWvf5aUejN F51kICux8tsolKu6XQuEsPPnYPgYm/tScc9drSm2Kq8aZXye8U+ojN9KCyC1eXgB umGYBavLnyjhrVFCewTPSQGkjA85tgOCagDu0qxV7NA9hjFZzS7rjPqffVH5eE01 0GnvV0P2RJc8hR4msiKWxQRxpbdzGyjwAI362Pt+Up0P9GIo5+Q1HObacUxFdGB2 3DguTgqLsMmIaxnYhLSKeWYXg+CMANvzV+EvKrKAQw4OaUfvxOSgsGnQCdtwHNcC jQaBtoz3CoC80hU7YF9Rx5CuvN+ckpBMnNxrFEDcx48haG/WbDJvAYRYhZ+hTVOD WVmLQ== Received: from dc5-exch05.marvell.com ([199.233.59.128]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 4da11crmu6-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 02 Apr 2026 19:56:07 -0700 (PDT) Received: from DC5-EXCH05.marvell.com (10.69.176.209) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.25; Thu, 2 Apr 2026 19:56:06 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id 15.2.1544.25 via Frontend Transport; Thu, 2 Apr 2026 19:56:06 -0700 Received: from rkannoth-OptiPlex-7090.. (unknown [10.28.36.165]) by maili.marvell.com (Postfix) with ESMTP id 344EE3F7073; Thu, 2 Apr 2026 19:55:59 -0700 (PDT) From: Ratheesh Kannoth To: , , CC: , , , , , , , , , , , , , , , , , Ratheesh Kannoth Subject: [PATCH v10 net-next 3/6] devlink: Implement devlink param multi attribute nested data values Date: Fri, 3 Apr 2026 08:25:30 +0530 Message-ID: <20260403025533.6250-4-rkannoth@marvell.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260403025533.6250-1-rkannoth@marvell.com> References: <20260403025533.6250-1-rkannoth@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=KeffcAYD c=1 sm=1 tr=0 ts=69cf2c47 cx=c_pps a=rEv8fa4AjpPjGxpoe8rlIQ==:117 a=rEv8fa4AjpPjGxpoe8rlIQ==:17 a=A5OVakUREuEA:10 a=VkNPw1HP01LnGYTKEx00:22 a=l0iWHRpgs5sLHlkKQ1IR:22 a=QXcCYyLzdtTjyudCfB6f:22 a=Ikd4Dj_1AAAA:8 a=M5GUcnROAAAA:8 a=fjkij7JY_VKj8B3xdwgA:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDAzMDAyNCBTYWx0ZWRfXwEa9xY8U9Ij7 67JmNxl6Ha8opUpSDhbu0MUy8O5TPNxt5sDDGm6/LbZk/saMjEGTAsGUw7lR0MJri0dpo5ufLUk V6+beDKjYo29F0UT/LqMHL9rpnojrNS4YIwasGDqiudHoUSB3qhc2LOtxGe/lVYsbt80LJgRAzJ iayHNH4yOffWpnzeiT5tKlbgqvEr3agqDX6T9JARroFygT5aFsomBSQPekVgdsLE27hktiVnQH1 prSgtK0NRAktkc8PrK3xIqPuxc/lqoX/gaGbCc562wy3K5UMqBaQcPXdmVbjvgpKyFTjgu5PouF BK/1/O8ArIIKQX/1iU8f1YG5jqMyO14v3lHvaswt8nT6ufGGyMRxcHDWfsqk4RM8qnSGbXXUd4f Pgz3YYhkKJvtCOMXQkTEyyA2z3ahEcuFzIV4rNqNBK7JcA7fSSVKsuKyQZ9GZ8BshuM/XhB1qct Gl7S89hbKIybzAde+UQ== X-Proofpoint-GUID: m9ddSCwXedH1COYyQ7SB22XUlkyJp8iY X-Proofpoint-ORIG-GUID: m9ddSCwXedH1COYyQ7SB22XUlkyJp8iY X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-03_01,2026-04-02_05,2025-10-01_01 Content-Type: text/plain; charset="utf-8" From: Saeed Mahameed Devlink param value attribute is not defined since devlink is handling the value validating and parsing internally, this allows us to implement multi attribute values without breaking any policies. Devlink param multi-attribute values are considered to be dynamically sized arrays of u64 values, by introducing a new devlink param type DEVLINK_PARAM_TYPE_U64_ARRAY, driver and user space can set a variable count of u32 values into the DEVLINK_ATTR_PARAM_VALUE_DATA attribute. Implement get/set parsing and add to the internal value structure passed to drivers. This is useful for devices that need to configure a list of values for a specific configuration. example: $ devlink dev param show pci/... name multi-value-param name multi-value-param type driver-specific values: cmode permanent value: 0,1,2,3,4,5,6,7 $ devlink dev param set pci/... name multi-value-param \ value 4,5,6,7,0,1,2,3 cmode permanent Signed-off-by: Saeed Mahameed Signed-off-by: Ratheesh Kannoth --- Documentation/netlink/specs/devlink.yaml | 4 ++ include/net/devlink.h | 8 +++ include/uapi/linux/devlink.h | 1 + net/devlink/netlink_gen.c | 2 + net/devlink/param.c | 91 +++++++++++++++++++----- 5 files changed, 89 insertions(+), 17 deletions(-) diff --git a/Documentation/netlink/specs/devlink.yaml b/Documentation/netli= nk/specs/devlink.yaml index b495d56b9137..b619de4fe08a 100644 --- a/Documentation/netlink/specs/devlink.yaml +++ b/Documentation/netlink/specs/devlink.yaml @@ -226,6 +226,10 @@ definitions: value: 10 - name: binary + - + name: u64-array + value: 129 + - name: rate-tc-index-max type: const diff --git a/include/net/devlink.h b/include/net/devlink.h index 3038af6ec017..3a355fea8189 100644 --- a/include/net/devlink.h +++ b/include/net/devlink.h @@ -432,6 +432,13 @@ enum devlink_param_type { DEVLINK_PARAM_TYPE_U64 =3D DEVLINK_VAR_ATTR_TYPE_U64, DEVLINK_PARAM_TYPE_STRING =3D DEVLINK_VAR_ATTR_TYPE_STRING, DEVLINK_PARAM_TYPE_BOOL =3D DEVLINK_VAR_ATTR_TYPE_FLAG, + DEVLINK_PARAM_TYPE_U64_ARRAY =3D DEVLINK_VAR_ATTR_TYPE_U64_ARRAY, +}; + +#define __DEVLINK_PARAM_MAX_ARRAY_SIZE 32 +struct devlink_param_u64_array { + u64 size; + u64 val[__DEVLINK_PARAM_MAX_ARRAY_SIZE]; }; =20 union devlink_param_value { @@ -441,6 +448,7 @@ union devlink_param_value { u64 vu64; char vstr[__DEVLINK_PARAM_MAX_STRING_VALUE]; bool vbool; + struct devlink_param_u64_array u64arr; }; =20 struct devlink_param_gset_ctx { diff --git a/include/uapi/linux/devlink.h b/include/uapi/linux/devlink.h index 7de2d8cc862f..5332223dd6d0 100644 --- a/include/uapi/linux/devlink.h +++ b/include/uapi/linux/devlink.h @@ -406,6 +406,7 @@ enum devlink_var_attr_type { DEVLINK_VAR_ATTR_TYPE_BINARY, __DEVLINK_VAR_ATTR_TYPE_CUSTOM_BASE =3D 0x80, /* Any possible custom types, unrelated to NLA_* values go below */ + DEVLINK_VAR_ATTR_TYPE_U64_ARRAY, }; =20 enum devlink_attr { diff --git a/net/devlink/netlink_gen.c b/net/devlink/netlink_gen.c index eb35e80e01d1..7aaf462f27ee 100644 --- a/net/devlink/netlink_gen.c +++ b/net/devlink/netlink_gen.c @@ -37,6 +37,8 @@ devlink_attr_param_type_validate(const struct nlattr *att= r, case DEVLINK_VAR_ATTR_TYPE_NUL_STRING: fallthrough; case DEVLINK_VAR_ATTR_TYPE_BINARY: + fallthrough; + case DEVLINK_VAR_ATTR_TYPE_U64_ARRAY: return 0; } NL_SET_ERR_MSG_ATTR(extack, attr, "invalid enum value"); diff --git a/net/devlink/param.c b/net/devlink/param.c index cf95268da5b0..2ec85dffd8ac 100644 --- a/net/devlink/param.c +++ b/net/devlink/param.c @@ -252,6 +252,14 @@ devlink_nl_param_value_put(struct sk_buff *msg, enum d= evlink_param_type type, return -EMSGSIZE; } break; + case DEVLINK_PARAM_TYPE_U64_ARRAY: + if (val.u64arr.size > __DEVLINK_PARAM_MAX_ARRAY_SIZE) + return -EMSGSIZE; + + for (int i =3D 0; i < val.u64arr.size; i++) + if (nla_put_uint(msg, nla_type, val.u64arr.val[i])) + return -EMSGSIZE; + break; } return 0; } @@ -304,56 +312,78 @@ static int devlink_nl_param_fill(struct sk_buff *msg,= struct devlink *devlink, u32 portid, u32 seq, int flags, struct netlink_ext_ack *extack) { - union devlink_param_value default_value[DEVLINK_PARAM_CMODE_MAX + 1]; - union devlink_param_value param_value[DEVLINK_PARAM_CMODE_MAX + 1]; bool default_value_set[DEVLINK_PARAM_CMODE_MAX + 1] =3D {}; bool param_value_set[DEVLINK_PARAM_CMODE_MAX + 1] =3D {}; const struct devlink_param *param =3D param_item->param; - struct devlink_param_gset_ctx ctx; + union devlink_param_value *default_value; + union devlink_param_value *param_value; + struct devlink_param_gset_ctx *ctx; struct nlattr *param_values_list; struct nlattr *param_attr; void *hdr; int err; int i; =20 + default_value =3D kcalloc(DEVLINK_PARAM_CMODE_MAX + 1, + sizeof(*default_value), GFP_KERNEL); + if (!default_value) + return -ENOMEM; + + param_value =3D kcalloc(DEVLINK_PARAM_CMODE_MAX + 1, + sizeof(*param_value), GFP_KERNEL); + if (!param_value) { + kfree(default_value); + return -ENOMEM; + } + + ctx =3D kmalloc_obj(*ctx); + if (!ctx) { + kfree(param_value); + kfree(default_value); + return -ENOMEM; + } + /* Get value from driver part to driverinit configuration mode */ for (i =3D 0; i <=3D DEVLINK_PARAM_CMODE_MAX; i++) { if (!devlink_param_cmode_is_supported(param, i)) continue; if (i =3D=3D DEVLINK_PARAM_CMODE_DRIVERINIT) { - if (param_item->driverinit_value_new_valid) + if (param_item->driverinit_value_new_valid) { param_value[i] =3D param_item->driverinit_value_new; - else if (param_item->driverinit_value_valid) + } else if (param_item->driverinit_value_valid) { param_value[i] =3D param_item->driverinit_value; - else - return -EOPNOTSUPP; + } else { + err =3D -EOPNOTSUPP; + goto get_put_fail; + } =20 if (param_item->driverinit_value_valid) { default_value[i] =3D param_item->driverinit_default; default_value_set[i] =3D true; } } else { - ctx.cmode =3D i; - err =3D devlink_param_get(devlink, param, &ctx, extack); + ctx->cmode =3D i; + err =3D devlink_param_get(devlink, param, ctx, extack); if (err) - return err; - param_value[i] =3D ctx.val; + goto get_put_fail; + param_value[i] =3D ctx->val; =20 - err =3D devlink_param_get_default(devlink, param, &ctx, + err =3D devlink_param_get_default(devlink, param, ctx, extack); if (!err) { - default_value[i] =3D ctx.val; + default_value[i] =3D ctx->val; default_value_set[i] =3D true; } else if (err !=3D -EOPNOTSUPP) { - return err; + goto get_put_fail; } } param_value_set[i] =3D true; } =20 + err =3D -EMSGSIZE; hdr =3D genlmsg_put(msg, portid, seq, &devlink_nl_family, flags, cmd); if (!hdr) - return -EMSGSIZE; + goto get_put_fail; =20 if (devlink_nl_put_handle(msg, devlink)) goto genlmsg_cancel; @@ -393,6 +423,9 @@ static int devlink_nl_param_fill(struct sk_buff *msg, s= truct devlink *devlink, nla_nest_end(msg, param_values_list); nla_nest_end(msg, param_attr); genlmsg_end(msg, hdr); + kfree(default_value); + kfree(param_value); + kfree(ctx); return 0; =20 values_list_nest_cancel: @@ -401,7 +434,11 @@ static int devlink_nl_param_fill(struct sk_buff *msg, = struct devlink *devlink, nla_nest_cancel(msg, param_attr); genlmsg_cancel: genlmsg_cancel(msg, hdr); - return -EMSGSIZE; +get_put_fail: + kfree(default_value); + kfree(param_value); + kfree(ctx); + return err; } =20 static void devlink_param_notify(struct devlink *devlink, @@ -507,7 +544,7 @@ devlink_param_value_get_from_info(const struct devlink_= param *param, union devlink_param_value *value) { struct nlattr *param_data; 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(unknown [10.28.36.165]) by maili.marvell.com (Postfix) with ESMTP id ECE1F3F7051; Thu, 2 Apr 2026 19:56:06 -0700 (PDT) From: Ratheesh Kannoth To: , , CC: , , , , , , , , , , , , , , , , , Ratheesh Kannoth Subject: [PATCH v10 net-next 4/6] octeontx2-af: npc: cn20k: add subbank search order control Date: Fri, 3 Apr 2026 08:25:31 +0530 Message-ID: <20260403025533.6250-5-rkannoth@marvell.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260403025533.6250-1-rkannoth@marvell.com> References: <20260403025533.6250-1-rkannoth@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: mtHmLJvndW4oMT7BZmECtdxH8f5Pp0Ck X-Authority-Analysis: v=2.4 cv=RfGdyltv c=1 sm=1 tr=0 ts=69cf2c4e cx=c_pps a=rEv8fa4AjpPjGxpoe8rlIQ==:117 a=rEv8fa4AjpPjGxpoe8rlIQ==:17 a=A5OVakUREuEA:10 a=VkNPw1HP01LnGYTKEx00:22 a=l0iWHRpgs5sLHlkKQ1IR:22 a=TtqV-g6YmW1Jfm2GSLaY:22 a=M5GUcnROAAAA:8 a=-COZLs7YStbzE7aUQ_YA:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDAzMDAyNCBTYWx0ZWRfX34qZlRfDmSfd l0nTXpFbEzE76yJnmEnqtu+10CZ+uKb1U5Fiif3DoWxWm1oIULqk7HAbcWnCdi+0regAde1u8Oe wxRYL291dwuVlBSy0lETXo+3ljn2l/SsTnuO4PbH/ptzEd+OuDXm6VxKoLEnLXXJL5hTVnaAxjz +md8foid2ef1URVxWAIj5IrQe2+VKOoFiEafQKIyNf2w/4rWrMUcTT27sivoBz3symbC8wHxTXK qaSjA1WtH6yilNVYpbM2NWDFXXhd49zFrYEhfdhHx/kBHgTz/yPusHwkCR2ghWVW5+bLK/DDbhN J2QCYTEWH0Q56DBp+lnSM2XUx1IBltfrBIwuWOFg+QnGICGJQXXzxmoK+RBvb4TUjUr0Zay/9pZ YHjCyETHe7ScKruiR4Wdj+8Yp6CGu5jl1RmO1FAMO5PQmWne2Sbe5heTcNQ5nEU38ILfMOigh0u 60sikWa2Yzv5h8pHbkQ== X-Proofpoint-GUID: mtHmLJvndW4oMT7BZmECtdxH8f5Pp0Ck X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-03_01,2026-04-02_05,2025-10-01_01 Content-Type: text/plain; charset="utf-8" CN20K NPC MCAM is split into 32 subbanks that are searched in a predefined order during allocation. Lower-numbered subbanks have higher priority than higher-numbered ones. Add a runtime devlink parameter "srch_order" ( DEVLINK_PARAM_TYPE_U32_ARRAY) to control the order in which subbanks are searched during MCAM allocation. Signed-off-by: Ratheesh Kannoth --- .../ethernet/marvell/octeontx2/af/cn20k/npc.c | 91 +++++++++++++++++- .../ethernet/marvell/octeontx2/af/cn20k/npc.h | 2 + .../marvell/octeontx2/af/rvu_devlink.c | 92 +++++++++++++++++-- 3 files changed, 173 insertions(+), 12 deletions(-) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/cn20k/npc.c b/driver= s/net/ethernet/marvell/octeontx2/af/cn20k/npc.c index e854b85ced9e..153765b3e504 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/cn20k/npc.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/cn20k/npc.c @@ -3317,7 +3317,7 @@ rvu_mbox_handler_npc_cn20k_get_kex_cfg(struct rvu *rv= u, return 0; } =20 -static int *subbank_srch_order; +static u32 *subbank_srch_order; =20 static void npc_populate_restricted_idxs(int num_subbanks) { @@ -3329,7 +3329,7 @@ static int npc_create_srch_order(int cnt) { int val =3D 0; =20 - subbank_srch_order =3D kcalloc(cnt, sizeof(int), + subbank_srch_order =3D kcalloc(cnt, sizeof(u32), GFP_KERNEL); if (!subbank_srch_order) return -ENOMEM; @@ -3809,6 +3809,93 @@ static void npc_unlock_all_subbank(void) mutex_unlock(&npc_priv.sb[i].lock); } =20 +int npc_cn20k_search_order_set(struct rvu *rvu, + u64 arr[MAX_NUM_SUB_BANKS], int cnt) +{ + struct npc_mcam *mcam =3D &rvu->hw->mcam; + u32 fslots[MAX_NUM_SUB_BANKS][2]; + u32 uslots[MAX_NUM_SUB_BANKS][2]; + int fcnt =3D 0, ucnt =3D 0; + struct npc_subbank *sb; + int idx, val, rc =3D 0; + + unsigned long index; + void *v; + + if (cnt !=3D npc_priv.num_subbanks) { + dev_err(rvu->dev, "Number of entries(%u) !=3D %u\n", + cnt, npc_priv.num_subbanks); + return -EINVAL; + } + + mutex_lock(&mcam->lock); + npc_lock_all_subbank(); + restrict_valid =3D false; + + for (int i =3D 0; i < cnt; i++) + subbank_srch_order[i] =3D (u32)arr[i]; + + xa_for_each(&npc_priv.xa_sb_used, index, v) { + val =3D xa_to_value(v); + uslots[ucnt][0] =3D index; + uslots[ucnt][1] =3D val; + xa_erase(&npc_priv.xa_sb_used, index); + ucnt++; + } + + xa_for_each(&npc_priv.xa_sb_free, index, v) { + val =3D xa_to_value(v); + fslots[fcnt][0] =3D index; + fslots[fcnt][1] =3D val; + xa_erase(&npc_priv.xa_sb_free, index); + fcnt++; + } + + /* xa_store() is done under lock. If xa_store fails + * ,no rollback is planned as it might also fail. + */ + for (int i =3D 0; i < ucnt; i++) { + idx =3D uslots[i][1]; + sb =3D &npc_priv.sb[idx]; + sb->arr_idx =3D subbank_srch_order[sb->idx]; + rc =3D xa_err(xa_store(&npc_priv.xa_sb_used, sb->arr_idx, + xa_mk_value(sb->idx), GFP_KERNEL)); + if (rc) { + dev_err(rvu->dev, + "Error to insert index to used list %u\n", + sb->idx); + goto fail_used; + } + } + + for (int i =3D 0; i < fcnt; i++) { + idx =3D fslots[i][1]; + sb =3D &npc_priv.sb[idx]; + sb->arr_idx =3D subbank_srch_order[sb->idx]; + rc =3D xa_err(xa_store(&npc_priv.xa_sb_free, sb->arr_idx, + xa_mk_value(sb->idx), GFP_KERNEL)); + if (rc) { + dev_err(rvu->dev, + "Error to insert index to free list %u\n", + sb->idx); + goto fail_used; + } + } + +fail_used: + npc_unlock_all_subbank(); + mutex_unlock(&mcam->lock); + + return rc; +} + +const u32 *npc_cn20k_search_order_get(bool *restricted_order, u32 *sz) +{ + *restricted_order =3D restrict_valid; + *sz =3D npc_priv.num_subbanks; + return subbank_srch_order; +} + /* Only non-ref non-contigous mcam indexes * are picked for defrag process */ diff --git a/drivers/net/ethernet/marvell/octeontx2/af/cn20k/npc.h b/driver= s/net/ethernet/marvell/octeontx2/af/cn20k/npc.h index 004a556c7b90..6f9f796940f3 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/cn20k/npc.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/cn20k/npc.h @@ -343,5 +343,7 @@ int npc_cn20k_defrag(struct rvu *rvu); int npc_mcam_idx_2_subbank_idx(struct rvu *rvu, u16 mcam_idx, struct npc_subbank **sb, int *sb_off); +const u32 *npc_cn20k_search_order_get(bool *restricted_order, u32 *sz); +int npc_cn20k_search_order_set(struct rvu *rvu, u64 arr[32], int cnt); =20 #endif /* NPC_CN20K_H */ diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_devlink.c b/driv= ers/net/ethernet/marvell/octeontx2/af/rvu_devlink.c index 6494a9ee2f0d..0e8e33c836c9 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_devlink.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_devlink.c @@ -1258,6 +1258,7 @@ enum rvu_af_dl_param_id { RVU_AF_DEVLINK_PARAM_ID_NPC_EXACT_FEATURE_DISABLE, RVU_AF_DEVLINK_PARAM_ID_NPC_DEF_RULE_CNTR_ENABLE, RVU_AF_DEVLINK_PARAM_ID_NPC_DEFRAG, + RVU_AF_DEVLINK_PARAM_ID_NPC_SRCH_ORDER, RVU_AF_DEVLINK_PARAM_ID_NIX_MAXLF, }; =20 @@ -1619,12 +1620,83 @@ static int rvu_devlink_eswitch_mode_set(struct devl= ink *devlink, u16 mode, return 0; } =20 +static int rvu_af_dl_npc_srch_order_set(struct devlink *devlink, u32 id, + struct devlink_param_gset_ctx *ctx, + struct netlink_ext_ack *extack) +{ + struct rvu_devlink *rvu_dl =3D devlink_priv(devlink); + struct rvu *rvu =3D rvu_dl->rvu; + + return npc_cn20k_search_order_set(rvu, + ctx->val.u64arr.val, + ctx->val.u64arr.size); +} + +static int rvu_af_dl_npc_srch_order_get(struct devlink *devlink, u32 id, + struct devlink_param_gset_ctx *ctx, + struct netlink_ext_ack *extack) +{ + bool restricted_order; + const u32 *order; + u32 sz; + + order =3D npc_cn20k_search_order_get(&restricted_order, &sz); + ctx->val.u64arr.size =3D sz; + for (int i =3D 0; i < sz; i++) + ctx->val.u64arr.val[i] =3D order[i]; + + return 0; +} + +static int rvu_af_dl_npc_srch_order_validate(struct devlink *devlink, u32 = id, + union devlink_param_value val, + struct netlink_ext_ack *extack) +{ + struct rvu_devlink *rvu_dl =3D devlink_priv(devlink); + struct rvu *rvu =3D rvu_dl->rvu; + bool restricted_order; + unsigned long w =3D 0; + u64 *arr; + u32 sz; + + npc_cn20k_search_order_get(&restricted_order, &sz); + if (sz !=3D val.u64arr.size) { + dev_err(rvu->dev, + "Wrong size %llu, should be %u\n", + val.u64arr.size, sz); + return -EINVAL; + } + + arr =3D val.u64arr.val; + for (int i =3D 0; i < sz; i++) { + if (arr[i] >=3D sz) + return -EINVAL; + + w |=3D BIT_ULL(arr[i]); + } + + if (bitmap_weight(&w, sz) !=3D sz) { + dev_err(rvu->dev, + "Duplicate or out-of-range subbank index. %lu\n", + find_first_zero_bit(&w, sz)); + return -EINVAL; + } + + return 0; +} + static const struct devlink_ops rvu_devlink_ops =3D { .eswitch_mode_get =3D rvu_devlink_eswitch_mode_get, .eswitch_mode_set =3D rvu_devlink_eswitch_mode_set, }; =20 -static const struct devlink_param rvu_af_dl_param_defrag[] =3D { +static const struct devlink_param rvu_af_dl_cn20k_params[] =3D { + DEVLINK_PARAM_DRIVER(RVU_AF_DEVLINK_PARAM_ID_NPC_SRCH_ORDER, + "npc_srch_order", DEVLINK_PARAM_TYPE_U64_ARRAY, + BIT(DEVLINK_PARAM_CMODE_RUNTIME), + rvu_af_dl_npc_srch_order_get, + rvu_af_dl_npc_srch_order_set, + rvu_af_dl_npc_srch_order_validate), DEVLINK_PARAM_DRIVER(RVU_AF_DEVLINK_PARAM_ID_NPC_DEFRAG, "npc_defrag", DEVLINK_PARAM_TYPE_STRING, BIT(DEVLINK_PARAM_CMODE_RUNTIME), @@ -1666,13 +1738,13 @@ int rvu_register_dl(struct rvu *rvu) } =20 if (is_cn20k(rvu->pdev)) { - err =3D devlink_params_register(dl, rvu_af_dl_param_defrag, - ARRAY_SIZE(rvu_af_dl_param_defrag)); + err =3D devlink_params_register(dl, rvu_af_dl_cn20k_params, + ARRAY_SIZE(rvu_af_dl_cn20k_params)); if (err) { dev_err(rvu->dev, - "devlink defrag params register failed with error %d", + "devlink cn20k params register failed with error %d", err); - goto err_dl_defrag; + goto err_dl_cn20k_params; } } =20 @@ -1695,10 +1767,10 @@ int rvu_register_dl(struct rvu *rvu) =20 err_dl_exact_match: if (is_cn20k(rvu->pdev)) - devlink_params_unregister(dl, rvu_af_dl_param_defrag, - ARRAY_SIZE(rvu_af_dl_param_defrag)); + devlink_params_unregister(dl, rvu_af_dl_cn20k_params, + ARRAY_SIZE(rvu_af_dl_cn20k_params)); =20 -err_dl_defrag: +err_dl_cn20k_params: devlink_params_unregister(dl, rvu_af_dl_params, ARRAY_SIZE(rvu_af_dl_para= ms)); =20 err_dl_health: @@ -1717,8 +1789,8 @@ void rvu_unregister_dl(struct rvu *rvu) devlink_params_unregister(dl, rvu_af_dl_params, ARRAY_SIZE(rvu_af_dl_para= ms)); =20 if (is_cn20k(rvu->pdev)) - devlink_params_unregister(dl, rvu_af_dl_param_defrag, - ARRAY_SIZE(rvu_af_dl_param_defrag)); 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(unknown [10.28.36.165]) by maili.marvell.com (Postfix) with ESMTP id B1BF33F7051; Thu, 2 Apr 2026 19:56:13 -0700 (PDT) From: Ratheesh Kannoth To: , , CC: , , , , , , , , , , , , , , , , , Ratheesh Kannoth Subject: [PATCH v10 net-next 5/6] octeontx2-af: npc: cn20k: dynamically allocate and free default MCAM entries Date: Fri, 3 Apr 2026 08:25:32 +0530 Message-ID: <20260403025533.6250-6-rkannoth@marvell.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260403025533.6250-1-rkannoth@marvell.com> References: <20260403025533.6250-1-rkannoth@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: awpIigy9U0sUvAfl32n61hgSSCi_0VU0 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDAzMDAyNCBTYWx0ZWRfX7nCjujiu1DJa /vsbso/EzyPgRKTmX4JSoJxjiu4LS1zRZ7o2hhDv+VkornMAqzgioYRk5MIimgnxoTJl+Stlpus Z+pkqCoekqGnvBq3RCMYVgilmasH5NXbkzs+EfyscSEqyNOVaWIPWLjukdHSjgrL25spyiw39J2 +DZHh5n3ENAAKEpDgNsRLwX96ljIQu2NNKFsTro6jnx3WZWokE7aWI2jwjhUWBkicVSRdg7ilNY nhQeNcPcKtvfocUImkYXed8+eVjI/i6OmH62uAb3H9brgrWGenRC4oUWLkpC9y/ImU5gdpoUePN a5//Hj8PsptmlJVh0nOOcciogNinL/FJHhY2Q+bH/jr7u6FdW/DqAnI1E1nQom7m73D0VrIc8Yb soiBAaWT80USSvLpz5Z1bm8zZnJFNfQh0+YV1oqYXlp7HwPSuXoXhEQAd+dK4uLRwenFF/eszqP d6/wY2O6QLpQ5Wxzc8w== X-Proofpoint-ORIG-GUID: awpIigy9U0sUvAfl32n61hgSSCi_0VU0 X-Authority-Analysis: v=2.4 cv=a9E9NESF c=1 sm=1 tr=0 ts=69cf2c56 cx=c_pps a=rEv8fa4AjpPjGxpoe8rlIQ==:117 a=rEv8fa4AjpPjGxpoe8rlIQ==:17 a=A5OVakUREuEA:10 a=VkNPw1HP01LnGYTKEx00:22 a=l0iWHRpgs5sLHlkKQ1IR:22 a=qit2iCtTFQkLgVSMPQTB:22 a=M5GUcnROAAAA:8 a=OQ0u4SyIz9oFantGSkkA:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-03_01,2026-04-02_05,2025-10-01_01 Content-Type: text/plain; charset="utf-8" Improve MCAM utilization by tying default (broadcast, multicast, promisc, ucast) entry lifetime to NIX LF usage. - On NIX LF alloc (e.g. kernel or DPDK), allocate default MCAM entries if missing; on NIX LF free, release them so they return to the pool. - Add NIX_LF_DONT_FREE_DFT_IDXS so the kernel PF driver can free the NIX LF without releasing default entries (e.g. across suspend/resume). - When NIX LF is used by DPDK, default entries are allocated on first use and freed when the LF is released if NIX_LF_DONT_FREE_DFT_IDXS is not set Signed-off-by: Ratheesh Kannoth --- .../ethernet/marvell/octeontx2/af/cn20k/npc.c | 108 ++++++++++----- .../ethernet/marvell/octeontx2/af/cn20k/npc.h | 1 + .../net/ethernet/marvell/octeontx2/af/mbox.h | 1 + .../ethernet/marvell/octeontx2/af/rvu_nix.c | 69 ++++++---- .../ethernet/marvell/octeontx2/af/rvu_npc.c | 125 +++++++++++++----- .../ethernet/marvell/octeontx2/nic/otx2_pf.c | 4 +- 6 files changed, 218 insertions(+), 90 deletions(-) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/cn20k/npc.c b/driver= s/net/ethernet/marvell/octeontx2/af/cn20k/npc.c index 153765b3e504..69439ff76e10 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/cn20k/npc.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/cn20k/npc.c @@ -808,6 +808,11 @@ npc_cn20k_enable_mcam_entry(struct rvu *rvu, int blkad= dr, u64 cfg, hw_prio; u8 kw_type; =20 + if (index < 0 || index >=3D mcam->total_entries) { + WARN(1, "Wrong mcam index %d\n", index); + return; + } + enable ? set_bit(index, npc_priv.en_map) : clear_bit(index, npc_priv.en_map); =20 @@ -1053,6 +1058,11 @@ void npc_cn20k_config_mcam_entry(struct rvu *rvu, in= t blkaddr, int index, int kw =3D 0; u8 kw_type; =20 + if (index < 0 || index >=3D mcam->total_entries) { + WARN(1, "Wrong mcam index %d\n", index); + return; + } + /* Disable before mcam entry update */ npc_cn20k_enable_mcam_entry(rvu, blkaddr, index, false); =20 @@ -1132,6 +1142,11 @@ void npc_cn20k_copy_mcam_entry(struct rvu *rvu, int = blkaddr, u16 src, u16 dest) int bank, i, sb, db; int dbank, sbank; =20 + if (src >=3D mcam->total_entries || dest >=3D mcam->total_entries) { + WARN(1, "Wrong mcam index src=3D%u dest=3D%u\n", src, dest); + return; + } + dbank =3D npc_get_bank(mcam, dest); sbank =3D npc_get_bank(mcam, src); npc_mcam_idx_2_key_type(rvu, src, &src_kwtype); @@ -1190,11 +1205,24 @@ void npc_cn20k_read_mcam_entry(struct rvu *rvu, int= blkaddr, u16 index, int kw =3D 0, bank; u8 kw_type; =20 + if (index >=3D mcam->total_entries) { + WARN(1, "Wrong mcam index %u\n", index); + return; + } + npc_mcam_idx_2_key_type(rvu, index, &kw_type); =20 bank =3D npc_get_bank(mcam, index); index &=3D (mcam->banksize - 1); =20 + cfg =3D rvu_read64(rvu, blkaddr, + NPC_AF_CN20K_MCAMEX_BANKX_ACTIONX_EXT(index, bank, 0)); + entry->action =3D cfg; + + cfg =3D rvu_read64(rvu, blkaddr, + NPC_AF_CN20K_MCAMEX_BANKX_ACTIONX_EXT(index, bank, 1)); + entry->vtag_action =3D cfg; + cfg =3D rvu_read64(rvu, blkaddr, NPC_AF_CN20K_MCAMEX_BANKX_CAMX_INTF_EXT(index, bank, 1)) & 3; @@ -1244,7 +1272,7 @@ void npc_cn20k_read_mcam_entry(struct rvu *rvu, int b= lkaddr, u16 index, bank, 0)); npc_cn20k_fill_entryword(entry, kw + 3, cam0, cam1); - goto read_action; + return; } =20 for (bank =3D 0; bank < mcam->banks_per_entry; bank++, kw =3D kw + 4) { @@ -1289,17 +1317,6 @@ void npc_cn20k_read_mcam_entry(struct rvu *rvu, int = blkaddr, u16 index, npc_cn20k_fill_entryword(entry, kw + 3, cam0, cam1); } =20 -read_action: - /* 'action' is set to same value for both bank '0' and '1'. - * Hence, reading bank '0' should be enough. - */ - cfg =3D rvu_read64(rvu, blkaddr, - NPC_AF_CN20K_MCAMEX_BANKX_ACTIONX_EXT(index, 0, 0)); - entry->action =3D cfg; - - cfg =3D rvu_read64(rvu, blkaddr, - NPC_AF_CN20K_MCAMEX_BANKX_ACTIONX_EXT(index, 0, 1)); - entry->vtag_action =3D cfg; } =20 int rvu_mbox_handler_npc_cn20k_mcam_write_entry(struct rvu *rvu, @@ -1671,8 +1688,8 @@ int npc_mcam_idx_2_key_type(struct rvu *rvu, u16 mcam= _idx, u8 *key_type) =20 /* mcam_idx should be less than (2 * bank depth) */ if (mcam_idx >=3D npc_priv.bank_depth * 2) { - dev_err(rvu->dev, "%s: bad params\n", - __func__); + dev_err(rvu->dev, "%s: bad params mcam_idx=3D%u\n", + __func__, mcam_idx); return -EINVAL; } =20 @@ -4024,6 +4041,13 @@ int npc_cn20k_dft_rules_idx_get(struct rvu *rvu, u16= pcifunc, u16 *bcast, void *val; int i, j; =20 + for (int i =3D 0; i < ARRAY_SIZE(ptr); i++) { + if (!ptr[i]) + continue; + + *ptr[i] =3D USHRT_MAX; + } + if (!npc_priv.init_done) return 0; =20 @@ -4039,7 +4063,6 @@ int npc_cn20k_dft_rules_idx_get(struct rvu *rvu, u16 = pcifunc, u16 *bcast, npc_dft_rule_name[NPC_DFT_RULE_PROMISC_ID], pcifunc); =20 - *ptr[0] =3D USHRT_MAX; return -ESRCH; } =20 @@ -4059,7 +4082,6 @@ int npc_cn20k_dft_rules_idx_get(struct rvu *rvu, u16 = pcifunc, u16 *bcast, npc_dft_rule_name[NPC_DFT_RULE_UCAST_ID], pcifunc); =20 - *ptr[3] =3D USHRT_MAX; return -ESRCH; } =20 @@ -4079,7 +4101,6 @@ int npc_cn20k_dft_rules_idx_get(struct rvu *rvu, u16 = pcifunc, u16 *bcast, __func__, npc_dft_rule_name[i], pcifunc); =20 - *ptr[j] =3D USHRT_MAX; continue; } =20 @@ -4174,7 +4195,7 @@ int rvu_mbox_handler_npc_get_dft_rl_idxs(struct rvu *= rvu, struct msg_req *req, return 0; } =20 -static bool npc_is_cgx_or_lbk(struct rvu *rvu, u16 pcifunc) +bool npc_is_cgx_or_lbk(struct rvu *rvu, u16 pcifunc) { return is_pf_cgxmapped(rvu, rvu_get_pf(rvu->pdev, pcifunc)) || is_lbk_vf(rvu, pcifunc); @@ -4182,9 +4203,10 @@ static bool npc_is_cgx_or_lbk(struct rvu *rvu, u16 p= cifunc) =20 void npc_cn20k_dft_rules_free(struct rvu *rvu, u16 pcifunc) { - struct npc_mcam_free_entry_req free_req =3D { 0 }; + struct npc_mcam *mcam =3D &rvu->hw->mcam; + struct rvu_npc_mcam_rule *rule, *tmp; unsigned long index; - struct msg_rsp rsp; + int blkaddr; u16 ptr[4]; int rc, i; void *map; @@ -4209,7 +4231,7 @@ void npc_cn20k_dft_rules_free(struct rvu *rvu, u16 pc= ifunc) index =3D NPC_DFT_RULE_ID_MK(pcifunc, NPC_DFT_RULE_PROMISC_ID); map =3D xa_erase(&npc_priv.xa_pf2dfl_rmap, index); if (!map) - dev_dbg(rvu->dev, + dev_err(rvu->dev, "%s: Err from delete %s mcam idx from xarray (pcifunc=3D%#x\n", __func__, npc_dft_rule_name[NPC_DFT_RULE_PROMISC_ID], @@ -4223,7 +4245,7 @@ void npc_cn20k_dft_rules_free(struct rvu *rvu, u16 pc= ifunc) index =3D NPC_DFT_RULE_ID_MK(pcifunc, NPC_DFT_RULE_UCAST_ID); map =3D xa_erase(&npc_priv.xa_pf2dfl_rmap, index); if (!map) - dev_dbg(rvu->dev, + dev_err(rvu->dev, "%s: Err from delete %s mcam idx from xarray (pcifunc=3D%#x\n", __func__, npc_dft_rule_name[NPC_DFT_RULE_UCAST_ID], @@ -4237,21 +4259,47 @@ void npc_cn20k_dft_rules_free(struct rvu *rvu, u16 = pcifunc) index =3D NPC_DFT_RULE_ID_MK(pcifunc, i); map =3D xa_erase(&npc_priv.xa_pf2dfl_rmap, index); if (!map) - dev_dbg(rvu->dev, + dev_err(rvu->dev, "%s: Err from delete %s mcam idx from xarray (pcifunc=3D%#x\n", __func__, npc_dft_rule_name[i], pcifunc); } =20 free_rules: + blkaddr =3D rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); + if (blkaddr < 0) + return; =20 - free_req.hdr.pcifunc =3D pcifunc; - free_req.all =3D 1; - rc =3D rvu_mbox_handler_npc_mcam_free_entry(rvu, &free_req, &rsp); - if (rc) - dev_err(rvu->dev, - "%s: Error deleting default entries (pcifunc=3D%#x\n", - __func__, pcifunc); + for (int i =3D 0; i < 4; i++) { + if (ptr[i] =3D=3D USHRT_MAX) + continue; + + mutex_lock(&mcam->lock); + npc_mcam_clear_bit(mcam, ptr[i]); + mcam->entry2pfvf_map[ptr[i]] =3D NPC_MCAM_INVALID_MAP; + npc_cn20k_enable_mcam_entry(rvu, blkaddr, ptr[i], false); + mcam->entry2target_pffunc[ptr[i]] =3D 0x0; + mutex_unlock(&mcam->lock); + + rc =3D npc_cn20k_idx_free(rvu, &ptr[i], 1); + if (rc) + dev_err(rvu->dev, + "%s:%d Error deleting default entries (pcifunc=3D%#x) mcam_idx=3D%u\n", + __func__, __LINE__, pcifunc, ptr[i]); + } + + mutex_lock(&mcam->lock); + list_for_each_entry_safe(rule, tmp, &mcam->mcam_rules, list) { + for (int i =3D 0; i < 4; i++) { + if (ptr[i] !=3D rule->entry) + continue; + + list_del(&rule->list); + kfree(rule); + break; + } + } + mutex_unlock(&mcam->lock); } =20 int npc_cn20k_dft_rules_alloc(struct rvu *rvu, u16 pcifunc) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/cn20k/npc.h b/driver= s/net/ethernet/marvell/octeontx2/af/cn20k/npc.h index 6f9f796940f3..1b4b4a6fa378 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/cn20k/npc.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/cn20k/npc.h @@ -345,5 +345,6 @@ int npc_mcam_idx_2_subbank_idx(struct rvu *rvu, u16 mca= m_idx, int *sb_off); const u32 *npc_cn20k_search_order_get(bool *restricted_order, u32 *sz); int npc_cn20k_search_order_set(struct rvu *rvu, u64 arr[32], int cnt); +bool npc_is_cgx_or_lbk(struct rvu *rvu, u16 pcifunc); =20 #endif /* NPC_CN20K_H */ diff --git a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h b/drivers/net= /ethernet/marvell/octeontx2/af/mbox.h index dc42c81c0942..e07fbf842b94 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h @@ -1009,6 +1009,7 @@ struct nix_lf_free_req { struct mbox_msghdr hdr; #define NIX_LF_DISABLE_FLOWS BIT_ULL(0) #define NIX_LF_DONT_FREE_TX_VTAG BIT_ULL(1) +#define NIX_LF_DONT_FREE_DFT_IDXS BIT_ULL(2) u64 flags; }; =20 diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c b/drivers/= net/ethernet/marvell/octeontx2/af/rvu_nix.c index ef5b081162eb..584e98e25f11 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c @@ -16,6 +16,7 @@ #include "cgx.h" #include "lmac_common.h" #include "rvu_npc_hash.h" +#include "cn20k/npc.h" =20 static void nix_free_tx_vtag_entries(struct rvu *rvu, u16 pcifunc); static int rvu_nix_get_bpid(struct rvu *rvu, struct nix_bp_cfg_req *req, @@ -1499,7 +1500,7 @@ int rvu_mbox_handler_nix_lf_alloc(struct rvu *rvu, struct nix_lf_alloc_req *req, struct nix_lf_alloc_rsp *rsp) { - int nixlf, qints, hwctx_size, intf, err, rc =3D 0; + int nixlf, qints, hwctx_size, intf, rc =3D 0; struct rvu_hwinfo *hw =3D rvu->hw; u16 pcifunc =3D req->hdr.pcifunc; struct rvu_block *block; @@ -1555,8 +1556,8 @@ int rvu_mbox_handler_nix_lf_alloc(struct rvu *rvu, return NIX_AF_ERR_RSS_GRPS_INVALID; =20 /* Reset this NIX LF */ - err =3D rvu_lf_reset(rvu, block, nixlf); - if (err) { + rc =3D rvu_lf_reset(rvu, block, nixlf); + if (rc) { dev_err(rvu->dev, "Failed to reset NIX%d LF%d\n", block->addr - BLKADDR_NIX0, nixlf); return NIX_AF_ERR_LF_RESET; @@ -1566,13 +1567,15 @@ int rvu_mbox_handler_nix_lf_alloc(struct rvu *rvu, =20 /* Alloc NIX RQ HW context memory and config the base */ hwctx_size =3D 1UL << ((ctx_cfg >> 4) & 0xF); - err =3D qmem_alloc(rvu->dev, &pfvf->rq_ctx, req->rq_cnt, hwctx_size); - if (err) + rc =3D qmem_alloc(rvu->dev, &pfvf->rq_ctx, req->rq_cnt, hwctx_size); + if (rc) goto free_mem; =20 pfvf->rq_bmap =3D kcalloc(req->rq_cnt, sizeof(long), GFP_KERNEL); - if (!pfvf->rq_bmap) + if (!pfvf->rq_bmap) { + rc =3D -ENOMEM; goto free_mem; + } =20 rvu_write64(rvu, blkaddr, NIX_AF_LFX_RQS_BASE(nixlf), (u64)pfvf->rq_ctx->iova); @@ -1583,13 +1586,15 @@ int rvu_mbox_handler_nix_lf_alloc(struct rvu *rvu, =20 /* Alloc NIX SQ HW context memory and config the base */ hwctx_size =3D 1UL << (ctx_cfg & 0xF); - err =3D qmem_alloc(rvu->dev, &pfvf->sq_ctx, req->sq_cnt, hwctx_size); - if (err) + rc =3D qmem_alloc(rvu->dev, &pfvf->sq_ctx, req->sq_cnt, hwctx_size); + if (rc) goto free_mem; =20 pfvf->sq_bmap =3D kcalloc(req->sq_cnt, sizeof(long), GFP_KERNEL); - if (!pfvf->sq_bmap) + if (!pfvf->sq_bmap) { + rc =3D -ENOMEM; goto free_mem; + } =20 rvu_write64(rvu, blkaddr, NIX_AF_LFX_SQS_BASE(nixlf), (u64)pfvf->sq_ctx->iova); @@ -1599,13 +1604,15 @@ int rvu_mbox_handler_nix_lf_alloc(struct rvu *rvu, =20 /* Alloc NIX CQ HW context memory and config the base */ hwctx_size =3D 1UL << ((ctx_cfg >> 8) & 0xF); - err =3D qmem_alloc(rvu->dev, &pfvf->cq_ctx, req->cq_cnt, hwctx_size); - if (err) + rc =3D qmem_alloc(rvu->dev, &pfvf->cq_ctx, req->cq_cnt, hwctx_size); + if (rc) goto free_mem; =20 pfvf->cq_bmap =3D kcalloc(req->cq_cnt, sizeof(long), GFP_KERNEL); - if (!pfvf->cq_bmap) + if (!pfvf->cq_bmap) { + rc =3D -ENOMEM; goto free_mem; + } =20 rvu_write64(rvu, blkaddr, NIX_AF_LFX_CQS_BASE(nixlf), (u64)pfvf->cq_ctx->iova); @@ -1615,18 +1622,18 @@ int rvu_mbox_handler_nix_lf_alloc(struct rvu *rvu, =20 /* Initialize receive side scaling (RSS) */ hwctx_size =3D 1UL << ((ctx_cfg >> 12) & 0xF); - err =3D nixlf_rss_ctx_init(rvu, blkaddr, pfvf, nixlf, req->rss_sz, - req->rss_grps, hwctx_size, req->way_mask, - !!(req->flags & NIX_LF_RSS_TAG_LSB_AS_ADDER)); - if (err) + rc =3D nixlf_rss_ctx_init(rvu, blkaddr, pfvf, nixlf, req->rss_sz, + req->rss_grps, hwctx_size, req->way_mask, + !!(req->flags & NIX_LF_RSS_TAG_LSB_AS_ADDER)); + if (rc) goto free_mem; =20 /* Alloc memory for CQINT's HW contexts */ cfg =3D rvu_read64(rvu, blkaddr, NIX_AF_CONST2); qints =3D (cfg >> 24) & 0xFFF; hwctx_size =3D 1UL << ((ctx_cfg >> 24) & 0xF); - err =3D qmem_alloc(rvu->dev, &pfvf->cq_ints_ctx, qints, hwctx_size); - if (err) + rc =3D qmem_alloc(rvu->dev, &pfvf->cq_ints_ctx, qints, hwctx_size); + if (rc) goto free_mem; =20 rvu_write64(rvu, blkaddr, NIX_AF_LFX_CINTS_BASE(nixlf), @@ -1639,8 +1646,8 @@ int rvu_mbox_handler_nix_lf_alloc(struct rvu *rvu, cfg =3D rvu_read64(rvu, blkaddr, NIX_AF_CONST2); qints =3D (cfg >> 12) & 0xFFF; hwctx_size =3D 1UL << ((ctx_cfg >> 20) & 0xF); - err =3D qmem_alloc(rvu->dev, &pfvf->nix_qints_ctx, qints, hwctx_size); - if (err) + rc =3D qmem_alloc(rvu->dev, &pfvf->nix_qints_ctx, qints, hwctx_size); + if (rc) goto free_mem; =20 rvu_write64(rvu, blkaddr, NIX_AF_LFX_QINTS_BASE(nixlf), @@ -1684,10 +1691,16 @@ int rvu_mbox_handler_nix_lf_alloc(struct rvu *rvu, if (is_sdp_pfvf(rvu, pcifunc)) intf =3D NIX_INTF_TYPE_SDP; =20 - err =3D nix_interface_init(rvu, pcifunc, intf, nixlf, rsp, - !!(req->flags & NIX_LF_LBK_BLK_SEL)); - if (err) - goto free_mem; + if (is_cn20k(rvu->pdev)) { + rc =3D npc_cn20k_dft_rules_alloc(rvu, pcifunc); + if (rc) + goto free_mem; + } + + rc =3D nix_interface_init(rvu, pcifunc, intf, nixlf, rsp, + !!(req->flags & NIX_LF_LBK_BLK_SEL)); + if (rc) + goto free_dft; =20 /* Disable NPC entries as NIXLF's contexts are not initialized yet */ rvu_npc_disable_default_entries(rvu, pcifunc, nixlf); @@ -1699,9 +1712,12 @@ int rvu_mbox_handler_nix_lf_alloc(struct rvu *rvu, =20 goto exit; =20 +free_dft: + if (is_cn20k(rvu->pdev)) + npc_cn20k_dft_rules_free(rvu, pcifunc); + free_mem: nix_ctx_free(rvu, pfvf); - rc =3D -ENOMEM; =20 exit: /* Set macaddr of this PF/VF */ @@ -1775,6 +1791,9 @@ int rvu_mbox_handler_nix_lf_free(struct rvu *rvu, str= uct nix_lf_free_req *req, =20 nix_ctx_free(rvu, pfvf); =20 + if (is_cn20k(rvu->pdev) && !(req->flags & NIX_LF_DONT_FREE_DFT_IDXS)) + npc_cn20k_dft_rules_free(rvu, pcifunc); + return 0; } =20 diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c b/drivers/= net/ethernet/marvell/octeontx2/af/rvu_npc.c index c2ca5ed1d028..8d260bcfbf38 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c @@ -165,12 +165,20 @@ int npc_get_nixlf_mcam_index(struct npc_mcam *mcam, =20 switch (type) { case NIXLF_BCAST_ENTRY: + if (bcast =3D=3D USHRT_MAX) + return -EINVAL; return bcast; case NIXLF_ALLMULTI_ENTRY: + if (mcast =3D=3D USHRT_MAX) + return -EINVAL; return mcast; case NIXLF_PROMISC_ENTRY: + if (promisc =3D=3D USHRT_MAX) + return -EINVAL; return promisc; case NIXLF_UCAST_ENTRY: + if (ucast =3D=3D USHRT_MAX) + return -EINVAL; return ucast; default: return -EINVAL; @@ -237,12 +245,8 @@ void npc_enable_mcam_entry(struct rvu *rvu, struct npc= _mcam *mcam, int bank =3D npc_get_bank(mcam, index); int actbank =3D bank; =20 - if (is_cn20k(rvu->pdev)) { - if (index < 0 || index >=3D mcam->banksize * mcam->banks) - return; - + if (is_cn20k(rvu->pdev)) return npc_cn20k_enable_mcam_entry(rvu, blkaddr, index, enable); - } =20 index &=3D (mcam->banksize - 1); for (; bank < (actbank + mcam->banks_per_entry); bank++) { @@ -1113,7 +1117,7 @@ void rvu_npc_update_flowkey_alg_idx(struct rvu *rvu, = u16 pcifunc, int nixlf, index =3D mcam_index; } =20 - if (index >=3D mcam->total_entries) + if (index < 0 || index >=3D mcam->total_entries) return; =20 bank =3D npc_get_bank(mcam, index); @@ -1158,16 +1162,18 @@ void rvu_npc_update_flowkey_alg_idx(struct rvu *rvu= , u16 pcifunc, int nixlf, /* If PF's promiscuous entry is enabled, * Set RSS action for that entry as well */ - npc_update_rx_action_with_alg_idx(rvu, action, pfvf, index, - blkaddr, alg_idx); + if (index >=3D 0) + npc_update_rx_action_with_alg_idx(rvu, action, pfvf, + index, blkaddr, alg_idx); =20 index =3D npc_get_nixlf_mcam_index(mcam, pcifunc, nixlf, NIXLF_ALLMULTI_ENTRY); /* If PF's allmulti entry is enabled, * Set RSS action for that entry as well */ - npc_update_rx_action_with_alg_idx(rvu, action, pfvf, index, - blkaddr, alg_idx); + if (index >=3D 0) + npc_update_rx_action_with_alg_idx(rvu, action, pfvf, + index, blkaddr, alg_idx); } } =20 @@ -1212,8 +1218,13 @@ static void npc_enadis_default_entries(struct rvu *r= vu, u16 pcifunc, { struct rvu_pfvf *pfvf =3D rvu_get_pfvf(rvu, pcifunc); struct npc_mcam *mcam =3D &rvu->hw->mcam; + int type =3D NIXLF_UCAST_ENTRY; int index, blkaddr; =20 + /* only CGX or LBK interfaces have default entries */ + if (is_cn20k(rvu->pdev) && !npc_is_cgx_or_lbk(rvu, pcifunc)) + return; + blkaddr =3D rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); if (blkaddr < 0) return; @@ -1221,8 +1232,11 @@ static void npc_enadis_default_entries(struct rvu *r= vu, u16 pcifunc, /* Ucast MCAM match entry of this PF/VF */ if (npc_is_feature_supported(rvu, BIT_ULL(NPC_DMAC), pfvf->nix_rx_intf)) { + if (is_cn20k(rvu->pdev) && is_lbk_vf(rvu, pcifunc)) + type =3D NIXLF_PROMISC_ENTRY; + index =3D npc_get_nixlf_mcam_index(mcam, pcifunc, - nixlf, NIXLF_UCAST_ENTRY); + nixlf, type); npc_enable_mcam_entry(rvu, mcam, blkaddr, index, enable); } =20 @@ -1232,9 +1246,13 @@ static void npc_enadis_default_entries(struct rvu *r= vu, u16 pcifunc, if ((pcifunc & RVU_PFVF_FUNC_MASK) && !rvu->hw->cap.nix_rx_multicast) return; =20 + type =3D NIXLF_BCAST_ENTRY; + if (is_cn20k(rvu->pdev) && is_lbk_vf(rvu, pcifunc)) + type =3D NIXLF_PROMISC_ENTRY; + /* add/delete pf_func to broadcast MCE list */ npc_enadis_default_mce_entry(rvu, pcifunc, nixlf, - NIXLF_BCAST_ENTRY, enable); + type, enable); } =20 void rvu_npc_disable_default_entries(struct rvu *rvu, u16 pcifunc, int nix= lf) @@ -1244,6 +1262,9 @@ void rvu_npc_disable_default_entries(struct rvu *rvu,= u16 pcifunc, int nixlf) =20 npc_enadis_default_entries(rvu, pcifunc, nixlf, false); =20 + if (is_cn20k(rvu->pdev) && is_vf(pcifunc)) + return; + /* Delete multicast and promisc MCAM entries */ npc_enadis_default_mce_entry(rvu, pcifunc, nixlf, NIXLF_ALLMULTI_ENTRY, false); @@ -1301,6 +1322,10 @@ void rvu_npc_disable_mcam_entries(struct rvu *rvu, u= 16 pcifunc, int nixlf) if (blkaddr < 0) return; =20 + /* only CGX or LBK interfaces have default entries */ + if (is_cn20k(rvu->pdev) && !npc_is_cgx_or_lbk(rvu, pcifunc)) + return; + mutex_lock(&mcam->lock); =20 /* Disable MCAM entries directing traffic to this 'pcifunc' */ @@ -2504,33 +2529,58 @@ void npc_mcam_clear_bit(struct npc_mcam *mcam, u16 = index) static void npc_mcam_free_all_entries(struct rvu *rvu, struct npc_mcam *mc= am, int blkaddr, u16 pcifunc) { + u16 dft_idxs[NPC_DFT_RULE_MAX_ID] =3D {[0 ... NPC_DFT_RULE_MAX_ID - 1] = =3D USHRT_MAX}; u16 index, cntr; + bool dft_rl; int rc; =20 + npc_cn20k_dft_rules_idx_get(rvu, pcifunc, + &dft_idxs[NPC_DFT_RULE_BCAST_ID], + &dft_idxs[NPC_DFT_RULE_MCAST_ID], + &dft_idxs[NPC_DFT_RULE_PROMISC_ID], + &dft_idxs[NPC_DFT_RULE_UCAST_ID]); + /* Scan all MCAM entries and free the ones mapped to 'pcifunc' */ for (index =3D 0; index < mcam->bmap_entries; index++) { - if (mcam->entry2pfvf_map[index] =3D=3D pcifunc) { - mcam->entry2pfvf_map[index] =3D NPC_MCAM_INVALID_MAP; - /* Free the entry in bitmap */ - npc_mcam_clear_bit(mcam, index); - /* Disable the entry */ - npc_enable_mcam_entry(rvu, mcam, blkaddr, index, false); - - /* Update entry2counter mapping */ - cntr =3D mcam->entry2cntr_map[index]; - if (cntr !=3D NPC_MCAM_INVALID_MAP) - npc_unmap_mcam_entry_and_cntr(rvu, mcam, - blkaddr, index, - cntr); - mcam->entry2target_pffunc[index] =3D 0x0; - if (is_cn20k(rvu->pdev)) { - rc =3D npc_cn20k_idx_free(rvu, &index, 1); - if (rc) - dev_err(rvu->dev, - "Failed to free mcam idx=3D%u pcifunc=3D%#x\n", - index, pcifunc); + if (mcam->entry2pfvf_map[index] !=3D pcifunc) + continue; + + mcam->entry2pfvf_map[index] =3D NPC_MCAM_INVALID_MAP; + + dft_rl =3D false; + if (is_cn20k(rvu->pdev)) { + if (dft_idxs[NPC_DFT_RULE_BCAST_ID] =3D=3D index || + dft_idxs[NPC_DFT_RULE_MCAST_ID] =3D=3D index || + dft_idxs[NPC_DFT_RULE_PROMISC_ID] =3D=3D index || + dft_idxs[NPC_DFT_RULE_UCAST_ID] =3D=3D index) { + dft_rl =3D true; } } + + /* Free the entry in bitmap.*/ + if (!dft_rl) + npc_mcam_clear_bit(mcam, index); + + /* Disable the entry */ + npc_enable_mcam_entry(rvu, mcam, blkaddr, index, false); + + /* Update entry2counter mapping */ + cntr =3D mcam->entry2cntr_map[index]; + if (cntr !=3D NPC_MCAM_INVALID_MAP) + npc_unmap_mcam_entry_and_cntr(rvu, mcam, + blkaddr, index, + cntr); + mcam->entry2target_pffunc[index] =3D 0x0; + if (is_cn20k(rvu->pdev)) { + if (dft_rl) + continue; + + rc =3D npc_cn20k_idx_free(rvu, &index, 1); + if (rc) + dev_err(rvu->dev, + "Failed to free mcam idx=3D%u pcifunc=3D%#x\n", + index, pcifunc); + } } } =20 @@ -3917,13 +3967,22 @@ void rvu_npc_clear_ucast_entry(struct rvu *rvu, int= pcifunc, int nixlf) struct npc_mcam *mcam =3D &rvu->hw->mcam; struct rvu_npc_mcam_rule *rule; int ucast_idx, blkaddr; + u8 type; =20 blkaddr =3D rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); if (blkaddr < 0) return; =20 + type =3D NIXLF_UCAST_ENTRY; + if (is_cn20k(rvu->pdev) && is_lbk_vf(rvu, pcifunc)) + type =3D NIXLF_PROMISC_ENTRY; + ucast_idx =3D npc_get_nixlf_mcam_index(mcam, pcifunc, - nixlf, NIXLF_UCAST_ENTRY); + nixlf, type); + + /* In cn20k, default rules are freed before detach rsrc */ + if (ucast_idx < 0) + return; =20 npc_enable_mcam_entry(rvu, mcam, blkaddr, ucast_idx, false); =20 diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c b/drivers= /net/ethernet/marvell/octeontx2/nic/otx2_pf.c index ee623476e5ff..366850742862 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c @@ -1729,7 +1729,7 @@ int otx2_init_hw_resources(struct otx2_nic *pf) mutex_lock(&mbox->lock); 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(unknown [10.28.36.165]) by maili.marvell.com (Postfix) with ESMTP id B65B03F7073; Thu, 2 Apr 2026 19:56:20 -0700 (PDT) From: Ratheesh Kannoth To: , , CC: , , , , , , , , , , , , , , , , , Ratheesh Kannoth Subject: [PATCH v10 net-next 6/6] octeontx2-af: npc: Support for custom KPU profile from filesystem Date: Fri, 3 Apr 2026 08:25:33 +0530 Message-ID: <20260403025533.6250-7-rkannoth@marvell.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260403025533.6250-1-rkannoth@marvell.com> References: <20260403025533.6250-1-rkannoth@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: sGfrVsC-G8FOcjpAYvRMTwPNcrxnS9gc X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDAzMDAyNCBTYWx0ZWRfX1JBcf65O/V7c tm1LP/Q7L63Ve2LU1FQe3nlX5ARkNvTXZIvx1754Q5deIyTY33xO9I1l+15lNRyYf99+gGR/TPP Ld0dy60bi3jRfwTrvM2BeeKjbZeNJwjQqeds0kX4/sMVx1TUOasZLXv1E/XILxcNYB1uCtfS0TL 4Gnrx9jHF5RDdTI8ePzF02OvjmPKeVwpV+AI6FBdqYQptaZZLUEmmwCaBBeGCsZTwyEFSj96zI+ Jm8rzHzO3vB0F+Vl3ioLb+FNLgq/wbbVzC1+SPF2ggHq4n2sQ2lyy5tGSADGsex++1OXrAEYCET NhNq9cF1GTEOyHw6F7kjTYfBiV4vaLS2ZDqe/d3Y1NvxQJXJcq7F55A8Wop3f7DHZ3RonPpgBub LJHvvbxCUbO1ien3lkJ9emC26U9fgvESicqg0EMcz1I9LNy9xU9fjz3ED7bqdZW7rU4FPBb7xW0 gjK3C4usI98WI4fbp6g== X-Proofpoint-GUID: sGfrVsC-G8FOcjpAYvRMTwPNcrxnS9gc X-Authority-Analysis: v=2.4 cv=fLs0HJae c=1 sm=1 tr=0 ts=69cf2c5c cx=c_pps a=rEv8fa4AjpPjGxpoe8rlIQ==:117 a=rEv8fa4AjpPjGxpoe8rlIQ==:17 a=A5OVakUREuEA:10 a=VkNPw1HP01LnGYTKEx00:22 a=l0iWHRpgs5sLHlkKQ1IR:22 a=EAYMVhzMl8SCOHhVQcBL:22 a=M5GUcnROAAAA:8 a=fPRu-RNDXv4BUTAVjlcA:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-03_01,2026-04-02_05,2025-10-01_01 Content-Type: text/plain; charset="utf-8" Flashing updated firmware on deployed devices is cumbersome. Provide a mechanism to load a custom KPU (Key Parse Unit) profile directly from the filesystem at module load time. When the rvu_af module is loaded with the kpu_profile parameter, the specified profile is read from /lib/firmware/kpu and programmed into the KPU registers. Add npc_kpu_profile_cam2 for the extended cam format used by filesystem-loaded profiles and support ptype/ptype_mask in npc_config_kpucam when profile->from_fs is set. Usage: 1. Copy the KPU profile file to /lib/firmware/kpu. 2. Build OCTEONTX2_AF as a module. 3. Load: insmod rvu_af.ko kpu_profile=3D Signed-off-by: Ratheesh Kannoth --- .../ethernet/marvell/octeontx2/af/cn20k/npc.c | 57 ++- .../net/ethernet/marvell/octeontx2/af/npc.h | 17 + .../net/ethernet/marvell/octeontx2/af/rvu.h | 12 +- .../ethernet/marvell/octeontx2/af/rvu_npc.c | 446 ++++++++++++++---- .../ethernet/marvell/octeontx2/af/rvu_npc.h | 17 + .../ethernet/marvell/octeontx2/af/rvu_reg.h | 1 + 6 files changed, 438 insertions(+), 112 deletions(-) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/cn20k/npc.c b/driver= s/net/ethernet/marvell/octeontx2/af/cn20k/npc.c index 69439ff76e10..9f71b7ea06ce 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/cn20k/npc.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/cn20k/npc.c @@ -521,13 +521,17 @@ npc_program_single_kpm_profile(struct rvu *rvu, int b= lkaddr, int kpm, int start_entry, const struct npc_kpu_profile *profile) { + int num_cam_entries, num_action_entries; int entry, num_entries, max_entries; u64 idx; =20 - if (profile->cam_entries !=3D profile->action_entries) { + num_cam_entries =3D npc_get_num_kpu_cam_entries(rvu, profile); + num_action_entries =3D npc_get_num_kpu_action_entries(rvu, profile); + + if (num_cam_entries !=3D num_action_entries) { dev_err(rvu->dev, "kpm%d: CAM and action entries [%d !=3D %d] not equal\n", - kpm, profile->cam_entries, profile->action_entries); + kpm, num_cam_entries, num_action_entries); =20 WARN(1, "Fatal error\n"); return; @@ -536,16 +540,18 @@ npc_program_single_kpm_profile(struct rvu *rvu, int b= lkaddr, max_entries =3D rvu->hw->npc_kpu_entries / 2; entry =3D start_entry; /* Program CAM match entries for previous kpm extracted data */ - num_entries =3D min_t(int, profile->cam_entries, max_entries); + num_entries =3D min_t(int, num_cam_entries, max_entries); for (idx =3D 0; entry < num_entries + start_entry; entry++, idx++) - npc_config_kpmcam(rvu, blkaddr, &profile->cam[idx], + npc_config_kpmcam(rvu, blkaddr, + npc_get_kpu_cam_nth_entry(rvu, profile, idx), kpm, entry); =20 entry =3D start_entry; /* Program this kpm's actions */ - num_entries =3D min_t(int, profile->action_entries, max_entries); + num_entries =3D min_t(int, num_action_entries, max_entries); for (idx =3D 0; entry < num_entries + start_entry; entry++, idx++) - npc_config_kpmaction(rvu, blkaddr, &profile->action[idx], + npc_config_kpmaction(rvu, blkaddr, + npc_get_kpu_action_nth_entry(rvu, profile, idx), kpm, entry, false); } =20 @@ -611,20 +617,23 @@ npc_enable_kpm_entry(struct rvu *rvu, int blkaddr, in= t kpm, int num_entries) static void npc_program_kpm_profile(struct rvu *rvu, int blkaddr, int num_= kpms) { const struct npc_kpu_profile *profile1, *profile2; + int pfl1_num_cam_entries, pfl2_num_cam_entries; int idx, total_cam_entries; =20 for (idx =3D 0; idx < num_kpms; idx++) { profile1 =3D &rvu->kpu.kpu[idx]; + pfl1_num_cam_entries =3D npc_get_num_kpu_cam_entries(rvu, profile1); npc_program_single_kpm_profile(rvu, blkaddr, idx, 0, profile1); profile2 =3D &rvu->kpu.kpu[idx + KPU_OFFSET]; + pfl2_num_cam_entries =3D npc_get_num_kpu_cam_entries(rvu, profile2); + npc_program_single_kpm_profile(rvu, blkaddr, idx, - profile1->cam_entries, + pfl1_num_cam_entries, profile2); - total_cam_entries =3D profile1->cam_entries + - profile2->cam_entries; + total_cam_entries =3D pfl1_num_cam_entries + pfl2_num_cam_entries; npc_enable_kpm_entry(rvu, blkaddr, idx, total_cam_entries); rvu_write64(rvu, blkaddr, NPC_AF_KPMX_PASS2_OFFSET(idx), - profile1->cam_entries); + pfl1_num_cam_entries); /* Enable the KPUs associated with this KPM */ rvu_write64(rvu, blkaddr, NPC_AF_KPUX_CFG(idx), 0x01); rvu_write64(rvu, blkaddr, NPC_AF_KPUX_CFG(idx + KPU_OFFSET), @@ -634,6 +643,7 @@ static void npc_program_kpm_profile(struct rvu *rvu, in= t blkaddr, int num_kpms) =20 void npc_cn20k_parser_profile_init(struct rvu *rvu, int blkaddr) { + struct npc_kpu_profile_action *act; struct rvu_hwinfo *hw =3D rvu->hw; int num_pkinds, idx; =20 @@ -665,9 +675,15 @@ void npc_cn20k_parser_profile_init(struct rvu *rvu, in= t blkaddr) num_pkinds =3D rvu->kpu.pkinds; num_pkinds =3D min_t(int, hw->npc_pkinds, num_pkinds); =20 - for (idx =3D 0; idx < num_pkinds; idx++) - npc_config_kpmaction(rvu, blkaddr, &rvu->kpu.ikpu[idx], + /* Cn20k does not support Custom profile from filesystem */ + for (idx =3D 0; idx < num_pkinds; idx++) { + act =3D npc_get_ikpu_nth_entry(rvu, idx); + if (!act) + continue; + + npc_config_kpmaction(rvu, blkaddr, act, 0, idx, true); + } =20 /* Program KPM CAM and Action profiles */ npc_program_kpm_profile(rvu, blkaddr, hw->npc_kpms); @@ -679,7 +695,7 @@ struct npc_priv_t *npc_priv_get(void) } =20 static void npc_program_mkex_rx(struct rvu *rvu, int blkaddr, - struct npc_mcam_kex_extr *mkex_extr, + const struct npc_mcam_kex_extr *mkex_extr, u8 intf) { u8 num_extr =3D rvu->hw->npc_kex_extr; @@ -708,7 +724,7 @@ static void npc_program_mkex_rx(struct rvu *rvu, int bl= kaddr, } =20 static void npc_program_mkex_tx(struct rvu *rvu, int blkaddr, - struct npc_mcam_kex_extr *mkex_extr, + const struct npc_mcam_kex_extr *mkex_extr, u8 intf) { u8 num_extr =3D rvu->hw->npc_kex_extr; @@ -737,7 +753,7 @@ static void npc_program_mkex_tx(struct rvu *rvu, int bl= kaddr, } =20 static void npc_program_mkex_profile(struct rvu *rvu, int blkaddr, - struct npc_mcam_kex_extr *mkex_extr) + const struct npc_mcam_kex_extr *mkex_extr) { struct rvu_hwinfo *hw =3D rvu->hw; u8 intf; @@ -1589,8 +1605,8 @@ npc_cn20k_update_action_entries_n_flags(struct rvu *r= vu, int npc_cn20k_apply_custom_kpu(struct rvu *rvu, struct npc_kpu_profile_adapter *profile) { + const struct npc_cn20k_kpu_profile_fwdata *fw =3D rvu->kpu_fwdata; size_t hdr_sz =3D sizeof(struct npc_cn20k_kpu_profile_fwdata); - struct npc_cn20k_kpu_profile_fwdata *fw =3D rvu->kpu_fwdata; struct npc_kpu_profile_action *action; struct npc_kpu_profile_cam *cam; struct npc_kpu_fwdata *fw_kpu; @@ -1635,8 +1651,15 @@ int npc_cn20k_apply_custom_kpu(struct rvu *rvu, } =20 /* Verify if profile fits the HW */ + if (fw->kpus > rvu->hw->npc_kpus) { + dev_warn(rvu->dev, "Not enough KPUs: %d > %d\n", fw->kpus, + rvu->hw->npc_kpus); + return -EINVAL; + } + + /* Check if there is enough memory */ if (fw->kpus > profile->kpus) { - dev_warn(rvu->dev, "Not enough KPUs: %d > %ld\n", fw->kpus, + dev_warn(rvu->dev, "Not enough KPUs: %d > %zu\n", fw->kpus, profile->kpus); return -EINVAL; } diff --git a/drivers/net/ethernet/marvell/octeontx2/af/npc.h b/drivers/net/= ethernet/marvell/octeontx2/af/npc.h index cefc5d70f3e4..c8c0cb68535c 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/npc.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/npc.h @@ -265,6 +265,19 @@ struct npc_kpu_profile_cam { u16 dp2_mask; } __packed; =20 +struct npc_kpu_profile_cam2 { + u8 state; + u8 state_mask; + u16 dp0; + u16 dp0_mask; + u16 dp1; + u16 dp1_mask; + u16 dp2; + u16 dp2_mask; + u8 ptype; + u8 ptype_mask; +} __packed; + struct npc_kpu_profile_action { u8 errlev; u8 errcode; @@ -290,6 +303,10 @@ struct npc_kpu_profile { int action_entries; struct npc_kpu_profile_cam *cam; struct npc_kpu_profile_action *action; + int cam_entries2; + int action_entries2; + struct npc_kpu_profile_action *action2; + struct npc_kpu_profile_cam2 *cam2; }; =20 /* NPC KPU register formats */ diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h b/drivers/net/= ethernet/marvell/octeontx2/af/rvu.h index a466181cf908..2a2f2287e0c0 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h @@ -553,17 +553,19 @@ struct npc_kpu_profile_adapter { const char *name; u64 version; const struct npc_lt_def_cfg *lt_def; - const struct npc_kpu_profile_action *ikpu; /* array[pkinds] */ - const struct npc_kpu_profile *kpu; /* array[kpus] */ + struct npc_kpu_profile_action *ikpu; /* array[pkinds] */ + struct npc_kpu_profile_action *ikpu2; /* array[pkinds] */ + struct npc_kpu_profile *kpu; /* array[kpus] */ union npc_mcam_key_prfl { - struct npc_mcam_kex *mkex; + const struct npc_mcam_kex *mkex; /* used for cn9k and cn10k */ - struct npc_mcam_kex_extr *mkex_extr; /* used for cn20k */ + const struct npc_mcam_kex_extr *mkex_extr; /* used for cn20k */ } mcam_kex_prfl; struct npc_mcam_kex_hash *mkex_hash; bool custom; size_t pkinds; size_t kpus; + bool from_fs; }; =20 #define RVU_SWITCH_LBK_CHAN 63 @@ -634,7 +636,7 @@ struct rvu { =20 /* Firmware data */ struct rvu_fwdata *fwdata; - void *kpu_fwdata; + const void *kpu_fwdata; size_t kpu_fwdata_sz; void __iomem *kpu_prfl_addr; =20 diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c b/drivers/= net/ethernet/marvell/octeontx2/af/rvu_npc.c index 8d260bcfbf38..9cb9a850e903 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c @@ -1384,7 +1384,8 @@ void rvu_npc_free_mcam_entries(struct rvu *rvu, u16 p= cifunc, int nixlf) } =20 static void npc_program_mkex_rx(struct rvu *rvu, int blkaddr, - struct npc_mcam_kex *mkex, u8 intf) + const struct npc_mcam_kex *mkex, + u8 intf) { int lid, lt, ld, fl; =20 @@ -1413,7 +1414,8 @@ static void npc_program_mkex_rx(struct rvu *rvu, int = blkaddr, } =20 static void npc_program_mkex_tx(struct rvu *rvu, int blkaddr, - struct npc_mcam_kex *mkex, u8 intf) + const struct npc_mcam_kex *mkex, + u8 intf) { int lid, lt, ld, fl; =20 @@ -1442,7 +1444,7 @@ static void npc_program_mkex_tx(struct rvu *rvu, int = blkaddr, } =20 static void npc_program_mkex_profile(struct rvu *rvu, int blkaddr, - struct npc_mcam_kex *mkex) + const struct npc_mcam_kex *mkex) { struct rvu_hwinfo *hw =3D rvu->hw; u8 intf; @@ -1582,8 +1584,12 @@ static void npc_config_kpucam(struct rvu *rvu, int b= lkaddr, const struct npc_kpu_profile_cam *kpucam, int kpu, int entry) { + const struct npc_kpu_profile_cam2 *kpucam2 =3D (void *)kpucam; + struct npc_kpu_profile_adapter *profile =3D &rvu->kpu; struct npc_kpu_cam cam0 =3D {0}; struct npc_kpu_cam cam1 =3D {0}; + u64 *val =3D (u64 *)&cam1; + u64 *mask =3D (u64 *)&cam0; =20 cam1.state =3D kpucam->state & kpucam->state_mask; cam1.dp0_data =3D kpucam->dp0 & kpucam->dp0_mask; @@ -1595,6 +1601,14 @@ static void npc_config_kpucam(struct rvu *rvu, int b= lkaddr, cam0.dp1_data =3D ~kpucam->dp1 & kpucam->dp1_mask; cam0.dp2_data =3D ~kpucam->dp2 & kpucam->dp2_mask; =20 + if (profile->from_fs) { + u8 ptype =3D kpucam2->ptype; + u8 pmask =3D kpucam2->ptype_mask; + + *val |=3D FIELD_PREP(GENMASK_ULL(57, 56), ptype & pmask); + *mask |=3D FIELD_PREP(GENMASK_ULL(57, 56), ~ptype & pmask); + } + rvu_write64(rvu, blkaddr, NPC_AF_KPUX_ENTRYX_CAMX(kpu, entry, 0), *(u64 *)&cam0); rvu_write64(rvu, blkaddr, @@ -1606,34 +1620,104 @@ u64 npc_enable_mask(int count) return (((count) < 64) ? ~(BIT_ULL(count) - 1) : (0x00ULL)); } =20 +struct npc_kpu_profile_action * +npc_get_ikpu_nth_entry(struct rvu *rvu, int n) +{ + struct npc_kpu_profile_adapter *profile =3D &rvu->kpu; + + if (profile->from_fs) + return &profile->ikpu2[n]; + + return &profile->ikpu[n]; +} + +int +npc_get_num_kpu_cam_entries(struct rvu *rvu, + const struct npc_kpu_profile *kpu_pfl) +{ + struct npc_kpu_profile_adapter *profile =3D &rvu->kpu; + + if (profile->from_fs) + return kpu_pfl->cam_entries2; + + return kpu_pfl->cam_entries; +} + +struct npc_kpu_profile_cam * +npc_get_kpu_cam_nth_entry(struct rvu *rvu, + const struct npc_kpu_profile *kpu_pfl, int n) +{ + struct npc_kpu_profile_adapter *profile =3D &rvu->kpu; + + if (profile->from_fs) + return (void *)&kpu_pfl->cam2[n]; + + return (void *)&kpu_pfl->cam[n]; +} + +int +npc_get_num_kpu_action_entries(struct rvu *rvu, + const struct npc_kpu_profile *kpu_pfl) +{ + struct npc_kpu_profile_adapter *profile =3D &rvu->kpu; + + if (profile->from_fs) + return kpu_pfl->action_entries2; + + return kpu_pfl->action_entries; +} + +struct npc_kpu_profile_action * +npc_get_kpu_action_nth_entry(struct rvu *rvu, + const struct npc_kpu_profile *kpu_pfl, + int n) +{ + struct npc_kpu_profile_adapter *profile =3D &rvu->kpu; + + if (profile->from_fs) + return (void *)&kpu_pfl->action2[n]; + + return (void *)&kpu_pfl->action[n]; +} + static void npc_program_kpu_profile(struct rvu *rvu, int blkaddr, int kpu, const struct npc_kpu_profile *profile) { + int num_cam_entries, num_action_entries; int entry, num_entries, max_entries; u64 entry_mask; =20 - if (profile->cam_entries !=3D profile->action_entries) { + num_cam_entries =3D npc_get_num_kpu_cam_entries(rvu, profile); + num_action_entries =3D npc_get_num_kpu_action_entries(rvu, profile); + + if (num_cam_entries !=3D num_action_entries) { dev_err(rvu->dev, "KPU%d: CAM and action entries [%d !=3D %d] not equal\n", - kpu, profile->cam_entries, profile->action_entries); + kpu, num_cam_entries, num_action_entries); } =20 max_entries =3D rvu->hw->npc_kpu_entries; =20 + WARN(num_cam_entries > max_entries, + "KPU%u: err: hw max entries=3D%u, input entries=3D%u\n", + kpu, rvu->hw->npc_kpu_entries, num_cam_entries); + /* Program CAM match entries for previous KPU extracted data */ - num_entries =3D min_t(int, profile->cam_entries, max_entries); + num_entries =3D min_t(int, num_cam_entries, max_entries); for (entry =3D 0; entry < num_entries; entry++) npc_config_kpucam(rvu, blkaddr, - &profile->cam[entry], kpu, entry); + (void *)npc_get_kpu_cam_nth_entry(rvu, profile, entry), + kpu, entry); =20 /* Program this KPU's actions */ - num_entries =3D min_t(int, profile->action_entries, max_entries); + num_entries =3D min_t(int, num_action_entries, max_entries); for (entry =3D 0; entry < num_entries; entry++) - npc_config_kpuaction(rvu, blkaddr, &profile->action[entry], + npc_config_kpuaction(rvu, blkaddr, + (void *)npc_get_kpu_action_nth_entry(rvu, profile, entry), kpu, entry, false); =20 /* Enable all programmed entries */ - num_entries =3D min_t(int, profile->action_entries, profile->cam_entries); + num_entries =3D min_t(int, num_action_entries, num_cam_entries); entry_mask =3D npc_enable_mask(num_entries); /* Disable first KPU_MAX_CST_ENT entries for built-in profile */ if (!rvu->kpu.custom) @@ -1677,26 +1761,166 @@ static void npc_prepare_default_kpu(struct rvu *rv= u, npc_cn20k_update_action_entries_n_flags(rvu, profile); } =20 -static int npc_apply_custom_kpu(struct rvu *rvu, - struct npc_kpu_profile_adapter *profile) +static int npc_alloc_kpu_cam2_n_action2(struct rvu *rvu, int kpu_num, + int num_entries) +{ + struct npc_kpu_profile_adapter *adapter =3D &rvu->kpu; + struct npc_kpu_profile *kpu; + + kpu =3D &adapter->kpu[kpu_num]; + + kpu->cam2 =3D devm_kcalloc(rvu->dev, num_entries, + sizeof(*kpu->cam2), GFP_KERNEL); + if (!kpu->cam2) + return -ENOMEM; + + kpu->action2 =3D devm_kcalloc(rvu->dev, num_entries, + sizeof(*kpu->action2), GFP_KERNEL); + if (!kpu->action2) + return -ENOMEM; + + return 0; +} + +static int npc_apply_custom_kpu_from_fw(struct rvu *rvu, + struct npc_kpu_profile_adapter *profile) { size_t hdr_sz =3D sizeof(struct npc_kpu_profile_fwdata), offset =3D 0; + const struct npc_kpu_profile_fwdata *fw; struct npc_kpu_profile_action *action; - struct npc_kpu_profile_fwdata *fw; struct npc_kpu_profile_cam *cam; struct npc_kpu_fwdata *fw_kpu; - int entries; - u16 kpu, entry; + int entries, entry, kpu; =20 - if (is_cn20k(rvu->pdev)) - return npc_cn20k_apply_custom_kpu(rvu, profile); + fw =3D rvu->kpu_fwdata; + + /* Check if there is enough memory */ + if (fw->kpus > profile->kpus) { + dev_warn(rvu->dev, "Not enough KPUs: %d > %zu\n", fw->kpus, + profile->kpus); + return -EINVAL; + } + + for (kpu =3D 0; kpu < fw->kpus; kpu++) { + if (rvu->kpu_fwdata_sz < hdr_sz + offset) { + dev_warn(rvu->dev, + "Profile size mismatch on KPU%i parsing\n", + kpu + 1); + return -EINVAL; + } + + fw_kpu =3D (struct npc_kpu_fwdata *)(fw->data + offset); + if (fw_kpu->entries > KPU_MAX_CST_ENT) + dev_warn(rvu->dev, + "Too many custom entries on KPU%d: %d > %d\n", + kpu, fw_kpu->entries, KPU_MAX_CST_ENT); + entries =3D min(fw_kpu->entries, KPU_MAX_CST_ENT); + cam =3D (struct npc_kpu_profile_cam *)fw_kpu->data; + offset +=3D sizeof(*fw_kpu) + fw_kpu->entries * sizeof(*cam); + action =3D (struct npc_kpu_profile_action *)(fw->data + offset); + offset +=3D fw_kpu->entries * sizeof(*action); + if (rvu->kpu_fwdata_sz < hdr_sz + offset) { + dev_warn(rvu->dev, + "Profile size mismatch on KPU%i parsing.\n", + kpu + 1); + return -EINVAL; + } + for (entry =3D 0; entry < entries; entry++) { + profile->kpu[kpu].cam[entry] =3D cam[entry]; + profile->kpu[kpu].action[entry] =3D action[entry]; + } + } + + return 0; +} + +static int npc_apply_custom_kpu_from_fs(struct rvu *rvu, + struct npc_kpu_profile_adapter *profile) +{ + size_t hdr_sz =3D sizeof(struct npc_kpu_profile_fwdata), offset =3D 0; + const struct npc_kpu_profile_fwdata *fw; + struct npc_kpu_profile_action *action; + struct npc_kpu_profile_cam2 *cam2; + struct npc_kpu_fwdata *fw_kpu; + int entries, ret, entry, kpu; =20 fw =3D rvu->kpu_fwdata; =20 + /* Binary blob contains ikpu actions entries at start of data[0] */ + profile->ikpu2 =3D devm_kcalloc(rvu->dev, 1, + sizeof(ikpu_action_entries), + GFP_KERNEL); + if (!profile->ikpu2) + return -ENOMEM; + + action =3D (struct npc_kpu_profile_action *)(fw->data + offset); + + if (rvu->kpu_fwdata_sz < hdr_sz + sizeof(ikpu_action_entries)) + return -ENOMEM; + + memcpy((void *)profile->ikpu2, action, sizeof(ikpu_action_entries)); + offset +=3D sizeof(ikpu_action_entries); + + for (kpu =3D 0; kpu < fw->kpus; kpu++) { + if (rvu->kpu_fwdata_sz < hdr_sz + offset) { + dev_warn(rvu->dev, + "profile size mismatch on kpu%i parsing\n", + kpu + 1); + return -EINVAL; + } + + fw_kpu =3D (struct npc_kpu_fwdata *)(fw->data + offset); + entries =3D min(fw_kpu->entries, rvu->hw->npc_kpu_entries); + dev_info(rvu->dev, + "Loading %u entries on KPU%d\n", entries, kpu); + + cam2 =3D (struct npc_kpu_profile_cam2 *)fw_kpu->data; + offset +=3D sizeof(*fw_kpu) + fw_kpu->entries * sizeof(*cam2); + action =3D (struct npc_kpu_profile_action *)(fw->data + offset); + offset +=3D fw_kpu->entries * sizeof(*action); + if (rvu->kpu_fwdata_sz < hdr_sz + offset) { + dev_warn(rvu->dev, + "profile size mismatch on kpu%i parsing.\n", + kpu + 1); + return -EINVAL; + } + + profile->kpu[kpu].cam_entries2 =3D entries; + profile->kpu[kpu].action_entries2 =3D entries; + ret =3D npc_alloc_kpu_cam2_n_action2(rvu, kpu, entries); + if (ret) { + dev_warn(rvu->dev, + "profile entry allocation failed for kpu=3D%d for %d entries\n", + kpu, entries); + return -EINVAL; + } + + for (entry =3D 0; entry < entries; entry++) { + profile->kpu[kpu].cam2[entry] =3D cam2[entry]; + profile->kpu[kpu].action2[entry] =3D action[entry]; + } + } + + return 0; +} + +static int npc_apply_custom_kpu(struct rvu *rvu, + struct npc_kpu_profile_adapter *profile, + bool from_fs, int *fw_kpus) +{ + size_t hdr_sz =3D sizeof(struct npc_kpu_profile_fwdata); + const struct npc_kpu_profile_fwdata *fw; + struct npc_kpu_profile_fwdata *sfw; + + if (is_cn20k(rvu->pdev)) + return npc_cn20k_apply_custom_kpu(rvu, profile); + if (rvu->kpu_fwdata_sz < hdr_sz) { dev_warn(rvu->dev, "Invalid KPU profile size\n"); return -EINVAL; } + + fw =3D rvu->kpu_fwdata; if (le64_to_cpu(fw->signature) !=3D KPU_SIGN) { dev_warn(rvu->dev, "Invalid KPU profile signature %llx\n", fw->signature); @@ -1724,42 +1948,28 @@ static int npc_apply_custom_kpu(struct rvu *rvu, return -EINVAL; } /* Verify if profile fits the HW */ - if (fw->kpus > profile->kpus) { - dev_warn(rvu->dev, "Not enough KPUs: %d > %ld\n", fw->kpus, - profile->kpus); + if (fw->kpus > rvu->hw->npc_kpus) { + dev_warn(rvu->dev, "Not enough KPUs: %d > %d\n", fw->kpus, + rvu->hw->npc_kpus); return -EINVAL; } =20 + *fw_kpus =3D fw->kpus; + + sfw =3D devm_kcalloc(rvu->dev, 1, sizeof(*sfw), GFP_KERNEL); + if (!sfw) + return -ENOMEM; + + memcpy(sfw, fw, sizeof(*sfw)); + profile->custom =3D 1; - profile->name =3D fw->name; + profile->name =3D sfw->name; profile->version =3D le64_to_cpu(fw->version); - profile->mcam_kex_prfl.mkex =3D &fw->mkex; - profile->lt_def =3D &fw->lt_def; + profile->mcam_kex_prfl.mkex =3D &sfw->mkex; + profile->lt_def =3D &sfw->lt_def; =20 - for (kpu =3D 0; kpu < fw->kpus; kpu++) { - fw_kpu =3D (struct npc_kpu_fwdata *)(fw->data + offset); - if (fw_kpu->entries > KPU_MAX_CST_ENT) - dev_warn(rvu->dev, - "Too many custom entries on KPU%d: %d > %d\n", - kpu, fw_kpu->entries, KPU_MAX_CST_ENT); - entries =3D min(fw_kpu->entries, KPU_MAX_CST_ENT); - cam =3D (struct npc_kpu_profile_cam *)fw_kpu->data; - offset +=3D sizeof(*fw_kpu) + fw_kpu->entries * sizeof(*cam); - action =3D (struct npc_kpu_profile_action *)(fw->data + offset); - offset +=3D fw_kpu->entries * sizeof(*action); - if (rvu->kpu_fwdata_sz < hdr_sz + offset) { - dev_warn(rvu->dev, - "Profile size mismatch on KPU%i parsing.\n", - kpu + 1); - return -EINVAL; - } - for (entry =3D 0; entry < entries; entry++) { - profile->kpu[kpu].cam[entry] =3D cam[entry]; - profile->kpu[kpu].action[entry] =3D action[entry]; - } - } - - return 0; + return from_fs ? npc_apply_custom_kpu_from_fs(rvu, profile) : + npc_apply_custom_kpu_from_fw(rvu, profile); } =20 static int npc_load_kpu_prfl_img(struct rvu *rvu, void __iomem *prfl_addr, @@ -1847,45 +2057,19 @@ static int npc_load_kpu_profile_fwdb(struct rvu *rv= u, const char *kpu_profile) return ret; } =20 -void npc_load_kpu_profile(struct rvu *rvu) +static int npc_load_kpu_profile_from_fw(struct rvu *rvu) { struct npc_kpu_profile_adapter *profile =3D &rvu->kpu; const char *kpu_profile =3D rvu->kpu_pfl_name; - const struct firmware *fw =3D NULL; - bool retry_fwdb =3D false; - - /* If user not specified profile customization */ - if (!strncmp(kpu_profile, def_pfl_name, KPU_NAME_LEN)) - goto revert_to_default; - /* First prepare default KPU, then we'll customize top entries. */ - npc_prepare_default_kpu(rvu, profile); - - /* Order of preceedence for load loading NPC profile (high to low) - * Firmware binary in filesystem. - * Firmware database method. - * Default KPU profile. - */ - if (!request_firmware_direct(&fw, kpu_profile, rvu->dev)) { - dev_info(rvu->dev, "Loading KPU profile from firmware: %s\n", - kpu_profile); - rvu->kpu_fwdata =3D kzalloc(fw->size, GFP_KERNEL); - if (rvu->kpu_fwdata) { - memcpy(rvu->kpu_fwdata, fw->data, fw->size); - rvu->kpu_fwdata_sz =3D fw->size; - } - release_firmware(fw); - retry_fwdb =3D true; - goto program_kpu; - } + int fw_kpus =3D 0; =20 -load_image_fwdb: /* Loading the KPU profile using firmware database */ if (npc_load_kpu_profile_fwdb(rvu, kpu_profile)) - goto revert_to_default; + return -EFAULT; =20 -program_kpu: /* Apply profile customization if firmware was loaded. */ - if (!rvu->kpu_fwdata_sz || npc_apply_custom_kpu(rvu, profile)) { + if (!rvu->kpu_fwdata_sz || + npc_apply_custom_kpu(rvu, profile, false, &fw_kpus)) { /* If image from firmware filesystem fails to load or invalid * retry with firmware database method. */ @@ -1899,10 +2083,6 @@ void npc_load_kpu_profile(struct rvu *rvu) } rvu->kpu_fwdata =3D NULL; rvu->kpu_fwdata_sz =3D 0; - if (retry_fwdb) { - retry_fwdb =3D false; - goto load_image_fwdb; - } } =20 dev_warn(rvu->dev, @@ -1910,7 +2090,7 @@ void npc_load_kpu_profile(struct rvu *rvu) kpu_profile); kfree(rvu->kpu_fwdata); rvu->kpu_fwdata =3D NULL; - goto revert_to_default; + return -EFAULT; } =20 dev_info(rvu->dev, "Using custom profile '%s', version %d.%d.%d\n", @@ -1918,14 +2098,90 @@ void npc_load_kpu_profile(struct rvu *rvu) NPC_KPU_VER_MIN(profile->version), NPC_KPU_VER_PATCH(profile->version)); =20 - return; + return 0; +} + +static int npc_load_kpu_profile_from_fs(struct rvu *rvu) +{ + struct npc_kpu_profile_adapter *profile =3D &rvu->kpu; + const char *kpu_profile =3D rvu->kpu_pfl_name; + const struct firmware *fw =3D NULL; + int ret, fw_kpus =3D 0; + char path[512] =3D "kpu/"; + + if (strlen(kpu_profile) > sizeof(path) - strlen("kpu/") - 1) { + dev_err(rvu->dev, "kpu profile name is too big\n"); + return -ENOSPC; + } + + strcat(path, kpu_profile); + + if (request_firmware_direct(&fw, path, rvu->dev)) + return -ENOENT; + + dev_info(rvu->dev, "Loading KPU profile from filesystem: %s\n", + path); + + rvu->kpu_fwdata =3D fw->data; + rvu->kpu_fwdata_sz =3D fw->size; + + ret =3D npc_apply_custom_kpu(rvu, profile, true, &fw_kpus); + release_firmware(fw); + rvu->kpu_fwdata =3D NULL; + + if (ret) { + rvu->kpu_fwdata_sz =3D 0; + dev_err(rvu->dev, + "Loading KPU profile from filesystem failed\n"); + return ret; + } + + rvu->kpu.kpus =3D fw_kpus; + profile->kpus =3D fw_kpus; + profile->from_fs =3D true; + return 0; +} + +void npc_load_kpu_profile(struct rvu *rvu) +{ + struct npc_kpu_profile_adapter *profile =3D &rvu->kpu; + const char *kpu_profile =3D rvu->kpu_pfl_name; + + profile->from_fs =3D false; + + npc_prepare_default_kpu(rvu, profile); + + /* If user not specified profile customization */ + if (!strncmp(kpu_profile, def_pfl_name, KPU_NAME_LEN)) + return; + + /* Order of preceedence for load loading NPC profile (high to low) + * Firmware binary in filesystem. + * Firmware database method. + * Default KPU profile. + */ + + /* Filesystem-based KPU loading is not supported on cn20k. + * npc_prepare_default_kpu() was invoked earlier, but control + * reached this point because the default profile was not selected. + * No need to call it again. + */ + if (!is_cn20k(rvu->pdev)) { + if (!npc_load_kpu_profile_from_fs(rvu)) + return; + } + + /* First prepare default KPU, then we'll customize top entries. */ + npc_prepare_default_kpu(rvu, profile); + if (!npc_load_kpu_profile_from_fw(rvu)) + return; =20 -revert_to_default: npc_prepare_default_kpu(rvu, profile); } =20 static void npc_parser_profile_init(struct rvu *rvu, int blkaddr) { + struct npc_kpu_profile_adapter *profile =3D &rvu->kpu; struct rvu_hwinfo *hw =3D rvu->hw; int num_pkinds, num_kpus, idx; =20 @@ -1949,7 +2205,9 @@ static void npc_parser_profile_init(struct rvu *rvu, = int blkaddr) num_pkinds =3D min_t(int, hw->npc_pkinds, num_pkinds); =20 for (idx =3D 0; idx < num_pkinds; idx++) - npc_config_kpuaction(rvu, blkaddr, &rvu->kpu.ikpu[idx], 0, idx, true); + npc_config_kpuaction(rvu, blkaddr, + npc_get_ikpu_nth_entry(rvu, idx), + 0, idx, true); =20 /* Program KPU CAM and Action profiles */ num_kpus =3D rvu->kpu.kpus; @@ -1957,6 +2215,11 @@ static void npc_parser_profile_init(struct rvu *rvu,= int blkaddr) =20 for (idx =3D 0; idx < num_kpus; idx++) npc_program_kpu_profile(rvu, blkaddr, idx, &rvu->kpu.kpu[idx]); + + if (profile->from_fs) { + rvu_write64(rvu, blkaddr, NPC_AF_PKINDX_TYPE(54), 0x03); + rvu_write64(rvu, blkaddr, NPC_AF_PKINDX_TYPE(58), 0x03); + } } =20 void npc_mcam_rsrcs_deinit(struct rvu *rvu) @@ -2186,18 +2449,21 @@ static void rvu_npc_hw_init(struct rvu *rvu, int bl= kaddr) =20 static void rvu_npc_setup_interfaces(struct rvu *rvu, int blkaddr) { - struct npc_mcam_kex_extr *mkex_extr =3D rvu->kpu.mcam_kex_prfl.mkex_extr; - struct npc_mcam_kex *mkex =3D rvu->kpu.mcam_kex_prfl.mkex; + const struct npc_mcam_kex_extr *mkex_extr; struct npc_mcam *mcam =3D &rvu->hw->mcam; struct rvu_hwinfo *hw =3D rvu->hw; + const struct npc_mcam_kex *mkex; u64 nibble_ena, rx_kex, tx_kex; u64 *keyx_cfg, reg; u8 intf; =20 + mkex_extr =3D rvu->kpu.mcam_kex_prfl.mkex_extr; + mkex =3D rvu->kpu.mcam_kex_prfl.mkex; + if (is_cn20k(rvu->pdev)) { - keyx_cfg =3D mkex_extr->keyx_cfg; + keyx_cfg =3D (u64 *)mkex_extr->keyx_cfg; } else { - keyx_cfg =3D mkex->keyx_cfg; + keyx_cfg =3D (u64 *)mkex->keyx_cfg; /* Reserve last counter for MCAM RX miss action which is set to * drop packet. This way we will know how many pkts didn't * match any MCAM entry. diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.h b/drivers/= net/ethernet/marvell/octeontx2/af/rvu_npc.h index 83c5e32e2afc..662f6693cfe9 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.h @@ -18,4 +18,21 @@ int npc_fwdb_prfl_img_map(struct rvu *rvu, void __iomem = **prfl_img_addr, =20 void npc_mcam_clear_bit(struct npc_mcam *mcam, u16 index); void npc_mcam_set_bit(struct npc_mcam *mcam, u16 index); + +struct npc_kpu_profile_action * +npc_get_ikpu_nth_entry(struct rvu *rvu, int n); + +int +npc_get_num_kpu_cam_entries(struct rvu *rvu, + const struct npc_kpu_profile *kpu_pfl); +struct npc_kpu_profile_cam * +npc_get_kpu_cam_nth_entry(struct rvu *rvu, + const struct npc_kpu_profile *kpu_pfl, int n); + +int +npc_get_num_kpu_action_entries(struct rvu *rvu, + const struct npc_kpu_profile *kpu_pfl); +struct npc_kpu_profile_action * +npc_get_kpu_action_nth_entry(struct rvu *rvu, + const struct npc_kpu_profile *kpu_pfl, int n); #endif /* RVU_NPC_H */ diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h b/drivers/= net/ethernet/marvell/octeontx2/af/rvu_reg.h index 62cdc714ba57..ab89b8c6e490 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h @@ -596,6 +596,7 @@ #define NPC_AF_INTFX_KEX_CFG(a) (0x01010 | (a) << 8) #define NPC_AF_PKINDX_ACTION0(a) (0x80000ull | (a) << 6) #define NPC_AF_PKINDX_ACTION1(a) (0x80008ull | (a) << 6) +#define NPC_AF_PKINDX_TYPE(a) (0x80010ull | (a) << 6) #define NPC_AF_PKINDX_CPI_DEFX(a, b) (0x80020ull | (a) << 6 | (b) << 3) #define NPC_AF_KPUX_ENTRYX_CAMX(a, b, c) \ (0x100000 | (a) << 14 | (b) << 6 | (c) << 3) --=20 2.43.0