From nobody Tue Apr 7 19:27:11 2026 Received: from szxga01-in.huawei.com (szxga01-in.huawei.com [45.249.212.187]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C880E34D929 for ; Fri, 3 Apr 2026 02:57:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.187 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775185034; cv=none; b=urJsRGC8QX16a0tTBQwyBXlPLqGVIxKmV7oHVMQOONcdTz7xV+SQbzOKAmN8R3P1RijG2ARjlBAjOV7PT2U7yI9Iq2Jpv3nL2RNXdYdyk7qV+nSxZS/YdyeVaNGur8yuTUH3LU+24GaSUzzBKTaQt1HitAJjUXG/4/a474cW5L4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775185034; c=relaxed/simple; bh=bN196w5uJnNuEAb3j6bpJxTmAtl+qTJzPnu45xjF5Uw=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=DCJebHZ4rQ+3KvyVSzZhuU2LfjsrnKO+vy6X9Vlbp+KshTWkKJNMV546cdYG/P5cqEsNEWl08HlHQJqTDCVID27cZk1izh4R4VMzpUqSRGYxUNxi8TH0nQ2JllaQ+SBxNzeBJ78DpwOCF8rRunJhgQCZfZ8GtV6tEou5ghGSiCw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; dkim=pass (1024-bit key) header.d=huawei.com header.i=@huawei.com header.b=29a3P6Su; dkim=pass (1024-bit key) header.d=huawei.com header.i=@huawei.com header.b=29a3P6Su; arc=none smtp.client-ip=45.249.212.187 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=huawei.com header.i=@huawei.com header.b="29a3P6Su"; dkim=pass (1024-bit key) header.d=huawei.com header.i=@huawei.com header.b="29a3P6Su" dkim-signature: v=1; a=rsa-sha256; d=huawei.com; s=dkim; c=relaxed/relaxed; q=dns/txt; h=From; bh=0/7lhIvptValFLsO6c31JQ9gejNIVCOLMyQbvxnGgV4=; b=29a3P6SuJf9KG3k7fPQDFHCmzJ+qG7yBPljJp3c06HRTBKe/d0CZ1zf4QlnSB4YqJFofFiXuH AgN1VGnliiuwuBFuNMQ4U8GS3F9iXnXrBfKNzA/nKq0yxtlzSQ7aict0Lf3dqv2Y7YFji37XhTq ZeZ8cKGnMCLLGbbvYcRK6fw= Received: from canpmsgout03.his.huawei.com (unknown [172.19.92.159]) by szxga01-in.huawei.com (SkyGuard) with ESMTPS id 4fn3KH3tvNz1BFnV for ; Fri, 3 Apr 2026 10:56:51 +0800 (CST) dkim-signature: v=1; a=rsa-sha256; d=huawei.com; s=dkim; c=relaxed/relaxed; q=dns/txt; h=From; bh=0/7lhIvptValFLsO6c31JQ9gejNIVCOLMyQbvxnGgV4=; b=29a3P6SuJf9KG3k7fPQDFHCmzJ+qG7yBPljJp3c06HRTBKe/d0CZ1zf4QlnSB4YqJFofFiXuH AgN1VGnliiuwuBFuNMQ4U8GS3F9iXnXrBfKNzA/nKq0yxtlzSQ7aict0Lf3dqv2Y7YFji37XhTq ZeZ8cKGnMCLLGbbvYcRK6fw= Received: from mail.maildlp.com (unknown [172.19.163.0]) by canpmsgout03.his.huawei.com (SkyGuard) with ESMTPS id 4fn3Bm0XQ7zpSw3; Fri, 3 Apr 2026 10:51:12 +0800 (CST) Received: from dggemv712-chm.china.huawei.com (unknown [10.1.198.32]) by mail.maildlp.com (Postfix) with ESMTPS id 17B7740572; Fri, 3 Apr 2026 10:57:03 +0800 (CST) Received: from kwepemq100007.china.huawei.com (7.202.195.175) by dggemv712-chm.china.huawei.com (10.1.198.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Fri, 3 Apr 2026 10:57:02 +0800 Received: from localhost.huawei.com (10.169.71.169) by kwepemq100007.china.huawei.com (7.202.195.175) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Fri, 3 Apr 2026 10:57:02 +0800 From: Yongbang Shi To: , , , , , , , , CC: , , , , , , , , Subject: [PATCH for drm-misc-fixes v2 3/4] drm/hisilicon/hibmc: move display contrl config to hibmc_probe() Date: Fri, 3 Apr 2026 10:48:27 +0800 Message-ID: <20260403024828.1131906-4-shiyongbang@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20260403024828.1131906-1-shiyongbang@huawei.com> References: <20260403024828.1131906-1-shiyongbang@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: kwepems100002.china.huawei.com (7.221.188.206) To kwepemq100007.china.huawei.com (7.202.195.175) Content-Type: text/plain; charset="utf-8" From: Lin He If there's no VGA output, this encoder modeset won't be called, which will cause displaying data from GPU being cut off. It's actually a common display config for DP and VGA, so move the vdac encoder modeset to driver load stage. Fixes: 5294967f4ae4 ("drm/hisilicon/hibmc: Add support for VDAC") Signed-off-by: Lin He Signed-off-by: Yongbang Shi --- ChangeLog: v1 -> v2: - remove tag "Reviewed-by: Tao Tian ", witch will be given in public. - add 'drm-misc-fixes' in subject prefix. --- .../gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c | 14 ++++++++++++ .../gpu/drm/hisilicon/hibmc/hibmc_drm_vdac.c | 22 ------------------- 2 files changed, 14 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c b/drivers/gpu/= drm/hisilicon/hibmc/hibmc_drm_drv.c index 289304500ab0..8fd92e4755d1 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c +++ b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c @@ -214,6 +214,18 @@ void hibmc_set_current_gate(struct hibmc_drm_private *= priv, unsigned int gate) writel(gate, mmio + gate_reg); } =20 +static void hibmc_display_ctrl(struct hibmc_drm_private *priv) +{ + u32 reg; + + reg =3D readl(priv->mmio + HIBMC_DISPLAY_CONTROL_HISILE); + reg |=3D HIBMC_DISPLAY_CONTROL_FPVDDEN(1); + reg |=3D HIBMC_DISPLAY_CONTROL_PANELDATE(1); + reg |=3D HIBMC_DISPLAY_CONTROL_FPEN(1); + reg |=3D HIBMC_DISPLAY_CONTROL_VBIASEN(1); + writel(reg, priv->mmio + HIBMC_DISPLAY_CONTROL_HISILE); +} + static void hibmc_hw_config(struct hibmc_drm_private *priv) { u32 reg; @@ -245,6 +257,8 @@ static void hibmc_hw_config(struct hibmc_drm_private *p= riv) reg |=3D HIBMC_MSCCTL_LOCALMEM_RESET(1); =20 writel(reg, priv->mmio + HIBMC_MISC_CTRL); + + hibmc_display_ctrl(priv); } =20 static int hibmc_hw_map(struct hibmc_drm_private *priv) diff --git a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_vdac.c b/drivers/gpu= /drm/hisilicon/hibmc/hibmc_drm_vdac.c index 806d54120d89..f5c7857c6586 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_vdac.c +++ b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_vdac.c @@ -86,26 +86,6 @@ static const struct drm_connector_funcs hibmc_connector_= funcs =3D { .atomic_destroy_state =3D drm_atomic_helper_connector_destroy_state, }; =20 -static void hibmc_encoder_mode_set(struct drm_encoder *encoder, - struct drm_display_mode *mode, - struct drm_display_mode *adj_mode) -{ - u32 reg; - struct drm_device *dev =3D encoder->dev; - struct hibmc_drm_private *priv =3D to_hibmc_drm_private(dev); - - reg =3D readl(priv->mmio + HIBMC_DISPLAY_CONTROL_HISILE); - reg |=3D HIBMC_DISPLAY_CONTROL_FPVDDEN(1); - reg |=3D HIBMC_DISPLAY_CONTROL_PANELDATE(1); - reg |=3D HIBMC_DISPLAY_CONTROL_FPEN(1); - reg |=3D HIBMC_DISPLAY_CONTROL_VBIASEN(1); - writel(reg, priv->mmio + HIBMC_DISPLAY_CONTROL_HISILE); -} - -static const struct drm_encoder_helper_funcs hibmc_encoder_helper_funcs = =3D { - .mode_set =3D hibmc_encoder_mode_set, -}; - int hibmc_vdac_init(struct hibmc_drm_private *priv) { struct drm_device *dev =3D &priv->dev; @@ -128,8 +108,6 @@ int hibmc_vdac_init(struct hibmc_drm_private *priv) goto err; } =20 - drm_encoder_helper_add(encoder, &hibmc_encoder_helper_funcs); - ret =3D drm_connector_init_with_ddc(dev, connector, &hibmc_connector_funcs, DRM_MODE_CONNECTOR_VGA, --=20 2.33.0