From nobody Tue Apr 7 01:36:37 2026 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D11223DA7CF; Fri, 3 Apr 2026 16:10:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.171.202.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775232644; cv=none; b=up8XmFRkFdg34JL7tvDD4fikR16BvIK+Tyc0IJG42tzlcaTIfIqWG8pUtYYe1vTxAcIDyjamSN7mPA4S+JteUEm/DL+Oh/R6kY6LLKbP/Qg+YSvPrPnxdUjX2diFYH4x8XPw7qkM11FUcsn8eaJWAtEbnMxDjuYqdKGk2IkW0ns= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775232644; c=relaxed/simple; bh=CqbYqkoQqh+0D35g5HcSsYYzUUg1QfemNwma1WIXWyM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=OJkrNUutDENNy3KGFyKzeP4VPEKKReROkKk7A8mCnq05ZZpBIXVUuFTuG58X7RXYf9CY9z4YohcTDDaUporEH1KxcegVfrxk5XbLEQrqzGQJraVpcgxmKPtuSyIg7Z5TrVlDrFUxtxyAVql/SoLIeQ6sbSVSyLB/HUUpDiRIDsU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=mdDBZJMT; arc=none smtp.client-ip=185.171.202.116 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="mdDBZJMT" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-04.galae.net (Postfix) with ESMTPS id C12D8C59F67; Fri, 3 Apr 2026 16:11:13 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id C67B1603C1; Fri, 3 Apr 2026 16:10:41 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id F3AA210450103; Fri, 3 Apr 2026 18:10:38 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1775232641; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=AGr7/3+8bpTRkTV5LZlQ/ojfudXHIefGQxlwloROzME=; b=mdDBZJMTvZOeGrG8HRZS3PKJMvv0xM5ZjFPUizOP3bS8fi9nXilmjfxOH76UoNsGsSs8yv BBjhMsiZ51Pj01u8p2uqerbEZYzk0ABQnlV4OAfjtVBkBElIyR/Ua96GzLY2xtwxOF10Da I836w3+lAmj5o18vsbU+HIOOr9VR8CUZ6V5NABaZ9BMrcHpTul1hBSQ5X7YIprY5inUOH2 HkXRr1ryrQJkwRjhYWr3HKe7Av1IlMXNcqLQjgwABCzuum9yH0zE0Vq/kEvYVpxWrvZHcM QFy2aOzwCivI5gWbJdOGxVGK5ClRMQ4gS76UzD7WJYA9utdA8e19i7CeanJ4HQ== From: Miquel Raynal Date: Fri, 03 Apr 2026 18:09:45 +0200 Subject: [PATCH v4 27/27] mtd: spi-nor: winbond: Add W25Q02NWxxIM CMP locking support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260403-winbond-v6-18-rc1-spi-nor-swp-v4-27-833dab5e7288@bootlin.com> References: <20260403-winbond-v6-18-rc1-spi-nor-swp-v4-0-833dab5e7288@bootlin.com> In-Reply-To: <20260403-winbond-v6-18-rc1-spi-nor-swp-v4-0-833dab5e7288@bootlin.com> To: Pratyush Yadav , Michael Walle , Takahiro Kuwano , Richard Weinberger , Vignesh Raghavendra , Jonathan Corbet Cc: Sean Anderson , Thomas Petazzoni , Steam Lin , linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 This chip has support for the locking complement (CMP) feature. Add the relevant bit to enable it. Unfortunately, this chip also comes with an incorrect BFPT table, indicating the Control Register cannot be read back. This is wrong, reading back the register works and has no (observed) side effect. The datasheet clearly indicates supporting the 35h command and all bits from the CR are marked readable. QE and CMP bits are inside, and can be properly read back. Add a fixup for this, otherwise it would defeat the use of the CMP feature. Signed-off-by: Miquel Raynal --- Test run with W25Q02NWxxIM: $ flash_lock -u /dev/mtd0 $ flash_lock -l /dev/mtd0 $bs $all_but_one # all but the first $ show_sectors locked sectors region (in hex) | status | #blocks ------------------+----------+-------- 00000000-0000ffff | unlocked | 1 00010000-0fffffff | locked | 4095 $ flash_lock -u /dev/mtd0 $bs 1 # all but the two first $ show_sectors locked sectors region (in hex) | status | #blocks ------------------+----------+-------- 00000000-0001ffff | unlocked | 2 00020000-0fffffff | locked | 4094 $ flash_lock -u /dev/mtd0 $ flash_lock -l /dev/mtd0 0 $all_but_one # same from the other side $ show_sectors locked sectors region (in hex) | status | #blocks ------------------+----------+-------- 00000000-0ffeffff | locked | 4095 0fff0000-0fffffff | unlocked | 1 $ flash_lock -u /dev/mtd0 $(($size - (2 * $bs))) 1 # all but two $ show_sectors locked sectors region (in hex) | status | #blocks ------------------+----------+-------- 00000000-0ffdffff | locked | 4094 0ffe0000-0fffffff | unlocked | 2 --- drivers/mtd/spi-nor/winbond.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/spi-nor/winbond.c b/drivers/mtd/spi-nor/winbond.c index 72053a4505f9..639d72f48769 100644 --- a/drivers/mtd/spi-nor/winbond.c +++ b/drivers/mtd/spi-nor/winbond.c @@ -377,7 +377,9 @@ static const struct flash_info winbond_nor_parts[] =3D { }, { /* W25Q02NWxxIM */ .id =3D SNOR_ID(0xef, 0x80, 0x22), - .flags =3D SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 | SPI_= NOR_4BIT_BP, + .flags =3D SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 | + SPI_NOR_4BIT_BP | SPI_NOR_HAS_CMP, + .fixups =3D &winbond_rdcr_fixup, }, { /* W25H512NWxxAM */ .id =3D SNOR_ID(0xef, 0xa0, 0x20), --=20 2.53.0